Cryogenic semiconductor structure and method for operating the same

Abstract

The present disclosure relates to a cryogenic (MOSFET-like) semiconductor structure configured for low-dissipation high-speed operation at cryogenic temperatures. The structure is characterized by an overlapping multi-gate configuration in which a first gate electrode is arranged between a second gate electrode and a conductive channel formed under a surface portion of a dielectric substrate between spaced-apart n-doped and / or p-doped first and second regions. The first gate electrode is embedded in a dielectric layer covering the surface portion, while the second gate electrode may be either provided on the dielectric layer or also embedded in the dielectric layer above the first gate electrode. The first gate electrode is configured to partly overlap the surface portion, while the second gate electrode is configured to (at least partly) overlap the first gate electrode and (at least partly) overlap the surface portion on either side of the first gate electrode.

Description

[0001] CRYOGENIC SEMICONDUCTOR STRUCTURE AND METHOD FOR OPERATING THE SAME

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of quantum computers. More particularly, the present disclosure relates to a cryogenic semiconductor structure that may be used as an ultra-low dissipation logic (e.g., transistor) or memory element in the quantum computers, as well as to a method for operating the cryogenic semiconductor structure.

[0004] BACKGROUND

[0005] The development of electronic circuits at cryogenic temperatures (120 K or even lower) has great importance for a range of applications, such as high-performance classical computing, cryogenic sensors and detectors, space electronics, low-power neuromorphic circuits, and quantum computing. In this regard, Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) are of particular interest, since they can be combined with quantum bit (qubit) systems at the cryogenic temperatures to enable fast and efficiently- controlled manipulation and read-out of a large number of qubits.

[0006] The CMOS ICs are usually based on a MOS Field-Effect Transistor (MOSFET) technology. To improve their integrability and operating speed, MOSFETs are constantly being miniaturized. For example, thin-film Silicon-On- Insulator (SOI) MOSFETs are characterized by improved isolation and reduced parasitic capacitances compared to a bulk silicon technology.

[0007] However, as MOSFET dimensions are reduced, the so-called Short Channel Effects (SCE) become increasingly important, since a channel length becomes comparable to depletion layer widths of source and drain junctions. From the SCEs, the degradation of a threshold voltage and the increase of a subthreshold swing are the most significant. The subthreshold swing can be reduced by cooling a MOSFET, but at the same time the threshold voltage will increase with decreasing temperature, thereby not allowing one to achieve the high-speed performance and low-power operation of the MOSFET.

[0008] SUMMARY

[0009] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features of the present disclosure, nor is it intended to be used to limit the scope of the present disclosure.

[0010] The objective of the present disclosure is to provide a technical solution that enables low-power high-speed operation of a MOSFET-like semiconductor structure at cryogenic temperatures.

[0011] The objective above is achieved by the features of the independent claims in the appended claims. Further embodiments and examples are apparent from the dependent claims, the detailed description, and the accompanying drawings.

[0012] According to a first aspect, a cryogenic semiconductor structure is provided. The structure comprises a substrate comprising a first region and a second region spaced from the first region such that there is a surface portion between the first region and the second region. Each of the first region and the second region is n-doped and / or p-doped. The structure further comprises a dielectric layer covering the surface portion between the first region and the second region. A first gate electrode is embedded in the dielectric layer such that the first gate electrode partly overlaps the surface portion between the first region and the second region. Additionally, a second gate electrode is embedded in or provided on the dielectric layer such that the second gate electrode at least partly overlaps the first gate electrode and at least partly overlaps the surface portion between the first region and the second region on either side of the first gate electrode.

[0013] In the cryogenic semiconductor structure thus configured, the second gate electrode may be used to induce a two-dimensional electron / hole gas (2DEG / 2DHG) by drawing electrons / holes from the doped first and second regions (e.g., serving as source and drain regions, respectively) on either side of the first gate electrode, while the first gate electrode may be used to adjust a chemical potential such that a small non-zero voltage applied to the first gate electrode causes coupling between these 2DEGs / 2DHGs. This small non-zero voltage may be defined by the subthreshold swing that may be below 15 K ( kt>T) in energy. By doing so, the power consumption of the cryogenic semiconductor structure may be reduced significantly. Furthermore, the possibility of adjusting the chemical potential may provide a switching function, for which reason the cryogenic semiconductor structure may be used in different switching / logic circuits.

[0014] Additionally, in the cryogenic semiconductor structure thus configured, ambipolar transport is possible (when each of the first and second regions is n- and p-doped), i.e., holes and electrons can transport concurrently within a channel formed under the surface potion between the first and second regions. This may further reduce the power consumption and enable a new type of logic circuits or reconfigurable circuits with multifunctionality achieved with the same geometrical layout. In this case, a threshold voltage for both holes and electrons may be tuned close to zero with the second gate electrode, while the first gate electrode may be used to deplete the channel locally (i.e., underthe first gate electrode) to provide the above switching function.

[0015] In one exemplary embodiment of the first aspect, the substrate is made of bulk silicon and has a doping concentration less than 5 x 1018cm'3. In this embodiment, each of the first region and the second region has a doping concentration more than 5 x 1018cm'3. By using such doping concentrations, it is possible to provide more effective operation of the whole structure at cryogenic temperatures.

[0016] In one exemplary embodiment of the first aspect, the substrate further comprises a first layer between the first region and the second region. The first layer is n-doped or p-doped with a doping concentration such that the first layer is non-conductive at an operation temperature of the cryogenic semiconductor structure. In this embodiment, the first layer may be either n- doped or p-doped, but its doping concentration needs to be low enough for it not to be conductive at the operation (cryogenic) temperature. For example, the doping concentration may be less than 1 x 1018cm'3at 3 K and less than 1 x 1016cm'3at 100 K. With such a first layer, it is possible to provide better isolation of the channel formed under the surface portion from the substate, as well as to deplete the channel from charge carriers under the first gate electrode more efficiently (which in turn will provide better switching behavior of the structure).

[0017] In one exemplary embodiment of the first aspect, the substrate further comprises a second layer provided under the first layer. The second layer is n-doped or p-doped with a doping concentration such that the first layer and the second layer form a p-n junction. By using such a second layer, it is possible to provide much better channel isolation from the substrate and much better channel depletion.

[0018] In one exemplary embodiment of the first aspect, the second layer at least partly surrounds each of the first region and the second region from below. Thus, the second layer may not only extend under the channel (which is formed under the surface portion), but also may partly (i.e., not where the channel is) surround the first and second regions to provide better isolation of the cryogenic semiconductor structure from other possible densely packed components in an electronic circuit in which the cryogenic semiconductor structure may be used. In other words, the second layer according to this embodiment may limit a potential leakage current between the densely packed components in the electronic circuit.

[0019] In one exemplary embodiment of the first aspect, the substrate is alternatively made as a Silicon-On-lnsulator (SOI) wafer comprising a bulk silicon layer, an insulating layer provided on the bulk silicon layer, and a crystalline silicon layer provided on the insulating layer. The crystalline silicon layer comprises the first region and the second region. In this embodiment, the crystalline silicon layer has a doping concentration less than 5 x 1018cm'3, and each of the first region and the second region has a doping concentration more than 5 x 1018cm'3. By using such a multi-layered substrate with such doping concentrations, it is possible to provide more effective operation of the whole structure at the cryogenic temperatures.

[0020] In one exemplary embodiment of the first aspect, the crystalline silicon layer further comprises a first sub-layer between the first region and the second region. The first sub-layer is n-doped or p-doped with a doping concentration such that the first sub-layer is non-conductive at an operation temperature of the cryogenic semiconductor structure. Similarly, the first sublayer may be either n-doped or p-doped, but its doping concentration needs to be low enough for it not to be conductive at the operation (cryogenic) temperature. For example, the doping concentration may be less than 1 x 1018cm'3at 3 K and less than 1 x 1016cm'3at 100 K. With such a first sub-layer, it is possible to provide better isolation of the channel formed under the surface portion from the substate, as well as to deplete the channel from charge carriers under the first gate electrode more efficiently (which in turn will provide better switching behavior of the structure).

[0021] In one exemplary embodiment of the first aspect, the crystalline silicon layer further comprises a second sub-layer provided under the first sublayer. The second sub-layer is n-doped or p-doped with a doping concentration such that the first sub-layer and the second sub-layer form a p-n junction. By using such a second sub-layer, it is possible to provide much better channel isolation from the substrate and much better channel depletion.

[0022] In one exemplary embodiment of the first aspect, the second sublayer at least partly surrounds each of the first region and the second region from below. Thus, the second sub-layer may not only extend under the channel (which is formed under the surface portion), but also may partly (i.e., not where the channel is) surround the first and second regions to provide better isolation of the cryogenic semiconductor structure from other possible densely packed components in an electronic circuit in which the cryogenic semiconductor structure may be used. In other words, the second sub-layer according to this embodiment may limit a potential leakage current between the densely packed components in the electronic circuit.

[0023] In one exemplary embodiment of the first aspect, the dielectric layer is made of SiO2, SiN, AI2O3, HfO2, HfSiON, HfSiO, or ZrO2. These materials have dielectric properties suitable for the effective operation of the cryogenic semiconductor structure at cryogenic temperatures.

[0024] In one exemplary embodiment of the first aspect, the first gate electrode has a middle portion and at least one edge portion surrounding the middle portion. In this embodiment, the second gate is shaped to overlap each of the at least one edge portion of the first gate electrode and leave the middle portion of the first gate electrode non-overlapped. This embodiment may be used to reduce possible parasitic coupling between the first and second gate electrodes.

[0025] In one exemplary embodiment of the first aspect, the first gate electrode has a curved shape. The curved shape of the first gate electrode may improve an on / off resistance ratio of the cryogenic semiconductor structure.

[0026] In one exemplary embodiment of the first aspect, the first gate electrode is shaped as a multi-finger gate. The multi-finger gate may maximize the on / off resistance ratio of the cryogenic semiconductor structure. In one exemplary embodiment of the first aspect, the first gate electrode is made of doped polysilicon. Unlike metal gate electrodes which typically cause a high trap density at metal-oxide interfaces, polysilicon gate electrodes may allow one to achieve the best electron / hole mobilities of 2DEGs / 2DHGs. Furthermore, the other benefits provided by polysilicon are related to CMOS processing, namely: no metals should typically be utilized for the front-end process (there are exceptions due to metal gate electrodes and dielectrics using metal precursors, but these limit the whole processing and require special tricks or additional tools). Additionally, such a polysilicon gate electrode may be efficiently used if the substrate is made of silicon. Since the work-function of the polysilicon gate is slightly different from that of the silicon substrate, the cryogenic semiconductor structure with the near-zero threshold voltage may be implemented, which further contributes to the low-power operation of the cryogenic semiconductor structures at the cryogenic temperatures. Last but not least, such a polysilicon gate may be compatible with self-aligned processes in which the gate doping and the formation of the first and second regions are carried out in a single ion implantation step.

[0027] In one exemplary embodiment of the first aspect, the doped polysilicon has a doping concentration equal to or higher than 1 x 1016cm'3. By using such doping concentrations of the first (polysilicon) gate electrode, it is possible to improve the operation of the cryogenic semiconductor structure at the cryogenic temperatures.

[0028] In one exemplary embodiment of the first aspect, the first gate electrode has a length-to-width ratio less than 0.1. More specifically, the first gate electrode may have a length of about 10 nm, while still having good isolation between the first and second regions, as well as may have a width much larger compared to the length. The maximum operating speed of the cryogenic semiconductor structure is determined by the first gate electrode, which is provided by the above aspect ratio. In one exemplary embodiment of the first aspect, the first gate electrode has at least one transverse through hole filled with a dielectric material of the dielectric layer. By using such a perforated first gate electrode, it is possible to form one or more quantum dots in the channel under the surface portion, thereby making the structure according to the first aspect more flexible in use.

[0029] According to a second aspect, a method for operating the cryogenic semiconductor structure according to the first aspect is provided. The method starts with the step of cooling the cryogenic semiconductor structure to a cryogenic temperature equal to or less than 120 K. Then, the method proceeds to the step of applying a voltage signal to the second gate electrode. The voltage signal has a signal level at which a two-dimensional electron or hole gas is formed under the surface portion where there is no overlap of the surface portion by the first gate electrode. The method further goes on to the step of applying a static or pulsed voltage signal to the first gate electrode. The static or pulsed voltage signal has a signal level selected based on the signal level of the voltage signal applied to the second gate electrode.

[0030] With the method according to the second aspect, it is possible to use the cryogenic semiconductor structure as a switching or memory element at the cryogenic temperature. More specifically, at the cryogenic temperature, single electron effects may be leveraged to enable charge transport between the first and second regions through one or more quantum dots (depending on the configuration of the first gate electrode) formed under the first gate electrode due to the local depletion of the channel under the surface portion between the first and second regions. Said charge transport may take place when the energy level(s) of the quantum dot(s) is(are) aligned with the chemical potential of the 2DEG / 2DHG formed under the second gate electrode on either side of the first gate electrode. For this purpose, the cryogenic semiconductor structure should be tuned, with the aid of the second gate electrode, to an operation point such that even minute changes in the voltage signal applied to the first gate electrode will have dramatic effect on the conductance of the cryogenic semiconductor structure due to the above-indicated energy level alignment.

[0031] Furthermore, if the first gate electrode is purposefully made floating and its doping concentration is selected suitably for the purpose (i.e., the first gate electrode does not have too many free charge carriers at the operation temperature), the voltage signal applied to the second gate electrode will distribute the charge carriers in the first gate electrode such that the structure operation is hysteretic with respect to the operation of the second gate electrode. This may be used to create a fast and potentially durable memory element with very low dissipation. Such a memory element may have a substantially continuous state spectrum, i.e., the conductance between the first and second regions may be varied in multiple small steps, making the structure suitable, for example, for use in neuromorphic computing.

[0032] Other features and advantages of the present disclosure will be apparent upon reading the following detailed description and reviewing the accompanying drawings.

[0033] BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present disclosure is explained below with reference to the accompanying drawings in which:

[0035] FIGs. 1A and IB show schematic views of a cryogenic semiconductor structure according to a first exemplary embodiment, namely: FIG. 1A shows a sectional front view of the cryogenic semiconductor structure, and FIG. IB shows a top view of the cryogenic semiconductor structure;

[0036] FIGs. 2A and 2B schematically show an energy-band diagram of a channel, which may be formed in the cryogenic semiconductor structure according to the first exemplary embodiment, in the absence (FIG. 2A) and presence (FIG. 2B) of charge transport; FIG. 3 shows how a pulsed voltage signal applied to a first gate electrode included in the cryogenic semiconductor structure according to the first exemplary embodiment may affect the conductance of the channel over time;

[0037] FIG. 4 shows how another pulsed voltage signal applied to the first gate electrode may affect the conductance of the channel over time;

[0038] FIGs. 5A and 5B show schematic views of a cryogenic semiconductor structure according to a second exemplary embodiment, namely: FIG. 5A shows a sectional front view of the cryogenic semiconductor structure, and FIG. 5B shows a top view of the cryogenic semiconductor structure;

[0039] FIGs. 6A and 6B show schematic views of a cryogenic semiconductor structure according to a third exemplary embodiment, namely: FIG. 6A shows a sectional front view of the cryogenic semiconductor structure, and FIG. 6B shows a top view of the cryogenic semiconductor structure;

[0040] FIGs. 7A and 7B show schematic views of a cryogenic semiconductor structure according to a fourth exemplary embodiment, namely: FIG. 7A shows a sectional front view of the cryogenic semiconductor structure, and FIG. 7B shows a top view of the cryogenic semiconductor structure;

[0041] FIG. 8 shows a schematic sectional front view of a cryogenic semiconductor structure according to a fifth exemplary embodiment;

[0042] FIG. 9 shows a schematic sectional front view of a cryogenic semiconductor structure according to a sixth exemplary embodiment;

[0043] FIG. 10 shows a schematic sectional front view of a cryogenic semiconductor structure according to a seventh exemplary embodiment;

[0044] FIG. 11 shows a schematic top view of a cryogenic semiconductor structure according to an eighth exemplary embodiment; and

[0045] FIG. 12 shows a schematic top view of a cryogenic semiconductor structure according to a tenth exemplary embodiment.

[0046] DETAILED DESCRIPTION Various embodiments of the present disclosure are further described in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in many other forms and should not be construed as limited to any certain structure or function discussed in the following description. In contrast, these embodiments are provided to make the description of the present disclosure detailed and complete.

[0047] According to the detailed description, it will be apparent to the ones skilled in the art that the scope of the present disclosure encompasses any embodiment thereof, which is disclosed herein, irrespective of whether this embodiment is implemented independently or in concert with any other embodiment of the present disclosure. For example, the cryogenic semiconductor structure and its operation method disclosed herein may be implemented in practice using any numbers of the embodiments provided herein. Furthermore, it should be understood that any embodiment of the present disclosure may be implemented using one or more of the elements presented in the appended claims.

[0048] The word "exemplary" is used herein in the meaning of "used as an illustration". Unless otherwise stated, any embodiment described herein as "exemplary" should not be construed as preferable or having an advantage over other embodiments.

[0049] Any positioning terminology, such as "left", "right", "top", "bottom", "above" "below", "upper", "lower", etc., may be used herein for convenience to describe one element's or feature's relationship to one or more other elements or features in accordance with the figures. It should be apparent that the positioning terminology is intended to encompass different orientations of the apparatus disclosed herein, in addition to the orientation(s) depicted in the figures. As an example, if one imaginatively rotates the apparatus in the figures 90 degrees clockwise, elements or features described as "left" and "right" relative to other elements or features would then be oriented, respectively, "above" and "below" the other elements or features. Therefore, the positioning terminology used herein should not be construed as any limitation of the present disclosure.

[0050] Although the numerative terminology, such as "first", "second", etc., may be used herein to describe various embodiments, elements or features, these embodiments, elements or features should not be limited by this numerative terminology. This numerative terminology is used herein only to distinguish one embodiment, element or feature from another embodiment, element or feature. For example, a first region discussed below could be re-called a second region, and vice versa, without departing from the teachings of the present disclosure.

[0051] The exemplary embodiments disclosed herein provide a technical solution that allows mitigating or even eliminating the drawbacks of the prior art which are mentioned in the description part "Background". In particular, the technical solution disclosed herein relates to a cryogenic (MOSFET-like) semiconductor structure configured for low-dissipation high-speed operation at cryogenic temperatures. The structure is characterized by an overlapping multigate configuration in which a first gate electrode is arranged between a second gate electrode and a conductive channel formed under a surface portion of a dielectric substrate between spaced-apart n-doped and / or p-doped first and second regions. The first gate electrode is embedded in a dielectric layer covering the surface portion, while the second gate electrode may be either provided on the dielectric layer or also embedded in the dielectric layer above the first gate electrode. The first gate electrode is configured to partly overlap the surface portion, while the second gate electrode is configured to (at least partly) overlap the first gate electrode and (at least partly) overlap the surface portion on either side of the first gate electrode.

[0052] In this overlapping multi-gate configuration, the second gate electrode may be used to induce a 2DEG / 2DHG layer under the surface portion on either side of the first gate electrode, while the first gate electrode may be used to form a (local) depletion layer under it (i.e., under the surface portion where there is an overlap of the surface portion by the first gate electrode). The second gate electrode may be at a substantially fixed potential, in which case the first gate electrode may define a switching behavior. All of this may allow the cryogenic semiconductor structure to be used as a switching or memory element at cryogenic temperatures. It should be noted that the cryogenic temperatures used herein may refer to those ranging from 120 K to absolute zero.

[0053] FIGs. 1A and IB show schematic views of a cryogenic semiconductor structure 100 according to a first exemplary embodiment. More specifically, FIG. 1A shows a sectional front view of the cryogenic semiconductor structure 100, and FIG. IB shows a top view of the cryogenic semiconductor structure 100. In the first exemplary embodiment, the structure 100 comprises a substrate 102 comprising a first region 104 and a second region 106 spaced from the first region 104 such that there is a surface portion 108 between the first region 104 and the second region 106. The dielectric substrate 102 may be made of bulk silicon. Each of the first region 104 and the second region 106 may be n-doped and / or p- doped, as well as may have a depth, e.g., equal to 2 nm, 20 nm, 200 nm, or 2000 nm, depending on the substrate 102 and applications of the structure 100. Preferably, the dielectric substrate 102 has a doping concentration less than 5 x 1018cm'3, while each of the first region 104 and the second region 106 has a doping concentration more than 5 x 1018cm'3. As shown in FIG. IB, the surface portion 108 has a length a corresponding to an inter-region spacing or, in other words, the distance between the regions 104 and 106, as well as a width b corresponding to the extension of each of the regions 104 and 106 in the vertical direction.

[0054] The structure 100 further comprises a dielectric layer 110 fully covering the surface portion 108 between the regions 104 and 106, as well as the regions 104 and 106 themselves. The dielectric layer 110 may be made of SiO2, SiN, AI2O3, HfO2, HfSiON, HfSiO, or ZrO2.

[0055] A first gate electrode 112 is embedded in the dielectric layer 110 such that the first gate electrode 112 partly overlaps the surface portion 108 between the regions 104 and 106. The first gate electrode 112 may be made of aluminum, copper, titanium, hafnium, nickel, zirconium, niobium, tungsten, molybdenum, any alloy or combination thereof, or any conducting polymer, conducting co-polymer, or any semiconductor material belonging to groups lll-V of Mendeleev's periodic table (e.g., Ge, Si). For example, the first gate electrode 112 may be made of doped polysilicon with a preferable doping concentration equal to or higher than 1 x 1016cm'3. As shown in FIG. IB, the first gate electrode 112 has a rectangular shape, but this should not be construed as any limitation of the present disclosure - in other embodiments, the first gate electrode 112 may have any other regular or irregular polygonal shape (e.g., triangular, square, trapezoidal, pentagonal, etc.) or any non-polygonal shape (e.g., circular, oval, etc.), depending on applications of the structure 100. Furthermore, the first gate electrode 112 may be shaped such that its length-to-width ratio is less than 0.1.

[0056] In the structure 100, there is also a second gate electrode 114 provided on the dielectric layer 110 such that the second gate electrode 114 fully overlaps the first gate electrode 112 and the surface portion 108 between the regions 104 and 106, as well as partly overlaps each of the regions 104 and 106. The second gate electrode 114 may be made of the same material as the first gate electrode 112, or it may be made of a different material, for example, selected from the group of materials given above when discussing the first gate electrode 112. Again, the rectangular shape of the second gate electrode 114 is shown for illustrative purposes only and should not be construed as any limitation of the present disclosure - in other embodiments, the second gate electrode 114 may have any other regular or irregular polygonal shape (e.g., triangular, square, trapezoidal, pentagonal, etc.) or any non-polygonal shape (e.g., circular, oval, etc.), depending on applications of the structure 100. The only requirement is that the second gate electrode 114 at least partly overlaps the first gate electrode 112, as well as at least partly overlaps the surface portion 108 on either side of the first gate electrode 112. The structure 100 may be obtained by using industry standard silicon / semiconductor fabrication processes. These processes can include, but not limited to, deposition techniques (e.g., Atomic Layer Deposition (ALD), Molecular-Beam Epitaxy (MBE), Chemical Beam Epitaxy (CBE), Metal Organic Chemical Vapor Deposition (MOCVD), Low Pressure CVD (LPCVD), Plasma- Enhanced CVD (PECVD), Ultra-High Vacuum CVD (UHV-CVD), etc.), lithography techniques (e.g., photolithography, Ultraviolet (UV) lithography, Deep Ultraviolet (DUV) lithography, Extreme Ultraviolet (EUV) lithography, Electron-Beam Lithography (EBL), etc.), sputtering techniques (e.g., RF radio sputtering, magnetron sputtering, etc.), etching techniques (e.g., wet etching, reactive ion etching, etc.), doping techniques (e.g., diffusion doping, ion implantation, etc.), or any combination thereof.

[0057] Those skilled in the art would recognize that the structure 100 (as well as other cryogenic semiconductor structures which will be discussed below) may be considered as a MOSFET-like structure, in which the regions 104 and 106 serve as source and drain regions, respectively (or vice versa), and the second gate electrode 114 serves to form the conductive channel therebetween under the surface portion 108. At the same time, the main distinction consists in the presence of the first gate electrode 112 between the second gate electrode 114 and the conductive channel. To the best of the authors' knowledge, such an overlapping multi-gate configuration is not known in the prior art.

[0058] The operational principle of the structure 100 is as follows.

[0059] At first, the structure 100 is cooled to a cryogenic temperature equal to or less than 120 K, depending on applications of the structure 100. Then, a voltage signal V2 is applied to the second gate electrode 114. The voltage signal V2 should have a signal level at which a 2DEG / 2DHG is formed under the surface portion 108 where there is no overlap of the surface portion 108 by the first gate electrode 112. Subsequently, a voltage signal Vi is applied to the first gate electrode 112. The voltage signal Vi may be static or pulsed, depending on applications of the structure 100. The structure 100 is operated by tuning the voltage signal Vi. At the same time, the voltage signal V2 should additionally be set such that the voltage signal Vi is close to 0 V for both n-type and p-type operation modes of the structure 100. This is limited ultimately by thermal broadening only. It is well-known that the dynamic power dissipation of a MOSFET is as follows: P oc V2f, where V is the supply voltage and f is the operating frequency. Given this relationship, it is crucial that the supply voltage be as small as possible. In this case, the supply voltage may be represented by Vi, which may be set close to 0 V by properly tuning V2.

[0060] FIGs. 2A and 2B schematically show an energy-band diagram 200 of the conductive channel, which may be formed in the structure 100, in the absence (FIG. 2A) and presence (FIG. 2B) of charge transport. By applying V2, a 2DEG / 2DHG 202 is formed, on either side of the first gate electrode 112, under those subportions of the surface portion 108 which are overlapped by the second gate electrode 114. By applying Vi, one or more quantum dots (i.e., one or more local potential wells where charge carriers may be accumulated) 204 are formed under that sub-portion of the surface portion 108 which is overlapped by the first gate electrode 112. The formation of the quantum dot(s) may depend, for example, on surface defects, etc. At the same time, their number may be adjusted by properly engineering the first gate electrode 112. If there is no alignment of the chemical potential of the 2DEGs / 2DHGs 202 with any discrete level of the quantum dot(s) 204, there will be no charge transport between the 2DEGs / 2DHGs 204 through the quantum dot(s) 204 (see the crossed-out arrow in FIG. 2A). If the chemical potential of each of 2DEGs / 2DHGs 202 is aligned (by properly selecting Vi) with any discrete level of the quantum dot(s) 204, charge transport will take place (see the arrows in FIG. 2B).

[0061] FIG. 3 shows how the pulsed voltage signal Vi applied to the first gate electrode 112 included in the structure 100 may affect the conductance of the channel over time. As follows from FIG. 3, Vi may be represented by positive and negative pulses in an alternating sequence. The pulses may have an amplitude of about few millivolts. If the signal V2 is a static voltage signal, the voltage pulses of Vi may be used to distribute charges in different interfaces, in the dielectric materials of the structure 100, as well as in other weakly conducting regions of the structure 100. In this case, Vi should have a signal level at which there is no charge transport between the second gate electrode 114 and the first gate electrode 112. In other words, the structure 100 may function as a "macroscopic" memory element at the cryogenic temperature without tunneling between the first gate electrode 112 and the second gate electrode 114. It is assumed that this type of memory would be semi-volatile, i.e., the memory element will have finite retention time but potentially may keep information relatively long time.

[0062] FIG. 4 shows how another pulsed voltage signal Vi applied to the first gate electrode 112 may affect the conductance of the channel over time. As follows from FIG. 4, Vi may also be represented by a sequence of positive pulses having an amplitude of about few millivolts. By using this Vi, the structure 100 may function as a memory element that may have an almost continuous state spectrum, i.e., the conductance between the first and second regions 104 and 106 may change in multiple small steps (see time instants ti and t2 in FIG. 4), making the memory element suitable, for example, for use in neuromorphic computing.

[0063] FIGs. 5A and 5B show schematic views of a cryogenic semiconductor structure 500 according to a second exemplary embodiment. More specifically, FIG. 5A shows a sectional front view of the cryogenic semiconductor structure 500, and FIG. 5B shows a top view of the cryogenic semiconductor structure 500. In the second exemplary embodiment, the structure 500 comprises a substrate 502 comprising a first region 504 and a second region 506 spaced from the first region 504 such that there is a surface portion 508 between the first region 504 and the second region 506. Similar to the surface portion 108, the surface portion 508 is defined by the parameters a and b (see FIG. 5B). The dielectric substrate 502 may be the same as the dielectric substrate 102, and each of the regions 504 and 506 may similarly (like the regions 104 and 106) be n- and / or p-doped. The structure 500 further comprises a dielectric layer 510 which may be implemented in the same manner as the dielectric layer 110, i.e., may be made of the same dielectric material and may fully cover the surface portion 508 and the regions 504 and 506.

[0064] The structure 500 differs from the structure 100 by the overlapping multi-gate configuration used therein, which is constituted by a first gate electrode 512 and a second gate electrode 514. As shown from FIG. 5B, the first gate electrode 512 embedded in the dielectric layer 510 and partly overlapping the surface portion 508 is shaped as a meander extending in the vertical direction. In other embodiments, the first gate electrode 512 may be implemented as any multi-finger gate (the number of fingers may vary depending on applications of the structure 500) or may even have any curved shape (e.g., circular, oval, sawlike, wavy, etc.). The second gate electrode 514 is provided on the dielectric layer 510 such that it fully overlaps not only the surface portion 508 and the first gate electrode 512, but also each of the regions 504 and 506. At the same time, the first and second gate electrodes 512 and 514 may be made of the same materials as the first and second gate electrodes 112 and 114, respectively, as well as the second gate electrode 514 may be shaped in a similar manner as the second gate electrode 114.

[0065] The operational principle of the structure 500 is similar to that of the structure 100. More specifically, the voltage signals Vi and V2 may be applied to the first gate electrode 512 and the second gate electrode 514, respectively, in the same manner as discussed above with respect to the structure 100.

[0066] FIGs. 6A and 6B show schematic views of a cryogenic semiconductor structure 600 according to a third exemplary embodiment. More specifically, FIG. 6A shows a sectional front view of the cryogenic semiconductor structure 600, and FIG. 6B shows a top view of the cryogenic semiconductor structure 600. In the third exemplary embodiment, the structure 600 comprises a substrate 602 comprising a first region 604 and a second region 606 spaced from the first region 604 such that there is a surface portion 608 between the first region 604 and the second region 606. Similar to the surface portion 108, the surface portion 608 is defined by the parameters a and b (see FIG. 6B). The dielectric substrate 602 may be the same as the dielectric substrate 102, and each of the regions 604 and 606 may similarly (like the regions 104 and 106) be n- and / or p-doped. The structure 600 further comprises a dielectric layer 610 which may be implemented in the same manner as the dielectric layer 110, i.e., may be made of the same dielectric material and may fully cover the surface portion 608 and the regions 604 and 606.

[0067] The structure 600 differs from the structures 100 and 500 by the overlapping multi-gate configuration used therein, which is constituted by a first gate electrode 612 and a second gate electrode. As shown from FIGs. 6A and 6B, the first gate electrode 612 embedded in the dielectric layer 610 and partly overlapping the surface portion 608 is implemented in the same manner as the first gate electrode 112. However, the second gate electrode comprises two gate sub-electrodes 614-1 and 614-2 which are both provided on the dielectric layer 610 such that the first (right) gate sub-electrode 614-1 partly overlaps the right edge portion of the first gate electrode 612 and the surface portion 608 on the right side of the first gate electrode 612, while the second (left) gate subelectrode 614-2 partly overlaps the left edge portion of the first gate electrode 612 and the surface portion 608 on the left side of the first gate electrode 612. Thus, the middle portion of the first gate electrode 612 remains non-overlapped by the gate sub-electrodes 614-1 and 614-2. It should be again noted that the shape of the first gate electrode 612 and each of the gate sub-electrodes 614-1 and 614-2 may vary depending on applications of the structure 600. For example, the first gate electrode 612 may be implemented as the first gate electrode 512 (i.e., as a meander), or the first gate electrode 612 and each of the gate subelectrodes 614-1 and 614-2 may have any other (identical or different) regular or irregular polygonal or curved shapes. At the same time, the first gate electrode 612 and the second gate electrode of the structure 600 may be made of the same materials as the first and second gate electrodes 112 and 114, respectively. The operational principle of the structure 600 is similar to that of the structure 100. More specifically, the voltage signal Vi should be applied to the first gate electrode 612, and the voltage signal V2 should be applied to each of the gate sub-electrodes 614-1 and 614-2. At the same time, the voltage signal V2 may be configured in the same manner as discussed above with reference to FIGs 3 and 4.

[0068] FIGs. 7A and 7B show schematic views of a cryogenic semiconductor structure 700 according to a fourth exemplary embodiment. More specifically, FIG. 7A shows a sectional front view of the cryogenic semiconductor structure 700, and FIG. 7B shows a top view of the cryogenic semiconductor structure 700. In the fourth exemplary embodiment, the structure 700 comprises a substrate 702 comprising a first region 704 and a second region 706 spaced from the first region 704 such that there is a surface portion 708 between the first region 704 and the second region 706. Similar to the surface portion 108, the surface portion 708 is defined by the parameters a and b (see FIG. 7B). The dielectric substrate 702 may be the same as the dielectric substrate 102, and each of the regions 704 and 706 may similarly (like the regions 104 and 106) be n- and / or p-doped. The structure 700 further comprises a dielectric layer 710 which may be implemented in the same manner as the dielectric layer 110, i.e., may be made of the same dielectric material and may fully cover the surface portion 708 and the regions 704 and 706.

[0069] The structure 700 differs from the structures 100, 500 and 600 by the overlapping multi-gate configuration used therein, which is constituted by a first gate electrode and a second gate electrode. As shown from FIGs. 7A and 7B, the first gate electrode comprises two gate sub-electrodes 712-1 and 712-2 which are embedded in the dielectric layer 710 parallel to each other and partly overlap different sub-portions of the surface portion 708. The second gate electrode comprises three gate sub-electrodes 714-1, 714-2 and 714-3 which are all provided on the dielectric layer 710. The first (right) gate sub-electrode 714-1 overlaps the right edge portion of the first (right) gate sub-electrode 712-1 and the surface portion 708 on the right side of the first gate sub-electrode 712-1. The second (middle) gate sub-electrode 714-2 overlaps the left edge portion of the first gate sub-electrode 712-1 and the right edge portion of the second (left) gate sub-electrode 712-2, as well as overlaps the surface portion 708 between the gate sub-electrodes 712-1 and 712-2. The third (left) gate sub-electrode 714-3 overlaps the left edge portion of the second gate sub-electrode 712-2 and the surface portion 608 on the left side of the first gate sub-electrode 712-2. Thus, the middle portions of the gate sub-electrodes 712-1 and 712-2 remain nonoverlapped by the gate sub-electrodes 714-1, 714-2 and 714-3. It should be again noted that the shape of all the gate sub-electrodes in the structure 700 may vary depending on applications of the structure 700. For example, each of the gate sub-electrodes 712-1 and 712-2 may be implemented as the first gate electrode 512 (i.e., as a meander), or all the gate sub-electrodes shown in the structure 700 may have any other (identical or different) regular or irregular polygonal or curved shapes. At the same time, the first gate electrode and the second gate electrode of the structure 700 may be made of the same materials as the first and second gate electrodes 112 and 114, respectively.

[0070] The operational principle of the structure 700 is similar to that of the structure 100. More specifically, the voltage signal Vi should be applied to each of the gate sub-electrodes 712-1 and 712-2, and the voltage signal V2 should be applied to each of the gate sub-electrodes 714-1, 714-2 and 714-3. At the same time, the voltage signal V2 may be configured in the same manner as discussed above with reference to FIGs 3 and 4. It should be also noted that the presence of the two gate sub-electrodes 712-1 and 712-2 allows one to form two separate depletion regions in the channel formed under the surface portion 708. In each of these depletion regions, there will be one or more quantum dots (each like the quantum dot(s) 204) in the energy-band diagram of the channel, with the quantum dots being separated by the 2DEG / 2DHG formed under each of the gate sub-electrodes 714-1, 714-2 and 714-3. It should be also noted that the number of the gate sub-electrodes used in the first and second gate electrodes of the structure 700 should not be construed as any limitation of the present disclosure - in any other embodiments, the first gate electrode of the structure 700 may comprise more than two gate sub-electrodes, while the second gate electrode of the structure 700 may comprise more than three gate sub-electrodes.

[0071] FIG. 8 shows a schematic sectional front view of a cryogenic semiconductor structure 800 according to a fifth exemplary embodiment. In the fifth exemplary embodiment, the structure 800 comprises a substrate 802 comprising a first region 804 and a second region 806 spaced from the first region 804 such that there is a surface portion 808 between the first region 804 and the second region 806. The surface portion 808 may be defined by the same parameters a and b as the surface portion 108. The dielectric substrate 802 may be the same as the dielectric substrate 102, and each of the regions 804 and 806 may similarly (like the regions 104 and 106) be n- and / or p-doped.

[0072] The structure 800 differs from the structures 100, 500-700 by a dielectric layer 810 fully covering the surface portion 808 and the regions 804 and 806. The dielectric layer 810 may be made of the same dielectric material as the dielectric layer 110, but it has a non-unform cross-section with thinner edge portions and a thicker middle portion. This non-uniform cross-section of the dielectric layer 810, in turn, results in a different overlapping multi-gate configuration compared to those discussed above. More specifically, the overlapping multi-gate configuration of the structure 800 is constituted by a first gate electrode 812 and a second gate electrode 814. The first gate electrode 812 embedded in the middle portion of the dielectric layer 810 and partly overlapping the surface portion 808 may be implemented in the same manner as the first gate electrode 112 or the first gate electrode 512. The second gate electrode 814 is provided on the dielectric layer 810, and fully overlaps the first gate electrode 812 and the surface portion 808 and partly overlaps each of the regions 804 and 806. As can be seen, the second gate electrode 814 has an inverted U-like shape, which is caused by the above-indicated non-uniform cross-section of the dielectric layer

[0073] 810.

[0074] The operational principle of the structure 800 is similar to that of the structure 100. More specifically, the voltage signals Vi and V2 may be applied to the first gate electrode 812 and the second gate electrode 814, respectively, in the same manner as discussed above with respect to the structure 100.

[0075] FIG. 9 shows a schematic sectional front view of a cryogenic semiconductor structure 900 according to a sixth exemplary embodiment. In the sixth exemplary embodiment, the structure 900 comprises a substrate 902 comprising a first region 904 and a second region 906 spaced from the first region 904 such that there is a surface portion between the first region 904 and the second region 906. The surface portion may be defined by the same parameters a and b as the surface portion 108. The dielectric substrate 902 may be made of the same material as the dielectric substrate 102, and each of the regions 904 and 906 may similarly (like the regions 104 and 106) be n- and / or p-doped. Unlike the substrates discussed above, the substrate 902 comprises a first doping layer 908 provided under the surface portion between the regions 904 and 906, as well as a second doping layer 910 provided under the first doping layer 908. The first doping layer 908 may be n-doped or p-doped with a doping concentration such that it is non-conductive at the operation (cryogenic) temperature of the structure 900. The second doping layer 910 may also be n-doped or p-doped with a doping concentration such that the first and second doping layers 908 and 910 form a p-n junction. As can be seen, the second doping layer 910 may (at least partly) surround each of the regions 904 and 910 from below. It should be also noted that the second doping layer 910 is optional in the sixth exemplary embodiment.

[0076] In one other embodiment, the substrate 902 may be made as a Silicon-On-lnsulator (SOI) wafer comprising a bulk silicon layer, an insulating layer provided on the bulk silicon layer, and a crystalline silicon layer provided on the insulating layer. In this embodiment, the crystalline silicon layer is assumed to comprise the regions 904 and 906. Furthermore, the crystalline silicon layer may have a doping concentration less than 5 x 1018cm'3, and each of the regions 902 and 904 may have a doping concentration more than 5 x 1018cm'3. Optionally, the SOI wafer may comprise doping sub-layers like the doping layers 908 and 910 in its crystalline silicon layer. That is, a first doping sub-layer like the doping layer 908 may be provided between the regions 904 and 906, while a second doping sub-layer like the doping layer 910 may be provided under the first doping sublayer and may at least partly surround each of the regions 904 and 906 from below.

[0077] As follows from FIG. 9, the structure 900 further comprises a dielectric layer 912 which is implemented in the same manner as the dielectric layer 910. For this reason, the overlapping multi-gate configuration used in the structure 900 is similar to that used in the structure 800. More specifically, a first gate electrode 914 is embedded in the (thicker) middle portion of the dielectric layer 912, and a second gate electrode 916 having an inverted U-like shape is provided on the dielectric layer 912.

[0078] The operational principle of the structure 900 is similar to that of the structure 100. More specifically, the voltage signals Vi and V2 may be applied to the first gate electrode 912 and the second gate electrode 914, respectively, in the same manner as discussed above with respect to the structure 100.

[0079] FIG. 10 shows a schematic sectional front view of a cryogenic semiconductor structure 1000 according to a seventh exemplary embodiment. In the seventh exemplary embodiment, the structure 1000 comprises a substrate 1002 comprising a first region 1004 and a second region 1006 spaced from the first region 1004 such that there is a surface portion 1008 between the first region 1004 and the second region 1006. Similar to the surface portion 108, the surface portion 1008 may be defined by the same parameters a and b. The dielectric substrate 1002 may be the same as the dielectric substrate 102, and each of the regions 1004 and 1006 may similarly (like the regions 104 and 106) be n- and / or p-doped. The structure 1000 further comprises a dielectric layer 1010 which may be implemented in the same manner as the dielectric layer 110, i.e., may be made of the same dielectric material and may fully cover the surface portion 1008 and the regions 1004 and 1006.

[0080] The structure 1000 differs from the structures 100, 500-900 by the overlapping multi-gate configuration used therein, which is constituted by a first gate electrode 1012 and a second gate electrode 1014. The first gate electrode 1012 embedded in the dielectric layer 1010 and partly overlapping the surface portion 1008 may be implemented in the same manner as the first gate electrode 112 or the first gate electrode 512. However, unlike the second gate electrodes discussed above, the second gate electrode 1014 is also embedded in the dielectric layer 1010 above the first gate electrode 1012. Furthermore, the second gate electrode 1014 may not necessarily fully overlap the surface portion 1008 on either side of the first gate electrode 1012. In other words, the surface portion 1008 may have sub-portions of (different or equal) lengths gi and g2 which are not overlapped by the second gate electrode 1014. At the same time, the first and second gate electrodes 1012 and 1014 may be made of the same materials as the first and second gate electrodes 112 and 114, respectively.

[0081] The operational principle of the structure 1000 is similar to that of the structure 100. More specifically, the voltage signals Vi and V2 may be applied to the first gate electrode 1012 and the second gate electrode 1014, respectively, in the same manner as discussed above with respect to the structure 100.

[0082] FIG. 11 shows a schematic top view of a cryogenic semiconductor structure 1100 according to a ninth exemplary embodiment. In the ninth exemplary embodiment, the structure 1100 comprises a substrate (not shown) comprising a first region 1102 and a second region 1104 spaced from the first region 1102 such that there is a surface portion between the first region 1102 and the second region 1104. Similar to the surface portion 108, the surface portion in the structure 1100 may be defined by the same parameters a and b. The dielectric substrate of the structure 1100 may be the same as the dielectric substrate 102, and each of the regions 1102 and 1104 may similarly (like the regions 104 and 106) be n- and / or p-doped. The structure 1100 further comprises a dielectric layer 1106 which may be implemented in the same manner as the dielectric layer 110, i.e., may be made of the same dielectric material and may fully cover the surface portion and the regions 1102 and 1104. The overlapping multi-gate configuration used in the structure 1100 is similar to that used in the structure 100. That is, the structure 1100 comprises a first gate electrode 1108 embedded in the dielectric layer 1106 and partly overlapping the surface portion between the regions 1102 and 1104, as well as a second gate electrode 1110 provided on the dielectric layer 1106 and overlapping the surface portion and the first gate electrode 1108. At the same time, unlike the second gate electrode 114, the second gate electrode 1110 has a transverse through hole 1112 which is arranged and shaped such that the second gate electrode 1110 overlaps only the edge portions of the first gate electrode 1108 and leaves the middle portion of the first gate electrode 1108 non-overlapped. Those skilled in the art would recognize that the rectangular shape of the hole 1112 in FIG. 11 should not be construed as any limitation of the present disclosure and, in other embodiments, may be replaced with any other regular or irregular polygonal shape or any other curved shape (e.g., circular, oval, etc.), depending on the shape of the first gate electrode 1108 and / or applications of the structure 1110. Furthermore, the shape of the hole 1112 should not necessarily repeat the shape of the first gate electrode 1108 and / or the shape of the second gate electrode 1110. In some other embodiments, the second gate electrode 1110 may be perforated such that it comprises multiple transverse through holes; in these embodiments, the holes may be identically or differently shaped and sized, depending on the shape of the first electrode gate 1108 and applications of the structure 1100.

[0083] The operational principle of the structure 1100 is similar to that of the structure 100. More specifically, the voltage signals Vi and V2 may be applied to the first gate electrode 1108 and the second gate electrode 1110, respectively, in the same manner as discussed above with respect to the structure 100. FIG. 12 shows a schematic top view of a cryogenic semiconductor structure 1200 according to a tenth exemplary embodiment. In the tenth exemplary embodiment, the structure 1200 comprises a substrate (not shown) comprising a first region 1202 and a second region 1204 spaced from the first region 1202 such that there is a surface portion between the first region 1202 and the second region 1204. Similar to the surface portion 108, the surface portion in the structure 1200 may be defined by the same parameters a and b. The dielectric substrate of the structure 1200 may be the same as the dielectric substrate 102, and each of the regions 1202 and 1204 may similarly (like the regions 104 and 106) be n- and / or p-doped. The structure 1200 further comprises a dielectric layer 1206 which may be implemented in the same manner as the dielectric layer 110, i.e., may be made of the same dielectric material and may fully cover the surface portion and the regions 1202 and 1204.

[0084] The overlapping multi-gate configuration used in the structure 1200 is similar to that used in the structure 100. That is, the structure 1200 comprises a first gate electrode 1208 embedded in the dielectric layer 1206 and partly overlapping the surface portion between the regions 1202 and 1204, as well as a second gate electrode 1210 provided on the dielectric layer 1206 and overlapping the surface portion and the first gate electrode 1208. At the same time, unlike the first gate electrode 112, the first gate electrode 1208 is perforated, i.e., it has four transverse through holes 1212 each at least partly filled with the dielectric material of the dielectric layer 1206. Those skilled in the art would recognize that the circular shape of the holes 1212 in FIG. 12 should not be construed as any limitation of the present disclosure and, in other embodiments, may be replaced with any other regular or irregular polygonal shape or any other curved shape (e.g., circular, oval, etc.), depending on the shape of the first gate electrode 1208 and / or applications of the structure 1210. The same is true for the number and arrangement of the holes 1212 - in other embodiments, the first gate electrode 1208 may comprise less than or more than four through holes that may be aligned in one direction (e.g., diagonal, horizontal, vertical) or arranged randomly or in accordance with a certain pattern (e.g., a staggered pattern). In some other embodiments, the first gate electrode 1208 may be perforated such that it comprises identically or differently shaped and sized transverse through holes.

[0085] The operational principle of the structure 1200 is similar to that of the structure 100. More specifically, the voltage signals Vi and V2 may be applied to the first gate electrode 1208 and the second gate electrode 1210, respectively, in the same manner as discussed above with respect to the structure 100. In this case, the electric field from the second gate electrode 1210 may pass through the holes 1212 of the first gate electrode 1208, thereby resulting in the formation of quantum dots in the channel formed under the surface portion between the regions 1202 and 1204.

[0086] Although the exemplary embodiments of the present disclosure are described herein, it should be noted that various changes and modifications could be made in these embodiments, without departing from the scope of legal protection which is defined by the appended claims. In the appended claims, the word "comprising" does not exclude other elements or operations, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS1. A cryogenic semiconductor structure comprising: a substrate comprising a first region and a second region spaced from the first region such that there is a surface portion between the first region and the second region, each of the first region and the second region being n-doped and / or p-doped; a dielectric layer covering the surface portion between the first region and the second region; a first gate electrode embedded in the dielectric layer such that the first gate electrode partly overlaps the surface portion between the first region and the second region; and a second gate electrode embedded in or provided on the dielectric layer such that the second gate electrode at least partly overlaps the first gate electrode and at least partly overlaps the surface portion on either side of the first gate electrode.

2. The cryogenic semiconductor structure of claim 1, wherein the substrate is made of bulk silicon and has a doping concentration less than 5 x 1018cm'3, and wherein each of the first region and the second region has a doping concentration more than 5 x 1018cm'3.

3. The cryogenic semiconductor structure of claim 2, wherein the substrate further comprises a first layer between the first region and the second region, the first layer being n-doped or p-doped with a doping concentration such that the first layer is non-conductive at an operation temperature of the cryogenic semiconductor structure.

4. The cryogenic semiconductor structure of claim 3, wherein the substrate further comprises a second layer provided under the first layer, the second layer being n-doped or p-doped with a doping concentration such that the first layer and the second layer form a p-n junction.

5. The cryogenic semiconductor structure of claim 4, wherein the second layer at least partly surrounds each of the first region and the second region from below.

6. The cryogenic semiconductor structure of claim 1, wherein the substrate is made as a Silicon-On-lnsulator (SOI) wafer comprising: a bulk silicon layer; an insulating layer provided on the bulk silicon layer; and a crystalline silicon layer provided on the insulating layer, the crystalline silicon layer comprising the first region and the second region, the crystalline silicon layer having a doping concentration less than 5 x 1018cm'3, and each of the first region and the second region having a doping concentration more than 5 x 1018cm'3.

7. The cryogenic semiconductor structure of claim 6, wherein the crystalline silicon layer further comprises a first sub-layer between the first region and the second region, the first sub-layer being n-doped or p-doped with a doping concentration such that the first sub-layer is non-conductive at an operation temperature of the cryogenic semiconductor structure.

8. The cryogenic semiconductor structure of claim 7, wherein the crystalline silicon layer further comprises a second sub-layer provided under the first sub-layer, the second sub-layer being n-doped or p-doped with a doping concentration such that the first sub-layer and the second sub-layer form a p-n junction.

9. The cryogenic semiconductor structure of claim 8, wherein the second sub-layer at least partly surrounds each of the first region and the second region from below.

10. The cryogenic semiconductor structure of any one of claim 1 to 9, wherein the dielectric layer is made of SiO2, SiN, AI2O3, HfO2, HfSiON, HfSiO, or ZrO2.

11. The cryogenic semiconductor structure of any one of claims 1 to 10, wherein the first gate electrode has a middle portion and at least one edge portion surrounding the middle portion, and wherein the second gate is shaped to overlap each of the at least one edge portion of the first gate electrode and leave the middle portion of the first gate electrode nonoverlapped.

12. The cryogenic semiconductor structure of any one of claims 1 to 11, wherein the first gate electrode has a curved shape.

13. The cryogenic semiconductor structure of claim 12, wherein the first gate electrode is shaped as a multi-finger gate.

14. The cryogenic semiconductor structure of any one of claims 1 to 13, wherein the first gate electrode is made of doped polysilicon.

15. The cryogenic semiconductor structure of claim 14, wherein the doped polysilicon has a doping concentration equal to or higher than 1 x 101616. The cryogenic semiconductor structure of any one of claims 1 to 15, wherein the first gate electrode has a length-to-width ratio less than 0.1.

17. The cryogenic semiconductor structure of any one of claims 1 to 16, wherein the first gate electrode has at least one transverse through hole, each of the at least one transverse through hole being at least partly filled with a dielectric material of the dielectric layer.

18. A method for operating the cryogenic semiconductor structure according to any one of claims 1 to 17, comprising: cooling the cryogenic semiconductor structure to a cryogenic temperature equal to or less than 120 K; applying a voltage signal to the second gate electrode, the voltage signal having a signal level at which a two-dimensional electron or hole gas is formed under the surface portion where there is no overlap of the surface portion by the first gate electrode; and applying a static or pulsed voltage signal to the first gate electrode, the static or pulsed voltage signal having a signal level selected based on the signal level of the voltage signal applied to the second gate electrode.

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