Semiconductor assembly with a first semiconductor element
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- SIEMENS AG
- Filing Date
- 2024-09-05
- Publication Date
- 2026-05-27
AI Technical Summary
Existing semiconductor arrangements face reliability issues due to the failure of wiring elements under load, which can lead to the degradation of semiconductor elements.
A semiconductor arrangement with a first substrate having electrically isolated line sections, where the first semiconductor element is connected to the first substrate metallization, and additional wiring elements connect the semiconductor element to a second substrate metallization, which is electrically isolated from the first substrate metallization, thereby distributing current asymetrically and enhancing connection robustness.
The described semiconductor arrangement significantly reduces the likelihood of wiring element failure under load, enhancing the reliability and extending the lifespan of the semiconductor arrangement by counteracting shear forces through asymmetrical current flow and additional connections.
Smart Images
Figure EP2024074837_01052025_PF_FP_ABST
Abstract
Description
[0001] Description
[0002] Semiconductor arrangement with a first semiconductor element
[0003] The invention relates to a semiconductor device comprising a first semiconductor element, a first substrate, a second substrate and at least one wiring element.
[0004] Furthermore, the invention relates to a power converter with at least one such semiconductor arrangement.
[0005] Furthermore, the invention relates to a method for producing a semiconductor device with a first semiconductor element, a first substrate, a second substrate and at least one wiring element.
[0006] Such a semiconductor arrangement is generally used in a power converter. A power converter can be, for example, a rectifier, an inverter, a converter or a DC-DC converter. The semiconductor elements used in the semiconductor module include transistors, triacs, thyristors or diodes. Transistors are designed, for example, as insulated-gate bipolar transistors (IGBTs), field-effect transistors or bipolar transistors. The semiconductor elements of a semiconductor arrangement are usually contacted via wiring elements on a substrate. Such wiring elements can include, among other things, bond wires and / or bond strips. In particular, load contacts of a semiconductor element, including an emitter contact of an IGBT, are usually contacted with a plurality of wiring elements on the substrate.
[0007] The published patent application EP 4 128 337 A1 describes a power module with at least two power units, each comprising at least one power semiconductor and a substrate. In order to reduce the required area of the power module and improve heat dissipation, it is proposed that the respective at least one power semiconductor be connected, in particular in a materially bonded manner, to the respective substrate, wherein the substrates of the at least two power units are each directly bonded to a surface of a common heat sink.
[0008] The scientific publication "Electro-thermo-mechanical analyses on silver sintered IGBT-module reliability in power cycling" , R . Dudek et al . , 2015 16th International Conference on Thermal , Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems , 2015 describes new requirements for the thermomechanical design of sintered silver joints . The focus is on new requirements for the thermomechanical design of sintered silver joints .
[0009] During operation of the semiconductor devices, wiring elements can detach from the load contact, leading to failure of the semiconductor device. More robust wiring leads to improved reliability of the semiconductor device.
[0010] Against this background, the object of the present invention is to provide a semiconductor device which has improved reliability.
[0011] The object is achieved according to the invention by a semiconductor arrangement with a first semiconductor element, a first substrate, a second substrate and at least one wiring element, wherein the first substrate has a first substrate metallization with line sections arranged electrically insulated from one another, wherein the first semiconductor element and the second substrate are connected, in particular materially, to a first line section of the first substrate metallization, wherein the second substrate has a second substrate metallization on a side facing away from the first substrate, which is arranged electrically insulated from the first line section of the first substrate metallization via a second dielectric material layer, wherein the first semiconductor element has a contact surface on a side facing away from the first substrate, wherein the contact surface is connected to at least one wiring element,wherein the at least one wiring element has a first connecting section which connects the contact surface to a second line section of the first substrate metallization arranged electrically insulated from the first line section, and a second connecting section which connects the contact surface to the second substrate metallization of the second substrate, wherein the second substrate metallization of the second substrate is arranged open-circuit.,
[0012] Furthermore, the object is achieved according to the invention by a power converter with at least one such semiconductor arrangement.
[0013] Furthermore, the object is achieved according to the invention by a method for producing a semiconductor arrangement with a first semiconductor element, a first substrate, a second substrate and at least one wiring element, wherein the first substrate has a first substrate metallization with line sections arranged electrically insulated from one another, wherein the first semiconductor element and the second substrate are connected, in particular materially, to a first line section of the first substrate metallization, wherein the second substrate has a second substrate metallization on a side facing away from the first substrate, which second substrate metallization is arranged electrically insulated from the first line section of the first substrate metallization via a second dielectric material layer, wherein the first semiconductor element has a contact surface on a side facing away from the first substrate,wherein the contact surface is connected to at least one wiring element, wherein the at least one wiring element has a first connecting section, via which the contact surface is connected to a second line section of the first substrate metallization arranged electrically insulated from the first line section, and a second connecting section, via which the contact surface is connected to the second substrate metallization of the second substrate.
[0014] The advantages and preferred embodiments listed below with regard to the semiconductor device can be transferred analogously to the power converter and the method.
[0015] The invention is based on the idea of improving the reliability of a semiconductor device by significantly reducing the probability of a failure during operation of the semiconductor device due to wiring elements being detached from a first semiconductor element. Such a semiconductor device has a first substrate with a first substrate metallization. The first substrate can be designed, among other things, as a DCB (Direct Copper Bonded) substrate. The first substrate metallization is structured, i.e. it has line sections arranged so as to be electrically insulated from one another. The first semiconductor element is connected, in particular in a material-to-material connection, to a first line section of the first substrate metallization. The material-to-material connection is produced, for example, by soldering, sintering or adhesion.Furthermore, the semiconductor element has a contact surface on a side facing away from the first substrate, which contact surface is connected to the first substrate via at least one wiring element. For example, the first semiconductor element is designed as an IGBT, the collector side of which is soldered or sintered onto the first conduction section of the first substrate metallization, while the emitter side of which is connected to the substrate via the at least one wiring element.
[0016] The at least one wiring element is designed, for example, as a bonding wire or bonding strip, wherein the connection between the substrate and the contact surface of the semiconductor element can be established in particular by ultrasonic bonding connections. The at least one wiring element comprises a first connecting section which establishes a connection between the contact surface and a second line section of the first substrate metallization. If current, in particular load current, flows through the at least one wiring element, a shearing force acts on connections, in particular ultrasonic bonding connections, between the contact surface of the first semiconductor element and the wiring element.
[0017] In order to counteract such a shear force, the at least one wiring element comprises a second connecting section which connects the contact surface to a second substrate which is connected, in particular in a materially bonded manner, to the first line section of the first substrate metallization. The second substrate has, on a side facing away from the first substrate, a second substrate metallization to which the second connecting section of the wiring element is connected, wherein the second substrate metallization is arranged electrically insulated from the first line section of the first substrate metallization via a second dielectric material layer. The second dielectric material layer can contain, among other things, a ceramic material, in particular aluminum nitride or aluminum oxide, or an organic material, in particular a polymer.
[0018] Thus, during operation of the semiconductor arrangement, the first connecting section and the second connecting section have an asymmetrical current flow, wherein a current from the semiconductor arrangement flows at least predominantly, in particular substantially exclusively, via the first connecting section of the at least one wiring element. Due to the additional connection of the at least one wiring element via the second connecting section to the second substrate metallization of the second substrate, which is also called "overbonding", a counterforce counteracts the shear force, such that the connection of the at least one wiring element to the contact surface is more robust, in particular under load, which has a positive effect on the reliability of the semiconductor arrangement and extends its service life.Due to the second dielectric material layer, which electrically insulates the second substrate metallization of the second substrate from the first substrate metallization of the first substrate, the first substrate metallization of the first substrate is not noticeably influenced in its electrical properties, in particular in comparison to a bonding island, so that, for example, a current, in particular load current, of the first semiconductor element can flow essentially unhindered, which likewise has a positive effect on the reliability of the semiconductor arrangement.
[0019] The second substrate metallization of the second substrate is arranged in an open-circuit configuration. An open-circuit configuration of the second substrate metallization means that, apart from the at least one wiring element, it is not electrically connected to any other component. In this way, optimal robustness of the connections between the at least one wiring element and the contact surface is achieved, particularly under load.
[0020] A further embodiment provides that the second substrate is arranged on the first conduction section of the first substrate in such a way that, during operation of the semiconductor device, a current in the first conduction section of the first substrate flows at least partially beneath the second substrate. Thus, more cross-sectional area is available for the current flow, which has a positive effect on the reliability of the semiconductor device. Furthermore, such an arrangement saves space.
[0021] A further embodiment provides that the current flowing beneath the second substrate is a load current of the first semiconductor element. Especially for load currents, a sufficiently large cross-sectional area of the conductor is an important factor for achieving low series resistances, so that semiconductor elements are driven evenly, leading to improved reliability of the semiconductor device.
[0022] A further embodiment provides that the second substrate lies flat on the first line section of the first substrate metallization. In particular, the second substrate is connected flat to the first line section of the first substrate metallization. Such a flat connection is robust, which has a positive effect on the reliability of the semiconductor device.
[0023] A further embodiment provides that the first dielectric material layer of the first substrate differs from the second dielectric material layer of the second substrate, in particular with regard to its electrical insulation and / or thermal conductivity. For example, the electrical insulation and / or thermal conductivity of the first dielectric material layer is greater than that of the second dielectric material layer. In particular, the first dielectric material layer contains a ceramic material, while the second dielectric material layer contains an organic material. Costs can be saved by using cheaper materials.
[0024] A further embodiment provides that the first dielectric material layer of the first substrate has a first thickness and the second dielectric material layer of the second substrate has a second thickness, wherein the second thickness is smaller than the first thickness. A thin second substrate optimally counteracts the shear force, which has a positive effect on the reliability of the semiconductor device.
[0025] A further embodiment provides that the first connecting section and the second connecting section of the respective wiring element are designed substantially symmetrically with respect to a plane of symmetry, wherein the plane of symmetry is perpendicular to a conduction direction of the wiring elements. Such symmetry optimally counteracts the shear force, which has a positive effect on the reliability of the semiconductor device.
[0026] A further embodiment provides that the semiconductor arrangement comprises a plurality of wiring elements, each of which is connected from the second line section of the first substrate metallization via the contact area to the second substrate metallization of the second substrate. Such a configuration is particularly advantageous for higher load currents. Furthermore, parasitic inductances are reduced by connecting wiring elements in parallel, which leads to lower switching losses, thus achieving improved reliability of the semiconductor arrangement.
[0027] A further embodiment provides that the semiconductor arrangement has a second semiconductor element which is connected to the first substrate metallization of the first substrate and has a contact surface on a side facing away from the first substrate, wherein the contact surface of the second semiconductor element is connected to the second substrate metallization of the second substrate via at least one wiring element. By connecting the wiring elements of the first semiconductor element and the second semiconductor element to a common second substrate, space and thus costs are saved.
[0028] A further embodiment provides that the semiconductor elements are connected to one another via at least one, in particular identical, load connection. The semiconductor elements can, for example, be connected in parallel. By connecting the wiring elements of the semiconductor elements to a common second substrate, space and thus costs are saved.
[0029] A further embodiment provides that the second substrate metallization of the second substrate has at least two electrically insulated line sections, wherein the at least one wiring element of the first semiconductor element and the at least one wiring element of the second semiconductor element are each connected to one of the electrically insulated line sections of the second substrate metallization. The semiconductor elements can, for example, be connected anti-serially. By connecting the wiring elements of the semiconductor elements to a common second substrate, space and thus costs are saved.
[0030] In the following, the invention is described and explained in more detail with reference to the exemplary embodiments shown in the figures.
[0031] It shows :
[0032] FIG 1 is a schematic representation of a first embodiment of a semiconductor device in a plan view,
[0033] FIG 2 shows a schematic representation of the first embodiment of the semiconductor device in a cross-sectional view,
[0034] FIG 3 is a schematic representation of a second embodiment of a semiconductor device in a cross-sectional view,
[0035] FIG 4 is a schematic representation of a third embodiment of a semiconductor device in a plan view,
[0036] FIG 5 is a schematic representation of a fourth embodiment of a semiconductor device in a plan view and
[0037] FIG 6 shows a schematic representation of a power converter. The exemplary embodiments explained below are preferred embodiments of the invention. In the exemplary embodiments, the described components of the embodiments each represent individual features of the invention that are to be considered independently of one another, which also further develop the invention independently of one another and are thus to be regarded as a component of the invention, either individually or in a combination other than that shown. Furthermore, the described embodiments can also be supplemented by further features of the invention already described.
[0038] The same reference symbols have the same meaning in the different figures.
[0039] FIG 1 shows a schematic representation of a first embodiment of a semiconductor arrangement 2 in a plan view, which comprises a first semiconductor element 4 which is contact-connected to a first substrate 6. By way of example, the first semiconductor element 4 is designed as an insulated-gate bipolar transistor (IGBT). Further examples of such semiconductor elements are triacs, thyristors, diodes or other transistor types such as field-effect transistors or bipolar transistors. The IGBT comprises a control terminal, which is designed as a gate terminal G, and load terminals, which are designed as a collector terminal C and an emitter terminal E, the collector terminal C being materially connected to the first substrate 6 on a side of the first semiconductor element 4 facing the first substrate 6.
[0040] The emitter connection E has a contact area 8. The contact area 8 and the control contact area 10 have at least one metallic layer which contains, for example, aluminum, copper and / or gold. The collector connection C of the IGBT is materially connected, for example via a soldered or sintered connection, to a first line section 12 of a first substrate metallization 14 of the first substrate 6. Furthermore, the first substrate 6 has a second line section 16 which is electrically insulated from the first line section 12. In addition, the first substrate 6 comprises a first dielectric material layer 18 which contains, for example, a ceramic material, in particular aluminum nitride or aluminum oxide. The first substrate 6 can be designed, among other things, as a DCB (Direct Copper Bonded) substrate.
[0041] On a side of the first semiconductor element 4 opposite the second line section 16, a second substrate 20 is materially connected, for example adhesively or via a soldered or sintered connection, to the first line section 12 of the first substrate 6. The second substrate 20 has, on a side facing away from the first substrate 6, a second substrate metallization 22 which is arranged electrically insulated from the first line section 12 of the first substrate metallization 14 via a second dielectric material layer 24. The second dielectric material layer 24 can contain, among other things, a ceramic material, in particular aluminum nitride or aluminum oxide, or an organic material, in particular a polymer.
[0042] Furthermore, the semiconductor arrangement 2 has a plurality of wiring elements 26 for connecting the contact area 8 of the emitter terminal E to the second line section 16 of the first substrate 6 and to the second substrate metallization 22 of the second substrate 20. The substantially planar substrate 6 defines an xy plane. The wiring elements 26 are designed as bonding wires or bonding strips that run substantially parallel in the x direction and contain, for example, aluminum, copper and / or gold. By way of example, the wiring elements 26 are arranged in a straight line, in particular running in the x direction.In addition, the wiring elements 26 each have a first connecting section 28, which connects the contact surface 8 of the emitter terminal E to the second conducting section 16 of the first substrate metallization 14, and a second connecting section 30, which connects the contact surface 8 of the emitter terminal E to the second substrate metallization 22 of the second substrate 20. The second substrate metallization 22 connected to the second connecting section 30 of the respective wiring element 26 is designed to be open-circuited due to the second dielectric material layer 24.The open-circuit arrangement has the consequence that, during operation of the semiconductor arrangement 2, a first current II, in particular a load current, flows from the emitter E via the first connecting sections 28 of the respective wiring elements 26, while a, in particular negligibly small, second current I2 flows via the second connecting sections 30. In particular, the first current II is a hundred times, in particular a thousand times, greater than the second current I2. Thus, the first connecting section 28 and the second connecting section 30 have an asymmetrical current flow during operation of the semiconductor arrangement 2.
[0043] Due to the second dielectric material layer 24, which electrically insulates the second substrate metallization 22 of the second substrate 20 from the first substrate metallization 14 of the first substrate 6, a current I can flow in the first line section 12 even below the second substrate 20. Thus, the electrical properties of the first substrate metallization 14 of the first substrate 6 are not noticeably affected, particularly in comparison to a bonding island. The current I in the first line section 12 of the first substrate 6 can flow essentially unhindered or unchanged to the collector C of the first semiconductor element 4.
[0044] FIG 2 shows a schematic representation of the first embodiment of the semiconductor arrangement 2 in a cross-sectional representation. The first dielectric material layer 18 of the first substrate 6 has a first thickness s1 of 25 gm to 400 gm, in particular 50 gm to 250 gm, while the second dielectric material layer 24 of the second substrate 20 has a second thickness s2 of 10 pm to 250 pm, in particular 20 pm to 150 pm. The wiring elements 26 are designed as bonding wires and form a plurality of connections 32 on the contact surface 8 between the first connecting section 28 and the second connecting section 30, the connection being produced by means of ultrasonic bonding. The connection of the wiring elements 26 to the contact surface 8 of the first semiconductor element 4 is produced by looping through the wiring elements 26, in particular by means of multi-stitch wedge-to-wedge wire bonding.Multiple bonding is also called "stitching". Such connections 32 are usually also referred to as "stitch contacts" or "stitch bonds" and can be designed, for example, as "wedge bonds". The first connecting section 28 and the second connecting section 30 of the respective wiring elements 26 are designed essentially symmetrically with respect to a plane of symmetry 34, wherein the plane of symmetry 34 is designed perpendicular to the conduction direction of the wiring elements 26 arranged running in the x-direction.
[0045] If a first current II, in particular load current, flows via the wiring elements 26, a shearing force Fl acts on the connections 32, in particular ultrasonic bonded connections. As a result of the overbonding of the wiring elements 26 via the second connecting section 30 to the second substrate 20, a counterforce F2 can counteract the shearing force Fl, so that the connections 32 are more robust, in particular under load. The result is that the overbonding results in a longer service life of the semiconductor arrangement 2.
[0046] The second substrate 20 has a third substrate metallization 36 arranged above the second dielectric material layer 24, electrically separated from the second substrate metallization 22. The second substrate 20 is materially connected to the first substrate metallization 14 of the first substrate 6 via the third substrate metallization 36. Alternatively, the third substrate metallization 36 can be omitted, the materially bonded connection being produced, for example, adhesively. In particular, the second substrate metallization 22 can be designed as a metal plate and the second dielectric material layer 24 as an electrically insulating adhesive layer, the metal plate being connected to the first substrate 6 via the electrically insulating adhesive layer.A current I , in particular load current, which is not noticeably influenced by the second substrate 20, flows to the collector C of the first semiconductor element 4 via the first line section 12 of the first substrate metallization 14 of the first substrate 6 below the second substrate 20.
[0047] 3 shows a schematic representation of a second embodiment of a semiconductor arrangement 2 in a cross-sectional representation, wherein a half-bridge is formed with the first semiconductor element 4 designed as an IGBT and a second semiconductor element 38, which is also designed as an IGBT. The second semiconductor element 38 is connected, in particular in a material-locking manner, to a third line section 40 of the first substrate metallization 14. The first semiconductor element 4 is configured as a low-side switch and the second semiconductor element 38 as a low-side switch of the half-bridge. A current I, in particular load current, flows below the second substrate 20 from the emitter E of the second semiconductor element 38 designed as a high-side switch to the collector C of the first semiconductor element 4 designed as a low-side switch.Both semiconductor elements 4, 38 are bonded via the second connecting sections 30 of the respective wiring elements 26, which has a positive effect on the service life of the semiconductor arrangement 2. The further design of the semiconductor arrangement 2 in FIG. 3 corresponds to that in FIG. 1 or FIG. 2.
[0048] FIG 4 shows a schematic representation of a third embodiment of a semiconductor arrangement 2 in a plan view, wherein the semiconductor elements 4, 38 each have an anti-parallel connected diode 42 and, as in FIG 3, form a half-bridge. The first line section 12 of the substrate 6 is connected via a shunt resistor 44 to an AC terminal AC, while the second line section 16 is connected to a negative DC terminal DCN of the half-bridge. The second semiconductor element 38 is materially connected to the third line section 40 of the first substrate metallization 14, wherein the third line section 40 is connected to a positive DC terminal DCP of the half-bridge. Furthermore, the semiconductor arrangement 2 comprises a temperature sensor 46, which is designed for example as an NTC thermistor (Negative Temperature Coefficient Thermistor).A current I , in particular load current, flows beneath the second substrate 20 from the emitter E of the second semiconductor element 38, designed as a high-side switch of the half-bridge, to the collector C of the first semiconductor element 4, designed as a low-side switch of the half-bridge. The further embodiment of the semiconductor arrangement 2 in FIG. 4 corresponds to that in FIG. 3.
[0049] FIG 5 shows a schematic representation of a fourth embodiment of a semiconductor arrangement 2 in a plan view, which comprises, for example, four semiconductor elements 4, 38, 48, 50. The semiconductor elements 4, 38, 48, 50 are, for example, designed as vertical field-effect transistors, in particular as vertical SiC MOSFETs. Alternatively, the semiconductor elements 4, 38, 48, 50 can be designed, among other things, as IGBTs. A first and a second semiconductor element 4, 38 and a third and a fourth semiconductor element 48, 50 are each connected in parallel in pairs. The semiconductor elements 4, 38, 48, 50 connected in parallel in pairs are materially connected to the first line section 12 of the first substrate metallization 14 of the first substrate 6, so that they are connected on the drain side. Such an anti-serial connection can be used, among other things, in a Vienna rectifier.
[0050] The second substrate metallization 22 of the second substrate 20 is structured and has two line sections 52, 54 that are electrically insulated from one another. The wiring elements 26 of the parallel-connected first and second semiconductor elements 4, 38 are connected from the second line section 16 of the first substrate 6 via the contact areas 8 of the parallel-connected semiconductor elements 4, 38 to a fourth line section 52 of the second substrate metallization 22 of the second substrate 20. Furthermore, the wiring elements 26 of the parallel-connected third and fourth semiconductor elements 48, 50 are connected from the third line section 40 of the first substrate 6 via the contact areas 8 of the parallel-connected semiconductor elements 48, 50 to a fifth line section 54 of the second substrate metallization 22 of the second substrate 20.Thus, a current I , in particular load current, can flow beneath the second substrate 20 between the anti-serially connected semiconductor elements 4, 38, 48, 50. A potential equalization is achieved between the semiconductor elements 4, 38, 48, 50 connected in parallel in pairs via the common second substrate 20. The further embodiment of the semiconductor arrangement 2 in FIG. 5 corresponds to that in FIG. 1 or FIG. 2.
[0051] FIG 6 shows a schematic representation of a power converter 56, which comprises, for example, a semiconductor device 2
[0052] In summary, the invention relates to a semiconductor arrangement 2 with a first semiconductor element 4, a first substrate 6, a second substrate 20 and at least one wiring element 26. In order to achieve improved reliability, it is proposed that the first substrate 6 has a first substrate metallization 14 with line sections 12, 16 arranged electrically insulated from one another, wherein the first semiconductor element 4 and the second substrate 20 are connected, in particular in a materially bonded manner, to a first line section 12 of the first substrate metallization 14, wherein the second substrate 20 has, on a side facing away from the first substrate 6, a second substrate metallization 22 which is arranged electrically insulated from the first line section 12 of the first substrate metallization 14 via a second dielectric material layer 24.wherein the first semiconductor element 4 has a contact surface 8 on a side facing away from the first substrate 6, wherein the contact surface 8 is connected to at least one wiring element 26, wherein the at least one wiring element 26 has a first connecting section 28 which connects the contact surface 8 to a second conducting section 16 of the first substrate metallization 14, which is arranged electrically insulated from the first conducting section 12, and a second connecting section 30 which connects the contact surface 8 to the second substrate metallization 22 of the second substrate 20.
Claims
Patent claims 1. A semiconductor arrangement (2) comprising a first semiconductor element (4), a first substrate (6), a second substrate (20), and at least one wiring element (26), wherein the first substrate (6) has a first substrate metallization (14) with line sections (12, 16) arranged so as to be electrically insulated from one another, wherein the first semiconductor element (4) and the second substrate (20) are connected, in particular materially, to a first line section (12) of the first substrate metallization (14), wherein the second substrate (20) has, on a side facing away from the first substrate (6), a second substrate metallization (22), which is arranged so as to be electrically insulated from the first line section (12) of the first substrate metallization (14) via a second dielectric material layer (24), wherein the first semiconductor element (4) has a contact surface (8) on a side facing away from the first substrate (6),wherein the contact surface (8) is connected to at least one wiring element (26), wherein the at least one wiring element (26) has a first connecting section (28) which connects the contact surface (8) to a second line section (16) of the first substrate metallization (14) arranged electrically insulated from the first line section (12), and a second connecting section (30) which connects the contact surface (8) to the second substrate metallization (22) of the second substrate (20), wherein the second substrate metallization (22) of the second substrate (20) is arranged open-circuit.
2. Semiconductor device (2) according to claim 1, wherein the second substrate (20) is arranged on the first line section (12) of the first substrate (6) in such a way that during operation of the semiconductor arrangement (2) a current (I) in the first line section (12) of the first substrate (6) flows at least partially below the second substrate (20).
3. Semiconductor arrangement (2) according to claim 2, wherein the current (I) flowing beneath the second substrate (20) is a load current of the first semiconductor element (4).
4. Semiconductor arrangement (2) according to one of claims 1 to 3, wherein the second substrate (20) lies flat on the first line section (12) of the first substrate metallization (14).
5. Semiconductor arrangement (2) according to one of the preceding claims, wherein the first dielectric material layer (18) of the first substrate (6) differs from the second dielectric material layer (24) of the second substrate (20), in particular with regard to its electrical insulation and / or thermal conductivity.
6. Semiconductor arrangement (2) according to one of the preceding claims, wherein the first dielectric material layer (18) of the first substrate (6) has a first thickness (s1) and the second dielectric material layer (24) of the second substrate (20) has a second thickness (s2), wherein the second thickness (s2) is smaller than the first thickness.
7. Semiconductor device (2) according to one of the preceding claims, wherein the second substrate (20) is arranged on a side of the first semiconductor element (4) opposite the second line section (16).
8. Semiconductor arrangement (2) according to one of the preceding claims, wherein the first connecting section (28) and the second connecting section (30) of the respective wiring element (26) are designed substantially symmetrically with respect to a plane of symmetry (34), wherein the plane of symmetry 34 is designed perpendicular to a conduction direction of the wiring elements 26.
9. Semiconductor arrangement (2) according to one of the preceding claims, wherein the semiconductor arrangement (2) comprises a plurality of wiring elements (26) which are each connected from the second line section (16) of the first substrate metallization (14) via the contact area (8) to the second substrate metallization (22) of the second substrate (20).
10. Semiconductor arrangement (2) according to one of the preceding claims, which has a further semiconductor element (38, 48, 50) which is connected to the first substrate metallization (14) of the first substrate (6) and has a contact surface (8) on a side facing away from the first substrate (6), wherein the contact surface (8) of the second semiconductor element (38) is connected to the second substrate metallization (22) of the second substrate (20) via at least one wiring element (26).
11. Semiconductor arrangement (2) according to claim 10, wherein the semiconductor elements (4, 38, 48, 50) are connected to one another at least via one, in particular identical, load connection.
12. Semiconductor arrangement (2) according to one of claims 10 or 11, wherein the second substrate metallization (22) of the second substrate (20) has at least two line sections (52, 54) which are electrically insulated from one another, wherein the at least one wiring element (26) of the first semiconductor element (4) and the at least one wiring element (26) of the second semiconductor element (38) are each connected to one of the line sections (52, 54) of the second substrate metallization (22) which are electrically insulated from one another.
13. Power converter (56) with at least one semiconductor arrangement (2) according to one of the preceding claims.
14. A method for producing a semiconductor device (2) with a first semiconductor element (4), a first substrate (6), a second substrate (20) and at least one wiring element (26), wherein the first substrate (6) has a first substrate metallization (14) with line sections (12, 16) arranged so as to be electrically insulated from one another, wherein the first semiconductor element (4) and the second substrate (20) are connected, in particular materially, to a first line section (12) of the first substrate metallization (14), wherein the second substrate (20) has, on a side facing away from the first substrate (6), a second substrate metallization (22), which is arranged so as to be electrically insulated from the first line section (12) of the first substrate metallization (14) via a second dielectric material layer (24), wherein the first semiconductor element (4) has a contact surface (8) on a side facing away from the first substrate (6),wherein the contact surface (8) is connected to at least one wiring element (26), wherein the at least one wiring element (26), a first connecting section (28) via which the contact surface (8) is connected to a second line section (16) of the first substrate metallization (14) arranged electrically insulated from the first line section (12), and a second connecting section (30) via which the contact surface (8) is connected to the second substrate metallization (22) of the second substrate (20), wherein the second substrate metallization (22) of the second substrate (20) is arranged open-circuit.
15. The method according to claim 14, wherein the second substrate (20) is arranged on the first line section (12) of the first substrate (6) in such a way that during operation of the semiconductor arrangement (2) a current (I), in particular a load current of the first semiconductor element (4), flows in the first line section (12) of the first substrate (6) at least partially below the second substrate (20).