Method and device for soft demapping a modulation symbol

Abstract

Disclosed is a method for demapping a modulation symbol, comprising: - classifying (101) each bit of the symbol into a first group or into a second group, - determining (102) N different pairs (αk,βk) each defining a slope and an ordinate at the origin of an edge of a Voronoi sector defined for a bit belonging to the second group and taking the value '0' or '1' in a first quadrant of the constellation, - for each bit of the first group, calculating (103) an LLR as a product between a multiplicative factor and a real part or an imaginary part of the symbol, - verifying (104) N inequalities αk|Re(s)| + βk ≤ |Im(s)|, - for each bit of the second group, calculating (108) the LLR depending on the real part and imaginary part of the symbol and depending on parameters (107) selected from subsets of the results obtained for the N inequalities (105, 106).

Description

[0001]Method and Device for Soft Demapping of a Modulation Symbol Field of the Invention The present invention belongs to the field of digital signal demodulation. More particularly, the invention relates to a method for calculating a log-likelihood ratio for the soft demapping of modulation symbols. Prior Art Methods for calculating a log-likelihood ratio (LLR) are commonly used in soft-input decoding algorithms.As a non-exhaustive example, this can include the BCJR algorithm (maximum a posteriori decoding algorithm for error-correcting codes defined on lattices, such as turbo codes), successive cancellation decoding (SC) for polar codes, or belief propagation (BP) algorithms for decoding low-density parity check (LDPC) codes. LLR calculations are used in soft demapping methods for modulation symbols (soft decision decoding). In LDPC decoding, soft demapping methods are generally preferred due to their superior performance compared to hard decision decoding.However, flexible demapping operations can prove costly in terms of computational complexity, especially for higher-order modulations. For example, the DVB-S2 ("Digital Video Broadcasting - Satellite 2", second-generation digital video broadcasting via satellite), DVB-S2X (extension of the DVB-S2 standard), CCSDS ("Consultative Committee for Space Data Systems"), and 5G standards use high-order amplitude and phase modulations, such as type 2 modulations. M -APSK ("Amplitude and Phase Shift Keying"), with M greater than or equal to five. M is the number of bits of information represented by a modulation symbol, 2 MThis corresponds to the number of symbols in the constellation. The exact calculation of an LLR can be obtained using the maximum a posteriori method (MAP), or the maximum likelihood (ML) method when the symbols are equally probable. The ML method is often used as a benchmark to compare the performance of an LLR approximation method. The ML method is a flexible demodulation approach based on calculating the probability that a received symbol corresponds to each of the possible symbols in the constellation. The LLR for each bit is calculated by taking the logarithmic ratio of the sum of the probabilities that each symbol is transmitted, separating them into two subsets: the numerator considers symbols such that the transmitted bit is '0', and the denominator those such that the transmitted bit is '1'. The exact calculation of an LLR for a bit ^^ of a symbol ^, with ^ ∈ ^0, … , ^ − 1^ is then given by the following formula: [Math.1]. with where -.^ / 0 is the set of symbol indices for which = 0 ; -.^ / 2 is the set of indices of the symbols for which = 1; ^^ is the Gaussian probability density function of the symbol ^, knowing that the symbol ^ ^ has been transmitted; ^ ^ corresponds to a symbol with the index + in the constellation; # is the variance of the noise in the propagation channel (we are considering the case of a channel with additive white Gaussian noise, AWGN). It should be noted, however, that we are not necessarily limited to an AWGN-type propagation channel. Any propagation channel for which we can calculate the probabilities 34^ | ^ ^5 could be taken into consideration. To reduce the complexity of calculating the LLR, and thus limit the hardware complexity of a receiving device, several LLR approximation methods have been proposed. The "Max LLR" method is an approximation of the ML method used to reduce computational complexity without significantly compromising decoder performance. In this approximation, instead of summing the probabilities of all possible symbols for a given bit, only the probability of the most likely symbol (or its logarithm, to be more precise) is considered for each case (bit set to 1 or bit set to 0). This simplification can, however, lead to a degradation in decoding performance compared to the ML method, as all contributions from other symbols are ignored. The ML method is generally used as a benchmark in terms of maximum achievable performance.The method described in the paper "Efficient Soft Demapping for M-ary APSK" by Meixang Zhang et al. relies on soft demapping based on firm decision thresholds. However, this method requires fairly complex norm and angle calculations. For implementation on an FPGA target, these angle calculations cannot be easily implemented, necessitating approximations that lead to a performance degradation in addition to that described in the paper. The paper "Efficient Demodulation of General APSK Constellations" by Magnus Sandell et al. describes a soft demapping method based on decision trees. The paper "Look-Up Table Based Low Complexity LLR Calculation for High-Order Amplitude Phase Shift Keying Signals" by Nan Wu et al. describes a soft demapping method based on a lookup table.There are also demapping methods that rely on dividing the constellation plane into different Voronoi sectors and solving inequalities to determine which sectors the different bits of a symbol to be demapped belong to. Again, the proposed methods are generally not optimal for implementation on an FPGA target. US patent applications US2023 / 042213A1 and US2006 / 045211A1 each describe a method and a system for optimizing the calculation of LLRs for symbol decoding in a mobile telephony communication system. Description of the Invention: The present invention aims to provide a new method for calculating LLRs for the flexible demapping of modulation symbols. The proposed method aims in particular to avoid, as much as possible, calculations of norm or angle and multiplications or divisions by non-constant values.The method also aims to exhibit constant complexity regardless of the received symbol (in other words, the goal is to keep the number of calculations the same regardless of the received symbol). Furthermore, the proposed method is adaptable to different types of modulations and constellations. The proposed method offers performance very similar (bordering on equal) to that of the ML method. Thus, in its first aspect, a method for unmapping a modulation symbol is proposed. The modulation symbol represents several bits of information. The method aims to calculate a logarithmic likelihood ratio (LLR) for each bit of the symbol. The method is implemented by a unmapping module of a receiving device.The modulation presents a constellation of symbols with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group. The method comprises: - a classification of each symbol bit into the first group or the second group, - a determination of 6 pairs 478, 985, : ∈ ;1, 6<, where 6 is an integer strictly greater than one, the 6 pairs being distinct from one another and each defining a slope of 7. ^ and an ordinate at the origin of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation, - for each bit of the symbol ^ belonging to the first group, a calculation of the LLR for said bit in the form of a product between a multiplicative factor and a real part ^$4^5 or an imaginary part =>4^5 of the symbol ^, - a verification of 6 inequalities 78|^$4^5| + 98 ≤ |=>4^5|, : ∈ ;1, 6<,- for each bit of the symbol ^ belonging to the second group: o for each value '0' or '1' that can be taken by the bit, a determination of a subset of the results obtained for the 6 inequalities, and a comparison of the subset of results with predetermined candidate values,o a selection of a set of parameters defined by an index > representing the candidate value corresponding to the subset of results for the case where the bit value is '1' and an index A representing the candidate value corresponding to the subset of results for the case where the bit value is '0', o a calculation of the LLR for the bit as a function of the selected parameters and as a function of the real and imaginary parts of the symbol. In particular implementations, the method may further include one or more of the following features, taken individually or in any technically possible combination. In particular implementations, the modulation is an APSK phase-amplitude modulation, or a quadrature amplitude QAM modulation. In particular implementations, the modulation includes 2, ,symbols, where ^ is an integer greater than or equal to four. In certain implementations, the modulation is APSK modulation, where ^ equals five, and 6 equals eighteen. In certain implementations, the modulation exhibits a constellation defined in a DVB-S2, DVB-S2X, CCSDS, or 5G communication standard. In certain implementations, for each value equal to '0' or '1' that can be taken by a bit ^ ^ belonging to the second group, the subset of results and each candidate value are each defined in the form of a champ In certain implementation modes, the multiplicative factor is calculated in the form # where " is an estimated value of the variance of an additive white Gaussian noise in a propagation channel of a signal carrying the symbol ^. In particular implementation modes, - takes at least two possible values ​​depending on the value of the real part ^$4^5 or the imaginary part =>4^5 of the symbol ^. According to a second aspect, a demapping module for a modulation symbol ^ is proposed. The modulation symbol represents several bits of information. The modulation presents a constellation of symbols with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group. The demapping module is configured to store 6 pairs 478, 985, : ∈ ;1, 6<, where 6 is an integer strictly greater than one, the 6 pairs being distinct and each defining a slope 7 ^ and a y-intercept 9 ^of a straight line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation. The unmapping module is also configured to implement the following steps: - for each bit of the ^ symbol belonging to the first group, a calculation of a logarithmic likelihood ratio (LLR) for said bit in the form of a product between a multiplicative factor and a real part ^$4^5 or an imaginary part =>4^5 of the ^ symbol, - a verification of 6 inequalities 78|^$4^5| + 98 ≤ |=>4^5|, : ∈ ;1, 6<, - for each bit of the ^ symbol belonging to the second group: o for each value '0' or '1' that can be taken by the bit, a determination of a subset of the results obtained for the 6 inequalities, and a comparison of the subset of results with predetermined candidate values,o a selection of a set of parameters defined by an index > representing the candidate value corresponding to the subset of results for the case where the bit value is '1' and an index A representing the candidate value corresponding to the subset of results for the case where the bit value is '0', o a calculation of an LLR for the bit as a function of the selected parameters and as a function of the real and imaginary parts of the symbol. In particular implementations, the demapping module may further include one or more of the following features, taken individually or in any technically possible combination. In particular embodiments, the modulation is an APSK phase-amplitude modulation, or a quadrature amplitude QAM modulation, comprising 2, ,symbols, where ^ is an integer greater than or equal to four. In particular embodiments, the modulation is APSK modulation, where ^ equals five, and 6 equals eighteen. In particular embodiments, for each value equal to '0' or '1' that can be taken by a bit ^ ^ belonging to the second group, the subset of results and each candidate value are each defined as a field In certain embodiments, the multiplicative factor is calculated in the form where " is an estimated value of a standard deviation of additive white-Gaussian noise in a propagation channel of a signal carrying the symbol ^. In particular embodiments, - takes at least two possible values ​​depending on the value of the real part ^$4^5 or the imaginary part =>4^5 of the symbol ^. According to a third aspect, a receiving device is proposed comprising a demapping module according to any one of the preceding embodiments. According to a fourth aspect, a satellite intended to be placed in orbit around the Earth is proposed and comprising such a receiving device according to the invention. According to a fifth aspect, a ground station is proposed comprising a receiving device according to the invention.According to a sixth aspect, the invention relates to a satellite communications system comprising at least one satellite including a receiving device according to the invention and / or at least one ground station including a receiving device according to the invention. Presentation of the figures The invention will be better understood upon reading the following description, given by way of non-limiting example, and made with reference to the following figures: [Fig. 1] a schematic representation of the main steps of an implementation of the demapping method according to the invention, [Fig. 2] a schematic representation of a satellite carrying a receiving device including a demapping module according to the invention, [Fig. 3] a representation of an example constellation of a 32-APSK modulation, [Fig. 4] a representation of the symbols of the constellation of Figure 3 for which bit ^2 is equal to '0', and those for which bit ^2 is equal to '1', [Fig.5] a representation of the symbols of the constellation in Figure 3 for which the bit ^. # is equal to '0', and those for which the bit ^ #is equal to '1', [Fig. 6] a graph representing the calculated value of the LLR of bit ^2, as a function of the value of the imaginary part of the symbol, for the ML method and for a first example of an implementation of the method according to the invention, [Fig. 7] a graph representing the calculated value of the LLR of bit ^2, as a function of the value of the imaginary part of the symbol, for the ML method and for a second example of an implementation of the method according to the invention, [Fig. 8] a representation of the symbols in the constellation of Figure 3 for which bit ^0 is equal to '0', and those for which bit ^0 is equal to '1', [Fig. 9] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation of Figure 3 for which bit ^0 is equal to '1', [Fig. 10] a representation of the Voronoi sectors of the symbols in the first quadrant of the constellation of Figure 3 for which bit ^0 is equal to '0', [Fig.11] a representation of the symbols of the constellation in Figure 3 for which the bit ^. E is equal to '0', and those for which the bit ^ E is equal to '1', [Fig.12] a representation of the Voronoi sectors of the symbols of the first quadrant of the constellation in Figure 3 for which the bit ^ E is equal to '1', [Fig.13] a representation of the Voronoi sectors of the symbols of the first quadrant of the constellation in Figure 3 for which the bit ^ E is equal to '0', [Fig.14] a representation of the symbols of the constellation in Figure 3 for which the bit ^ F is equal to '0', and those for which the bit ^ F is equal to '1', [Fig.15] a representation of the Voronoi sectors of the symbols of the first quadrant of the constellation in Figure 3 for which the bit ^ Fis equal to '1', [Fig.16] a representation of the Voronoi sectors of the symbols of the first quadrant of the constellation in Figure 3 for which the bit ^ F is equal to '0'. In these figures, identical reference numerals from one figure to another designate identical or analogous elements. For clarity, the elements shown are not necessarily to the same scale unless otherwise stated. Detailed description of the invention Figure 1 schematically represents the main steps of an implementation of Method 100 according to the invention for unmapping a modulation symbol. A modulation symbol represents several bits of information. For example, a 32-APSK modulation has thirty-two symbols, and each symbol represents five bits of information. Typically, the number of symbols in the modulation constellation is written in the form 2 ,where ^ is the number of bits represented by a symbol in the constellation. The demapping method aims to calculate a logarithmic likelihood ratio, LLR, for each bit of a received symbol. Figure 2 schematically represents a receiving device 20 comprising a demapping module 23 configured to implement the demapping method 100 according to the invention. This device 20 may, in particular, be a receiving device for a radio signal or an optical signal. The receiving device 20 may, in particular, be carried on a satellite 10 placed in orbit around the Earth, for receiving signals on an uplink from a ground station. The receiving device 20 may also be integrated into a ground station, for receiving signals on a downlink from the satellite 10. However, nothing would prevent considering other applications of the invention.For example, the invention could also be applied to a receiving device for a mobile terminal in a terrestrial communication system. As illustrated in Figure 2, the receiving device 20 includes an antenna 21 for receiving a radio signal or an optical signal sent by a transmitting device. The receiving device 20 also includes a demodulation module 22. Conventionally, the demodulation module 22 is configured to determine a real and an imaginary part of at least one modulation symbol contained in the received signal. The demapping module 23 is adapted to calculate a logarithmic likelihood ratio (LLR) for each bit of a received symbol, from the real and imaginary parts of the symbol. The receiving device 20 also includes a channel decoding module 24, for example, an LDPC decoder, adapted to decode the received signal from the calculated LLRs.Conventionally, the symbol frame input to the demapping module 23 is synchronized in time, frequency, and phase. In the example considered, the demodulation module 22, the demapping module 23, and the channel decoding module 24 are implemented as FPGA (Field-Programmable Gate Array) type programmable integrated circuits. However, in alternative configurations, they could be implemented as an ASIC (Application-Specific Integrated Circuit) type, or using a processor or microcontroller. More generally, the demapping module 23 is hereafter considered to include software and / or hardware means configured to implement method 100 according to the invention.The demapping module 23 may include memory, for example RAM (Random Access Memory), to store the parameters necessary for implementing method 100. In the following description, we consider, as a non-limiting example, the case of phase-amplitude modulation with thirty-two symbols (32-APSK modulation, with ^ = 5). The invention is indeed particularly well-suited to type 2 modulations. ,High-order APSK, for example, modulations for which ^ is at least equal to four (^ ≥ 4). 32-APSK modulation is notably used in the DVB-S2, DVB-S2X, and CCSDS communication standards. Figure 3 illustrates an example of a constellation for 32-APSK modulation. This constellation is similar to that used in the DVB-S2X standard. As illustrated in Figure 3, the constellation consists of thirty-two symbols s1 to s32 represented in a complex plane with a coordinate system where the x-axis represents the real parts of the symbols and the y-axis represents the imaginary parts of the symbols. Each symbol represents five bits of information, named ^^, ^ ∈ ^0, … ,4^. In the example considered, the bit with index ^ = 0 corresponds to the least significant bit (rightmost bit in the notation used in Figure 3), and the bit with index ^ = 4 corresponds to the most significant bit (leftmost bit in the notation used in Figure 3).For example, the symbol s9 corresponds to the binary value b01001; for this symbol, we have ^0 = 1, ^2 = 0, ^# = 0, ^E = 1, and ^F = 0. It should be noted, however, that the invention could also be applied to other types of modulation, particularly quadrature amplitude modulation (QAM). Higher-order QAM modulations (for example, with constellations containing thirty-two, sixty-four, or one hundred and twenty-eight symbols) are notably used in the 5G communication standard. Therefore, for a given modulation, the invention can be applied to different examples of constellations. In particular, different constellations can correspond to different ways of distributing the bit values ​​of the symbols within the constellation.However, it is necessary to limit ourselves to symbol constellations with half-plane symmetry for some symbol bits (bits belonging to a first group), and quadrant symmetry for other symbol bits (bits belonging to a second group). Half-plane symmetry means that, for a bit belonging to the first group, the set of symbols for which the bit value is '0' is symmetric to the set of symbols for which the bit value is '1' with respect to the x-axis or the y-axis of the constellation's coordinate system. In this application, a first set of symbols is considered symmetric with respect to a second set of symbols if each symbol in the first set has a symmetrical counterpart in the second set, and vice versa. For the constellation illustrated in Figure 3, the bit ^2 exhibits half-plane symmetry with respect to the x-axis.Indeed, as illustrated in Figure 4, the set of symbols for which the bit ^2 takes the value '0' (symbols represented by dots in Figure 4) is symmetric to the set of symbols for which the bit ^2 takes the value '1' (symbols represented by crosses in Figure 4) with respect to the x-axis. For example, the symbol s9 for which the bit ^2 takes the value '0' is symmetric to the symbol s11 for which the bit ^2 takes the value '1'; the symbol s16 for which the bit ^2 takes the value '0' is symmetric to the symbol s18 for which the bit ^2 takes the value '1'; and so on. For the constellation illustrated in Figure 3, the bit ^. # exhibits a half-plane symmetry with respect to the y-axis. Indeed, as illustrated in Figure 5, the set of symbols for which the bit ^ # takes the value '0' (symbols represented by dots in Figure 5) is symmetric to the set of symbols for which the bit ^# takes the value '1' (symbols represented by crosses in Figure 5) with respect to the y-axis. As an example, the symbol s9 for which the bit ^ # takes the value '0' is symmetric to the symbol s13 for which the bit ^ # takes the value '1'; the s16 symbol for which the bit ^ # takes the value '0' is symmetric to the symbol s20 for which the bit ^ #takes the value '1'; etc. Quadrant symmetry means that, for a bit belonging to the second group, the set of symbols for which the bit value is '0' (respectively '1') in one quadrant of the constellation is symmetric, for each of the other quadrants of the constellation, to the set of symbols for which the bit value is '0' (respectively '1') in that other quadrant. For example, let's number the quadrants of the constellation illustrated in Figure 3, starting with the first quadrant in the upper right, and proceeding clockwise.The first quadrant contains symbols whose real and imaginary parts are positive, the second quadrant contains symbols whose real part is positive and whose imaginary part is negative, the third quadrant contains symbols whose real and imaginary parts are negative, and the fourth quadrant contains symbols whose real part is negative and whose imaginary part is positive. Therefore, for some bits, the symbols in the first quadrant may exhibit symmetry with respect to the x-axis with the symbols in the second quadrant, the symbols in the first quadrant may exhibit symmetry with respect to the y-axis with the symbols in the fourth quadrant, and the symbols in the first quadrant may exhibit symmetry with respect to the origin of the coordinate system with the symbols in the third quadrant. This is the case, in particular, for the bits ^0 and ^. E and ^ FIn particular, and as illustrated in Figure 8, the set of symbols for which the bit ^0 takes the value '0' in the first quadrant is symmetric, for each of the other three quadrants of the constellation, to the set of symbols for which the bit ^0 takes the value '0' in said other quadrant. Indeed, the set of symbols {s0, s8, s24, s16} for which the bit ^0 takes the value '0' in the first quadrant is symmetric to the set of symbols {s2, s10, s26, s18} in the second quadrant with respect to the x-axis; the set of symbols {s0, s8, s24, s16} is symmetric to the set of symbols {s6, ​​s14, s30, s22} in the third quadrant with respect to the origin of the coordinate system; the set of symbols {s0, s8, s24, s16} is symmetric to the set of symbols {s4, s12, s28, s20} in the third quadrant with respect to the ordinate axis.Similarly, the set of symbols for which the bit ^0 takes the value '1' in the first quadrant is symmetric, for each of the other three quadrants of the constellation, to the set of symbols for which the bit ^0 takes the value '1' in said other quadrant. Indeed, the set of symbols {s17, s1, s9, s25} for which the bit ^0 takes the value '1' in the first quadrant is symmetric to the set of symbols {s19, s3, s11, s27} in the second quadrant with respect to the x-axis; the set of symbols {s17, s1, s9, s25} is symmetric to the set of symbols {s23, s7, s15, s31} in the third quadrant with respect to the origin of the coordinate system; The set of symbols {s17, s1, s9, s25} is symmetric to the set of symbols {s21, s5, s13, s29} in the fourth quadrant with respect to the y-axis. Similarly, and as illustrated in Figure 11, the set of symbols for which the bit ^. Etakes the value '0' (respectively '1') in the first quadrant is symmetric, for each of the three other quadrants of the constellation, to the set of symbols for which the bit ^ E takes the value '0' (respectively '1') in this other quadrant. Finally, and as illustrated in Figure 14, the set of symbols for which the bit ^ F takes the value '0' (respectively '1') in the first quadrant is symmetric, for each of the three other quadrants of the constellation, to the set of symbols for which the bit ^ F takes the value '0' (respectively '1') in this other quadrant. As illustrated in Figure 1, for the constellation considered, method 100 includes a classification step 101 of each symbol bit into the first group (bits with half-plane symmetry) or into the second group (bits with quadrant symmetry). For the example considered, the bits ^2 and ^ #are classified in the first group, and the bits ^0, ^ E and ^ Fare classified in the second group. Method 100 also relies on the concept of a Voronoi diagram. A Voronoi diagram is a division of the constellation plane into several sectors. Each sector takes the form of a polygon, the number of sides of which can vary from one sector to another. Each sector surrounds a symbol of the constellation, such that any point in a given sector is closer to the symbol associated with that sector than to any other symbol in the constellation. The Voronoi sector division is performed for each symbol bit, and for each possible value of '0' or '1' for that bit. The LLR of a bit of a received symbol can then be calculated by determining the two Voronoi sectors corresponding to the values ​​'0' and '1' of the bit in question, respectively, in which the symbol is located.Each edge of a Voronoi sector (that is, each side of the polygon forming the sector) corresponds to a straight line equidistant between two symbols of the constellation. Each edge of a sector can therefore be represented by a slope and a y-intercept. It is then possible to determine in which Voronoi sectors a received symbol lies by solving a set of inequalities involving the real and imaginary parts of the received symbol, each inequality corresponding to an edge of a Voronoi sector for a given value of a symbol bit. In Method 100 according to the invention, and as will be detailed later, Voronoi sectors are used only for the bits of the second group (bits exhibiting quadrant symmetry). It is then possible to limit the number of inequalities to be solved by taking into account, on the one hand, quadrant symmetry, and on the other hand, the fact that some sectors share edges.Indeed, thanks to quadrant symmetry, for a given case ^^ = 40|15, the Voronoi sectors of the first quadrant are mirrored in the other three quadrants. Thus, it suffices to determine in which sector of the first quadrant lies the symbol having a real part |^$4^5| and an imaginary part |=>4^5| (this symbol being the image of the symbol ^ in the first quadrant). Thus, and as illustrated in Figure 1, method 100 comprises a step 102 of determining 6 pairs 478, 985, : ∈ ;1, 6<, 6 being an integer strictly greater than one (steps 101 to 102 shown in Figure 1 are implemented upstream, for example in the design of the receiving device 20; the other steps are implemented for each new symbol received). The 6 pairs are different in pairs and each defines a slope of 7. ^ and a y-intercept 9 ^of a line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in the first quadrant of the constellation. In the example considered of the 32-APSK constellation in Figure 3, we have 6 = 18. The eighteen lines are represented by the references d1 to d18 in Figures 9, 10, 12, 13, 15, and 16. For each case ^^ = 40|15, it is necessary to consider four Voronoi sectors in the first quadrant (for each case there are 2 , / 8 symbols for which the bit ^ ^(takes a given value). Figure 9 is a representation of the Voronoi sectors of the symbols s1, s9, s17, and s25 in the first quadrant of the constellation for which the bit ^0 is equal to '1'. The sector corresponding to the symbol s1 is delimited by the lines d2, d5, and d3. The line d2 is located equidistant between the symbol s1 and the symbol s9. The line d3 is located equidistant between the symbol s1 and the symbol s25. The line d5 is located equidistant between the symbol s1 and the symbol s17. The sector corresponding to the symbol s9 is delimited by the lines d1 and d2. The line d1 is located equidistant between the symbol s9 and the symbol s25. The sector corresponding to the symbol s25 is delimited by the lines d1, d3, and d4. The line d4 is located equidistant between the symbol s17 and the symbol s25. The sector corresponding to the symbol s17 is delimited by the lines d4 and d5.For the case ^0 = 1, it is then possible to determine in which sector the image of the symbol ^ is located in the first quadrant by verifying five inequalities corresponding to the five lines d1 to d5, each inequality being written in the form: [Math.2]. Figure 10 is a representation of the Voronoi sectors of the symbols s0, s8, s16, and s24 in the first quadrant of the constellation for which the bit ^0 is equal to '0'. The sector corresponding to the symbol s0 is delimited by the lines d6 and d9. The line d6 is located equidistant between the symbol s0 and the symbol s8. The line d9 is located equidistant between the symbol s0 and the symbol s16. The sector corresponding to the symbol s8 is delimited by the lines d6, d7, and d10. The line d7 is located equidistant between the symbol s8 and the symbol s24. The line d10 is located equidistant between the symbol s8 and the symbol s16. The sector corresponding to the symbol s24 is delimited by the lines d7 and d8. The line d8 is located equidistant between the symbol s16 and the symbol s24. The sector corresponding to the symbol s16 is delimited by the lines d8, d9 and d10.For the case ^0 = 0, it is then possible to determine in which sector the image of the symbol ^ is located in the first quadrant by verifying five inequalities corresponding to the five lines d6 to d10, each inequality being written in the form: [Math.3]. Figure 12 is a representation of the Voronoi sectors of the symbols s9, s25, s8 and s24 of the first quadrant of the constellation for which the bit ^ Eis equal to '1'. The sector corresponding to the symbol s9 is bounded by the line d1. The sector corresponding to the symbol s25 is bounded by the lines d1 and d11. The line d11 is located equidistant between the symbols s25 and s8. The sector corresponding to the symbol s8 is bounded by the lines d7 and d11. The sector corresponding to the symbol s24 is bounded by the line d7. For the case ^E = 1, it is then possible to determine in which sector the image of the symbol ^ is located in the first quadrant by verifying three inequalities corresponding to the three lines d1, d7, and d11, each inequality being written in the form: [Math.4] Figure 13 is a representation of the Voronoi sectors of the symbols s0, s1, s16 and s17 of the first quadrant of the constellation for which the bit ^ Eis equal to '0'. The sector corresponding to the symbol s1 is bounded by the lines d5 and d13. The line d13 is located equidistant between the symbols s0 and s1. The sector corresponding to the symbol s0 is bounded by the lines d9, d12, and d13. The line d12 is located equidistant between the symbols s0 and s17. The sector corresponding to the symbol s16 is bounded by the lines d9 and d14. The line d14 is located equidistant between the symbols s16 and s17. The sector corresponding to the symbol s17 is bounded by the lines d5, d12, and d14. For the case ^E = 0, it is then possible to determine in which sector the image of the symbol ^ is located in the first quadrant by verifying five inequalities corresponding to the five lines d5, d9, d12, d13 and d14, each inequality being written in the form: [Math.5] Figure 15 is a representation of the Voronoi sectors of the symbols s25, s17, s16 and s24 of the first quadrant of the constellation for which the bit ^ F is equal to '1'. The sector corresponding to the symbol s25 is bounded by the lines d4, d15, and d16. The line d15 is located equidistant between the symbols s25 and s16. The line d16 is located equidistant between the symbols s25 and s24. The sector corresponding to the symbol s17 is bounded by the lines d4 and d14. The sector corresponding to the symbol s16 is bounded by the lines d8, d14, and d15. The sector corresponding to the symbol s24 is bounded by the lines d8 and d16. For the case ^ F= 1, it is then possible to determine in which sector the image of the symbol ^ is located in the first quadrant by verifying five inequalities corresponding to the five lines d4, d8, d14, d15 and d16, each inequality being written in the form: [Math.6] Figure 16 is a representation of the Voronoi sectors of the symbols s0, s1, s8 and s9 of the first quadrant of the constellation for which the bit ^ Fis equal to '0'. The sector corresponding to the symbol s0 is bounded by the lines d6, d13, and d18. The line d18 is located equidistant between the symbol s0 and the symbol s9. The sector corresponding to the symbol s1 is bounded by the lines d2 and d13. The sector corresponding to the symbol s8 is bounded by the lines d6 and d17. The line d17 is located equidistant between the symbol s8 and the symbol s9. The sector corresponding to the symbol s9 is bounded by the lines d2, d17, and d18. For the case ^F = 0, it is then possible to determine in which sector the image of the symbol ^ is located in the first quadrant by verifying five inequalities corresponding to the five lines d2, d6, d13, d17, and d18, each inequality being written in the form: [Math.7] In Figures 9, 10, 12, 13, 15, and 16, some sectors appear open. However, it should be considered that these sectors are also delimited by a line representing a maximum value for the real part and / or by a line representing a maximum value for the imaginary part. The steps of classifying 101 the symbol bits and determining 102 the pairs 478, 985 are, for example, carried out during the design of the receiving device 20, based on the constellation of the intended modulation. Then, as illustrated in Figure 1, for each received symbol ^, method 100 includes the following steps to unmap the symbol. For each bit of the symbol ^ belonging to the first group, method 100 includes a calculation 103 of the LLR for that bit in the form of a product between a multiplicative factor and a real part ^$4^5 or an imaginary part =>4^5 of the symbol ^.More specifically, the LLR of bit ^2 (which has symmetry with respect to the x-axis) can be calculated in the form: [Math.8]. and the LLR of the bit ^ # (which has symmetry with respect to the y-axis) can be calculated in the form: [Math.9] " # is an estimated value of the variance of a white Gaussian noise in the propagation channel of a signal carrying the symbol ^ (it is conventionally assumed that the receiving device 20 is equipped with a noise estimator that allows this value to be determined). - is a weighting parameter whose optimal value can be found empirically; for example, the value - =# is used. √20Figure 6 is a graph representing the calculated LLR value of bit ^2, as a function of the value of the imaginary part of the symbol, for the ML method and for method 100 according to the invention. It can be observed that the results obtained for the two methods are relatively close, and that the loss of precision due to the approximation of the calculation is quite acceptable given the resulting simplification of complexity. To gain precision, it is also possible to perform a multi-part linear interpolation, using at least two possible values ​​for the parameter - depending on the value of the real part ^$4^5 or the imaginary part =>4^5 of the symbol ^. This amounts to performing a linear interpolation with several slopes; the slope values ​​are the same for the bit where the real part of the symbol is used and for the bit where the imaginary part is used.Figure 7 illustrates this particular method of implementation for the calculation of ^^^4^25, with two values ​​for the parameter - depending on the value of the imaginary part =>4^5 of the symbol ^: one value. when the imaginary part is less than or equal to 0.5 and a value - # when the imaginary part is greater than 0.5. As illustrated in Figure 7, such arrangements allow for results closer to those of the ML method. This linear interpolation approach with two slopes increases accuracy at the cost of increased complexity (in particular, calibration may be necessary because the position of the slope change can vary depending on the amount of noise). In the example considered, = 0,4286and -# = 1.0712. Steps 104 to 108 shown in Figure 1 concern the bits of the second group. Step 104 corresponds to a verification of the 6 inequalities 78|^$4^5| + 98 ≤|=>4^5|, : ∈ ;1, 6<. In the example considered, each of these inequalities is associated with one of the lines d1 to d18. For each inequality associated with a line R ^ The inequality is true if the image of the ^ symbol in the first quadrant is located above the line in the first quadrant of the constellation, and the inequality is false if the image of the ^ symbol is located below the line in the first quadrant of the constellation. The result of verifying each of these 6 inequalities can be represented by a bit, with the bit taking the value '1' when the inequality is true and the value '0' when the inequality is false. The set of results obtained for the 6 inequalities can therefore be written as a bit field: [Math.10] where ^L( is a bit taking the value '1' when the inequality associated with the line R ^ is verified and the value '0' when the inequality is not verified. For each bit of the ^ symbol belonging to the second group, and for each value '0' or '1' that can be taken by this bit, method 100 then involves determining 105 a subset of the results obtained for the 6 inequalities. Each subset is defined in terms of the lines that define the Voronoi sectors for the case considered. Thus, for the case ^0 = 1, the subset of results is written in the form: [Math.11] For the case ^0 = 0, the subset of results is written in the form: [Math.12] For the case ^E = 1, the subset of results is written in the form: [Math.13] For the case ^E = 0, the subset of results is written in the form: [Math.14] ^.V / 0 = S^LX , ^L[ , ^L^) , ^L^V , ^L^WU For the case ^F = 1, the subset of results is written in the form: [Math.15] For the case ^F = 0, the subset of results is written in the form: [Math.16] In general, for a case denoted \^ corresponding to ^^ = 40|15, the subset of results can be noted : [Math.17] The value of 6 ]^ may vary for different cases (this depends on the number of inequalities to be checked to determine the Voronoi sector in the first quadrant for the case considered).6 ]^is less than 6. For each case, it is possible to determine which sector the image of the symbol ^ belongs to in the first quadrant by comparing the subset of results with different possible candidate values ​​(by focusing on certain bits of the subset of results for each sector). For example, for the case ^0 = 1, we can consider that the received symbol is in the sector corresponding to the symbol s9 if the inequalities corresponding to the lines d1 and d2 are satisfied, that is, if: [Math.18] ^.^ / 2 & ;1,1,0,0,0< == ;1,1,0,0,0 <L’opérateur & correspond à l’opérateur « ET bit à bit ». On peut par exemple associercette première égalité à un indice > = 1 (this amounts to associating the sector corresponding to the symbol s9 for the case ^0 = 1 with the index > = 1).Still for the case ^0 = 1, we can consider that the received symbol is in the sector corresponding to the symbol s1 if the inequalities corresponding to the lines d2 and d3 are not verified and if the one corresponding to the line d5 is verified, that is to say if: [Math.19] ^.^ / 2 & ;0,1,1,0,1< == ;0,0,0,0,1<On peut par exemple associer cette deuxième égalité à un indice > = 2 (this amounts to associating the sector corresponding to the symbol s1 for the case ^0 = 1 with the index > = 2). Similarly, we can consider that the received symbol is in the sector corresponding to the symbol s17 if the inequalities corresponding to the lines d4 and d5 are not satisfied, that is, if: [Math.20] ^.^ / 2 & ;0,0,0,1,1< == ;0,0,0,0,0<On peut par exemple associer cette troisième égalité à un indice > = 3 (this amounts to associating the sector corresponding to the symbol s17 for the case ^0 = 1 with the index > = 3).Finally, we can consider that the received symbol is in the sector corresponding to the symbol s25 if the inequality corresponding to the line d1 is not verified, and if the inequalities corresponding to the lines d3 and d4 are verified, that is to say if: [Math.21] ^.^ / 2 & ;1,0,1,1,0< == ;0,0,1,1,0<On peut par exemple associer cette quatrième égalité à un indice > = 4 (this amounts to associating the sector corresponding to the symbol s25 for the case ^0 = 1 with the index > = 4). For a received symbol, only one of the four equalities above is verified, and the corresponding index represents the Voronoi sector in which the received symbol is located. Similarly, we can identify in which sector the received symbol is located for the case ^0 = 0. More specifically, the symbol is located in the sector corresponding to the symbol s0, associated with an index A = 1, if: [Math.22] ^.^ / 0 & ;1,0,0,1,0< == ;0,0,0,1,0 <Le symbole se trouve dans le secteur correspondant au symbole s8, associé à un indiceA = 2, si :[Math.23] ^.^ / 0 & ;1,1,0,0,1< == ;1,1,0,0,1<Le symbole se trouve dans le secteur correspondant au symbole s16, associé à unindice A = 3, si :[Math.24] ^.^ / 0 & ;0,0,1,1,1< == ;0,0,1,0,0<Le symbole se trouve dans le secteur correspondant au symbole s24, associé à unindice A = 4, si :[Math.25] ^.^ / 0 & ;0,1,1,0,0< == ;0,0,0,0,0<La valeur du LLR pour le bit ^0peut alors être calculé sous la forme : [Math.26]. with j.^ / 24>5 is the symbol associated with the index > for the case ^0 = 1 (it is the constellation symbol closest to the symbol ^ for which ^0 = 1). j.^ / 2415 is the symbol 9; j .^ / 2 425 is the symbol s1; j .^ / 2 435 is the symbol s17; j .^ / 2445 is the symbol 25. j.^ / 04A5 is the symbol associated with the index A for the case ^0 = 0 (it is the symbol of the constellation closest to the symbol ^ for which ^0 = 0). j.^ / 0415 is the symbol 0; j .^ / 0 425 is the symbol s8; j .^ / 0 435 is the symbol s16; j .^ / 0 445 is the symbol s24. The indices > and A each take their value from the set ^0, 1, 2, 3^. As explained previously, the index > (respectively A) identifies the sector of the first quadrant corresponding to the received symbol for the case where the value of the bit in question is '1' (respectively for the case where the value of the bit in question is '0'). The reasoning developed above for the bit ^0 can be carried out similarly for the bits ^ E and ^ F In general, and as illustrated in Figure 1, method 100 involves, for each bit ^ ^of the symbol ^ belonging to the second group: -for each case denoted \^ corresponding to ^^ = 40|15, a determination 105 of a subset ^]^ results obtained for the 6 inequalities, and a comparison 106 of said subset of results with predetermined candidate values, - a selection 107 of a set of parameters i.^,d,em defined by an index > representing the candidate value corresponding to the subset of results for the case where the bit value is '1' and an index A representing the candidate value corresponding to the subset of results for the case where the bit value is '0' (the index > identifies the sector of the first quadrant for the case ^^ = 1, and the index A identifies the sector of the first quadrant for the case ^^ = 0), - a calculation 108 of the LLR for the bit ^ ^ depending on the selected parameters and depending on the real and imaginary parts of the symbol: [Math.27] with As we saw previously in detail for the bit ^0, the subset of results ^ ]^ and each candidate value q ]^,r are each defined as a 6-bit field, with 6 < 6. Comparing the subset with the candidate values ​​is equivalent to performing bitwise comparisons of the type: [Math.28] ^ ]^,r is a binary mask to apply to the result ^ ]^ , and q ]^,r is a predetermined candidate value. A mask and a candidate value are defined for each sector. v of the first quadrant for the case \ ^ considered. There is sectors in the first quadrant for each case. However, nothing would prevent implementing step 106 of comparison differently, for example by expressing ^ ]^ in decimal form and by identifying the different decimal values ​​that can be taken by ^ ]^in each sector of the first quadrant. The above description clearly illustrates that, through its various features and their advantages, the present invention achieves the stated objectives. In particular, the proposed solution does not use angle calculations, nor multiplication or division by non-constant values ​​(noise power normalization is not taken into account). In the example considered, for each symbol to be unmapped, method 100 comprises: - twenty-four additions (eighteen additions in formulas [Math.2] to [Math.7], and two additions in formula [Math.27] for each of the three bits of the second group), - twenty-six multiplications by constant values ​​(eighteen multiplications in formulas [Math.2] to [Math.7], two multiplications in formula [Math.27] for each of the three bits of the second group, and one multiplication in formulas [Math.8] and [Math.9] for each of the two bits in the first group), - eighteen comparisons in formulas [Math.2] to [Math.7], and - twenty-four bit-by-bit comparisons according to formula [Math.28] for each of the three bits in the second group. Furthermore, method 100 performs the same number of calculations to unmold a symbol, regardless of the received symbol. These characteristics are particularly interesting when the method is implemented by a unmold module 23 implemented on an FPGA target. The parameter values ​​-, 78, 98,. i .^,d,eThese can be determined during the design of the receiving device 20, depending on the intended constellation, and stored by the demapping module 23. Advantageously, the sets of steps 105 to 108 performed respectively for the different bits of the second group can be executed in parallel. Similarly, the steps 103 performed respectively for the different bits of the first group can be executed in parallel with each other and with the sets of actions 105 to 108 performed for the bits of the second group. It should be noted that the implementation and embodiment methods considered above have been described by way of non-limiting examples, and that other variants are therefore conceivable. The invention has been described with regard to a particular 32-APSK modulation.However, nothing prevents us, following other examples, from considering other constellations or other modulations (for example by changing the arrangement of symbols, the number of symbols, and / or the type of modulation).

Claims

Claims 1. A method (100) for unmapping a modulation symbol, said symbol representing several bits of information, the method for calculating a logarithmic likelihood ratio, LLR, for each bit of the symbol, the method (100) being implemented by a unmapping module (23) of a receiving device (20), the modulation having a symbol constellation with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group, the method (100) being characterized in that it comprises: a classification (101) of each symbol bit into the first group or into the second group, a determination (102) of 6 pairs 478, 985, : ∈ ;1, 6<, 6 being an integer strictly greater than one, the 6 pairs being distinct and each defining a slope 7 ^ and a y-intercept 9 ^of a straight line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation, for each bit of the symbol ^ belonging to the first group, a calculation (103) of the LLR for said bit in the form of a product between a multiplicative factor and a real part ^$4^5 or an imaginary part =>4^5 of the symbol ^, a verification (104) of 6 inequalities 78|^$4^5| + 98 ≤ |=>4^5|, : ∈ ;1, 6<,for each bit of the symbol ^ belonging to the second group: - for each value '0' or '1' that can be taken by the bit, a determination (105) of a subset of the results obtained for the 6 inequalities, and a comparison (106) of the subset of results with predetermined candidate values, - a selection (107) of a set of parameters defined by an index > representing the candidate value corresponding to the subset of results for the case where the value of the bit is '1' and an index A representing the candidate value corresponding to the subset of results for the case where the value of the bit is '0', - a calculation (108) of the LLR for the bit as a function of the selected parameters and as a function of the real and imaginary parts of the symbol.; 2. Method (100) according to claim 1 wherein the modulation is an APSK modulation in phase and amplitude, or a QAM modulation of quadrature amplitude.

3. Method (100) according to claim 2 wherein the modulation comprises 2 , symbols, ^ being an integer greater than or equal to four.

4. Method (100) of claim 3 wherein the modulation is APSK modulation, ^ is equal to five, and 6 is equal to eighteen.

5. Method (100) of any one of claims 1 to 4 wherein the modulation has a constellation defined in a DVB-S2, DVB-S2X, CCSDS, or 5G communication standard.

6. Method (100) of any one of claims 1 to 5 wherein, for each value equal to '0' or '1' that can be taken by a bit belonging to the second group, the subset of results and each candidate value are each defined as a field of bits, with < 6.

7. Method (100) according to any one of claims 1 to 6 wherein the multiplicative factor is calculated in the form # where " is an estimated value of a variance of additive white Gaussian noise of a propagation channel of a signal carrying the symbol ^.

8. Method (100) according to claim 7 in which - takes at least two possible values ​​depending on the value of the real part ^$4^5 or the imaginary part =>4^5 of the symbol ^.

9. Module (23) for unmapping a modulation symbol ^, said symbol representing several bits of information, the modulation having a constellation of symbols with half-plane symmetry for one or more symbol bits belonging to a first group, and quadrant symmetry for one or more symbol bits belonging to a second group, the unmapping module (23) being characterized in that it is configured to store 6 pairs 478, 985, : ∈;1, 6<, 6 being an integer strictly greater than one, the 6 pairs being different two by two, each defining a slope 7 ^ and a y-intercept 9^of a straight line forming an edge of a Voronoi sector defined for a symbol bit belonging to the second group and taking the value '0' or the value '1' in a first quadrant of the constellation, and to implement the following steps: for each bit of the symbol ^ belonging to the first group, a calculation (103) of a logarithmic likelihood ratio, LLR, for said bit in the form of a product between a multiplicative factor and a real part ^$4^5 or an imaginary part =>4^5 of the symbol ^, a verification (104) of 6 inequalities 78|^$4^5| + 98 ≤ |=>4^5|, : ∈ ;1, 6<, for each bit of the ^ symbol belonging to the second group: - for each '0' or '1' value that can be taken by the bit, a determination (105) of a subset of the results obtained for the 6 inequalities, and a comparison (106) of the subset of results with predetermined candidate values, - a selection (107) of a set of parameters defined by an index > representing the candidate value corresponding to the subset of results for the case where the value of the bit is '1' and an index A representing the candidate value corresponding to the subset of results for the case where the value of the bit is '0', - a calculation (108) of an LLR for the bit as a function of the selected parameters and as a function of the real and imaginary parts of the symbol.

10. Demapping module (23) according to claim 9, wherein the modulation is an APSK modulation in phase and amplitude, or a QAM amplitude quadrature modulation, comprising 2; ,symbols, ^ being an integer greater than or equal to four.

11. Demapping module (23) according to claim 10, wherein the modulation is APSK modulation, ^ is equal to five, and 6 is equal to eighteen.

12. Demapping module (23) according to any one of claims 9 to 11, wherein, for each value equal to '0' or '1' that can be taken by a bit belonging to the second group, the subset of results and each candidate value are each defined as a bit field, with 6.^ / ^0B1^ < 6.

13. Demapping module (23) according to any one of claims 9 to 12, wherein the multiplicative factor is calculated in the form , where " is an estimated value of a standard deviation of additive white Gaussian noise of a propagation channel of a signal carrying the symbol ^.

14. Demapping module (23) according to claim 13 wherein - takes at least two possible values ​​depending on the value of the real part ^$4^5 or the imaginary part =>4^5 of the symbol ^.

15. Receiving device (20) comprising a demapping module (23) according to any one of claims 9 to 14.

16. Satellite (10) comprising a receiving device (20) according to claim 15.

17. Ground station comprising a receiving device according to claim 15.

18. Communication system comprising at least one satellite according to claim 16 and / or at least one ground station according to claim 17.

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