In-situ cleaning of dry-etched semiconductor mesas for overgrown structures

Abstract

A method is provided for preparing a semiconductor wafer for fabricating a semiconductor heterostructure device, or for fabricating the semiconductor heterostructure device on the semiconductor wafer. The method comprises dry etching at least one epitaxial layer to produce a dry-etched semiconductor wafer defining a mesa structure. Then, an etchant gas is flowed through a reaction chamber to remove material from sidewalls of the mesa structure and thereby produce a cleaned semiconductor wafer in which the sidewalls of the mesa structure undercut a mask layer and have reduced surface defects in comparison to the sidewalls of the mesa structure of the dry-etched semiconductor wafer. Then, an overgrowth layer is grown on the sidewalls of the mesa structure of the cleaned semiconductor wafer.

Description

IN-SITU CLEANING OF DRY-ETCHED SEMICONDUCTOR MESAS FOR OVERGROWN STRUCTURESFIELD OF THE DISCLOSURE

[0001] This disclosure relates to methods for fabricating semiconductor heterostructure devices, such as buried heterostructure (BH) lasers and BH semiconductor optical amplifiers (SOAs).BACKGROUND OF THE DISCLOSURE

[0002] International patent application publication WO 2022 / 058963 A1 (National Research Council of Canada; 24 March 2022) (hereinafter "Einabad et al.") describes a prior art method of manufacturing a semiconductor buried heterostructure laser, as illustrated in Figs. 1 (a) to 1 (e).

[0003] First, a semiconductor wafer of stacked layers, including an n-type substrate 100, active region 110 and p-type layer 120, is epitaxially grown on the substrate layer 100 (Fig. 1 (a)). Then, a dielectric mask 130 is patterned and the wafer is etched through the active region 110 forming a narrow mesa 140 (Fig. 1 (b1 )). Conventionally, the etching process resulting in the structure of Fig. 1 (b1 ) is either a dry reactive ion etch or a wet etch.

[0004] Next, the semiconductor wafer is loaded in a growth tool and blocking layers 150 and 160 are grown as a p-n junction, followed by a further thin p-type layer 170, resulting in the p-n-p layer sequence shown in Fig. 1 (b2). Conventionally, the growth of blocking layers resulting in the structure of Fig. 1 (b2) is carried out after a wet preclean process to remove etch damage and / or surface oxide.

[0005] Next, the dielectric mask 130 is removed and after a preclean process, the wafers are loaded in a growth tool and a final p-type overclad layer 180 and p-contact layer 185 are grown such that the p-type layers 170 and 180 merge to form an overall n-p-n-p structure (Fig. 1 (c)).

[0006] Next, the wafer is patterned, and an isolation etch is carried out through layers 150, 160, 170, 180 and 185 to form a larger mesa 190 (Fig. 1 (d )) . Conventionally, this etch is either carried out via a reactive ion etch process or a wet etch process.

[0007] Finally, the n-type substrate 100 is thinned and dielectric cladding layer 194, p-metal deposition layer 196 and backside n-metal deposition layer 198 are deposited (Fig. 1 (e)).

[0008] The narrow mesa etch (Fig. 1 (b)), and isolation etch (Fig. 1 (d)) can be performed as either dry-dry processes, respectively; wet-wet processes, respectively or wet-dry processes, respectively. The main drawback with the use of wet etch processes is that they may introduce large variations in the widths of the mesas 140 and 190, leading to device failure and yield loss.

[0009] Dry etching is comparatively advantageous by allowing for better controlled and smoother etching without dependence on layer composition. The main drawback with dry-etch processes is that they can cause surface defects on the sidewall surfaces of the mesa structure. These surface defects impair the quality of the regrowth interface for the overgrown blocking layers, and may lead to performance and degradation and reliability issues of the BH laser over its lifetime. (See: Y. Takino, M. Shirao, T. Sato, N. Nishiyama and S. Arai, "Investigation of regrowth interface quality of AIGalnAs / lnP buried heterostructure lasers," 2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM), 2010, pp. 1-4; Huang, Jia-Sheng. "Design-in Reliability for Modern Wavelength-division Multiplex (WDM) Distributed Feedback (DFB) InP Lasers." Applied Physics research 4 (2012): 15. See also: Sakata, Yasutaka et al. "All-selective MOVPE-grown 1 .3 pm strained multi-quantum- well buried-heterostructure laser diodes." IEEE Journal of Quantum Electronics 35 (1999): 368-376.)

[0010] There remains a need in the art to mitigate the damage to the regrowth interface caused by use of dry etching processes to define the mesa structures.SUMMARY OF THE DISCLOSURE

[0011] In one aspect, a method for preparing a semiconductor wafer for fabricating a semiconductor heterostructure device, or for fabricating the semiconductor heterostructure device on the semiconductor wafer, wherein the semiconductor wafer comprises a substrate layer having at least one epitaxial layer disposed on the substrate and a mask layer for defining a mesa structure and disposed on the at least one epitaxial layer, the method comprising:dry etching the at least one epitaxial layer to produce a dry-etched semiconductor wafer defining the mesa structure; and placing the semiconductor wafer in a rection chamber, and flowing an etchant gas through the reaction chamber to remove material from sidewalls of the mesa structure and thereby produce a cleaned semiconductor wafer in which the sidewalls of the mesa structure undercut the mask layer and have reduced surface defects in comparison to the sidewalls of the mesa structure of the dry-etched semiconductor wafer.BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the embodiment(s) described herein and to show more clearly how the embodiment(s) may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings.

[0013] Figs. 1 (a) to 1 (e) show stages of fabrication of a heterostructure device, according to the prior art. Fig. 1 (a) shows a semiconductor wafer having a substrate layer with epitaxially grown layers. Fig. 1 (b1 ) shows the semiconductor wafer after a mesa etch step. Fig. 1 (b2) shows the semiconductor wafer after overgrowth of blocking layers and additional layers. Fig. 1 (c) shows the semiconductor wafer after overgrowth of further additional layers. Fig. 1 (d) shows the semiconductor wafer after an isolation etch step. Fig. 1 (e) shows the semiconductor wafer after a metal layer deposition step.

[0014] Figs. 2(a) to 2(e) show stages of fabrication of a heterostructure device, according to an embodiment of a method of the present disclosure. Fig. 2(a) shows a semiconductor wafer having a substrate layer with epitaxially grown layers. Fig. 2(b1 ) shows the semiconductor wafer after a mesa etch step. Fig. 2(b2) shows the semiconductor wafer after overgrowth of blocking layers and additional layers and a cleaning step of Fig. 3(b). Fig. 2(c) shows the semiconductor wafer after overgrowth of further additional layers. Fig. 2(d) shows the semiconductor wafer after an isolation etch step. Fig. 2(e) shows the semiconductor wafer after a metal layer deposition step.

[0015] Figs. 3(a) to 3(c) show stages of fabrication of a heterostructure device, according to an embodiment of a method of the present disclosure. Fig. 3(a) showsthe dry-etched semiconductor wafer. Fig. 3(b) shows the cleaned semiconductor wafer. Fig. 3(c) shows the cleaned semiconductor wafer with an overgrowth layer.

[0016] Fig. 4 shows steps in a method for fabricating a heterostructure device for Figs. 3(a) to 3(c), according to an embodiment of the present disclosure.

[0017] Figs. 5(a) to 5(c) are SEM images showing a semiconductor wafer during stages of an embodiment of a method of the present disclosure. Fig. 5(a) shows the dry-etched semiconductor wafer after a wet pre-clean step. Fig. 5(b) shows the cleaned semiconductor wafer. Fig. 5(c) shows the cleaned semiconductor wafer with an overgrowth layer.

[0018] Fig. 6 is a graph showing input current and output power for BH laser diodes fabricated according to an embodiment of a method of the present disclosure.

[0019] Fig. 7 is a graph showing life test data of threshold current versus time for BH laser diodes fabricated according to an embodiment of a method of the present disclosure.

[0020] Fig. 8 is a graph showing life test data of time-to-failure versus the inverse of a cumulative distribution function (CDF) for BH laser diodes fabricated according to an embodiment of a method of the present disclosure.

[0021] Fig. 9 is a table showing values of process conditions used for the cleaning step in embodiments of a method of the present disclosure.

[0022] Figs. 10(a) to 10(c) are SEM images showing a semiconductor wafer during stages of an embodiment of a method of the present disclosure, using the high temperature, low PH3 flow rate, and low time process conditions of Fig. 9. Fig. 10(a) shows the dry-etched semiconductor wafer after a wet pre-clean. Fig. 10(b) shows the cleaned semiconductor wafer. Fig. 10(c) shows the cleaned semiconductor wafer with an overgrowth of blocking layers.

[0023] Figs. 11 (a) and 11 (b) are SEM images showing heterostructure devices fabricated according to an embodiment of the method of the present disclosure, using the high temperature (Fig. 11 (a)) and low temperature (Fig. 11 (b)), low PH3 flow rate, and low time process conditions of Fig. 9.

[0024] Fig. 12 is a table showing values of process conditions used for an annealing step for treating a dry-etched semiconductor wafer, and / or a cleaning step in embodiments of the method of the present disclosure.

[0025] Figs. 13(a) and 13(b) are SEM images of cleaned semiconductor wafers fabricated using process conditions of case no. 5 and 7, respectively, of Fig. 12.

[0026] Figs. 14(a) and 14(b) are SEM images of annealed semiconductor wafers fabricated using process conditions of case no. 4 and 1 , respectively, of Fig. 12.

[0027] Figs. 15(a) and 15(b) are SEM images of cleaned semiconductor wafers fabricated using process conditions of case no. 6 and 8, respectively, of Fig. 12.

[0028] Figs. 16(a) and 16(b) are SEM images of annealed, and annealed and cleaned, semiconductor wafers fabricated using process conditions of case no. 3 and 2 respectively, of Fig. 12.

[0029] Figs. 17(a) and 17(b) are SEM images of cleaned semiconductor wafers fabricated using process conditions of case no. 6 and 8, respectively, of Fig. 12.DETAILED DESCRIPTION OF THE DISCLOSURE

[0030] The present disclosure relates to a method for fabricating semiconductor heterostructure devices. Any term or expression not expressly defined herein shall have its commonly accepted definition understood by a person skilled in the art.

[0031] As used herein, the term "heterostructure device" refers to a semiconductor structure having at least one interface between semiconductor materials of different compositions. Non-limiting examples of heterostructure devices that may fabricated using the method of the present disclosure include buried heterostructure (BH) semiconductor laser diodes, BH semiconductor optical amplifiers (SOAs), and other semiconductor opto-electronic devices such as optical modulators. The method of the present disclosure may be applied to fabricate a variety of different types of heterostructure devices, and is not limited to the examples provided herein.

[0032] Figs. 2(a) to 2(e) in conjunction with Figs. 3(a) to 3(c) and the method of Fig. 4 show stages and steps of fabrication of a BH Fabry-Perot (FP) laser diode, according to an embodiment of a method of the present disclosure.

[0033] In this embodiment, a semiconductor wafer of stacked of layers, includes a substrate layer 200 (e.g., indium phosphide (InP)) of first dopant type (e.g. n-type), and active region 210 and layer 220 of second dopant type (e.g. p-type) epitaxially grown on the substrate layer 200 (Fig. 2(a)). A dielectric mask layer 230 (as shown in Fig. 2(b1 )) is patterned and deposited on the layer 220 of second dopant. In other embodiments, the semiconductor wafer may include one or more ballast layers (not shown).

[0034] The foregoing processes may be performed to fabricate the semiconductor wafer shown in Fig. 2(a) with a mask layer 230 (as shown in Fig. 2(b 1 )) using a variety of known epitaxial growth techniques. Then, the fabricated semiconductor wafer may be placed in a reaction chamber used in subsequent steps. Alternatively, the foregoing processes may be performed using epitaxial growth techniques to fabricate the semiconductor wafer in situ of a same reaction chamber that is used to perform subsequent steps of the method to the extent possible. This is advantageous for continuity of workflow, with subsequent processes performed using the reaction chamber. In the embodiment described below, the epitaxial growth techniques used include metal organic chemical vapor deposition (MOCVD) performed in a MOCVD reaction chamber. In other embodiments of the method, reaction chambers used for other epitaxial growth techniques may be used.

[0035] Stated more generally, as shown in Fig. 3(a) and step 400 of Fig. 4, the semiconductor wafer in Fig. 2(a) comprising a substrate layer 200, at least one epitaxial layer (e.g., active region 210 and layer 220) disposed on the substrate layer 200 and a mask layer 230 disposed on the at least one epitaxial layer is provided in a first reaction chamber (e.g., MOCVD reaction chamber 300).

[0036] Next, at step 402 of Fig. 4, the semiconductor wafer is removed from the MOCVD reaction chamber 300 to form an oxide mask thereon to be used to produce a narrow mesa structure. The semiconductor wafer with the oxide mask is then moved to a vacuum chamber and dry-etched through the at least one epitaxial layer (e.g.,active region 210 and layer 200) to produce a narrow mesa structure 240 (Fig. 2(b1 )). The resulting semiconductor wafer structure after this step is hereinafter referred to as a "dry-etched semiconductor wafer" to distinguish it from the semiconductor wafer before step 402. As used herein, the term "dry etch" or "dry etching" refers to a process in which a bombardment of ions (e.g., a plasma of reactive gas(es)) is targeted toward the semiconductor wafer to remove material from the semiconductor wafer. This process may also be referred to as a “reactive ion etch” .

[0037] Optionally, at step 404 of Fig. 4, the dry-etched semiconductor wafer may be subjected to a wet pre-clean step, such as on a wet bench in a fume hood. That is, the dry-etched semiconductor wafer is exposed to an acid or another reactive chemical to remove some etch damage and / or surface oxide.

[0038] Notwithstanding the optional wet pre-clean step, the sidewalls of the narrow mesa structure 240 of the dry-etched semiconductor wafer may have surface defects due to damage caused by dry etching of the narrow mesa structure 240, or damage due to atmospheric contamination. These surface defects are shown in an exaggerated manner by the jagged lines of the sidewalls shown in Fig. 3(a). These surface defects may impair the quality of the sidewalls of the narrow mesa structure 240 for use as a regrowth surface for layers to be overgrown on them, which may degrade the performance and the reliability of the BH laser diode.

[0039] To reduce these surface defects and prepare the sidewalls of the mesa structure as an interface for overgrowth layers, a cleaning step is therefore performed. As shown in Fig. 3(b) and step 406 of Fig. 4, the semiconductor wafer is returned to the MOCVD reaction chamber 300, and an etchant gas is flowed through the MOCVD reaction chamber 300 to remove material from sidewalls of the narrow mesa structure 240 such that the etched sidewalls of the narrow mesa structure 240 has an undercut 250 of the mask layer 230 and reduced surface defects in comparison to the sidewalls of the narrow mesa structure 240 of the dry-etched semiconductor wafer. That is, the sidewalls of the narrow mesa structure 240 after this cleaning step 406 may be relatively smoother and have less surface defects that than the sidewalls of the narrow mesa structure 240 of the dry-etched semiconductor wafer before the cleaning step 406. The resulting semiconductor wafer after the cleaning step 406 is hereinafter referred to as a "cleaned semiconductor wafer" to distinguish it from the dry-etchedsemiconductor wafer before the cleaning step 406. In step 406 of Fig. 4, it is stated that the etchant gas is flowed through a "second" reaction chamber, which may be the same as or different from the "first" reaction chamber used in step 400 of Fig. 4. As a non-limiting example, the size of the undercut (i.e., in Fig. 3(b) measured by the horizontal overhang of the outer edge of the mask layer 230 from the face of the underlying epitaxial layer such as layer 220) may be about 100 nm to about 200 nm.

[0040] The etchant gas may be flowed through the MOCVD reaction chamber 300 via a gas inlet and exhaust gas outlet, assisted with a process pump (not shown), as are typically provided with a MOCVD reaction chamber 300. The person of ordinary skill in the art will be able to select appropriate process conditions to control the rate and amount of material that is removed from the sidewalls of the narrow mesa structure 240, and to reduce surface defects on the sidewalls of the narrow mesa structure 240.

[0041] One process condition of the cleaning step 406 is the composition of the etchant gas, which may be selected having regard to the semiconductor material forming the mesa structure to be cleaned. Non-limiting examples of etchant gases that may be used may comprise chlorine, bromine, or iodine (e.g., chlorine gas (Ch), bromine gas (Br2), or fluorinated compounds, chlorinated or brominated gas species, such as bromotrichloromethane (CBrCh), carbon tetrachloride (CCU), terbium(lll) chloride (TbCI)). Other etchant gases known in the art may also be used.

[0042] In embodiments of the method, a mixture of the etchant gas and a carrier gas may be flowed through the MOCVD reaction chamber 300. As a non-limiting example, the carrier gas may include hydrogen or nitrogen, that is compatible for an indium phosphide (InP) based semiconductor wafer. The mixture may include phosphine PH3 for the overpressure during the etching. Other carrier gases may be selected for compatibility with the composition of semiconductor wafer.

[0043] Another process condition of the cleaning step 406 is the flow rate of the gas mixture of the etchant gas and the carrier gas through the reaction chamber, which may be controlled by the operation of a mass flow controller. A process pump of the MOCVD reaction chamber 300 may be used to control the overall pressure inside the MOCVD reaction chamber 300. In a non-limiting embodiment, the gas mixture may beflowed through the MOCVD reaction chamber 300 at a flow rate of between 800 seem (standard cubic centimeter per minute) and 3000 seem.

[0044] Another process condition of the cleaning step 406 is the time period for which the etchant gas is flowed through the MOCVD reaction chamber 300. This time period multiplied by the flow rate of the etchant gas dictates the total amount of etchant gas that is exposed to the mesa structure over the time period. In a non-limiting embodiment, the time period may be between 5 second and 900 seconds, and more particularly between 150 seconds and 900 seconds.

[0045] Another process condition of the cleaning step 406 is the temperature of the dry-etched semiconductor wafer, which may be controlled by the operation of heating elements of the support stage of the MOCVD reaction chamber 300. In a non-limiting embodiment, the temperature may be between 500 degrees Celsius and 700 degrees Celsius, more particularly between 560 degrees Celsius and 670 degrees Celsius, and more particularly 625 degrees Celsius.

[0046] Effects of the foregoing process conditions of the cleaning step are further discussed in Examples no. 2 to 4 described below.

[0047] After the cleaning step, blocking layers 250, 260 and 270, are immediately grown within the MOCVD reaction chamber 300, without any need to transfer the semiconductor wafer and therefore no exposure to oxygen, resulting in the n-p-n- layer sequence shown in Fig. 2(b2). Stated more generally, as shown in Fig. 3(c) and step 408 of Fig. 4, at least one overgrowth layer (e.g., blocking layers 250, 260 and 270) are grown on the sidewalls of the mesa structure (e.g., narrow mesa structure 240) of the cleaned semiconductor wafer.

[0048] The semiconductor wafer is removed from the MOCVD reaction chamber 300 and the dielectric mask 230 is removed ex situ. The semiconductor wafer is then returned to the MOCVD reaction chamber 300 and a final p-type overclad layer 280 and p-contact layer 285 are grown (Fig. 2(c)) in a separate MOCVD step. Then, the semiconductor wafer is patterned, and an isolation etch is carried out through layers 250, 260, 270, 280 and 285 to form a larger mesa structure 290 (Fig. 2(d)). Conventionally, the isolation etch is either carried out via a combination of a reactive ion etch process in a vacuum chamber, and a wet etch process such as on a wetbench in a fume hood. Finally, the p-type deposition layer 296 is deposited, the n-type substrate layer 200 is thinned and dielectric cladding layer 294, and backside n-metal deposition layer 298 are deposited to form a deeper mesa (Fig. 2(e)).

[0049] Alternative Embodiments

[0050] The method illustrated by Fig. 4 may be applied to alternative workflows for epitaxial growth processes to produce different heterostructure devices on a semiconductor wafer. Non-limiting examples of such workflows and devices include those described in international patent application publication W02020 / 124205 A1 (National Research Council of Canada; 25 June 2020) and WO2021 / 113981 A1 (National Research Council of Canada; 17 June 2021 ), the entire contents of which are incorporated herein by reference, where permitted.

[0051] Examples

[0052] The following examples illustrate applications of the method shown in Fig. 4.

[0053] Example no. 1

[0054] Figs. 5(a) to 5(c) are SEM images showing a semiconductor wafer during stages of the method for fabricating a BH laser diode. Fig. 5(a) shows the dry-etched semiconductorwaferaftera wet pre-clean. Fig. 5(b) shows the cleaned semiconductor wafer. Fig. 5(c) shows the cleaned semiconductor wafer with an overgrowth of blocking layers.

[0055] The fabricated BH laser diodes were subjected to accelerated life testing. The testing results are shown in terms of measured relationships between input current and output power (Fig. 6), threshold current versus time (Fig. 7), time-to-failure versus the inverse of a cumulative distribution function (CDF) (Fig. 8). The fabrication method of the present disclosure improved the degradation rate of the BH laser diodes from 0.5 - 1 pA / h to 0.16 pA / h (i.e. , deceased by a factor of about 3 to 10). In other examples the degradation rate of the BH laser diode was decreased to as low as 0.03 pA / h. The degradation rate of the best BH laser diodes is comparable to or better than the degradation rate (0.15 pA / h) of BH laser diodes having a fully in-situ etched mesa.Further, the median time to failure of the fabricated BH laser diodes was about 87600 hours.

[0056] Example no. 2

[0057] Fig. 9 is a table showing values of process conditions used for the cleaning step 406 in a method of the present disclosure. These process conditions are the temperature of the semiconductor wafer, the flow rate of the gas mixture of etchant gas and phosphine gas, and the time period for which the gas mixture was flowed through the MOCVD reaction chamber during the cleaning step. In experiments, the product of the flow rate and the time period were kept constant.

[0058] Example no. 3

[0059] Further experiments were performed using two sets of process conditions to study the effect of temperature of the semiconductor wafer during the cleaning step 406. The first set of process conditions were high temperature, high PH3 flow rate and low time process conditions of Fig. 9. The second set of process conditions were low temperature, high PH3 flow rate and low time process conditions of Fig. 9.

[0060] Figs. 10(a) to 10(c) are SEM images showing a semiconductor wafer during stages of a method of the present disclosure, using the high temperature process conditions during the cleaning step 406. Fig. 10(a) shows the dry-etched semiconductor wafer after a wet pre-clean. Fig. 10(b) shows the cleaned semiconductor wafer. Fig. 10(c) shows the cleaned semiconductor wafer with an overgrowth of blocking layers. Referring to Fig. 10(b), some residues 1100 were visible on sidewalls of some but not all of the mesas, after the cleaning step 406. Referring to Fig. 10(c), however, the residues were no longer visible after the overgrowth of the blocking layers.

[0061] Figs. 11 (a) and 11 (b) are SEM images showing heterostructure devices fabricated using the high temperature conditions and the low temperature conditions, respectively, during the cleaning step 406. The high temperature conditions resulted in a reduction of mesa structure width at the multiple quantum well (MQW) (Fig. 12(a)), whereas the low temperature conditions did not (Fig. 11 (b)). Further, the high temperature conditions resulted in the sidewalls of the mesa structure having ashallower slope (Fig. 11 (a)) than the sidewalls of the mesa structure (Fig. 11 (b)) resulting from use of the low temperature conditions. These experiments suggest that use of higher temperatures may be advantageous for removing material from the sidewalls of mesa structures for reducing surface defects.

[0062] Example no. 4

[0063] Experiments were performed to try to select process conditions for the cleaning step 406 that would reduce or eliminate the residues 1100 observed in the example shown in Fig. 10(b). For comparative purposes, these experiments included annealing the dry-etched mesa structure without performing the cleaning step 406 of the method of the present disclosure, and annealing the dry-etched mesa structure before performing the cleaning step 406 of the method of the present disclosure. Fig. 12 is a table showing values of process conditions used for the annealing step and / or the cleaning step 46.

[0064] Figs. 13(a) and 13(b) are SEM images of cleaned semiconductor wafers fabricated using process conditions of case no. 5 and 7, respectively, of Fig. 12. Defects were still observed with higher PH3 flow rate, and were worse at higher times (Fig. 13(b)). Higher PH3 flow rates of 2000 seem resulted in a reduced undercut of the mesa structure, as compared with lower PH3 flow rates of 1600 seem used in other experimental cases.

[0065] Figs. 14(a) and 14(b) are SEM images of annealed semiconductor wafers fabricated using process conditions of case no. 4 and 1 , respectively, of Fig. 12. The annealing step reduced the kink at the top of the mesa structure, but roughened it near Q layers. The longer anneal (Fig. 14(b)) roughened all surfaces.

[0066] Figs. 15(a) and 15(b) are SEM images of cleaned semiconductor wafers fabricated using process conditions of case no. 6 and 8, respectively, of Fig. 12. Use of the cleaning step 406 at a semiconductor wafer temperature of 625°C produced an optimal morphology, and resulted in a significant undercut. A significant undercut may be indicative that, in the cleaning step 406, the etchant gas was effective in removing material from the sidewalls to reduce surface defects of the sidewalls.

[0067] Figs. 16(a) and 16(b) are SEM images of dry-etched semiconductor wafers after an annealing step (Fig. 16(a)), and after annealing and cleaning steps (Fig. 16(b)) fabricated using process conditions of case no. 3 and 2, respectively, of Fig. 12. An annealing step followed by the cleaning step 406 (Fig. 16(b)) did not improve the morphology of the mesa structure as compared with an annealing step alone (Fig. 16(a)).

[0068] Figs. 17(a) and 17(b) are SEM images of cleaned semiconductor wafers fabricated using process conditions of case no. 3 and 2, respectively, of Fig. 12. The cleaning step 406 at a semiconductor wafer temperature of 625°C was found to be optimal in terms of morphology, and resulted in a waveguide width of about 1 .6 pm at the multiple quantum well (MQW).

[0069] Interpretation

[0070] The many features and advantages of the present disclosure are apparent from the detailed specification and, thus, it is intended by the appended claims to cover all such features and advantages of the present disclosure that fall within the scope of the present disclosure. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the present disclosure to the exact construction and operation illustrated and described, and accordingly all suitable modifications and equivalents may be resorted to, falling within the scope of the present disclosure.

[0071] The singular forms "a," "an", and "the" include the plural reference unless the context clearly dictates otherwise. The term "and / or" means any one of the items, any combination of the items, or all of the items with which this term is associated.

[0072] All ranges recited herein also encompass any and all possible sub-ranges and combinations of sub-ranges thereof, as well as the individual values making up the range, particularly integer values. A recited range includes each specific value, integer, decimal, or identity within the range. Any listed range can be easily recognized as sufficiently describing and enabling the same range being broken down into at least equal halves, thirds, quarters, fifths, or tenths. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc.

[0073] A recited range includes each specific value, integer, decimal, or identity within the range. Any listed range can be easily recognized as sufficiently describing and enabling the same range being broken down into at least equal halves, thirds, quarters, fifths, or tenths. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc.

Claims

CLAIMS1 . A method for preparing a semiconductor wafer for fabricating a semiconductor heterostructure device, or for fabricating the semiconductor heterostructure device on the semiconductor wafer, wherein the semiconductor wafer comprises a substrate layer having at least one epitaxial layer disposed on the substrate and a mask layer for defining a mesa structure and disposed on the at least one epitaxial layer, the method comprising: dry etching the at least one epitaxial layer to produce a dry-etched semiconductor wafer defining the mesa structure; and placing the semiconductor wafer in a reaction chamber, and flowing an etchant gas through the reaction chamber to remove material from sidewalls of the mesa structure and thereby produce a cleaned semiconductor wafer in which the sidewalls of the mesa structure undercut the mask layer and have reduced surface defects in comparison to the sidewalls of the mesa structure of the dry-etched semiconductor wafer.

2. The method of claim 1 further comprising: growing at least one overgrowth layer on the sidewalls of the mesa structure of the cleaned semiconductor wafer.

3. The method of claim 1 , wherein the cleaning etchant gas comprises chlorine, bromine, or iodine.

4. The method of any one of claims 1 to 3, wherein the cleaning etchant gas comprises bromotrichloromethane (CBrCh).

5. The method of any one of claims 1 to 4, wherein the cleaning etchant gas comprises carbon tetrachloride (CCU).

6. The method of any one of claims 1 to 5, wherein the cleaning etchant gas comprises terbium(lll) chloride (TbCI).

7. The method of any one of claims 1 to 6, wherein flowing the etchant gas through the reaction chamber is performed while the dry-etched semiconductor wafer is at a temperature between 500 degrees Celsius and 700 degrees Celsius.

8. The method of claim 7, wherein the temperature is between 560 degrees Celsius and 670 degrees Celsius.

9. The method of any one of claims 1 to 8, wherein flowing the etchant gas through the reaction chamber comprises flowing a gas mixture of the etchant gas and a carrier gas through the reaction chamber.

10. The method of claim 9, wherein the mixture comprises phosphine PH3.

11. The method of claim 9 or 10, wherein the gas mixture is flowed through the reaction chamber at a flow rate of between 800 seem to 3000 seem.

12. The method of any one of claims 1 to 11 , flowing the etchant gas through the reaction chamber is performed for a time period of between 5 seconds to 900 seconds.

13. The method of claim 12, wherein the time period is between 150 seconds to 900 seconds.

14. The method of any one of claims 1 to 13, further comprising: before flowing the etchant gas through the reaction chamber, exposing the dry- etched semiconductor wafer to a liquid solvent to pre-clean the dry- etched semiconductor wafer.

15. The method of any one of claims 1 to 14, wherein the reaction chamber is a metal organic chemical vapor deposition (MOCVD) reaction chamber.

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