Multiplexing digital-to-analog converter

Abstract

A multiplexing digital-to-analog converter (100) includes an input interface, a phase generator (104), N Bit-Multiplexers (102), N bit-to-analog converters (106), and a summing circuit (108). The input interface receives M digital data words for conversion into a sequence of M analog values, each M data word including N bits. The phase generator receives a clock signal having a clock-cycle length, and generates M phase signals of the clock signal, wherein active times of adjacent phase signals partially overlap. Each Bit-Multiplexer multiplexes, responsively to an overlap between pairs of adjacent phase signals, M bits of a given bit-significance taken from one of the M digital data words, thereby producing a respective bit sequence. The N bit-to-analog converters convert the bit sequences into respective sequences of bit-level analog values. The summing circuit sums corresponding bit-level analog values, thereby producing a sequence of the M analog values representing the M digital data words.

Description

[0001]1512-2003.1 MULTIPLEXING DIGITAL-TO-ANALOG CONVERTER CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application 63 / 518,327, filed August 9, 2023, whose disclosure is incorporated herein by reference. FIELD OF THE INVENTION The present invention relates generally to digital-to-analog converters (DACs), and particularly to multiplexing, also referred to as mixer-based, DACs. BACKGROUND OF THE INVENTION High-speed digital to analog converters (DACs) sometimes use a multiplexing scheme, in which the digital input is provided in multiple concurrent inputs that are sequentially multiplexed to produce a single high-speed analog output. U.S. patent 10,778,263 discloses various embodiments of a system, apparatus, and method to provide a poly-phased, time-interleaved radio frequency (RF) digital-to-analog converter (DAC) suitable for use in radar, radio, mobile and other RF systems. In an “An Interleaved full Nyquist high-speed DAC Technique”, Olieman and Nauta (University of Twente, CTIT Institute, IC Design group, Enschede, The Netherlands, IEEE Journal of Solid-State Circuits Volume 50, Issue 3, March 2015), the authors present a 9-bit 11GS / s DAC that achieves an SFDR of more than 50 dB across Nyquist and IM3 below -50 dBc across Nyquist. The DAC uses a two-times interleaved architecture to suppress spurs that typically limit DAC performance. In “A 72-GS / s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb / s Serial Links” Dickson et. al., (IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 58, NO. 4, APRIL 2023), the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter for wireline applications in 4-nm FinFET CMOS technology is detailed. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Lastly, in “A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz”, Bechthum et.al. (IEEE Journal of Solid-State Circuits, Volume 51, Issue 6, June 2016), the authors present a highly linear wideband Mixing-DAC architecture. A current-steering DAC core and a mixer are co-integrated at a unit current-cell level. A 1-bit DAC output stage is cascoded by a 1-bit mixer to form the Mixing-DAC current cell. 1512-2003.1 SUMMARY OF THE INVENTION An embodiment of the present invention that is described herein provides a multiplexing digital-to-analog converter (M-DAC) circuit including an input interface, a phase generator, a set of N Bit-Multiplexers, a set of N bit-to-analog converters, and a summing circuit. The input interface is configured to receive M digital data words for conversion into a sequence of M respective analog values, each of the M data words including N bits. The phase generator is configured to receive a clock signal having a clock-cycle length, and to generate M phase signals of the clock signal, wherein active times of adjacent phase signals partially overlap each other. In the set of N Bit-Multiplexers, each Bit-Multiplexer is configured to multiplex, responsively to an overlap between pairs of adjacent phase signals from the M phase signals, M bits of a given bit-significance taken from a respective one of the M digital data words, thereby producing a respective bit sequence. The N bit-to-analog converters are configured to convert the bit sequences produced by the N Bit-Multiplexers into respective sequences of bit-level analog values. The summing circuit is configured to sum corresponding bit-level analog values from the sequences of bit-level analog values, thereby producing a sequence of the M analog values representing the M digital data words. In some embodiments, the active times of the phase signals of the clock signal are longer than the clock-cycle length divided by M. In an embodiment, a given bit-to-analog converter, which is associated with a given bit-significance, is configured to scale the bit-level analog values according to the given bit-significance. In a disclosed embodiment, the phase generator is configured to adjust an overlap period between the active times of at least two of the phase signals. In some embodiments, the summing circuit includes a galvanic connection of the sequences of bit-level analog values produced by at least some of the bit-to-analog converters. There is additionally provided, in accordance with an embodiment of the present invention, a method for digital-to-analog conversion. The method includes receiving M digital data words for conversion into a sequence of M respective analog values, each of the M data words including N bits. A clock signal having a clock-cycle length is received, and M phase signals of the clock signal are generated, wherein active times of adjacent phase signals partially overlap each other. M bits of a given bit-significance taken from a respective one of the M digital data words are multiplexed responsively to an overlap between pairs of adjacent phase signals from the M phase signals, thereby producing a respective bit sequence. The bit sequences are converted into respective sequences of bit-level analog values. Corresponding 1512-2003.1 bit-level analog values from the sequences of bit-level analog values are summed, thereby producing a sequence of the M analog values representing the M digital data words. The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which: BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram that schematically illustrates a multiplexing digital-to-analog converter (M-DAC), in accordance with an embodiment of the present invention; Fig.2 is a block diagram that schematically illustrates a P-channel Metal Oxide Silicon (PMOS) 4-way Bit-Multiplexer, in accordance with and embodiment of the present invention; Fig.3 is a timing diagram that schematically illustrates the waveforms of a 4-input Bit- Multiplexer, in accordance with an embodiment of the present invention; Fig. 4 is a block diagram that schematically illustrates an N-channel Metal Oxide Silicon (NMOS) 4-way Bit-Multiplexer, in accordance with and embodiment of the present invention; Fig. 5 is a block diagram that schematically illustrates a Complementary Metal Oxide Silicon (CMOS) Bit-Multiplexer, in accordance with an embodiment of the present invention; Fig. 6 is a timing diagram that schematically illustrates waveforms of an indirect contention in a PMOS-based Bit-Multiplexer, in accordance with an embodiment of the present invention; and Fig. 7 is a flowchart that schematically illustrates a method for multiplexed digital to analog conversion, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS OVERVIEW Multiplexing Digital-to-Analog Converters (M-DACs) are typically used in high-speed applications. The M-DAC receives multiple digital words in parallel, at a reduced rate, sequentially multiplexes the input words, and generates a high-speed analog signal at a rate that is equal to the input rate multiplied by the number of parallel words. (Multiplexing DACs are sometimes referred to as Mixer-Based DACs. We use the two terms interchangeably below.) As the multiplexing selection time for each input word is short (equal to the input time for each group of parallel words, divided by the number of parallel words, referred to hereinbelow as Tm), the selection signals may be short and, thus, noisy. 1512-2003.1 Embodiments of the present invention that are disclosed herein provide M-DACs and associated methods wherein a phase generator generates phase signals that are wider than Tm, and the multiplexing is done responsively to an overlap between multiple phase signals. In embodiments, the M-DAC receives M N-bit parallel words, which are input to N M-input Bit- Multiplexers; the outputs of the Bit-Multiplexers are input to N bit-to-analog converters, which convert the outputs of the Bit-Multiplexers to N respective analog signals, where the high level of the analog signal is proportional to 2bs (bs is a bit-significance value, e.g., 0 for the least-significant bit, 1 for the next bit, etc.). A Summing circuit then sums the N analog signals, to produce a sequence of the M analog values representing the M digital data words. Further embodiments to be described below assume that M=4 and produce complementary analog outputs (any other suitable value of M can be used in other embodiments, with unipolar and / or complementary outputs). In an embodiment to be disclosed below, P-channel Metal Oxide Silicon (PMOS)- transistors-based Bit-Multiplexers are used. Each Bit-Multiplexer selects a bit from M input bits of a given bit-significance. The Bit-Multiplexer comprises a current source, a first set of four PMOS transistors that forward the current to a first resistor and a second set of four PMOS transistors that forward the current to a second resistor. Gating circuits are configured to enable each one of the first set of PMOS transistors responsively to an overlap between two adjacent phase signals and to a set bit-input, and to enable each one of the second set of PMOS transistors responsively to an overlap between the two adjacent phase signals and a clear bit- input (“enable”, for PMOS transistor, is a low voltage at the gate). The Bit-Multiplexer outputs complementary signals – an Out+ signal, connected to the first resistor and having a logic value according to the logic level of the selected bit-input, and an Out- signal, connected to the second resistor and having a logic value according to the inverse of the logic level of the selected bit-input. In a similar embodiment that is disclosed below, the Bit-Multiplexer is based on N- channel Metal Oxide Silicon (NMOS) transistors. A current source sinks current from the positive power rail, through two resistors and two sets of NMOS transistors. The gating circuits, like those of the PMOS-based Bit-Multiplexer, enable transistors from the first or the second set in response to an overlap of phase signals and to the level of the bit-input (“enable”, for NMOS transistors, is a high gate voltage). In yet another embodiment, the Bit-Multiplexer is Complementary-Metal-Oxide- Silicon (CMOS)-based. Four NMOS-PMOS transistor-pairs, one for every bit-input, drive a 1512-2003.1 common output node; when a pair of adjacent phase signals overlap, one of the NMOS-PMOS transistor-pairs drives the node high or low, according to the logic level of a selected bit-input. SYSTEM DESCRIPTION High-speed DAC design poses several limitations and challenges. One primary concern is maintaining the desired accuracy and linearity of the analog output in the face of increased speed. The complexity of the conversion process, coupled with power consumption, area utilization, and signal integrity constraints necessitates innovative architectures that can overcome these limitations. Embodiments of the present invention introduce a high-speed DAC featuring a mixer- based N-to-1 architecture, which effectively addresses those limitations, providing enhanced performance in terms of speed, accuracy, power efficiency, and signal integrity. The mixer-based architecture utilizes M-switched current sources at the DAC output, each responsible for combining a portion of the analog signals pertaining to a given bit- significance, to generate the final output. This approach ensures efficient conversion of the digital input by utilizing parallel processing techniques while minimizing the impact of non- idealities, such as non-linearity and distortion. In the description below we use the term Multiplexing (M-DAC). Such DACs are also referred to in the industry as Mixer-Based DAC, with the same M-DAC acronym. Fig. 1 is a block diagram that schematically illustrates a multiplexing digital-to-analog converter (M-DAC) 100, in accordance with an embodiment of the present invention. M-DAC 100 receives a clock input and M N-bit digital data words, for conversion into a single analog value. The M-DAC receives, in each clock cycle, M digital data words, which represent successive digital inputs, to be converted to a sequence of M respective analog words at a rate that is M times faster than the clock rate. For example, if M=4 and the clock frequency is 1Ghz, the M-DAC will receive 4*109 words per second, for conversion to an analog signal; during the first quarter of the clock period, the M-DAC will convert a first of the four digital words to analog, during the second quarter the M-DAC will convert the second digital word, and so one. We will refer hereinbelow to bit-significances of the M-bits of each digital word, starting with a bit-significance value of 0 assigned to the least significant bit of the digital word, and up to a bit-significance value of N-1 for the most significant bit. M-DAC 100 comprises a suitable input interface (not seen in the figure) for receiving the M N-bit digital data words in each clock cycle. M-DAC 100 further comprises N M-bit 1512-2003.1 Bit-Multiplexers 102, one bit for each bit-significance. Each Bit-Multiplexer receives M bit- inputs of the same bit-significance from each of the M N-bit inputs. A Phase-Generator 104 is configured to generate M phase signals in a recurring sequence that repeats after each M clock cycles. In embodiments, the active and inactive time of each phase signal is more than the clock period time divided by M (more than 0.25nS in the 1GHz example above). Thus, in embodiments, generation of very fast signals is avoided. Each of the Bit-Multiplexers is configured to produce a single bit, selected from the M bit-inputs according to the phase signals; the output of each Bit-Multiplexer, thus, comprising a bit sequence. We refer to an ordered set of the phase signals as a set comprising all the phase signals, ordered by the respective time of the inactive to active transition. Two phase signals will be referred to as adjacent to each other if they are next to each other in the ordered set (but, as the sequence of phase signals is cyclic, the Mth phase signal is also adjacent to the first phase signal). In embodiments, the active times of adjacent phase signals partly overlap each other. For example, assuming M=4, if we designate four consecutive quarters of the clock periods as T0, T1, T2 and T3, a first phase signal may be active at T0 and T1, a second phase signal at T1 and T2, a third phase signal at T2 and T3, and a fourth phase signal at T3 and T0. As can be seen, the first and second phase signals overlap at T0, the second and third phase signals overlap at T1, the third and the fourth phase signals overlap at T2, and the fourth and the first phase signals overlap at T3. In an embodiment, the Bit-Multiplexers are configured to produce an output responsively to an overlap between two adjacent phase signals. For example, the produced output of the Bit-Multiplexer corresponding to bit-significance n will equal to bit n of input-1 when the first phase signal overlaps with the second phase signal, bit n of input-2 when the second phase signal overlaps with the third phase signal, bit n of input-3 when the third phase signal overlaps with the fourth phase signal, and bit n of input-4 when the fourth phase signal overlaps with the first phase signal. The produced bit sequence will comprise the set I11, I12, I13, I14(Imnis the mth bit of the nth input). outputs produced by the N Bit-Multiplexers are input to corresponding Bit-to- Analog Converters 106; each Bit-to-Analog Converter is configured to convert a bit value (either logic-1 or logic-0) to an analog value that is scaled according to the given bit- significance. For example, the Bit-to-Analog Converter corresponding to the least-significant 1512-2003.1 bit may output a 10mV voltage when the input bit is logic-1, and 0 voltage when the input bit is logic-0; the converter corresponding to bit-significance of 1 will output a 20mV or 0mV according to the input bit, and so on (in another embodiment the Bit-to-Analog Converters may product currents). The outputs of all Bit-to-Analog Converters 106 are input to a Summing circuit 108, which is configured to sum the input signals and generate the analog Output signal. Thus, in embodiments, M-DAC 100 receives a clock signal and M digital data words, each data word comprising N bits, and produces a sequence of M respective analog values, using a series of Bit-Multiplexers, Bit-to-Analog Converters and a summing circuit. Each Bit- Multiplexer is configured to multiplex input bits responsively to an overlap between phase signals, the phase signals being generated by a phase generator and include relatively low- frequency signals. The configuration of M-DAC 100, illustrated in Fig. 1 and presented herein above, is cited by way of example. Other configurations may be used in alternative embodiments. For example, in an embodiment, the Bit-Multiplexer is configured to produce an analog output, according to the bit inputs and to an overlap between phase signals (and, hence, Bit-to-Analog 106 is not used). In another embodiment, Summing circuit 108 comprises a resistor network, wherein the resistor values are set according to respective bit-significances values, and, thus, bit-to-analog circuits 106 and Summing-circuit 108 are not needed. We will now proceed to describe the Bit-Multiplexer of an M-DAC, wherein bit- multiplexing is done by switching P-channel Metal Oxide Silicon (PMOS) transistors. Fig.2 is a block diagram that schematically illustrates a P-channel Metal Oxide Silicon (PMOS) 4-way Bit-Multiplexer 200, in accordance with and embodiment of the present invention. Bit-Multiplexer 200 receives four complementary inputs (M=4) and produces a differential output. The Bit-Multiplexers have a complementary structure, generating a positive OUT+ output and a negative and OUT- output. A common current source 202 sources current to a common node 204. A group of four PMOS transistors 206 routes the current, through a resistor 208, to ground, driving the positive OUT+ output high, if any of the transistors is on. Similarly, a group of four PMOS transistors 210 routes the current, through a resistor 212, to ground, driving the negative OUT- output high, if any of transistors 210 is on. The Bit-Multiplexer comprises eight identical gating circuits 214, each gating circuit comprising a NOR gate 216 having a PHI-A phase input and a D data input, and a NAND gate 218 having a PHI-B phase input and the NOR gate output at the second input. Four gating circuits 214A drive the gates of PMOS transistors 206, and four gating circuits 214B drive the 1512-2003.1 gates of PMOS transistors 210. The inputs of gating circuits 214A, 214B are connected to positive and negative polarities of phase signals PHI0 through PHI3, and to the D0 to D3 inputs (and to inverse polarities thereof), so that the logic function for driving OUT+ high is: OUT+ = |(Φ0&Φ1&D0|Φ1&Φ2&D1|Φ2&Φ3&D2|Φ3&Φ0&D3)And the logic function for driving OUT- high is: OUT- = |(Φ0&Φ1&~D0|Φ1&Φ2&~D1|Φ2&Φ3&~D2|Φ3&Φ0&~D3) Where Φ0through Φ3designate the phase signals PHI0 through PHI3, generated by Phase Generator 104 (Fig. 1). Thus, the OUT+ output will be set high responsively to a D input that is high when two adjacent phase signals are active (logic 1), and, similarly, the OUT- output will be set high responsively to a D input that is low when the same two adjacent phase signals are active. Fig. 3 is a timing diagram that schematically illustrates the waveforms 300 of a 4-input Bit-Multiplexer, in accordance with an embodiment of the present invention. It should be noted that, while the 4-bit inputs (M-bit inputs for other values of M) are denoted D0, D1, D2 and D3, the logic value applied on the input bit lines are denoted Inm, where m indicates an input bit-line and spans from 0 to M-1, and n is an index that indicates a clock-period number. A waveform 302 illustrates the logic value on D0; a waveform 304 illustrates the logic value on D1; a waveform 306 illustrates the logic value on D2; and a waveform 308 illustrates the logic value on D3. A waveform 310 illustrates PHI0, a waveform 312 illustrates PHI1, a waveform 314 illustrates PHI2, and a waveform 316 illustrates PHI3. A waveform 318 illustrates PG0 – the voltage at the gate of a first PMOS transistor from the four PMOS transistors 206 (Fig.2). When both PHI0=1 and PHI1=1 (e.g., during the overlap period of PHI0 and PHI1) PG0 will assume a low voltage (thereby causing the corresponding PMOS transistor 206 to conduct) only if D0, at the time of the overlap, is at logic-1. In a similar manner – a waveform 320 illustrates PG1, which is low only if, at the overlap time of PHI1 and PHI2, D1 is at logic-1; a waveform 322 illustrates PG2, which is low only if, at the overlap time of PHI2 and PHI3, D2 is at logic-1; and, a waveform 324 illustrates PG3, which is low only if, at the overlap time of PHI3 and PHI0, D3 is at logic-1. 1512-2003.1 The signals that drive gating-circuits 214B (Fig. 2) are identical to the signals that drive the respective gating circuits 214A, except that the polarities of the D inputs are inverted. When either one of PMOS transistors 206 conducts, the corresponding PMOS transistor 210 will not conduct; the current sourced by current source 202 (Fig. 2) will create a voltage drop across resistor 208, setting OUT+ to a high voltage. Conversely, when either one of PMOS transistors 210 conducts, the corresponding PMOS transistor 206 will not conduct, and the current will create a voltage drop across resistor 212, setting OUT- to a high voltage. A waveform 326 and a waveform 328 illustrate, respectively, the OUT+ and the OUT- voltages, each toggling at a rate that is four times higher than the rate at the D input. OUT+ and OUT- are complementary outputs. In some embodiments, the M-DAC comprises a Bit-Multiplexer that uses N-channel Metal Oxide Silicon (PMOS) transistors for multiplexing. Fig. 4 is a block diagram that schematically illustrates an N-channel Metal Oxide Silicon (NMOS) 4-way Bit-Multiplexer 400, in accordance with and embodiment of the present invention. Bit-Multiplexer 400 is, in some respects, a complementary implementation of Bit-Multiplexer 200 (Fig. 2), with inversed signal polarities, and with NMOS transistors instead of PMOS transistors. Like Bit-Multiplexer 200, Bit-Multiplexer 400 receives four complementary inputs (M=4) and produces a differential output. The Bit-Multiplexers has a complementary structure and generates a positive OUT+ output and a negative OUT- output. A common current source 402 sinks current from a common node 404. A group of four NMOS transistors 406 routes the current, from a positive supply rail, through a resistor 408, to node 404, driving the negative OUT- output high if any of the transistors is on. Similarly, a group of four NMOS transistors 410 routes the current, through a resistor 412, to node 404, driving the positive OUT+ output high if any of the transistors is on. Bit-Multiplexer 400 comprises eight identical gating circuits 414, each gating circuit comprising a NAND gate 416 having a PHI-A phase input and a D data input, and a NOR gate 418 having a PHI-B phase input and the NAND gate output at the second input. Four gating circuits 414A drive the gates of NMOS transistors 406, and four gating circuits 414B drive the gates of NMOS transistors 410. The inputs of gating circuits 414A, 414B are connected to positive and negative polarities of phase signals PHI0 to PHI3 and to the D0 to D3 inputs (and to inverse polarities thereof). As can be seen, the logic functions for OUT+ and OUT- are the same as the functions for Bit-Multiplexer 200: OUT+ = |(Φ0&Φ1&D0|Φ1&Φ2&D1|Φ2&Φ3&D2|Φ3&Φ0&D3) 1512-2003.1 OUT- = |(Φ0&Φ1&~D0|Φ1&Φ2&~D1|Φ2&Φ3&~D2|Φ3&Φ0&~D3). In some embodiments, the M-DAC comprises a Bit-Multiplexer that uses Complementary Metal Oxide Silicon (CMOS) gates for multiplexing. Fig.5 is a block diagram that schematically illustrates a CMOS Bit-Multiplexer 500, in accordance with an embodiment of the present invention. Bit-Multiplexer 500 comprises a common node 502, that is driven by four pairs of transistors, each pair comprising a pull-up PMOS transistor 504 (designated 504A, 504B, 504C and 504D) and a pull-down NMOS transistor 506 (designated 506A, 506B, 506C and 506D). Four P-Gating circuits 508 (designated 508A, 508B, 508C and 508D) drive the PMOS transistors 504, and four N-Gating circuits 510 (designated 510A, 510B, 510C and 510D) drive the NMOS transistors 506. Each P-Gating circuit 508 comprises a NOR gate 512 and a NAND gate 514. The P- Gating circuit receives a PHI-A input, a D input, and a PHI-B input, and implements the logic function: Out = ~(PHI-A & ~D & PHI-B). Each N-Gating circuit 510 comprises a NAND gate 516 and a NOR gate 518. Like the P-Gating circuit, The N-Gating circuit receives a PHI-A input, a D input, and a PHI-B input, and implements the complementary logic function: Out = PHI-A & D & ~PHI-B. The table below depicts the on / off status of all PMOS transistor 504 and NMOS transistors 506, as a function of the overlap between the phase signals and the input logic value of the D inputs (for a given bit-significance) TransistorΦ0&Φ1=1 Φ1&Φ2=1 Φ2&Φ3=1 Φ3&Φ0=1 1512-2003.1 506C off off D2=0 ^on off D2=1 ^off als so that at all times, one and only one pair of adjacent phase signals overlap. Thus, node 502 will always be driven by a single PMOS transistor 504 or a single NMOS transistor 506 and will have a low impedance to the low or the high power-rail. CMOS Bit-Multiplexer 500 further comprises a resistor 520 that buffers node 502 from other circuitry; in some embodiments, multiple CMOS Bit-Multiplexers pertaining to different bit-significances are connected to a common node. The ratio of resistors 520 is set according to the bit-significance (e.g., the resistance of resistors 520 of a given CMOS Bit-Multiplexer will equal 1 / 2bs, where bs is the bit-significance of the bit line inputs connected to the Bit- Multiplexer). If the voltage at the common node is 0 (e.g., virtual ground), the sum of the currents sourced into the common node will be proportional to the required analog output of the M-DAC. Thus, CMOS Bit-Multiplexer 500 will include the functionality of Bit-to-Analog Converter 106 (Fig. 1), and Summing Circuit 108 will comprise a galvanic connection of the Bit-Multiplexing to a common node (and, in some embodiments, include current to voltage conversion). The configurations of Bit-Multiplexers 200, 400 and 500, illustrated in Figs. 2, 4, and 5, and described hereinabove, are example embodiments that are cited merely for the sake of conceptual clarity. Other configurations may be used in alternative embodiments. For example, in some embodiments, the gating circuits or parts thereof are replaced by additional PMOS or NMOS transistors (e.g., to select a bit input when a first and a second phase signals overlap, three transistors may be connected in series, gated by the first and second phase signals and by the bit-input). In some embodiments, the Bit-Multiplexer selects a bit-input responsively to an overlap of three phase signals. In other embodiments, the Bit-Multiplexer outputs current rather than voltage. 1512-2003.1 MITIGATING CONTENTIONS High speed multiplexing often entails contention as, due to inaccuracies of the select signals, the multiplexer output may temporarily be driven to different values. In the example embodiments illustrated in Figs. 2 and 3, as the PMOS or the NMOS transistors drive current in the same direction, direct contention in the Bit-Multiplexers is not possible; however, in embodiments, to improve speed, Bit-to-Analog Converter 106 (Fig. 1) may comprise a differential stage, and contention may occur if the OUT+ and OUT- have the same polarity (referred to as indirect contention herein). In the example embodiment illustrated in Fig. 5, contention may occur within the Bit-Multiplexer. In embodiments, the contention can be mitigated by the addition of delays to gates of gating circuits, adjusting the beginning or the end of overlap periods. Fig. 6 is a timing diagram that schematically illustrates waveforms 600 of an indirect contention in a PMOS-based Bit-Multiplexer, in accordance with an embodiment of the present invention. D0 and D1 are initially at logic-0 and logic-1 (respectively) and change to logic-1 and logic-0 with PHI1 falling edge. The timing diagram illustrates signals of Gating Circuit 214A (Fig. 2), including a ~PHI0 waveform 602, a ~D0 waveform 604, a NOR waveform 606 (illustrating the logic level on NOR gate 216 of gating circuit 214A), a PHI1 waveform 608 and a PG0(+) waveform 610, illustrating the voltage level on the gate of a respective PMOS transistor 206. The timing diagram also includes signals of Gating Circuit 214B (Fig. 2), including a ~PHI1 waveform 612, a D1 waveform 614, a NOR waveform 616 (illustrating the logic level on NOR gate 216 of gating circuit 214B), a PHI2 waveform 608 and a PG1(-) waveform 620, illustrating the voltage level on the gate of a respective PMOS transistor 210. The thick arced arrow indicates a location of a potential contention – PG0(+) turns high when PG1(-) turns low; if the delays are not adjusted, there may be a time interval in which PG0(+) is still low (and, hence, OUT+ is high), but PG1(-) is already low (and, hence, OUT- is high as well). The thin arrow indicates that the falling edge of PG1(-) is driven by a rising edge in PHI2, which propagates through NAND gate 218 (Fig. 2). Hence, in embodiments, the contention may be avoided if a delay is added to the NAND gate, from the phase input to the output. Similar analysis may be carried out for other embodiments, which may require delays in other gates for contention avoidance. 1512-2003.1 Fig. 7 is a flowchart 700 that schematically illustrates a method for multiplexed digital to analog conversion, in accordance with an embodiment of the present invention. The flowchart is executed by an M-DAC 100 (Fig.1). The flowchart starts at a Receive-Clock-and-Data operation 702, wherein the M-DAC receives a clock input with frequency = F, and, synchronized to an edge of the clock, a stream of word-groups for conversion to an analog signal, each word-group comprising M N-bit words. In some embodiments the stream of word groups is synchronized to the rising edge of the clock input, in other embodiments the stream is synchronized to the falling edge of the clock, and, in yet other embodiments, the stream is synchronized to both the rising edge and the falling edge of the clock. In embodiments wherein the stream is synchronized to either the rising or and the falling edge of the clock, the rate R in which word-groups are input is F, whereas, in embodiments wherein the stream is synchronized to both the rising and the falling edge, R=2*F. At a Generate-Phase-Signals operation 704, the M-DAC generates M phase signals. The frequency of the phase signals is R, and the active period is k / (R*M), where k is an integer larger than one and smaller than M. Each pair of two adjacent phase signals will have an overlap period of 1 / (R*M). For example, if M=4, the M-DAC generates four phase signals, designated PHI0, PHI1, PHI2 and PHI3. Assuming R=250MHz, the clock period is 4nS. We divide this time into four 1nS intervals, designated T0, T1, T2 and T3. Then, PHI0 will be active during T0 and T1; PHI1 will be active during T1 and T2; PHI2 will be active during T2 and T3; and PHI3 will be active during T3 and T0. Each pair of adjacent phase signals overlap during a single 1nS interval. Note that no phase signal is narrower than 2nS. Next, at a Bit-Multiplex operation 706, the M-DAC bit-multiplexes N groups of M bit- inputs having the same bit-significance. For example, M bit-inputs comprising the least significant bits of the M words, M bit-inputs comprising bit-1 of the M inputs, and so on. Each Bit-Multiplexer selects a bit-line responsively to an overlap between two phase signals. In the M=4 example described above, each of the Bit-Multiplexers may select a first bit-input when PHI0 overlaps PHI1, a second bit-input when PHI1 overlaps PHI2, a third bit-input when PHI2 overlaps PHI3, and a fourth bit-input when PHI3 overlaps PHI0. At a Convert-Bit-to-Analog operation 708 the M-DAC then converts the outputs of the N Bit-Multiplexers to analog values, according to the respective bit-significance. For example, if N=8 and the MDAC resolution is 10mV, the M-DAC will convert an output of logic-0 in any of the Bit-Multiplexers to 0V; the M-DAC will convert an output of logic-1 to 10mV, 1512-2003.1 2*10mV, 4*10mV, 8*10mV and so on, for respective bit-significance values 0,1,2, and so on. A logic-1 at the output of the Bit-Multiplexer corresponding to the most-significant bit (bit- significance=7) will be converted to 27*10mV = 1.28V. Lastly, at a Sum-Signals operation 710, the M-DAC sums the N analog values to produce an analog signal representing the stream of input words. The configuration of flowchart 700, illustrated in Fig. 7 and described herein above, is cited by way of example. Other flowcharts may be used in alternative embodiments. For example, in some embodiments, the M-DAC produces complementary outputs, including positive and negative output signals. In and embodiment, the Bit-Multiplexer may select bit- inputs responsively to an overlap of more than two phase signals (this may be useful with large values of M, e.g., M=16). In some embodiments, the Bit-Multiplexers output the analog value according to the bit-significance and Convert-Bit-to-Analog operation 708 is not needed. The apparatuses and methods described hereinabove, with reference to Figs 1 through 7; the configurations of M-DAC 100, Bit-Multiplexers 200, 400 and 500, waveforms 300 and 600 and the method of flowchart 700, including all units and subunits thereof, are example configurations, waveforms and methods that are shown purely for the sake of conceptual clarity. Any other suitable methods and configurations can be used in alternative embodiments. For example, in embodiments, voltage-source-based instead of current-source- based Bit-Multiplexers may be used. In various embodiments, M-DAC 100, including subunits thereof, may be implemented using suitable hardware, such as one or more Application-Specific Integrated Circuits (ASIC) or Field-Programmable Gate Arrays (FPGA), or a combination of ASIC and FPGA. Although the embodiments described herein mainly address multiplexing digital to analog converters, the methods and systems described herein can also be used in other applications. It will thus be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art. Documents incorporated by reference in the present patent application are to be considered an integral part of the 1512-2003.1 application except that to the extent any terms are defined in these incorporated documents in a manner that conflicts with the definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered.

Claims

1512-2003.1 CLAIMS 1. A multiplexing digital-to-analog converter (M-DAC) circuit, comprising: an input interface, configured to receive M digital data words for conversion into a sequence of M respective analog values, each of the M data words comprising N bits; a phase generator, configured to receive a clock signal having a clock-cycle length, and to generate M phase signals of the clock signal, wherein active times of adjacent phase signals partially overlap each other; a set of N Bit-Multiplexers, each Bit-Multiplexer configured to multiplex, responsively to an overlap between pairs of adjacent phase signals from the M phase signals, M bits of a given bit-significance taken from a respective one of the M digital data words, thereby producing a respective bit sequence; a set of N bit-to-analog converters, configured to convert the bit sequences produced by the N Bit-Multiplexers into respective sequences of bit-level analog values; and a summing circuit, configured to sum corresponding bit-level analog values from the sequences of bit-level analog values, thereby producing a sequence of the M analog values representing the M digital data words.

2. The circuit according to claim 1, wherein the active times of the phase signals of the clock signal are longer than the clock-cycle length divided by M.

3. The circuit according to claim 1 or 2, wherein a given bit-to-analog converter, which is associated with a given bit-significance, is configured to scale the bit-level analog values according to the given bit-significance.

4. The circuit according to claim 1 or 2, wherein the phase generator is configured to adjust an overlap period between the active times of at least two of the phase signals.

5. The circuit according to claim 1 or 2, wherein the summing circuit comprises a galvanic connection of the sequences of bit-level analog values produced by at least some of the bit-to-analog converters.

6. A method for digital-to-analog conversion, comprising: receiving M digital data words for conversion into a sequence of M respective analog values, each of the M data words comprising N bits; receiving a clock signal having a clock-cycle length, and generating M phase signals of the clock signal, wherein active times of adjacent phase signals partially overlap each other;1512-2003.1 multiplexing, responsively to an overlap between pairs of adjacent phase signals from the M phase signals, M bits of a given bit-significance taken from a respective one of the M digital data words, thereby producing a respective bit sequence; converting the bit sequences into respective sequences of bit-level analog values; and summing corresponding bit-level analog values from the sequences of bit-level analog values, thereby producing a sequence of the M analog values representing the M digital data words.

7. The method according to claim 6, wherein the active times of the phase signals of the clock signal are longer than the clock-cycle length divided by M.

8. The method according to claim 6 or 7, further comprising scaling the bit-level analog values, which are associated with a given bit-significance, by a factor set according to the given bit-significance.

9. The method according to claim 6 or 7, wherein generating the phase signals comprises adjusting an overlap period between the active times of at least two of the phase signals.

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