Diode-less electrostatic discharge protection circuit
EP4759096A1Pending Publication Date: 2026-06-17VIASAT INC
Patent Information
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- VIASAT INC
- Filing Date
- 2023-08-25
- Publication Date
- 2026-06-17
AI Technical Summary
Technical Problem
Existing ESD protection solutions for circuits often rely on diodes, which may not be suitable for all IC fabrication processes and can prevent the application of proper bias voltage for normal operation.
Method used
A diode-less ESD protection circuit using a FET pair to provide a low impedance discharge path from the gate pad to ground, with an optional fuse to disconnect the ESD protection circuit after manufacturing or testing is complete.
Benefits of technology
The FET pair effectively protects functional components against ESD events without the limitations of diodes, and the fuse ensures that ESD protection is only active during manufacturing or testing, allowing proper bias voltage application during normal operation.
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Smart Images
Figure US2023031192_06032025_PF_FP_ABST
Abstract
An integrated circuit (IC) and a system for providing electrostatic discharge (ESD) protection is disclosed comprising a circuit (e.g., an ESD protection circuit) electrically connected to a circuit board. The circuit may comprise: a functional component; a gate pad connected to the functional component; and a FET pair connected to the gate pad and forming a low impedance discharge path from the gate pad to ground to protect the functional component against an ESD event. An ESD protection method is disclosed comprising: manufacturing a wafer comprising multiple circuits; dicing the wafer to form a IC; packaging the IC to form a chip; attaching the chip to a printed circuit board; and applying, from the printed circuit board, a DC voltage, exceeding a fusing voltage threshold level, to a gate pad of the IC to blow the fuse to disconnect the ESD protection circuit from the gate pad.
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