A power supply smooth switching control method for suppressing direct current bus voltage impact

Abstract

This application belongs to the field of power electronics and automatic control technology, and relates to a power supply smooth switching control method for suppressing DC bus voltage surges. It solves the problem of DC bus voltage surges caused by potential changes during primary / standby power supply switching, including: dynamically matching the standby power supply output to the primary power supply voltage and reserving a voltage difference margin through voltage closed-loop feedback; initiating switching when a primary power supply fault is detected or the bus voltage drop rate exceeds a threshold; utilizing controlled current injection into the MOSFET gate to bring it into the Miller plateau region and allowing it to remain in the linear operating region for a preset transition period; controlling the MOSFET drain-source equivalent resistance to continuously decrease according to an S-shaped function to absorb transient energy; and locking the fully conducting state to complete seamless switching when the drain-source voltage difference approaches zero. This method effectively eliminates high-frequency oscillations, achieves microsecond-level potential transitions, significantly improves system reliability and response speed, and is suitable for high-reliability power supply scenarios with stringent "zero-inductive switching" requirements.

Description

Technical Field

[0001] This application belongs to the field of power electronics and automatic control technology, specifically relating to a power supply smooth switching control method for suppressing DC bus voltage surges. Background Technology

[0002] In applications with stringent requirements for power continuity, such as data centers, communication base stations, precision medical equipment, and industrial automation, the stability of DC power supply systems directly affects the safe operation of critical loads. With the development of power electronics technology, redundant hot-standby architectures have become the mainstream design, achieving automatic switching between primary and backup power supplies through power switching devices. To meet the performance target of "zero-sensory switching," the industry's technological focus has shifted from simple logic control to the fine-tuning of energy flow during switching transients, particularly focusing on suppressing the impact and oscillation of DC bus voltage caused by potential changes during switching.

[0003] Among them, power smooth switching technology aims to reduce the potential difference between the primary and backup power supplies through pre-synchronization or transition control strategies, thereby reducing inrush current during the switching process. Existing solutions mostly employ a "monitor-response" mechanism based on voltage threshold triggering, rapidly activating the backup path after detecting an anomaly in the primary power supply. Some methods introduce pulse train driving or PWM modulation techniques, attempting to mitigate the impact of voltage steps through discrete switching actions or amplitude tracking.

[0004] However, existing technologies still have significant drawbacks: First, traditional switching methods are essentially hard-switching operations, with power devices rapidly switching between cutoff and saturation states, failing to effectively suppress high-frequency voltage oscillations caused by the charging and discharging of filter capacitors and sudden changes in line impedance. Second, the standby voltage of backup power supplies typically employs fixed bias or coarse tracking strategies, making it difficult to dynamically compensate for microsecond-level voltage differences caused by load changes or grid disturbances, resulting in significant drops or spikes in bus voltage during switching. Third, frequent current surges accelerate the thermal fatigue of power transistors and electrolytic capacitors, not only shortening system lifespan but also potentially inducing data errors or logic disturbances in sensitive loads. Therefore, a smooth power supply switching control method that can achieve continuous impedance evolution, precise potential connection, and active absorption of transient energy is urgently needed. Summary of the Invention

[0005] The purpose of this invention is to provide a power supply smooth switching control method to suppress DC bus voltage surges, which can effectively solve the problems in the background art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A power supply smooth switching control method for suppressing DC bus voltage surges includes the following specific steps: Step 1: Dynamic potential alignment: Real-time sampling of the main power supply voltage, and control of the backup power supply output voltage through voltage closed-loop feedback to establish a hot standby state where the backup power supply output voltage equals the main power supply voltage minus the voltage difference margin, wherein the voltage difference margin is a value dynamically compensated based on the bus load current, and its value is within a preset voltage difference margin range; Step 2: Switching transition state identification: When a main power supply fault signal is detected or the bus voltage drop rate exceeds a preset threshold, a smooth switching procedure is triggered; Step 3: Active impedance modulation in the Miller plateau region: At the start of switching, the controller injects a controlled current into the gate of the metal-oxide-semiconductor field-effect transistor at the output of the backup power supply. Step 4: Impedance S-type continuous evolution: During the transition period, the drain-source equivalent resistance of the MOSFET is controlled to continuously decrease from the high resistance state to the saturation conduction state according to the S-type function law, in order to absorb the transient potential difference energy between the main power supply and the backup power supply. Step 5: Zero-difference full conduction lockout: The drain-source voltage difference of the MOSFET is monitored in real time. When the drain-source voltage difference drops to a preset threshold close to zero, the gate drive voltage is increased to the saturation region to complete the seamless physical connection from the main power supply to the backup power supply.

[0008] Preferably, in step 1, the voltage closed-loop feedback control adopts a proportional-integral-derivative regulator, whose proportional gain coefficient, integral time constant and derivative time constant are all set to predetermined values ​​to ensure that the differential pressure margin can be dynamically adjusted and maintained within the preset differential pressure margin range when the load current changes suddenly.

[0009] Preferably, in step 2, the preset threshold for the bus voltage drop rate is set to a specified value. This threshold is obtained in real time by a high-speed analog-to-digital converter at a rate not lower than the preset sampling frequency, and is determined and responded to by a digital signal processor within a predetermined response time.

[0010] Preferably, in step 3, the Miller plateau voltage is determined according to the process parameters of the metal-oxide-semiconductor field-effect transistor used, and its typical value is within a preset voltage range. The injection rate of the controlled current is controlled by a dedicated gate drive circuit, and its rise time is precisely limited within a preset time window to ensure that the device reliably enters the linear region without overshoot.

[0011] Preferably, in step 4, the S-shaped function law is defined as follows: the rate of change of the drain-source equivalent resistance with time is less than the preset lower limit of the rate of change in the initial stage of conduction, increases to above the preset upper limit of the rate of change in the middle stage, and decreases again to below the preset lower limit of the rate of change in the final stage. This evolution process is achieved by nonlinear lookup table combined with real-time feedback correction to ensure that the impedance change is smooth and without abrupt changes.

[0012] Preferably, during the operation of the metal-oxide-semiconductor field-effect transistor in the linear region in step 4, the channel temperature is monitored in real time by an embedded thermistor. When the temperature rise rate exceeds a preset temperature rise rate threshold, the controller automatically extends the transition period and reduces the impedance drop slope to prevent thermal runaway.

[0013] Preferably, in step 5, the preset threshold for the voltage difference between the drain and source is set to a specific voltage value. This threshold value is detected by a differential amplifier and quantized by a multi-bit analog-to-digital converter before being sent to the controller. When multiple consecutive sampling points are all below this threshold, it is determined to be a zero voltage difference state and full conduction lockout is executed.

[0014] Preferably, the package structure of the metal-oxide-semiconductor field-effect transistor has a built-in Kelvin connection pin for independently leading out the gate drive circuit and the power circuit, eliminating the influence of common-mode interference on the control accuracy of the Miller plateau region, and its parasitic inductance is less than a preset inductance threshold.

[0015] Preferably, after the smooth switching program is started, the isolation diode at the output of the main power supply is turned off synchronously, and its reverse recovery time is less than a preset time threshold to avoid the formation of circulating current between the main and backup power supplies. At the same time, the output filter capacitor of the backup power supply is configured to be no less than a preset capacitance value to provide sufficient transient energy buffer.

[0016] Preferably, the method is integrated into a digital power management chip, which has a built-in multi-core processor. One core is dedicated to performing dynamic potential bonding and switching transition state identification, while the other core is dedicated to performing active impedance modulation of the Miller plateau region, impedance S-type continuous evolution, and zero-difference full conduction lockout. The two cores are coordinated through a hardware synchronization signal to ensure that the entire switching process is completed within a preset total time.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. Fundamentally eliminate high-frequency oscillations

[0019] By using metal-oxide-semiconductor field-effect transistors as active variable dampers, their drain-source equivalent resistance evolves continuously in an S-shape, completely avoiding impedance steps caused by traditional hard switching or discrete pulse switching. This eliminates high-frequency voltage oscillations and electromagnetic interference caused by sudden changes in di / dt on the DC bus from a physical mechanism perspective, and the bus voltage fluctuation amplitude is controlled within a preset fluctuation range.

[0020] 2. Achieve microsecond-level precise potential connection

[0021] The dynamic potential alignment mechanism dynamically compensates for the voltage difference margin through closed-loop feedback, combined with a zero-voltage-difference full-conduction locking strategy, to ensure that the potential difference between the main and backup power supplies approaches zero at the moment of switching. This effectively solves the problem of voltage tracking failure under heavy load conditions, and ensures that the bus voltage drop or spike amplitude does not exceed the preset voltage deviation threshold during the switching process.

[0022] 3. Significantly improves system reliability and lifespan.

[0023] By actively absorbing and mitigating transient energy in the linear region of metal-oxide-semiconductor field-effect transistors, the surge current stress on the DC bus electrolytic capacitor is significantly reduced, the thermal fatigue loss of power devices is significantly reduced, the mean time between failures (MTBF) of the system is greatly improved, and data errors or logic disorder caused by voltage transients in sensitive loads are avoided.

[0024] 4. Full-process independent control and high response speed

[0025] The entire process from transition state recognition to full conduction lock is completed by dedicated hardware and algorithms in collaboration. The response latency is lower than the preset latency threshold, and the total switching time does not exceed the preset total time limit. It meets the stringent requirements of application scenarios such as data centers and 5G communication base stations for "zero-sense handover". Moreover, it does not rely on external filtering components for passive suppression, and has high system integration and low cost. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the overall technical solution architecture of a power supply smooth switching control method for suppressing DC bus voltage surges proposed in this invention.

[0028] Figure 2 This is a schematic diagram of the core principle framework of the Miller plateau region active impedance modulation and impedance S-type continuous evolution in this invention.

[0029] Figure 3 This is a flowchart illustrating the logic of dynamic potential bonding and switching transition state identification in this invention.

[0030] Figure 4 This is a schematic diagram of the multi-level interaction relationship and data flow between the main power supply, the backup power supply and the metal-oxide-semiconductor field-effect transistor in this invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments.

[0032] like Figures 1 to 4 As shown:

[0033] Example 1

[0034] The power supply smooth switching control method for suppressing DC bus voltage surges in this invention includes the following specific steps: Step 1: Dynamic potential alignment: Real-time sampling of the main power supply voltage, and control of the backup power supply output voltage through voltage closed-loop feedback to establish a hot standby state where the backup power supply output voltage equals the main power supply voltage minus the voltage difference margin, wherein the voltage difference margin is a value dynamically compensated based on the bus load current, and its value is within a preset voltage difference margin range; Step 2: Switching transition state identification: When a main power supply fault signal or the bus voltage drop rate exceeds a preset threshold is detected, a smooth switching procedure is triggered; Step 3: Active impedance modulation in the Miller plateau region: At the start of switching, the controller injects a controlled current into the gate of the metal-oxide-semiconductor field-effect transistor at the output of the backup power supply, driving the gate-source voltage to rise rapidly to the Miller plateau voltage V. Miller While injecting controlled current, the gate-source voltage V is sampled in real time via the Kelvin pin. GS When V GS Deviation from Miller plateau voltage V Miller ±ΔV tol (deviation voltage ΔV) tol When the voltage is 50mV, the injection current amplitude is dynamically adjusted to form V. GS Closed-loop feedback stabilizes the MOSFET channel conductance within the corresponding range of the linear region and maintains this state for a preset transition period; Step 4: Impedance S-type continuous evolution: During the transition period, the transfer characteristics of the metal-oxide-semiconductor field-effect transistor in the linear region are utilized to control its drain-source equivalent resistance to continuously decrease from the high-resistance state to the saturation conduction state according to the S-type function law, so as to absorb the transient potential difference energy between the main and backup power supplies; Step 5: Zero-difference full-conduction lockout: The drain-source voltage difference of the metal-oxide-semiconductor field-effect transistor is monitored in real time. When the drain-source voltage difference drops to a preset threshold close to zero, the gate drive voltage is increased to the saturation region to complete the seamless physical connection from the main power supply to the backup power supply.

[0035] Step 1, dynamic potential bonding, establishes a closed-loop voltage feedback control system to maintain the backup power supply output at a highly synchronized hot standby potential state with the main power supply. Specifically, the system is equipped with a high-bandwidth differential voltage sampling circuit to acquire the voltage signal at the main power supply output in real time. The sampling circuit employs a 24-bit Σ-Δ analog-to-digital converter with a sampling frequency of no less than 500 kHz to ensure accurate capture of minute fluctuations in the bus voltage. The sampled digital signal is transmitted via a high-speed serial interface to the first processing core in the digital power management chip. This core incorporates a proportional-integral-derivative (PID) controller, whose control law expression is:

[0036] in, This is the closed-loop error signal. , , These are the preset proportional gain coefficient, integral gain coefficient, and derivative gain coefficient, whose values ​​are pre-calibrated and fixed in the controller firmware according to the system load characteristics and response speed requirements; V backup This is the feedback voltage signal. The controller's output adjustment applies to the backup power supply's digital pulse width modulation (DPWM) module, dynamically adjusting its output duty cycle to control... Precise tracking The target value.

[0037] Differential pressure margin It is not a fixed constant, but rather based on the real-time bus load current. Dynamic compensation is performed. The system obtains data through a Hall effect current sensor or a precision sampling resistor. The signal, after filtering and amplification, is sent to the analog-to-digital converter. The controller internally stores pre-calibrated... The mapping table, established through offline experiments under different load step conditions, specifies the pressure margin ΔV based on the formula ΔV = I. load × (R line_est + R margin Dynamic calculation, where R line_est The following steps are used for online estimation: (a) During the system initialization phase, while the main power supply is supplying power normally, the output of the backup power supply is adjusted to generate a small current disturbance, and R is estimated online based on the bus voltage fluctuation law. line_est (a) Record the bus voltage Vbusidle at this time; (b) Apply a preset light load current I light (e.g., 5% of rated current), record the bus voltage Vbus. light (c) Calculate R line_est = (Vbusidle - Vbus light ) / I light The light load current I light Power is supplied by a controllable electronic load or auxiliary DC-DC module for a duration not exceeding 10ms to prevent system power failure; R marginFor safety margin, the resistor should be 0.5–2 mΩ to ensure that ΔV is always within the range of 0.05V to 1% of the system's rated voltage (e.g., 0.05–0.5V). It is always constrained within a preset differential voltage margin range of 0.05V to 0.1V. For example, when When it is 10A, Set to 0.06V; when When it rises to 50A, It automatically adjusts to 0.09V to compensate for potential shifts caused by line impedance voltage drops. This dynamic compensation mechanism ensures that the backup power supply is in optimal hot standby mode under any load conditions, laying the potential foundation for seamless switching between primary and backup power.

[0038] In the above method, step 2, the transition state identification, relies on a dual criterion for rapid and reliable fault detection of the main power supply output state. The system continuously monitors two key signals: first, a hard-wired main power supply fault signal from the main control system, which is actively pulled low by the internal monitoring unit of the main power supply when overvoltage, undervoltage, overcurrent, or internal component failure is detected; second, the dynamic rate of change of the bus voltage itself. The latter acquires continuous voltage samples at a sampling frequency of no less than 1MHz using the aforementioned high-speed analog-to-digital converter, and the instantaneous voltage is calculated in real time by a digital signal processor using a three-point differential algorithm. Value. Preset. The threshold is set to -50 V / μs. This threshold was obtained through statistical analysis of a large amount of measured data and can effectively distinguish between normal load disturbances and real power supply failure events.

[0039] When any criterion is triggered—that is, the fault hardwire signal is valid or Upon exceeding the -50 V / μs threshold, the first processing core of the digital power management chip immediately generates a switching start command. This command contains a precise timestamp. The signal is then broadcast to the second processing core and peripheral drive circuits via a hardware synchronization bus. The delay of the entire identification and response process is strictly controlled within 500 nanoseconds to ensure a smooth switching procedure is initiated before the bus voltage drops to a critical level. Simultaneously, to prevent false triggering, the system incorporates software debouncing logic, requiring that dv / dt over-limit states be denoised by a digital filter, with a response time controlled within 500ns to ensure timely activation.

[0040] In the above method, the active impedance modulation of the Miller plateau region in step 3 occurs at the switching start time. The core of startup lies in applying a precisely controlled drive current to the gate of the metal-oxide-semiconductor field-effect transistor (MOSFET) at the backup power output terminal. The selected MOSFET is a superjunction N-channel device with a Miller plateau voltage. The voltage is determined by the thickness and doping concentration of the gate oxide layer inside the device, typically ranging from 2.8V to 3.5V. A dedicated gate drive circuit consists of a high-speed current source array, capable of receiving... After the command, within 5 nanoseconds The amplitude is increased from zero to the preset value.

[0041] The rise time is precisely limited to a time window of 10 nanoseconds to 20 nanoseconds. If the rise time is too fast, it may cause… If the rise time exceeds the Miller plateau region, the MOSFET will directly enter the saturation region, losing its linear control capability. If the rise time is too slow, the ineffective cutoff time will be prolonged, increasing the switching delay. Therefore, the driver circuit incorporates a programmable delay unit to fine-tune the delay according to the batch parameters of the MOSFETs. The injection slope. Once... Stable at Within a window of ±50mV, the MOSFET channel is forced to turn on into the linear operating region, at which point the drain-source equivalent resistance... It exhibits a high resistance state (typically several ohms to tens of ohms), but is continuously adjustable. The preset transition period during which the MOSFET remains in this state is... The initial value is set to 2 microseconds, and this cycle can be dynamically adjusted based on temperature feedback in subsequent steps.

[0042] In the above method, step 4, impedance S-type continuous evolution, is... Execution within a cycle is the core element for achieving smooth energy transfer. The controller utilizes the inherent transfer characteristics of MOSFETs in the linear region, i.e. and The nonlinear functional relationship between them can be finely adjusted. To control It decreases continuously according to a preset S-shaped function pattern. This S-shaped pattern is defined as follows: in the initial stage of conduction (0 to 0.4... ), The absolute value is less than 0.5 Ω / μs; in the medium term (0.4 to 0.7 Ω / μs). ), The absolute value increases to over 2.0 Ω / μs; in the final stage (0.7 to 1.0 Ω / μs). ), The absolute value decreased again to below 0.3 Ω / μs. The S-shaped function law adopts a third-order spline interpolation function or a modified sigmoid function under normalized time τ=t / Ttrans: RDS(τ) = Rhigh - (Rhigh - Rlow) / (1 + ek(τ-τ0)), where Rhigh is the initial high resistance, Rlow is the saturation on-resistance, k is the steepness coefficient, and τ0=0.5 is the inflection point. The value of k is obtained by looking up a table based on the current load current Iload, ensuring that dRDS / dt is <0.5 Ω / μs in the initial stage, >2.0 Ω / μs in the middle stage, and <0.3 Ω / μs in the final stage. In the modified sigmoid function, τ0 is fixed at 0.5. Rhigh is the measured RDS(on) value of the MOSFET at VGS=VMiller, and Rlow is its saturation on-resistance specification value. The value of k is obtained through offline calibration. The calibration method is: under the rated load current Iload_nom, adjust k so that dRDS / dt reaches 2.5 in the middle stage. Ω / μs, establish the mapping relationship table between Iload and k as follows: [Insert table, columns: Iload (A), k; rows: 10, 8; 50, 12; 100, 15]. The controller obtains k by looking up the table and interpolating based on the real-time Iload.

[0043] This evolutionary process is achieved through a combination of nonlinear lookup table and real-time feedback correction. The controller internally stores a three-dimensional lookup table (LUT), whose index dimension includes the current... Target value, load current and ambient temperature. The corresponding LUT output The control word is used by the drive circuit to adjust the current source output. Simultaneously, the system independently samples the MOSFET's current through the Kelvin connection pin. and Real-time calculation of actual The impedance is compared with the target value to form an inner loop feedback to correct the deviation of the LUT output. This dual-loop control structure ensures that the impedance change trajectory strictly follows an S-curve without any steps or oscillations.

[0044] Furthermore, MOSFETs exhibit significant power dissipation during linear operation, leading to a rapid rise in channel temperature. To address this, a miniature thermistor is integrated within the MOSFET package; its real-time temperature signal is amplified by a dedicated analog front-end before being fed into an analog-to-digital converter. The controller continuously calculates the temperature rise rate. When the rate exceeds 0.1°C / μs (or is set to a specific temperature rise slope constant), a risk of thermal runaway is identified. At this point, the controller automatically executes a protection strategy: on the one hand... Extend by 50%, on the other hand, reduce the mid-term of the S-shaped curve. The slope is capped at 1.0 Ω / μs, thereby slowing down the power dissipation rate and ensuring device safety.

[0045] In the above method, step 5, zero-difference full-conduction lockout, marks the final completion of the switching process. The system continuously monitors the voltage difference across the drain and source of the MOSFET using a differential amplifier. This amplifier features a common-mode rejection ratio exceeding 120dB and an input offset voltage below 10μV. Its output signal is quantized by a 16-bit analog-to-digital converter before being fed into the controller. (Preset...) The threshold value is set to 10mV, which takes into account both the normal voltage drop across the MOSFET's on-resistance and measurement noise.

[0046] The controller employs a multi-point confirmation mechanism: confirmation is only granted when five consecutive sampling points (intervals of 200 nanoseconds) are reached. Only when both voltages are below the 10mV threshold is the system considered to have reached zero differential voltage. Once this condition is met, the second processing core immediately outputs a full-conduction command, increasing the gate drive voltage. From Miller platform voltage The voltage is rapidly increased to 12V (the MOSFET's rated maximum gate-source voltage), bringing it fully into a milliohm-level saturation conduction state. At this point, the MOSFET's on-resistance... With a typical value below 2mΩ, the additional voltage drop on the busbar is negligible, thus achieving a seamless physical connection from the main power supply to the backup power supply.

[0047] Throughout the switching process, multiple auxiliary mechanisms work together to ensure system integrity. After the smooth switching procedure is initiated, the Schottky isolation diode at the main power supply output is synchronously turned off, with a reverse recovery time of less than 25 nanoseconds, effectively blocking any circulating current paths that may form between the main and backup power supplies. Simultaneously, the output filter capacitor of the backup power supply is configured to have a capacitance of no less than 2200μF, providing sufficient local energy buffering for switching transients and preventing bus voltage collapse due to remote power supply response delays.

[0048] The method is integrated into a custom digital power management chip. This chip is manufactured using a 40nm CMOS process and incorporates dual ARM Cortex-M7 processing cores. The first core, with a clock speed of 300MHz, is dedicated to dynamic potential alignment and transition state identification. The second core, with a clock speed of 400MHz and equipped with a hardware accelerator, is dedicated to active impedance modulation in the Miller plateau region, impedance S-shaped continuous evolution, and zero-dropout full-conduction lockout. When the first core generates the switching start command, it simultaneously triggers a single-pulse hardware synchronization signal, which is directly connected to the high-priority interrupt input of the second core. The second core immediately latches the system timestamp in its interrupt service routine and uses this as a reference to start the timer for step 3. All subsequent steps are phase-aligned based on the high-precision timer count value triggered by this hardware synchronization signal, ensuring that the timing deviation between the two cores does not exceed ±20 nanoseconds. The two cores coordinate through a low-latency hardware mailbox and interrupt signals, ensuring that the total time from the triggering of step 2 to the completion of step 5 does not exceed 5 microseconds. The hardware synchronization signal is an LVDS differential signal, driven by a dedicated low-jitter buffer, with a wiring length matching error of <1mm; the second core has a built-in high-resolution timestamp unit (TSC), whose clock source shares the same phase-locked loop (PLL) output as the first core; before the chip leaves the factory, the interrupt response delay difference Δt_delay between the two cores is measured by the built-in self-test (BIST) circuit, and the compensation value is written into the OTP memory; after latching the timestamp, the second core automatically subtracts Δt_delay as the starting time of step 3.

[0049] Specific application examples:

[0050] The method of this invention is deployed in a 48V / 100A data center server power system. Both the primary and backup power supplies are AC / DC rectifier modules, with their outputs connected in parallel to the 48V DC bus via MOSFETs controlled by this scheme. After system initialization, step 1 establishes a hot standby state. It is 48.00V. 80A, after dynamic compensation It is 0.085V, therefore It stabilized at 47.915V.

[0051] exist At any given moment, the main power supply simulates a fault. It drops at a rate of -60 V / μs. Step 2 identifies the fault and issues an alert within 800 nanoseconds. Instructions. Step 3 is then initiated, and the MOSFET's... It rises to 3.2V within 15 nanoseconds. (The system then enters the linear region.) Step 4 begins the S-type impedance evolution: Starting from an initial 15Ω, it is slowly reduced to 10Ω over 0.8 microseconds. Ω / μs), then rapidly decreased to 0.5Ω within 0.6 microseconds (Ω / μs). Ω / μs), and finally gradually decreased to 0.01Ω within 0.6 microseconds (Ω / μs). (Ω / μs). During this process, the MOSFET absorbs all transient energy between the main and backup power supplies, and the bus voltage fluctuation is suppressed to within ±50mV.

[0052] when When five consecutive samples are all below 10mV (occurring when...) (microseconds), triggered in step 5, The voltage jumped to 12V, and the MOSFET was fully turned on. The entire switching process was completed within 4.5 microseconds, with no perceptible drop or spike in the bus voltage. The power supply ripple of the back-end server CPU and memory remained within specifications, and the system operated without any interruption.

[0053] Example 2 In another embodiment, the method of the present invention is applied to a 24V / 200A 5G communication base station power supply system. Due to the larger load current, the system places higher demands on thermal management and dynamic response. Here, silicon carbide (SiC) devices are selected as MOSFETs, with a Miller plateau voltage of [missing information]. It operates at 4.5V, resulting in faster switching speed. The voltage differential margin in step 1... The range has been extended to 0.08V to 0.12V to accommodate higher line voltage drops.

[0054] In step 3, the controlled current Increased injection rate The rise time was shortened to 5 nanoseconds to match the high-speed characteristics of SiC devices. Step 4 The initial value was set to 1.5 microseconds, and the S-shaped evolution slope was increased accordingly: Mid-term The upper limit is 5.0 Ω / μs. To cope with greater power dissipation, multiple distributed thermistors are integrated into the MOSFET package. The controller uses a spatially weighted average algorithm to calculate the channel hot spot temperature, and the temperature rise rate threshold is set to 15°C / μs.

[0055] Furthermore, the digital power management chip has been upgraded to a tri-core architecture, with an additional core dedicated to handling thermal management tasks, tightly coupled with the second core executing step 4. When local overheating is detected, this core can dynamically adjust the local slope of the S-curve, and even trigger local current bypass in extreme cases. With this configuration, the system successfully completed the switching within 3.8 microseconds, and the bus voltage fluctuation was controlled within ±80mV, meeting the stringent requirements of 5G base stations for "zero interruption" power supply.

[0056] Example 3

[0057] In another embodiment, the method of the present invention is deployed in a 12V / 50A in-vehicle infotainment system. Considering the electromagnetic compatibility (EMC) challenges of the automotive electronic environment, the system is specifically optimized at the hardware level. The MOSFET is packaged in a shielded DFN package, and the parasitic inductance of its Kelvin connection pin is controlled to below 1nH. The gate drive circuit integrates an active Miller clamping function. near Automatic suppression factor False conduction caused by coupling.

[0058] Step 2 The threshold was set to -30 V / μs, and a soft signal indicating the main power supply health status based on the CAN bus was added as a third criterion, forming a triple-redundant fault detection. Step 5 The threshold value has been increased to 20mV to tolerate measurement noise from the longer leads in automotive wiring harnesses. Despite the parameter adjustments, the core technology chain of "Miller plateau active impedance modulation + S-type impedance continuous evolution + zero-dropout full conduction lockout" remains unchanged, ensuring smooth and reliable power switching even in harsh automotive environments.

[0059] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments; the embodiments and descriptions in the specification are merely preferred embodiments of the present invention. Various changes and modifications can be made to the present invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A power supply smoothing control method for suppressing DC bus voltage surges, characterized in that, Includes the following steps: Step 1: Dynamic Potential Fitting: Real-time sampling of the main power supply voltage, and control of the backup power supply output voltage through voltage closed-loop feedback, so that the backup power supply output voltage is equal to the main power supply voltage minus the voltage difference margin, wherein the voltage difference margin is dynamically compensated according to the bus load current and maintained within the preset voltage difference margin range. Step 2: Transitional state identification: When a main power supply fault signal is detected or the bus voltage drop rate exceeds a preset threshold, a smooth switching procedure is triggered. Step 3: Active impedance modulation of Miller plateau region: At the start of switching, a controlled current is injected into the gate of the metal-oxide-semiconductor field-effect transistor at the output of the backup power supply to drive the gate-source voltage to rise rapidly to the Miller plateau voltage. The amplitude of the controlled current is adjusted to force the metal-oxide-semiconductor field-effect transistor into the linear operating region and stay there for a preset transition period. Step 4 Impedance S-type continuous evolution: During the transition period, the transfer characteristics of the metal-oxide-semiconductor field-effect transistor in the linear region are utilized to control its drain-source equivalent resistance to continuously decrease from the high-resistance state to the saturated conduction state according to the S-type function law, so as to absorb the transient potential difference energy between the main and backup power supplies. Step 5 Zero-Difference Full-Conduction Lockout: Real-time monitoring of the drain-source voltage difference of the metal-oxide-semiconductor field-effect transistor. When the drain-source voltage difference drops to a preset threshold close to zero, the gate drive voltage is increased to the saturation region to complete the seamless physical connection from the main power supply to the backup power supply.

2. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, The voltage closed-loop feedback control in step 1 uses a proportional-integral-derivative regulator. The proportional gain coefficient, integral time constant, and derivative time constant of the regulator are all set to predetermined values ​​to dynamically adjust the differential pressure margin and maintain it within the preset differential pressure margin range when the load current changes abruptly.

3. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, The bus voltage sag rate in step 2 is acquired in real time by a high-speed analog-to-digital converter at a rate not lower than the preset sampling frequency, and the digital signal processor completes the judgment and response within a predetermined response time. The preset threshold of the bus voltage sag rate is set to a specified value.

4. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, The Miller plateau voltage in step 3 is determined based on the process parameters of the metal-oxide-semiconductor field-effect transistor used. The injection rate of the controlled current is controlled by a dedicated gate drive circuit, and its rise time is precisely limited within a preset time window to ensure that the device reliably enters the linear region without overshoot.

5. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, The S-shaped function law in step 4 is defined as follows: the rate of change of the drain-source equivalent resistance over time is less than the preset lower limit of the rate of change in the initial stage of conduction, increases to above the preset upper limit of the rate of change in the middle stage, and decreases again to below the preset lower limit of the rate of change in the final stage. This evolution process is achieved by nonlinear lookup table combined with real-time feedback correction.

6. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, In step 4, during the operation of the metal-oxide-semiconductor field-effect transistor in the linear region, its channel temperature is monitored in real time by an embedded thermistor. When the temperature rise rate exceeds the preset temperature rise rate threshold, the controller automatically extends the transition period and reduces the impedance drop slope.

7. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, In step 5, the voltage difference between the drain and source is detected by a differential amplifier and quantized by a multi-bit analog-to-digital converter before being sent to the controller. When multiple consecutive sampling points are all below the preset threshold, it is determined to be a zero voltage difference state and full conduction lockout is executed.

8. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, The package structure of the metal-oxide-semiconductor field-effect transistor has a built-in Kelvin connection pin for independently leading out the gate drive circuit and the power circuit, and its parasitic inductance is less than a preset inductance threshold.

9. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, After the smooth switching program is started, the isolation diode at the output of the main power supply is turned off synchronously, and its reverse recovery time is less than a preset time threshold. At the same time, the output filter capacitor of the backup power supply is configured to be no less than a preset capacitance value.

10. The power supply smooth switching control method for suppressing DC bus voltage surges according to claim 1, characterized in that, The method is integrated into a digital power management chip, which has a built-in multi-core processor. One core is dedicated to performing dynamic potential bonding and switching transition state identification, while the other core is dedicated to performing active impedance modulation of the Miller plateau region, continuous impedance S-type evolution, and zero-difference full conduction lockout. The two cores are coordinated through hardware synchronization signals to ensure that the entire switching process is completed within the preset total time.

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