Method for fast turn off and recovery of regulated outputs

Abstract

Disclosed is bias circuitry for an amplifier. The bias circuitry (10) includes a bias generator (12) having a bias generator output terminal (14), and a switch having a bias input terminal (28), an amplifier bias output terminal (24), a bias shunt terminal, and a switch control terminal. The switch is configured to switch a bias generated by the bias generator to the amplifier bias output terminal in response to a connect bias signal received at the switch control terminal and to switch from the amplifier bias output terminal to the bias shunt terminal in response to a disconnect bias signal. An overvoltage detector (38) is configured to monitor a supply voltage to the amplifier and in response to generate the disconnect bias signal when the supply voltage exceeds a reference voltage and to generate the connect bias signal when the supply voltage level is less that the reference voltage.

Description

METHOD FOR FAST TURN OFF AND RECOVERY OF REGULATED OUTPUTSRelated Applications

[0001] This application claims the benefit of provisional patent application serial number 63 / 569,764, filed March 26, 2024, and provisional patent application serial number 63 / 543,197, filed October 9, 2023, the disclosures of which are hereby incorporated herein by reference in their entireties.Field of the Disclosure

[0002] The present disclosure relates to power amplifiers with protective circuitry and in particular to radio frequency power amplifiers having overvoltage protective circuitry.Background

[0003] In a cellular network a power amplifier is used for transmitting data from the mobile phone to the basestation. The power amplifier can, however, experience a higher voltage than that for which it is designed. So as to protect the power amplifier, overvoltage protection is used. Current solutions for protecting power amplifiers against overvoltage work by turning off the bias to the power amplifier. This is currently achieved by turning off the bias circuit. This solution, however, presents a challenge in that the response time and especially the release time are too slow. This slow release time can cause unwanted loss of data when the bias circuit resumes biasing the power amplifier, which results in less data transmitted.Summary

[0004] Disclosed is a bias circuit designed to improve release time from when the bias output is low to when the bias output is ready again, which results in a lower loss of data after an overvoltage occurrence. The bias circuit according to the present disclosure is as fast or faster at turning off the output as the bias circuit in existing solutions. The disclosed circuit is much faster than existing solutions at turning output back on. In addition, the disclosed circuit keeps the bias circuit loop turned on while the output is off.

[0005] In another aspect, any of the foregoing aspects individually or together, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0006] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.Brief Description of the Drawing Figures

[0007] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0008] FIG. 1 is a generalized diagram of an embodiment of bias circuitry depicting nominal operation wherein a generated bias voltage and / or current is switched to a bias output terminal in accordance with the present disclosure.

[0009] FIG. 2 is a generalized diagram of the embodiment of the bias circuitry depicting protective operation wherein a generated bias voltage and / or current is switched to a protective load during an overvoltage event.

[0010] FIG. 3 is a diagram of an exemplary detailed embodiment of the bias circuitry of FIG. 1 and FIG. 2.

[0011] FIG. 4 is a schematic diagram of an exemplary communication device wherein the bias circuitry can be employed.Detailed Description

[0012] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. Itshould be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0013] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0014] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0015] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0016] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0018] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re-described.

[0019] FIG. 1 is a generalized diagram of an embodiment of bias circuitry 10 depicting normal operation wherein a bias generator 12 is configured togenerate a bias level that may be a bias voltage or bias current output through a bias generator output terminal 14. The bias generator 12 is configured to maintain the bias level by way of a regulation feedback loop 16 that is coupled between the bias generator output terminal 14 and feedback terminal 18. In this exemplary embodiment, the bias level is maintained in proportion to a first reference voltage REFI that is input at a first reference terminal 20. A switching circuitry 22 is configured to switch the bias level at the bias generator output terminal 14 to an amplifier bias output terminal 24 through a first switch SW1 during normal operation. The first switch SW1 is depicted symbolically as a single-pole-double-throw switch in FIG. 1 . However, the first switch SW1 is typically made up of transistors.

[0020] As shown in FIG. 1 , the bias level may be used to bias a radio frequency (RF) amplifier 26. The bias level is received at a bias input terminal 28. In normal operation, the RF amplifier 26 receives an RF signal at an RF input terminal 30 labeled RFIN and outputs an amplified version of the RF signal through an RF output terminal 32 labeled RFOUT. The RF amplifier 26 is powered through a supply terminal 34 and a fixed node terminal 36. A supply voltage Vcc is applied to the supply terminal 34 and ground (GND) is coupled to the fixed voltage node 36 in this exemplary embodiment. Other embodiments may couple a negative direct current (DC) voltage to the fixed node terminal 36.

[0021] RF amplifiers such as RF amplifier 26 may be damaged or destroyed by temporary spikes of overvoltage of the supply voltage Vcc. To mitigate this potential for overvoltage damage, the bias circuitry 10 includes an overvoltage detector 38 configured to generate a disconnect signal DIS_OUT that switches the bias level output from the bias generator 12 to a protective load 40 that is coupled between a load terminal 42 and the fixed voltage terminal 36. The protective load 40 may be a load resistor RLD and / or a load capacitor CLD. In the exemplary embodiment of FIG. 1 , the protective load 46 is a parallel combination of the load resistor RLD and the load capacitor CLD. In embodiments, wherein only the load capacitor CLD makes up the protective load 40, charge stored by the load capacitor will substantially dissipate before a subsequent charging event occurs.

[0022] A control terminal 44 of the first switch SW1 is coupled to an overvoltage signal terminal 46 of the overvoltage detector 38. Logic states of the disconnect signal DIS_OUT determine whether the bias level generator 12 is applied to the bias input terminal 28 or the protective load 40. The overvoltage detector 38 has a voltage sense terminal 48 to which an instantaneous voltage level of the supply voltage Vcc is sensed. The overvoltage detector 38 also has a second reference voltage terminal 50 at which a second reference voltage VREF2 is applied. The overvoltage detector 38 is configured to compare the instantaneous voltage level of the supply voltage Vcc with the second reference voltage VREF2 and in response to generate the logic states of the disconnect signal DIS_OUT. A first logic state of the disconnect signal DIS_OUT is a connect state that connects the bias generated by the bias generator to the amplifier bias output terminal 24 that is coupled to the bias input 28 of the RF amplifier 26. FIG. 1 depicts the bias level being applied to the bias input terminal 28 through the first switch SW1 because the overvoltage detector 38 is shown detecting the supply voltage being less than the second reference voltage VREF2.

[0023] FIG. 2 depicts the bias circuitry 10 in response to the overvoltage detector 38 generating a second logic state of the disconnect signal DIS_OUT, which in this case is a disconnect state in response to an overvoltage event. The disconnect state of the disconnect signal DIS_OUT disconnects the bias generated by the bias generator 12 from the amplifier bias output terminal 24 by way of the first switch SW1 . The first switch SW1 then connects the bias level to the protective load 40 for the duration of the overvoltage event. FIG. 2 depicts the bias level being applied to the load terminal 42 through the first switch SW1 because the overvoltage detector 38 is shown detecting the supply voltage being greater than the second reference voltage REF2. An advantage that the bias circuitry 10 has over traditional circuitry of similar function is that the bias circuitry 10 is configured to maintain the regulation feedback loop 16 closed while the generated bias level is switched to the protective load 40 to ensure a lower release time / turn- back-on time.

[0024] FIG. 3 is a diagram of an exemplary detailed embodiment of the bias circuitry 10 of FIG. 1 and FIG. 2. An exemplary version of the biasgenerator 12 includes a bias amplifier 52 that is coupled between the bias generator output terminal 1 , the feedback terminal 18, and the first reference terminal 20. A first feedback resistor RF1 is coupled within the feedback loop 16 between the bias generator output terminal 1 and the feedback terminal 18. A second feedback resistor RF2 is coupled between the feedback terminal and ground.

[0025] An exemplary embodiment of the switch circuitry 22 is also depicted in FIG. 3. In this exemplary embodiment, the first switch SW1 is made up of a first transistor M1 , a second transistor M2, and a third transistor M3. The first transistor M1 is a P-channel field-effect transistor (PFET) having a first source S1 coupled to the bias generator output terminal 14, a first drain D1 coupled to the amplifier bias output terminal 24, and a first gate G1 coupled to the control terminal 44. The second transistor M2 is an N-channel FET (NFET) having a second drain D2 coupled to the first drain D1 , a second source S2 coupled to ground, and a second gate G2 coupled to the control terminal 44. The third transistor M3 is a PFET having a third source S3 coupled to the bias generator output terminal 14, a third drain D3 coupled to the load terminal 42, and a third gate G3 coupled to the control terminal 44 through an inverter logic gate 54.

[0026] FIG. 3 also depicts an exemplary embodiment of the overvoltage detector 38. In this exemplary embodiment an operational transconductance amplifier (OTA) 56 is configured as a comparator to compare the supply voltage Vcc with the second reference voltage VREF2. The OTA 56 is coupled between the voltage sense terminal 48, the second reference voltage terminal 50, and an OTA output terminal 58. A Schmidt trigger 60 has a trigger input 62 coupled to the OTA output terminal 58 and a trigger output terminal 64 coupled to the overvoltage signal terminal 46.

[0027] The method according to the present disclosure gives a turn-back- on time / release time advantage in that it does not power off any of the circuitry in the bias generator and does not pull the feedback point low. The difference in release time can be seen in Table 1 . The feedback loop is similar to a traditional amplifier configuration of an operational transconductance amplifier or operational amplifier as shown in FIG. 3. The advantage of notswitching off the feedback is clear from the disclosed method response and release times made possible by the structure of the bias circuitry 10.Table 1

[0028] The disclosed bias circuitry 10 and method of operation use the first switch SW1 and the protective load 40 to keep the regulator operating if the bias level output to the RF amplifier 26 is only disabled for a shorter period or is turned back on in a short amount of time.

[0029] The disclosed method can be implemented with other kinds of loads as well; for example, a regulator capacitor may be constantly connected to the regulated voltage to act as a further load to keep the regulator operating while the output is disabled. This demonstrates how the disclosed method keeps the regulation loop operating even when the bias output is turned off, which results in a much faster recovery time.

[0030] FIG. 4 is a schematic diagram of an exemplary communication device 66 wherein the bias circuitry 10 can be employed. Herein, the communication device 66 can be a communication device, such as a mobile terminal, a smart watch, a tablet, a computer, a navigation device, an access point, a basestation (e.g., eNB or gNB), and any other type of wireless communication device that supports wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, ultra-wideband (UWB), and near-field communications. The communication device 66 generally includes a control system 68, a baseband processor 70, transmit circuitry 72, receive circuitry 74, antenna switching circuitry 76, multiple antennas 78, and user interface circuitry 80. In a non-limiting example, the control system 68 can be a field-programmable gate array (FPGA). In this regard, the control system 68 can include one or more of at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitry 74 receives radio frequency signals via theantennas 78 and through the antenna switching circuitry 76 from one or more basestations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using one or more analog-to-digital converters (ADCs).

[0031] The baseband processor 70 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 70 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0032] For transmission, the baseband processor 70 receives digitized data, which may represent voice, data, or control information, from the control system 68, which it encodes for transmission. The encoded data is output to the transmit circuitry 72, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier such as RF amplifier 26 (FIGS. 1 -3) amplifies the modulated carrier signal to a level appropriate for transmission and delivers the modulated carrier signal to the antennas 78 through the antenna switching circuitry 76. The multiple antennas 78 and the replicated transmit circuitry 72 and receive circuitry 74 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0033] In an embodiment, the bias circuitry 10 may be provided in any one or more of the circuitries in the communication device 66, such as the transmit circuitry 72 and / or the receive circuitry 74.

[0034] It is contemplated that any of the foregoing aspects, and / or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0035] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

AMENDED CLAIMS received by the International Bureau on 05. Feb. 2025 (05.02.2025)1 . Bias circuitry (10) for an amplifier comprising:• a bias generator (12) having a bias generator output terminal (14);• a switch coupled to the bias generator output terminal (14) and controllably coupled between an amplifier bias output terminal (24) and a load terminal (42), and a switch control terminal, wherein the switch is configured to switch a bias generated by the bias generator (12) to the amplifier bias output terminal (24) in response to a connect bias signal received at the switch control terminal and to switch from the amplifier bias output terminal to the load terminal (42) in response to a disconnect bias signal; and• an overvoltage detector (38) configured to monitor a supply voltage to the amplifier and in response to generate the disconnect bias signal when the supply voltage exceeds a reference voltage and to generate the connect bias signal when the supply voltage level is less that the reference voltage.

2. (Cancelled).

3. The bias circuitry of claim 1 further comprising a protective load coupled between the load terminal and ground.

4. The bias circuitry of claim 3 wherein the protective load is a resistor.

5. The bias circuitry of claim 3 wherein the protective load is a capacitor.

6. The bias circuitry of claim 3 wherein the protective load is a resistor coupled in parallel with a capacitor.15AMENDED SHEET (ARTICLE 19)7. The bias circuitry of claim 3 wherein the bias generator has a closed feedback loop that is configured to remain closed when the bias is switched to the load terminal.

8. A method for protecting an amplifier having bias circuitry (10) that includes a bias generator (12) having a bias generator output terminal (14), and a switch coupled to the bias generator output terminal (14) and controllably coupled to an amplifier bias output terminal (24) and a load terminal (42), and a switch control terminal, the method comprising:• switching a bias generated by the bias generator to the amplifier bias output terminal (24) in response to a connect bias signal received at the switch control terminal and to switch from the amplifier bias output terminal (24) to a protective load (40) in response to a disconnect bias signal; and• monitoring a supply voltage to the amplifier by way of an overvoltage detector (38) and in response to generate the disconnect bias signal when the supply voltage exceeds a reference voltage and to generate the connect bias signal when the supply voltage level is less than the reference voltage.

9. (Cancelled).

10. The method for protecting the amplifier of claim 8 further comprising shunting the bias to the protective load coupled between the load terminal and ground in response to the disconnect bias signal so that the protective load is maintained on the bias generator.

11. The method for protecting the amplifier of claim 10 wherein the protective load is a resistor.

12. The method for protecting the amplifier of claim 10 wherein the protective load is a capacitor.16AMENDED SHEET (ARTICLE 19)13. The method for protecting the amplifier of claim 10 wherein the protective load is a resistor coupled in parallel with a capacitor.

14. A wireless communication device (66) comprising:• a baseband processor (70);• transmit circuitry (72) configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data, wherein the transmit circuitry comprises:• the amplifier that is configured to amplify the carrier signal while being biased by the bias circuitry of claim 1 .

15. (Cancelled).

16. The wireless communication device of claim 14 further comprising a protective load coupled between the load terminal and ground.

17. The wireless communication device of claim 16 wherein the protective load is a resistor.

18. The wireless communication device of claim 16 wherein the protective load is a capacitor.

19. The wireless communication device of claim 16 wherein the protective load is a resistor coupled in parallel with a capacitor.

20. The wireless communication device of claim 16 wherein the bias generator has a closed feedback loop that is configured to remain closed when the bias is switched to the load terminal.17AMENDED SHEET (ARTICLE 19)STATEMENT UNDER ARTICLE 19(1)Applicant submits amendments under Article 19 PCT for the above-referenced application.Applicant has amended original claims 1, 3-8, 10-14, and 16-20. Claims 2, 9, and 15 have been cancelled.Claim 1 has been amended to delete the term “and” after the first limitation and to insert the subject matter of claim 2 as a third limitation. In the second limitation, terms are replaced as follows: “having” is replaced by “coupled to”; “bias input terminal (28)” by “bias generator output terminal (14)”; and “bias shunt terminal” by “load terminal (42).” Element numbers are inserted for the following terms: “bias generator (12)” and “amplifier bias output terminal (24)”; and the term “and” is inserted before the third limitation.Claim 3 has been amended to replace the term “shunt load” with the term “protective load” and to replace the term “bias shunt terminal” with the term “load terminal.”Claims 4 to 6 have been amended to replace the term “shunt load” with the term “protective load.”Claim 7 has been amended to replace the term “shunted” with the term “switched” and to replace the term “bias shunt terminal” with the term “load terminal.”Claim 8 has been amended to replace the phrase “having a bias input terminal (28),” with the phrase “coupled to the bias generator output terminal (14) and controllably coupled to”; to replace the phrase “(24), a bias shunt terminal” with the phrase “(24) and a load terminal (42)”; and to insert a colon immediately after the phrase “the method comprising” and before the term “switching.” The element number has been inserted for the term “amplifier bias output terminal (24)”; the phrase “the bias shunt terminal” is replaced by the phrase “a protective load (40)”; and a semicolon and the term “and” are inserted before the subject matter of claim 9, which is inserted as a second limitation.Claim 10 has been amended to replace the term “a shunt load” with the term “the protective load”; to replace the term “bias shunt terminal” with the term “load terminal”; and to replace the term “a load” with the term “the protective load.”Claims 11 to 13 have been amended to replace the term “shunt load” with the term “protective load.”Claim 14 has been amended to delete the last three limitations and to replace the text “an amplifier configured to amplify the carrier signal; and” with the text “the amplifier that is configured to amplify the carrier signal while being biased by the bias circuitry of claim 1.”Claim 16 has been amended to replace the term “shunt load” with the term “protective load” and to replace the term “bias shunt terminal” with the term “load terminal.”Claims 17 to 19 have been amended to replace the term “shunt load” with the term “protective load.”Claim 20 has been amended to replace the term “shunted” with the term “switched” and to replace the term “bias shunt terminal” with the term “load terminal.”

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