Microelectronic device

Abstract

Title: Microelectronic Device The invention relates to a GaN-based power transistor comprising: - a stack (1) of layers (10, 11, 12, 13, 14) in a vertical direction (z), said stack (1) comprising, from a top surface (100) of said stack: A first barrier (11) based on AlGaN, A layer (10) based on GaN, A second barrier (12) based on AlGaN, - a gate pattern (20) comprising: A metallic gate (21) A gate dielectric (22) electrically insulating the metallic gate (21) of the stack (1), Said gate pattern (20) passing through the first barrier (11) based on AlGaN. Advantageously, the gate pattern (20) of the transistor completely traverses the GaN-based layer (10) and at least partially the second AlGaN-based barrier (12), along the vertical (z) direction. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Microelectronic device technical field

[0001] The present invention relates to the field of microelectronics. Its particularly advantageous application lies in the fabrication of GaN-based power transistors. A specific application example concerns two-dimensional electron gas (2DEG) GaN transistors. STATE OF THE ART

[0002] In the field of power electronics, an important issue concerns the development of power transistors based on "wide band gap" semiconductors such as GaN.

[0003] Various architectures have been specifically developed for these GaN-based transistors. Architectures based on the use of a two-dimensional electron gas (2DEG) typically allow operation with high source-drain bias voltages. A positive threshold voltage advantageously simplifies the transistor's control circuit and ensures the safety of the conversion system in case of failure.

[0004] The document "Miyamoto et al., Jpn. J. Appl. Phys. 59 044002, 2020" discloses a 2DEG GaN transistor with a positive threshold voltage. This transistor comprises a stack of layers in a vertical (z) direction comprising, from a top surface of said stack: - A first barrier based on AlGaN, - A channel based on GaN, - A second barrier based on AlGaN.

[0005] This transistor further comprises a gate pattern including: - A metal grid - A grid dielectric separating the metallic grid from the layers of said stack.

[0006] The GaN-based channel is located between the first and second AlGaN-based barriers, and the gate pattern of this transistor passes through the first AlGaN-based barrier and opens at its lower end into the GaN-based channel. In this architecture, the two-dimensional electron gas is formed by piezoelectric and spontaneous polarization under the first AlGaN-based barrier, on either side of the gate pattern. Applying a source-gate voltage Vgs greater than the threshold voltage Vth allows electrons to flow in the channel. The threshold voltage is made positive here by the presence of the second AlGaN-based barrier. by a simple electrostatic effect.

[0007] One drawback of this solution is that the threshold voltage is relatively low (<1V), which may necessitate controlling the transistor in the off state with a Vgs value <0. Applying a Vgs <0 voltage requires a more complex control circuit. Furthermore, it turns out that, with this solution, the transistor's resistance in the on state increases. This degrades the on-state current.

[0008] There is therefore a need to propose a 2DEG GaN power transistor architecture that overcomes the disadvantages mentioned above.

[0009] An object of the present invention is to provide a GaN-based power transistor having a positive and sufficiently high threshold voltage Vth, typically Vth > IV and preferably Vth > 2 V.

[0010] The other objects, features, and advantages of the present invention will become apparent from an examination of the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0011] To achieve this objective, according to one embodiment, a GaN-based power transistor is provided comprising a stack of layers in a vertical direction (z), said stack comprising, from an upper surface of said stack: - A first barrier based on AlGaN, - A GaN-based layer, - A second barrier based on AlGaN.

[0012] This transistor further comprises a gate pattern including: - A metal grid - A grid dielectric electrically insulates the metallic grid of the stack.

[0013] The transistor gate pattern passes through the first AlGaN-based barrier.

[0014] Advantageously, the gate pattern of the transistor passes completely through the GaN-based layer and at least partially through the second AlGaN-based barrier. The lower end of the gate pattern opens into, or below, said second AlGaN-based barrier, for example, into a second GaN-based layer forming a conduction channel. There is thus an intersection between the gate pattern and the second AlGaN-based barrier.

[0015] The bias voltage Vgs required for electrons to flow around the gate pattern is thus increased. The threshold voltage Vth beyond which the transistor is in the conducting state is significantly increased.

[0016] This increase in Vth is induced to the first order by the physical barrier formed by the second AlGaN-based barrier for electron passage. The threshold voltage is no longer modulated solely by electrostatic repulsion, as is the case in the transistor disclosed by the prior art solution. On the contrary, the threshold voltage is augmented here by an additional potential barrier to overcome.

[0017] The threshold voltage also benefits to the second order from the electrostatic repulsion effect induced near the second AlGaN-based barrier.

[0018] A synergistic effect is thus obtained between the first, predominant effect, linked to the crossing of the second barrier itself, and the second, minor effect, linked to the electrostatic repulsion surrounding said second barrier.

[0019] The principle of increasing Vth on which the present invention is based is thus fundamentally different from the principle on which the prior art solution is based.

[0020] The transistor according to the present invention thus has a threshold voltage Vth significantly higher than that of the transistor according to the prior art.

[0021] Furthermore, during the development of the present invention, it became apparent that the increase in forward resistance observed when implementing the prior art solution was due to the proximity of the second AlGaN-based barrier to the first AlGaN-based barrier. The two-dimensional electron gas formed under the first AlGaN-based barrier is indeed scattered by the electrostatic field prevailing around the second barrier. Thus, the closer the second barrier is to the first barrier, the more the two-dimensional electron gas is scattered, and the greater the forward resistance.

[0022] According to the present invention, the gate pattern is extended in depth at least to the second barrier. This advantageously allows the second barrier to be moved further away from the first barrier, so as to limit or even eliminate the depletion of the two-dimensional electron gas formed under the first AlGaN-based barrier. By way of example, the second AlGaN-based barrier is separated from the first AlGaN-based barrier by a GaN layer with a thickness greater than or equal to 50 nm, preferably greater than or equal to 100 nm. This significantly limits the increase in on-state resistance of the transistor. BRIEF DESCRIPTION OF THE FIGURES

[0023] The aims, objects, features and advantages of the invention will become clearer from the detailed description of embodiments thereof, which are illustrated by the following accompanying drawings in which:

[0024] [Fig.1] Fig.1 schematically illustrates a transistor according to a first embodiment of the present invention.

[0025] [Fig.2] Fig.2 schematically illustrates a transistor according to a second mode of realization of the present invention.

[0026] [Fig.3] Fig.3 schematically illustrates a transistor according to a third mode of realization of the present invention.

[0027] [Fig.4] Figure [Fig.4] schematically illustrates a transistor according to a fourth mode of realization of the present invention.

[0028] [Fig. 5] Figure 5 shows a curve of the evolution of the threshold voltage Vth of the transistor gate as a function of the concentration of aluminium [Al]2 in the second AlGaN-based barrier.

[0029] [Fig.6] Figure [Fig.6] shows a curve of the evolution of the threshold voltage Vth of the transistor gate as a function of the thickness el2 of the second AlGaN-based barrier.

[0030] The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, in the schematic diagrams, the thicknesses of the different layers and the dimensions of the different motifs (grid, source, drain, etc.) are not representative of reality. DETAILED DESCRIPTION

[0031] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0032] According to one example, the GaN-based layer and the second AlGaN-based barrier are in contact with each other at an interface plane, and the grid pattern forms an intersection with said interface plane. The intersection between the grid pattern and the interface plane is understood in particular in a mechanical sense. According to one example, only the grid dielectric forms an intersection with the interface plane. According to another example, the grid dielectric and the metallic grid each form an intersection with said interface plane.

[0033] According to one example, the grid pattern totally crosses the second AlGaN-based barrier in the vertical direction z.

[0034] According to one example, the metallic grid of the grid pattern has one end at the level of a basal plane parallel to the interface plane and passing within the second AlGaN-based barrier.

[0035] According to one example, the metallic grid of the grid pattern has one end at the level of a basal plane parallel to the interface plane and passing within the GaN-based layer.

[0036] According to one example, the metal grid of the grid pattern has an end located at a depth d210 and the second AlGaN-based barrier has a surface located at a depth dl2, such that d210 < dl2, said depths d210 and dl2 being taken in the vertical direction from a reference plane passing through the top surface of the stack.

[0037] According to one example, the metal grid of the grid pattern has an end located at a depth d210 and the second AlGaN-based barrier has a surface located at a depth dl2, such that d210 > dl2, said depths d210 and dl2 being taken along the vertical direction from a reference plane passing through the top surface of the stack.

[0038] According to one example, the metallic grid of the grid pattern has an end located at a depth d210 and the GaN-based layer has a surface located at a depth dlO, such that d210 < dlO, said depths d210 and dlO being taken along the vertical direction from a reference plane passing through the top surface of the stack.

[0039] According to one example, the metallic grid of the grid pattern has an end located at a depth d210 and the GaN-based layer has a surface located at a depth dlO, such that d210 > dlO, said depths d210 and dlO being taken along the vertical direction from a reference plane passing through the top surface of the stack.

[0040] According to one example, the grid pattern has one end located at a depth d20 and the second AlGaN-based barrier has a surface located at a depth dl2, such that d20 < dl2, said depths d20 and dl2 being taken along the vertical direction from a reference plane passing through the top surface of the stack.

[0041] According to one example, the grid pattern has one end located at a depth d20 and the second AlGaN-based barrier has a surface located at a depth dl2, such that d20 > dl2, said depths d20 and dl2 being taken along the vertical direction from a reference plane passing through the top surface of the stack.

[0042] According to one example, the second AlGaN-based barrier has an aluminium [Al]2 concentration between 2%at and 8%at.

[0043] As an example, the concentration of aluminum [Al]2 exhibits a Gaussian profile along the vertical direction. This makes the second barrier less abrupt for the passage of the two-dimensional electron gas. The current of the transistor in the on-state is thus less degraded.

[0044] According to one example, the second AlGaN-based barrier exhibits an aluminum [Al]2(z) concentration gradient along the vertical direction.

[0045] According to one example, the second AlGaN-based barrier has a thickness el2 taken along the vertical direction between 20nm and 50nm.

[0046] According to one example, the second AlGaN-based barrier comprises a plurality of layers arranged in a superlattice. This plurality of layers can form quantum wells.

[0047] According to one example, the transistor further comprises a source and a drain on either side of the gate pattern, said source totally traversing in the vertical direction the second AlGaN-based barrier.

[0048] Except where incompatibility exists, technical features described in detail for a given embodiment may be combined with technical features described in the context of other embodiments described by way of example and without limitation, so as to form another embodiment which is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0049] Within the framework of the present invention, the power transistor architectures envisaged are typically lateral conduction, between a source and a drain, and more particularly based on a principle of conduction by two-dimensional electron gas (2DEG).

[0050] Such a transistor architecture includes the superposition of two semiconductor layers having different band gaps, which form a quantum well at their interface. This quantum well is induced by the spontaneous and piezoelectric polarization charges present. Electrons are confined within this quantum well to form a two-dimensional electron gas.

[0051] HEMT type transistors (acronym for "High Electron Mobility transistor", which means high electron mobility field-effect transistor), sometimes also referred to as heterostructure field-effect transistors, are examples of transistors based on this two-dimensional electron gas architecture.

[0052] For reasons of power handling (particularly high voltage) and temperature resistance, the semiconductor material of these transistors is chosen to exhibit a wide band gap. Among HEMT transistors with a wide band gap, gallium nitride-based transistors are very promising.

[0053] With a side-conducting transistor, the gate-to-drain breakdown voltage can be easily controlled by an appropriate gate-to-drain distance. A breakdown voltage on the order of 600 V can thus be achieved for a gate-to-drain distance of the transistor on the order of a few microns (6 to 15 pm, for example). Furthermore, such transistors allow for very high current densities due to the very high electron mobility and the high electron density in the interfacial electron gas.

[0054] In the context of the present invention, the passage of current is typically controlled by a grid that is positively biased with respect to the source.

[0055] This gate can be of the MOS or MOSFET type (Metal Oxide Semiconductor Field Effect Transistor). In this case, the metal gate is electrically isolated from the semiconductor layers by a gate dielectric. Other gate compositions can be considered. A particular feature of the transistor architectures according to the present invention is that the gate spans the quantum well in which the two-dimensional electron gas is confined. The continuity of the two-dimensional electron gas is thus broken by a trench in which the MOS gate of the transistor is formed.

[0056] Generally, if the gate of the transistor is brought to a voltage greater than a threshold voltage, there is an accumulation of electrons under the gate dielectric, thus connecting the two-dimensional gas of electrons on either side of it, which allows the source and the drain to be connected so that the transistor becomes conducting.

[0057] If the gate of the transistor is brought to a voltage lower than the threshold voltage, the source and the drain are no longer connected and the transistor is said to be blocked.

[0058] Components exhibiting a positive threshold voltage are called "enhancement" or, in English, "normally-off." The invention applies more particularly to 2DEG enhancement power transistors.

[0059] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0060] For example, and in a way known per se in the field of GaN-based HEMT transistors, a thin AIN layer can be intercalated between two GaN and AlGaN semiconductor layers.

[0061] A layer may also be composed of several sub-layers of the same material or of different materials.

[0062] A substrate, stack, layer, "based" on a material A means a substrate, stack, layer comprising only that material A or that material A and possibly other materials, for example alloying elements and / or dopant elements.

[0063] The doping ranges associated with the different types of doping indicated in this application are as follows: - P++ or n++ doping: greater than 1 x 1020 cm3 - p+ or n+ doping: 1 x 10¹⁸ cm³ to 9 x 10¹⁹ cm³ - Doping p or n: 1 x 1017 cm3 to 1 x 1018 cm3 - intrinsic doping or unintentionally doped: of the order of n. 1015 cm3 or below (n being typically between 1 and 9).

[0064] A preferably orthonormal coordinate system, comprising the x, y, z axes, is shown in the accompanying figures. When only one coordinate system is shown on the same sheet of figures, this coordinate system applies to all the figures on that sheet.

[0065] In the present patent application, the thickness of a layer is taken along a direction normal to the principal extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms "on", "overlies", "under", "subsoil" refer to positions taken along the z direction.

[0066] The terms "vertical" and "vertically" refer to a direction along z. The terms "horizontally" and "horizontally" refer to a direction in the xy plane.

[0067] An element located "in line with" or "directly above" another element means that these two elements are both located on the same line perpendicular to a plane in which extends mainly a lower or upper face of a substrate, that is to say on the same line oriented vertically in the figures.

[0068] Examples of transistors according to the present invention are illustrated in Figures 1 to 4. The general architecture of these transistors comprises a source 31 and a drain 32 formed on either side of a gate pattern 20. The gate pattern 20 extends partially through a stack 1 of layers 10, 11, 12, 13, 14 formed on a substrate 15. General characteristics of these transistors, common to all embodiments, are indicated below. The characteristics specific to each embodiment are detailed subsequently.

[0069] The substrate 15 may be a silicon-based substrate (111). Alternatively, the substrate 15 may be sapphire- or SiC-based. Known GaN-on-sapphire or GaN-on-silicon substrates can typically be used.

[0070] The stack 1 may comprise a plurality of layers based on III-V materials epitaxially deposited on the substrate 15. The stack 1 thus typically comprises, starting from the substrate 15 and along the z-direction: - One or more buffer layers 14. These layers 14 aim to improve the crystalline quality of the upper layers. They can, for example, compensate for differences in lattice parameters between the IILV materials used and the substrate, and / or absorb the plastic relaxation induced by different sources of mechanical stress, and / or limit the appearance or transmission of crystalline defects. - A layer 13 of GaN that was not intentionally doped. - The second barrier 12 based on AlGaN. The second barrier 12 based on AlGaN has a thickness el2 between 20 nm and 50 nm. - The GaN-based layer 10 is unintentionally doped. The GaN-based layer 10 has a thickness elO, for example between 50 nm and 200 nm. - The first barrier 11 based on AlGaN. The first barrier 11 based on AlGaN has a thickness el 1, for example between 20 nm and 100 nm.

[0071] The various epitaxial layers, in particular the first and second barriers 11, 12 and the GaN-based layer 10, can be very precisely controlled in thickness. A variability of less than 0.5 nm in thickness is typically obtained for these epitaxial layers. This ultimately allows precise control of the distances separating the different layers and the desired electrostatic effects.

[0072] The second AlGaN-based barrier 12 typically comprises an aluminum [Al]2 content between 2 at.% and 8 at.%. An [Al]2 content of approximately 8 at.% or less maintains a lattice parameter compatible with GaN epitaxy of the crystalline quality required for the transistor. The GaN-based layer 10 can thus be epitaxially grown on the second AlGaN-based barrier 12, limiting the occurrence of crystalline defects. A high aluminum content can decrease the current flowing through the second barrier 12. According to one possibility, the second AlGaN-based barrier 12 exhibits an aluminum concentration gradient [Al]2(z) along z. For example, [Al]2(z) has a Gaussian profile centered on half the thickness el2 of the second barrier 12. This helps to limit a steep barrier effect. The current in the conducting ion state is thus less degraded.

[0073] In this stacking 1, a two-dimensional electron gas 101 is formed under the first AlGaN-based barrier 11, in the GaN-based layer 10. The two-dimensional electron gas 101 is typically confined to the interface between the first AlGaN-based barrier 11 and the GaN-based layer 10.

[0074] The grid pattern 20 crosses this interface between the first AlGaN-based barrier 11 and the GaN-based layer 10, so as to interrupt the two-dimensional electron gas 101. Controlling the grid voltage Vgs allows or blocks the passage of electrons from the two-dimensional electron gas 101 on either side of the grid pattern 20. The grid pattern 20 comprises a metal grid 21 and a grid dielectric 22 separating the metal grid 21 from the stack 1.

[0075] The grid pattern 20 has a lower end 220, which corresponds to the lower end 220 of the grid dielectric 22, and this lower end 220 is located at a depth d20 along z relative to the reference plane pO. The metal grid 21 has a lower end 210 located at a depth d210 along z relative to the reference plane pO. The lower surface of the second barrier 12 is located at a depth dl2 along z relative to the reference plane pO. The surface lower of layer 10 based on GaN, which corresponds to the upper surface of the second barrier 12, is located at a depth dlO along z relative to the reference plane pO.

[0076] The grid pattern 20 passes completely through the GaN-based layer 10, and at least partially through the second AlGaN-based barrier 12. Thus, the lower end 220 is located in the second barrier 12, or below the second barrier 12.

[0077] The grid pattern 20 is typically formed by the following successive steps: - a trench is first formed in the stack 1, for example by engraving, then - the grid dielectric 22 is formed on the walls and bottom of the trench, for example by conformal deposition or by oxidation, then - the trench is filled with one or more metallic deposits.

[0078] Annealing and / or cleaning may be carried out before or after some of these steps.

[0079] The metal grid 21 may be based on a metal alloy, for example, gold and / or platinum and / or titanium. The grid dielectric 22 is typically alumina-based (Al₂O₃). Alternatively, the grid dielectric 22 may be based on SiN, SiO₂, or HFO₂, for example. The grid dielectric 22 preferably has a thickness e₂2 that is approximately constant along the walls and bottom of the trench.

[0080] In the first embodiment illustrated in [Fig. 1], the grid pattern 20 passes through the second AlGaN-based barrier 12 and opens into the unintentionally doped GaN layer 13. The second AlGaN-based barrier 12 has, for example, a thickness e12 of approximately 30 nm. The thickness e22 of the grid dielectric 22 is greater than the thickness e12, so that the lower end 220 is located below the second barrier 12, while the lower end 210 of the grid 21 is located above the second barrier 12. In particular, the depths d210, d10, d12, and d20 are such that d210 <dl0<dl2<d20. A l’état passant, le gaz bidimensionnel d’électrons 101 traverse la deuxième barrière 12 à base d’AlGaN et s’étend sous l’extrémité inférieure 220, dans la couche 13 de GaN non intentionnellement dopée.The threshold voltage Vth of the transistor is significantly increased due to the second barrier 12 based on AlGaN that must be crossed.

[0081] In the second embodiment illustrated in [Fig. 2], the grid pattern 20 only partially penetrates the second AlGaN-based barrier 12. The second AlGaN-based barrier 12 has, for example, a thickness el2 on the order of 50 nm. The lower end 220 is thus located within the second AlGaN-based barrier 12. In the on-state, the two-dimensional electron gas 101 extends into the second AlGaN-based barrier 12. It interacts with the second barrier 12 over a greater distance than in the first embodiment. This can further increase the threshold voltage Vth of the transistor. As shown in [Fig. 2], a second two-dimensional electron gas 102 typically forms under the second AlGaN-based barrier 12, in the unintentionally doped GaN-based layer 13.

[0082] In the third embodiment illustrated in [Fig. 3], the grid pattern 20 passes through the second AlGaN-based barrier 12 and opens into the unintentionally doped GaN layer 13. In this embodiment, the lower end 220 is located below the second barrier 12, and the lower end 210 of the grid 21 is located below the layer 10. In particular, the depths d210, d10, d12, and d20 are such that d10 <d210<dl2<d20.

[0083] In the fourth embodiment illustrated in [Fig. 4], the transistor source 31 passes through the first and second AlGaN-based barriers 11, 12, and emerges into the unintentionally doped GaN layer 13. The source 31 is thus connected to the second two-dimensional electron gas 102 beneath the second AlGaN-based barrier 12. This improves the electrostatic coupling between the source 31 and the gate 21.

[0084] These embodiments may optionally be combined with each other so as to form another embodiment which is not necessarily illustrated.

[0085] Regardless of the embodiment envisaged, the threshold voltage Vth is significantly increased by the effect of the second barrier 12, typically Vth > IV, and even Vth > 2 V.

[0086] Figures 5 and 6 show the evolution of the threshold voltage Vth as a function of the concentration of aluminium [Al]2 and / or the thickness el2 of the second barrier 12.

[0087] As illustrated in [Fig. 5], for a thickness el2 = 50 nm, the threshold voltage Vth is greater than or equal to 3 V over the entire concentration range 2 at.% < [Al]2 < 8 at.%. An Al content of 2% results in a high threshold voltage and a high current level. An Al content of 8% also results in a high threshold voltage, but the current level is relatively lower. The minimum observed on the (cl) curve of Vth around 5 at.% is due to a local minimum at the bottom of the conduction band in FAlGaN.

[0088] As illustrated in [Fig. 6], for a concentration [Al]2 = 5 at.%, the threshold voltage Vth is greater than or equal to 2.5V over the entire thickness range 20nm < el2 < 50nm. The curve (c2) is monotonic. Thus, as the thickness el2 increases, the threshold voltage Vth increases.

[0089] The 2DEG enhancement-mode transistors according to the present invention can advantageously be implemented in power converters, for example DC / AC (direct current / alternating current), DC / DC and AC / DC converters, or there are also "buck" type converters (voltage step-down) or "boost" type converters (voltage step-up).

[0090] The invention is not limited to the embodiments previously described.

Claims

Claims

1. GaN-based power transistor comprising: - a stack (1) of layers (10, 11, 12, 13, 14) in a vertical direction (z), said stack (1) comprising, from an upper surface (100) of said stack: • A first barrier (11) based on AlGaN, • A layer (10) based on GaN, • A second barrier (12) based on AlGaN, - a gate pattern (20) comprising: • A metal gate (21) • A gate dielectric (22) electrically insulating the metal gate (21) from the stack (1), the metal gate (21) being in contact with a bottom portion and a wall portion of the gate dielectric (22), said gate pattern (20) passing through the first barrier (11) based on AlGaN, then completely passing through the layer (10) based on GaN and at least partly the second barrier (12) based on AlGaN, in the vertical direction (z),said second barrier (12) based on AlGaN having an aluminum concentration [Al]2 of between 2%at and 8%at, said transistor being characterized in that it further comprises a source (31) and a drain (32) on either side of the gate pattern (20), said source (31) passing completely in the vertical direction (z) through the second barrier (12) based on AlGaN.,

2. Transistor according to the preceding claim in which the gate pattern (20) completely crosses in the vertical direction (z) the second barrier (12) based on AlGaN.

3. Transistor according to any one of the preceding claims in which the metal gate (21) of the gate pattern (20) has an end (210) at a basal plane (xy) passing within the second AlGaN-based barrier (12).

4. Transistor according to any one of claims 1 or 2 in which the metal grid (21) of the grid pattern (20) has an end (210) at a basal plane (xy) passing within the GaN-based layer (10).

5. A transistor according to any preceding claim in wherein the GaN-based layer (10) separating the second AlGaN-based barrier (12) from the first AlGaN-based barrier (11) has a thickness ei0 greater than or equal to 100 nm.

6. Transistor according to any one of the preceding claims in which the second barrier (12) based on AlGaN has an aluminum concentration gradient [Al]2(z) in the vertical direction (z).

7. Transistor according to the preceding claim in which the aluminum concentration [Al]2(z) has a Gaussian profile in the vertical direction (z), centered on half of the thickness el2 of the second barrier (12).

8. Transistor according to any one of the preceding claims in which the second barrier (12) based on AlGaN has a thickness el2 taken in the vertical direction (z) of between 20nm and 50nm.

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