Scalable IT system

Abstract

Scalable Computing Device This description relates to a network chip (108) comprising: a programmable infrastructure (201) having a plurality of access points (202); at least one 3D plug communication interface adapted to interface with at least one 110 fragment chip, each 3D plug communication interface being connected to a corresponding access point (202); and a plurality of network-to-network communication interfaces (206, 208, 210, 212), each adapted to interface with another network chip (108). Figure for the abstract: Fig. 2

Description

Title of the invention: Scalable computer device technical field

[0001] The present description relates generally to the field of computer architectures, and, in particular, to a scalable system-on-chip. Previous technique

[0002] As is known in the prior art, a system-on-a-chip (SoC) is an integrated circuit that integrates some or all of the components forming a computer system, comprising one or more elements such as CPUs (Central Processing Units), memory, input / output ports, among other functions. In some cases, a system-on-a-chip can be paired with another integrated circuit providing additional memory, advantageously taking advantage of advanced encapsulation techniques.

[0003] One drawback of existing system-on-chip architectures is the relatively significant design disadvantage of producing a system with the required amount of processing and memory resources for a given application. Furthermore, existing solutions have very limited scalability, meaning that when memory or processing resources need to be increased or decreased, a significant redesign is required, which is time-consuming and costly. In addition, component reusability is very limited, which in some cases can lead to high levels of scrap. Summary of the invention

[0004] One object of the embodiments of the present description is to overcome all or part of the disadvantages of the prior art.

[0005] According to one aspect, a network chip is provided comprising: a programmable infrastructure having a plurality of access points; at least one fragmented chip communications interface adapted to interface with at least one fragmented chip, each fragmented chip communications interface being connected to a corresponding point among the access points; and a plurality of network-to-network communications interfaces each adapted to interface with another network chip.

[0006] According to one embodiment, the network chip further includes a memory circuit connected to each router.

[0007] According to one embodiment, at least one of the memory circuits is reconfigurable as either a cache memory or a working memory of the first processing element, the first processing element comprising, for example, a unit of Memory management defining an allocation of cache memory and / or working memory to the first processing element.

[0008] According to one embodiment, at least one of the memory circuits is a non-volatile memory.

[0009] According to one embodiment, the programmable infrastructure is a network-on-chip, and the access points are NoC routers of the network-on-chip.

[0010] According to another aspect, a computer device is planned comprising: the previous network chip mounted on a substrate.

[0011] According to one embodiment, the computer device further comprises at least one additional network chip mounted on the substrate, the network chip and said at least one additional network chip being interconnected by network-to-network communication interfaces.

[0012] According to one embodiment, the network chips are identical to each other, at least one of the network chips having a different orientation from that of at least one other of the network chips.

[0013] According to one embodiment, each of the access points of each network chip is assigned and stores an address based on its location in its programmable infrastructure and based on the orientation of the network chip relative to other network chips.

[0014] According to one embodiment, each network chip includes, at a first of its edges, an external memory interface, and wherein a first of the network chips is oriented so that its first edge is adjacent to a first edge of the computing device, and a second of the network chips is oriented so that its first edge is adjacent to a second edge of the computing device, the first and second edges of the computing device being, for example, perpendicular edges, or opposite edges, of the computing device.

[0015] According to one embodiment, the computer device further comprises: at least one fragmented chip placed on the network chip, each fragmented chip comprising at least one first processing element connected, via a fragmented chip communications interface, to a first of the access points of the network chip on which the fragmented chip is placed.

[0016] According to one embodiment, each fragmented chip is configured to operate asynchronously with respect to the network chip on which it is placed.

[0017] According to one embodiment, said at least one fragmented chip is placed on the network chip in a face-to-face arrangement.

[0018] According to one embodiment, said at least one fragmented chip is placed on the network chip in a face-to-back arrangement.

[0019] According to another aspect, a method for designing the preceding computer device is provided, comprising the design of said at least one fragmented chip on the basis of a network chip model representing the network chip.

[0020] According to yet another aspect, a method for configuring a computer device comprising one or more network chips mounted on a substrate is provided, the method comprising: the detection, by a first of the network chips, of the number and orientation of the network chips of the computer device, in which each network chip implements a programmable infrastructure having a plurality of access points; and the detection, by the first network chip, of the presence or absence of at least one fragmented chip placed on each network chip and connected, via a fragmented chip communication interface, to at least one of the access points of the network chip on which the fragmented chip is placed. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] [Fig.1A] is a cross-sectional view schematically representing a computer device according to an example of an embodiment of the present description;

[0023] [Fig.1B] is a plan view schematically representing a computer device of [Fig.1A] according to an example embodiment;

[0024] [Fig.1C] is a cross-sectional view schematically representing part of the cross-sectional view of [Fig.1A] in more detail according to an example of an embodiment;

[0025] [Fig.2] schematically represents a network chip of the computer device of figures IA, IB and IC in more detail according to an example of an embodiment;

[0026] [Fig.3] is a plan view schematically representing an arrangement of components in a network chip of [Fig.2] according to an example embodiment;

[0027] [Fig.4] schematically represents a system on a chip comprising an arrangement of network chips according to an example embodiment;

[0028] [Fig.5] schematically represents the network chip in more detail according to an example of an embodiment;

[0029] [Fig.6] schematically represents a fragmented chip of the computer device of figures IA, IB and IC in more detail according to an example of an embodiment;

[0030] [Fig.7] schematically represents a computational group of the fragmented chip of [Fig.6] according to an example of an embodiment;

[0031] [Fig.8] schematically represents a computation group of the fragmented chip of [Fig.6] according to another example of an embodiment;

[0032] [Fig.9] is a plan view of a computer system according to another example of an embodiment of the present description;

[0033] [Fig. 10] is a plan view of a computer system according to yet another example of an embodiment of the present description;

[0034] [Fig.1 1] is a flowchart representing steps in a process for configuring a computer device according to an example of an embodiment of the present description;

[0035] Figure 12 schematically represents a fragmented chip detection circuit according to one embodiment; and

[0036] [Fig. 13] schematically represents a design system for the design of a computer device according to an example of an embodiment of the present description. Description of the implementation methods

[0037] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0038] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0040] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0041] Fig. 1A is a cross-sectional view schematically representing a computer device 100 according to an example of an embodiment of this description.

[0042] The computer device 100 is, for example, a three-dimensional 3D integrated circuit, which comprises an assembly of several chips to realize the in- The computing device 100 comprises a substrate 102, on which a plurality of computing stacks 104, 106 are mounted. Two such computing stacks are shown in the view of [Fig. 1A]. Each computing stack 104, 106 comprises a network chip 108, and one or more fragmented chips 110 mounted on the network chip 108. In the view of [Fig. 1A], two fragmented chips 110 are visible on each network chip 108. The substrate 102 is, for example, a PCB (printed circuit board). In one embodiment, it could be a housing substrate intended, for example, to be mounted on a PCB or similar device. For example, the substrate 102 could be an organic or ceramic substrate. According to yet another example, substrate 102 is another type of connection layer, such as an interposer, made for example of silicon.

[0044] The network chips 108 each have, for example, a lower portion 112 in contact with a surface 114 of the substrate 102. In some embodiments, the lower portions 112 of the network chips 108 each include connection interfaces, such as a network of bosses (not shown in [Fig. 1A]), providing electrical connections between the substrate 102 and the network chip 108. In addition, or according to a variant, other types of connection interfaces could be provided between the network chips 108 and the substrate 102, comprising one or more wired connections between the surface 114 of the substrate and a surface 116 of each network chip 108, each surface 116 being, for example, on an opposite side of the network chip 108 with respect to the lower portion 112.

[0045] The fragmented chips 110 each have, for example, a lower portion 118 in contact with the surface 116 of the network chip 108 on which it is mounted or placed. In some embodiments, the lower portions 118 of the fragmented chips each include connection interfaces, such as direct metal-to-metal bonding layers, also known as hybrid bonding layers (not shown), providing electrical connections between the network chip 108 and each fragmented chip 110. In addition, or according to a variant, other types of connection interfaces, such as micro-bumps or copper pillars, could be used between each fragmented chip 110 and the network chip 108 on which it is mounted.

[0046] The network chips 108 each have, for example, a footprint of between 40 and 300 mm2, for example of about 80 mm2, while each fragmented chip 110 has, for example, a footprint of between 10 and 100 mm2, and going, for example, up to 64 mm2 in certain embodiments.

[0047] Each network chip 108, for example, fulfills a networking role for communications between the fragmented chips 110 and / or other network chips 108. In In certain embodiments, the 108 network chips can be infrastructure chips that provide additional functions and / or resources beyond the networking role, such as memory resources, power management and security, as will be described in more detail later.

[0048] [Fig.1B] is a plan view schematically representing the computer device 100 of [Fig.1A] according to an example of an embodiment of the present description.

[0049] In the example of [Fig. 1B], the computing device 100 comprises four computing stacks 104, 106, 114, and 116 mounted on the substrate 102 in a two-by-two arrangement, in other words, in two columns of stacks, each column comprising two rows of stacks. A dashed line AA in [Fig. 1B], passing through stacks 104 and 106, represents the location from which the cross-sectional view of [Fig. 1A] is taken.

[0050] Each of the computer stacks 104, 106, 114, and 116 can, for example, communicate with at least one other computer stack via communication paths formed in and / or above the substrate 102. For example, although not shown in [Fig. 1B], communication paths exist between each computer stack 104, 106, 114, and 116 and its nearest neighbors in the column and row directions. Thus, in the case of a pairwise arrangement, each computer stack can communicate directly with two other computer stacks and with the third other computer stack via an intermediate computer stack.

[0051] In alternative embodiments, there could be a different number of computer stacks, and these could be arranged in a different configuration, such as a linear arrangement. One advantage of a two-dimensional rather than linear arrangement of the computer stacks is that it leads to shorter distances for at least some of the communication paths between the computer stacks.

[0052] In the example of [Fig.1B], each of the computer stacks 104, 106, 114, 116 comprises four fragmented chips 110 mounted on its corresponding network chip 108 in a two-by-two arrangement, in other words in two columns of fragmented chips, each column comprising two rows of fragmented chips.

[0053] Each of the fragmented chips 110 can, for example, communicate with each of the other fragmented chips of the same computer stack via communication paths formed in the network chip 108. In addition, each of the fragmented chips 110 can, for example, communicate with fragmented chips 110 mounted on other network chips 108 via network-to-network communication interfaces described in detail below.

[0054] In alternative embodiments, there could be a different number of fragmented chips 110 mounted or placed on each network chip 108, and these could be arranged in different ways. In some embodiments, one or more network chips 108 might not have any fragmented chips mounted on them and could be used to provide memory resources and / or other functions such as interfacing with external resources.

[0055] Furthermore, rather than having a plurality of network chips 108, it would also be possible for the device 100 to comprise only a single network chip 108, with or without a fragmented chip 110 mounted on it.

[0056] Indeed, the network chip 108 provides, for example, a generic building block of a computer device which can, for example, be manufactured on a relatively large scale so that the unit cost is relatively low, and which serves as a versatile module providing memory and routing resources, as well as other functions such as management functions (memory, energy, security, etc.).

[0057] [Fig. 1C] is a cross-sectional view schematically representing a portion BB' of the cross-sectional view of [Fig. 1A] in more detail according to an exemplary embodiment. In particular, portion BB' passes vertically through the substrate 102, and the network chip 108 and the fragmented chip 110 of the computer stack 106.

[0058] In the example of [Fig. 1C], the network chip 108 and the fragment chip 110 are assembled in a face-to-face arrangement. The "face" of an integrated circuit chip corresponds to the side closest to the metallic interconnect layers, while the "back" corresponds to the side closest to the substrate, generally made of silicon.

[0059] In some embodiments, the same transistor technology can be used to fabricate both the chip 108 and the fragmented chip 110. For example, both the chip 108 and the fragmented chip 110 could be fabricated using the technology known to those skilled in the art as 28 nm, 22 nm, 16 nm, or 14 nm FinFET technology. According to one variant, they could be fabricated using different technologies, the fragmented chip, for example, being fabricated using the technology known to those skilled in the art as 7 nm or 5 nm FinFET technology.

[0060] The network chip 108 comprises, for example, a substrate 154, for example made of silicon or another semiconductor, a transistor layer 156 formed on the substrate 154 and comprising, for example, stacks of transistor gates formed on the substrate 154, and an interconnection layer 158 formed on the transistor layer 156 and comprising metal layers interconnecting transistors of the transistor layer 156. For example, the interconnection layer 158 includes a layer of dielectric material in which metal levels have been formed according to defined patterns to provide connections between transistors or other devices formed in the transistor layer.

[0061] An interface between the fragmented chip 110 and the network chip 108 is implemented, for example, by a redistribution layer (RDL), for example, a hybrid link layer between the chips. For example, this layer includes interconnect pads 170. In one example, these interconnect pads 170 have a pitch between 1 and 10 pm. The interconnect pads 170 include, for example, copper-to-copper link pads formed between the interconnect layers 158 and 168 of the chip 108 and the fragmented chip 110, respectively.

[0062] A number of interconnection vias, such as TSVs (through Silicon vias), 160 extend from the interconnection layer 158, through the transistor layer 156 and the substrate 154, to a lower part or rear face of the network chip 108, where they are connected, for example, to bosses 162. In addition, in some embodiments, one or more of the interconnection vias 160 extend to a corresponding interconnection pad 170 formed on the surface of the interconnection layer 158 to interconnect with the fragmented chip 110.

[0063] The fragmented chip 110 includes for example a substrate 164, for example made of silicon or another semiconductor, a transistor layer 166 formed on the substrate 164 and comprising for example stacks of transistor gates formed on the substrate 164, and an interconnection layer 168 formed on the transistor layer 166 and comprising metal levels interconnecting transistors of the transistor layer 166, in a manner similar to the interconnection layer 158 of the network chip 108.

[0064] In some embodiments, a heat sink 172 is formed on the rear face of the fragmented chip 110.

[0065] The network chip 108 is mounted for example on the substrate 102 via the bosses 162. In some embodiments, the substrate 102 is a housing substrate comprising connection vias (not shown in figures IA, IB, IC) between the bosses 162 and BGA (Bail Grid Array) beads placed on a lower part of the substrate 102. The BGA 174 beads are used for example to electrically connect the housing to a circuit board (not shown).

[0066] The network chip 108 includes, for example, a network-on-chip (NoC) having memory circuits (not shown in [Fig. 1C]), and the interconnection vias 160 are, for example, formed at regular intervals in spaces formed between the NoC memory circuits In some embodiments, one or more of the interconnect vias 160 are connected to a power rail of the network chip 108 to provide a supply voltage, such as a VDD or GND voltage, to the network chip 108, and / or one or more of the interconnect vias 160 are connected, via one of the interconnect pads 170, to a power rail of the fragment chip 110 to provide a supply voltage, such as a VDD or GND voltage, to the fragment chip 110. An advantage of supplying power voltages to the network chip 108 and / or the fragment chip 110 via regularly spaced interconnect vias 160 is that they can be used to supply the power rails of the chip / fragment chip, which are, for example, regularly spaced in the interconnect layers. 158, 168 of the respective fragmented chip / chip.Advantageously, this allows one or both of the chip and fragmented chip to be powered with a relatively low IR drop (current resistance).

[0067] Although in the embodiment of [Fig.1C] the chip 108 and fragmented chip 110 are stacked face to face, in variant embodiments they could be stacked face to back, for example the interconnect layer 168 (face) of the fragmented chip 110 contacting the substrate 154 (back) of the network chip 108. Thus, the interconnect layer 158 of the network chip 108 contacts the substrate 102, for example via the bosses 162, facilitating interconnections between them.In such a case, the network chip 108 includes, for example, interconnection vias (not shown) extending from the bosses 162, through the substrate 154 and the transistor layer 156, to the interconnection layer 168 of the fragment chip 110, and providing supply voltages and / or other signals to the fragment chip 110, and also interconnection vias (also not shown) extending from the interconnection layer 158 of the network chip 108, through the substrate 154 and the transistor layer 156, to the interconnection layer 168 of the fragment chip 110, and providing communication channels between the network chip 108 and the fragment chip 110.

[0068] Although the interconnecting pads 170 have been described between the network chips 108 and the fragmented chips 110, which, for example, provide electrical connections on the basis of a hybrid link, in variant embodiments, other technologies could be used for the electrical interface between the network chips 108 and the fragmented chips 110, such as micro-bump arrays, copper pillar arrays, etc.

[0069] Fig. 2 schematically represents the network chip 108 of the computer device in Figures IA to IC in more detail according to an example embodiment.

[0070] The network chip 108 includes, for example, a NoC 201 consisting of a plurality of NoC 202 routers. NoC 202 routers are arranged in a two-dimensional network of rows and columns, with each NoC 202 router communicating, for example, with adjacent nodes in its row and column. In the example in [Fig. 2], there are nine NoC 202 routers arranged in three columns and three rows. However, in alternative embodiments, there could be a different number of nodes arranged in any pattern.

[0071] Each of the NoC 202 routers is connected to a corresponding memory circuit (M) 204, each of which is for example a volatile memory such as an SRAM (from the English "static random access memory") or a non-volatile memory (NVM).

[0072] In addition to the connection to each memory 204, each of the NoC routers 202 has, for example, five input / output interfaces, represented by double arrows in [Fig. 2]. One of these input / output interfaces of each NoC router 202 is, for example, reserved for a connection to a fragmented chip 110 located on the network chip 108. One or more of the NoC routers 202 have, for example, each of their other four input / output interfaces connected to their four neighboring nodes in the NoC 201. This is, for example, the case for the central NoC router 202 in the 3-by-3 arrangement of [Fig. 2]. More generally, this is, for example, the case for any node that is not located at an edge (including the corners) of the NoC.

[0073] At least one of the input / output interfaces of the NoC 202 routers along each of the four edges of the NoC 201 is, for example, connected to a corresponding network-to-network interface, which will also be referred to herein as a chip-to-chip interface, 206 (N D2D), 208 (E D2D), 210 (S D2D), 212 (W D2D). In the example in [Fig. 2], interfaces 206, 208, 210, and 212 are respectively on the top, right, bottom, and left sides of the NoC 201, which will be referred to herein as the north, east, south, and west sides. Interfaces 206, 208, 210, and 212 are, for example, connected to input / output interfaces of NoC 202 routers located along the edges, but not the corners, of NoC 201. Such NoC 202 routers have, for example, three of their input / output interfaces connected to three neighboring NoC 202 routers in the same row and column, and an additional input / output interface that is, for example, connected to the corresponding chip-to-chip interface 206, 208, 210, 212.The term "additional I / O interface" is used to refer to those I / O interfaces of the NoC 202 routers that are not used for interconnections in the NoC 201 or the fragmented chip 110, and are thus available to provide connections with components external to the NoC 201.

[0074] The NoC 202 routers located at the corners of NoC 201 have, for example, two of their input / output interfaces connected to two neighboring NoC 202 routers, and two additional input / output interfaces. For example: A NoC 202 router in the upper left corner of NoC 201, in other words at the corner between the north and west edges, has its additional input / output interfaces connected respectively to a power management circuit (PWR MGNT) 214 and a configuration and / or safety processor (CONFIG / SAFETY P) 216. The power management circuit 214 is configured, for example, to set a voltage and / or frequency operating point of one or more fragmented chips 110 that are placed on the network chip 108. For example, the power management circuit 214 is configured to perform a dynamic voltage and frequency conversion (DVFS) control procedure.The security processor 216, for example, handles the configuration and security management of the computer stack including the network chip 108, including, for example, system configuration, defining, for example, the global address space of the entire system which could implement several network chips 108, and / or the control and monitoring of security rules and the handling of errors that may occur in the system; . A NoC 202 router in the upper right corner of NoC 201, in other words, at the corner between the north and east edges, has its additional input / output interfaces connected respectively to an external memory interface (EXT MEM INT) 218 ​​located, for example, on the north edge of the network, the memory controller being, for example, a double data rate (DDR) memory controller, and to a memory access circuit (SMART DMA) 220 located, for example, on the east edge of the network, the memory access circuit 220 being, for example, a configurable direct memory access (DMA) circuit. In some embodiments, the DMA is an advanced DMA circuit implementing specific features such as data manipulation and / or memory-to-data flow, in addition to conventional memory-to-memory transfers. The advanced DMA also implements, for example, multiple configuration channels that must be usable by multiple requesters.The external memory interface 218 and the memory access circuit 220 can, for example, be connected to external memories on the chip (not shown in [Fig.2]), although, depending on the orientation of the network chip 108, one or both may be unused; a NoC router 202 in the lower right corner of NoC 201, in other words at the corner between the east and south edges, has its additional input / output interfaces connected respectively to a secure processor (SECURE P) 222, and to one or more peripherals (PERIPHERALS) 224. The secure processor 222 processes, for example, the . security of the computer stack including the 108 network chip, including for example the implementation of the secure hardware base, secure boot management and support for certain advanced cryptography services; - A NoC 202 router in the lower left corner has its additional input / output interfaces connected respectively to a general-purpose input / output (GPIO) interface 226, located, for example, on the south edge of the network, and to a bus (PCIe) interface 228, located, for example, on the west edge of the network. The bus interface 228 is, for example, a Peripheral Component Express (PCIe) interface. Interfaces 226 and 228 can, for example, be connected to circuits external to the chip (not shown in [Fig. 2]), but, depending on the orientation of the network chip 108, one or both may be unused.

[0075] The various interfaces, such as for example the chip-to-chip interfaces 206, 208, 210 and 212, the general purpose IO interface 226, the DMA interface 220, the external memory interface 218, and the bus interface 228, are for example not powered when not in use, or if not connected to any external device, in order to save energy.

[0076] The operation of NoC 201 is, for example, as follows. Each router 202 of NoC 201 is assigned, and stores, an address in the form of x,y coordinates based on its position in terms of row and column within the NoC. A data packet arriving at a router 202 compares, for example, the destination address of the data packet to its assigned address. If the addresses match, router 202 stores, for example, the data packet in its memory 204, from which it is accessible by another component connected to that router, such as a fragmented chip 110 or one of the communication interfaces connected to the router. Conversely, if the addresses do not match, the data packet is, for example, transmitted within the NoC based on the relative values ​​of the destination address coordinates with those of the router.In an example, data packets are transmitted by router 202 to the destination column (e.g., the x-direction) before being transmitted to the destination row (e.g., the y-direction). Thus, if the x-coordinate of the destination address is greater than the x-coordinate of the router's address, then the data packet is transmitted in the positive x-direction, which is oriented to the right in [Fig. 2], whereas if the x-coordinate of the destination address is less than the x-coordinate of the router's address, then the data packet is transmitted in the negative x-direction, which is oriented to the left in [Fig. 2]. If the x-coordinates match, then the data packet is already in the column. The correct path is found. Thus, if the y-coordinate of the destination address is greater than the y-coordinate of the router's address, the data packet is transmitted in the positive y-direction, which is, for example, upwards in [Fig. 2], whereas if the y-coordinate of the destination address is less than the y-coordinate of the router's address, the data packet is transmitted in the negative y-direction, which is, for example, downwards in [Fig. 2]. The next router then applies a similar operation. If the packet reaches one of the chip-to-chip interfaces 206, 208, 210, or 212, it is, for example, forwarded to the next network chip, where it continues its path to the target resource.Of course, many variations of this procedure can be applied, such as choosing to start by transmitting packets to the destination column or row, choosing positive and negative address directions in the network, etc.

[0077] Fig. 3 is a plan view schematically representing an arrangement of components in one of the network chips 108 of Fig. 2 according to an example embodiment.

[0078] The components (CONFIG / SAFETY P) 216, (N D2D) 206, (EXT MEM INT) 218, (SMART DMA) 220, (E D2D) 208, (SECURE P) 222, (PERIPHERALS) 224, (S D2D) 210, (GPIO) 226, (PCIe) 228, (W D2D) 212 and (PWR MGNT) 214 are, for example, located in a peripheral region of the network chip 108, which, in the example of [Fig. 3], is in the form of a rectangular strip extending along each edge of the NoC 201. In addition, a clock generation circuit (CLK GEN) 302 is also, for example, present in this peripheral region, for example between the chip-to-chip interface 210 and the interface GPIO 226. In some examples, the network chip 108 and one or more of the fragmented chips 110 placed on it operate synchronously.In such a case, the clock generation circuit 302 of the network chip 108 generates, for example, one or more clock signals supplied not only to the components of the network chip 108, but also to one or more of the fragmented chips 110 placed on it. According to one variant, one or more of the fragmented chips 110 can operate asynchronously with respect to the network chip 108 on which it is placed, such fragmented chips 110 comprising their own clock generators and thus their own clock domain. In such a case, a clock signal generated by the clock generation circuit 302 can also be supplied to such fragmented chips 110 for data communications, for example, for the synchronization, within the fragmented chip 110, of data signals from the network chip 108 to the fragmented chip 110.In some embodiments, no clock signal is provided by the network chip 108 to one or more of the fragmented chips 110. In such a case, communication between the network chip 108 and each fragmented chip 110 is by . asynchronous example, and resynchronization is for example performed on communications passing between these clock domains of the network chip 108 and the fragmented chip 110.

[0079] The NoC 201 of the network chip 108 is, for example, formed in a central rectangular region of the chip. As shown in [Fig. 3], the surface of this central region comprises, for example, groups of interconnect pads 170 for connecting to one or more fragmented chips 110. The example in [Fig. 3] is based on a network chip 108 having 12 groups of interconnect pads 170, arranged four by three, each of which is, for example, connected to a corresponding router among the NoC 202 routers of [Fig. 2]. Thus, this is a different example from that of [Fig. 3], in which the NoC 201 comprises a three-by-three arrangement of NoC 202 routers.

[0080] For example, the interconnect pads are arranged in pairs of pad groups 170a, 170b, each pair of pad groups 170a, 170b being connected to a NoC 202 router of NoC 201, one of the groups providing, for example, communications from the network chip 108 to the fragmented chip 110 and the other group of pads providing, for example, communications from the fragmented chip 110 to the network chip 108. Each pad group 170a, 170b includes, for example, one or more individual pads to ensure communications, which may be based on serial and / or parallel data transmission.

[0081] As represented by a rectangle 308, according to one embodiment, the fragmented chip 110 has a footprint that covers all the interconnection pad groups 170a, 170b, and has, for example, corresponding interconnection pads that contact all or some of the interconnection pad groups 170a, 170b.

[0082] According to alternative embodiments, a smaller fragmented chip 110, having a footprint that covers only part of the stud groups 170a, 170b, could be used. In the example in [Fig. 3], there are three rows of four pairs of stud groups 170a, 170b, and a dashed rectangle 310 represents an example in which the fragmented chip 110 has a footprint covering six pairs of stud groups 170a, 170b, while a dashed rectangle 312 represents an example in which the fragmented chip 110 has a footprint covering two pairs of stud groups 170a, 170b. In the case of fragmented chips 110 covering only part of the groups of studs 170a, 170b, it might be possible to have several fragmented chips 110, as in the example of Figures 1A and IB, each having a footprint which covers, for example, at least half of the pairs of groups of studs 170a, 170b.Each fragmented chip 110 covers, for example, and is connected to at least one pad of the pad pair 170a, 170b in order to interact with the . network chip 108. If a fragmented chip 110 covers more than one pair of pads 170a, 170b, it is, for example, connected to and uses at least one of the pairs of pads 170a, 170b, and may also use one, some, or all of the other pairs of pads 170a, 170b to communicate with the network chip 108. Indeed, this will depend on the bandwidth requirements for communication between the network chip 108 and the fragmented chip 110. Therefore, by covering and using several pairs of pads 170a, 170b, the fragmented chip 110 can also convert and adapt its communication bandwidth to the network chip 108 and other resources, such as external memory and the PCIe interface in particular.

[0083] According to some embodiments, each of the network chips 108 in Figures 1 to 3 is made from an identical chip, and these chips are oriented on the substrate 102 to allow desired interconnections among the network chips 108 and with components external to the computer device 100. A particular example comprising a two-by-two arrangement of network chips 108 will now be described in more detail in relation to [Fig. 4].

[0084] Figure 4 schematically represents a computer system 400 comprising the computer device 100, external memories 402 (DDR), and a host processor 404. Each of the memories 402 is, for example, a synchronous dynamic double data rate memory (DDR SDRAM).

[0085] The computer device 100 comprises four network chips 108, arranged in pairs, and which are referenced as 108A, 108B, 108C and 108D in [Fig. 4]. For example, each of the network chips 108 of the computer device 100 is connected to a corresponding memory of the memories 402; there are four memories 402 in the example of [Fig. 4]. Each memory 402 is, for example, connected to the external memory interface (EXT MEM INT) 218 ​​of the corresponding network chip 108. Since the memories 402 are located outside the computing device, the network chips 108A to 108D are arranged, for example, so that each has its external memory interface 218 adjacent to a corresponding edge of the device 100, and thus each of the network chips 108A to 108D is, for example, oriented differently in each of the four orientations 0°, 90°, 180° and 270°.

[0086] According to the example in [Fig. 4], the network chip 108A in an upper left corner of the device 100 has its northern edge adjacent to an upper edge of the device 100. This orientation will be considered to be the 0° orientation. The east and south chip-to-chip interfaces (E D2D, S D2D) 208, 210 of this network chip 108A are connected respectively to the network chip 108B in the upper right corner of the device 100 and to the network chip 108D in the lower left corner of the device 100. The north and west chip-to-chip interfaces (N D2D, W D2D) 206, 212 are not connected to anything.

[0087] Similarly, the 108B network chip in an upper right corner of the device 100 has its northern edge adjacent to a right edge of device 100, in other words it is at the 90° orientation. The east and south chip-to-chip interfaces (E D2D, S D2D) 208, 210 of network chip 108B are connected respectively to network chip 108C in the lower right corner of device 100 and to network chip 108A in the upper left corner of device 100, the north and west chip-to-chip interfaces (N D2D, W D2D) 206, 212 of network chip 108B are not connected to anything.

[0088] Similarly, the network chip 108C in a lower right corner of the device 100 has its northern edge adjacent to a lower edge of the device 100, in other words it is at the 180° orientation. The east and south chip-to-chip interfaces (E D2D, S D2D) 208, 210 of the network chip 108C are connected respectively to the network chip 108D in the lower left corner of the device 100 and to the network chip 108B in the upper right corner of the device 100, the north and west chip-to-chip interfaces (N D2D, W D2D) 206, 212 of the network chip 108C being not connected to anything.

[0089] Similarly, the network chip 108D in a lower left corner of the device 100 has its north edge adjacent to a left edge of the device 100, in other words it is at the 270° orientation. The east and south chip-to-chip interfaces (E D2D, S D2D) 208, 210 of the network chip 108D are connected respectively to the network chip 108A in the upper left corner of the device 100 and to the network chip 108C in the lower right corner of the device 100, the north and west chip-to-chip interfaces (N D2D, W D2D) 206, 212 of the network chip 108D being not connected to anything.

[0090] The host processor 404 is, for example, connected to the (PCIe) bus interface 228 of the network chip 108 in the upper left corner of the device 100. This bus interface 228 is, for example, located at the west edge of this network chip, and the host processor 404 is therefore connected, for example, via the left edge of the device 100. The (PCIe) bus interfaces 228 of the other three network chips 108 are, for example, inactive. In some embodiments, rather than having a host processor 404 connected to the computing device 100 via one of the bus interfaces 228, the computing device 100 includes an internal processor, for example, a microprocessor. For example, such an internal processor could be implemented in the network chip 108, or by a dedicated fragmented chip among the fragmented chips 110.

[0091] In order for data packets to reach any router on any of the network chips 108, the different routers have, for example, assigned addresses in the form of x,y coordinates, which are different in each network and are, for example, not only a function of the relative positions of the routers in each NoC 201, but also a function of the relative locations and orientations of the network chips 108. For example, the same x coordinate is assigned to routers in the same column of NoC 201 on two different network chips. different routers that are vertically aligned, while the y coordinates change. Similarly, the same y coordinate is assigned to routers in the same NoC 201 row from two different network chips that are horizontally aligned, while the x coordinates change. For example, assuming the case where each NoC comprises a nine-by-nine matrix of routers, the addresses are as follows: - routers in NoC 108A are assigned x,y coordinates ranging from (0,0) to (2,2), where (0,0) is the top left router in NoC chip 108A, and (2,2) is the bottom right router in NoC chip 108A; - routers in NoC 108B are assigned x,y coordinates ranging from (3,0) to (5,2), where (3,0) is the top left router in NoC chip 108B, and (5,2) is the bottom right router in NoC chip 108B; - The routers of the NoC 108C are assigned x,y coordinates ranging from (3,3) to (5,5), where (3,3) is the upper left router in the NoC of the 108C chip, and (5,5) is the lower right router in the NoC of the 108C chip; and - The routers of the NoC 108D are assigned x,y coordinates ranging from (0,3) to (2,5), where (0,3) is the top left router in the NoC of the 108D chip, and (2,5) is the bottom right router in the NoC of the 108D chip.

[0092] Although [Fig.4] represents an example with four network chips 108, in the case of a computer device 100 having fewer network chips 108, their orientations are chosen, for example, on the basis of the relative locations of the external memories 402. In the case of a larger number of network chips 108, such as six or nine network chips 108 arranged in rows of three, said one or more intermediate network chips 108 are arranged, for example, so that their northern edges are adjacent to an edge of the device 100, so that the external memory interfaces 218 are accessible.

[0093] Figure 5 schematically represents one of the network chips 108 in more detail according to an example embodiment.

[0094] The network chip 108 includes, for example, the components connected to the NoC 201, including the power management circuit (PWR MGNT) 214, the configuration and / or safety processor (CONFIG / SAFETY P) 216, the external memory interface 218, the memory access circuit (SMART DMA) 220, the secure processor (SECURE P) 222, the general purpose input / output interface 224 and the peripheral interface 226 (IO & PERIPH) and the bus interface 228, as described previously in relation to [Fig.2],

[0095] In the example of [Fig.5], the external memory interface 218 includes a DDR controller (DDR CTRLLR) 502 connected to the NoC 201, and a DDR physical layer (DDR PHY) 504 connecting the DDR controller 502 with the outside of the chip 108.

[0096] Furthermore, in the example of [Fig. 5], the bus interface 228 provides an interface with a serial bus external to the chip, and performs, for example, parallel-to-serial and serial-to-parallel conversion. For example, the bus interface 228 includes a PCIe termination circuit (PCIe EP) 506 connected to the NoC 201, and a serializer / deserializer (SERDES) 508 connecting the PCIe termination circuit 506 to the outside of the chip 108.

[0097] In some embodiments, the memories 204 of the NoC 201 are each reconfigurable to provide either cache memory, such as a last-level cache (LLC) 204' or a system-level cache, or working memory (SCRATCH PAD MEMORY) 204". In some embodiments, the network chip 108 includes all its memories configured as a cache 204', or all its memories configured as working memory 204", although in other embodiments, at least one of the memories of the network chip 108 is configured as a cache 204', and at least one of the memories is configured as working memory 204".One difference between a cache memory and working memory is that cache memory represents a local copy of data stored elsewhere, for example in one of the 402 external memories, whereas working memory provides local storage of data relatively close to a processor core that is not a cache memory, and thus its contents are not stored elsewhere. For example, working memory is memory deprived of a given processing element, and is used exclusively by that processing element.

[0098] For example, the NoC 201 includes a cache management system (CMS) 509, which manages those of the memories 204 that are used as cache memory, and participates, for example, in a hardware cache consistency scheme implemented on the NoC 201. The cache management system 509 is, for example, implemented using a decentralized approach among the NoC 202 nodes of the network, implying that there is no central cache mapping table, although other approaches would also be possible. The system's cache resources are, for example, defined during an initialization phase.

[0099] The use of certain memories 204 as working memory is defined for example in the global address space (GAS) of the system at the software level, and one or more memory management units (described in more detail later) of each fragmented chip 110 are configured for example during the initialization phase on the basis of the defined global address space.

[0100] The NoC 201 includes, for example, a plurality of 510 fragmented chip interface (3D PLUG) circuits. For example, there is a single 510 fragmented chip interface circuit per NoC 202 router of the NoC 201, allowing each to be connected NoC 202 router to a fragmented chip 110.

[0101] Figure 6 schematically represents the functions of a fragmented chip 110 of the computing device 100 of Figures IA, IB, and IC according to one exemplary embodiment. Each of the fragmented chips 110 of the computing device 100 comprises, for example, similar circuits. For example, each fragmented chip 110 comprises one or more processing elements (COMPUTE CLUSTER) 602, which will be referred to herein as computing groups. Each computing group 602 comprises, for example, a memory (MEMORY) 604 and a memory management unit (MMU) 606.

[0102] The memory management unit 606 provides, for example, a memory interface between each computing group 602 and one or more memory spaces allocated to it in the network chip. In particular, the MMU performs a translation between address spaces, for example, between the user address space, which is used by the programming language of the fragmented chip 110, and the physical address space, which exists at the hardware level. Thanks to the MMU, a large memory region can be continuous at the programmer level (user space) while being physically fragmented and distributed across several non-consecutive memory locations.

[0103] The fragmented chip 110 also includes, for example, one or more network chip interface circuits (3D PLUG) 610 for communicating with the network chip 108 on which the fragmented chip 110 is placed. For example, the number of network chip interface circuits 610 is equal to the number of compute groups 602 and, for example, also to the number of NOC routers 202 to which the fragmented chip 110 can be connected. This depends, for example, on the dimensions of the fragmented chip 110 and the bandwidth requirements between the network chip 108 and the fragmented chip 110.

[0104] The communication interface between the network chips 108 and the fragmented chips 110, comprising the fragmented chip interface circuit 510 and the network chip interface circuit 610, provides, for example, a physical channel on which one or more virtual channels are established for communication between the network chip 108 and the fragmented chip. For example, the physical channel includes at least one conductor for transmitting data and at least one conductor for transmitting a clock signal. Additional conductors may, for example, transmit a control signal, a reset signal, and / or test signals, such as BIST (built-in self-test) signals. In some embodiments, this interface includes buffering to manage data streams and may be based on a credit system.For example, the interface could be implemented according to any of the solutions described in the patent application published on January 10, 2018 under number EP3267305, these solutions being based on the use of credits between the receiving and receiving sides. transmission. For example, the communications interface allows bidirectional communication between the network chip and the fragmented chip, and thus includes, for example, a transmitter and a receiver on both sides.

[0105] In some embodiments, the fragmented chip interface circuit 510 and the network chip interface circuit 610 support at least one master port and / or at least one slave port. In some embodiments, there is at least one master port and at least one slave port. In some embodiments, the fragmented chip includes a slave port associated with accelerator compute groups and a master port associated with CPU compute groups.

[0106] The communication interface between the network chip 108 and each fragmented chip 110 supports, for example, a communication protocol between these elements, and, in particular, a communication protocol for the transmission of data, as well as addresses, instructions for operations to be performed, for example, a load, a store, requests to the MMU and / or cache reloads. Furthermore, the communication interface supports, for example, one or more of the following: data channels for control, security, power management and / or reliability, a data coherence channel, address translation within the fragmented chip, and interrupt handling.In some embodiments, the interface between the network chip 108 and each fragmented chip 110 also supports the crossing of the synchronization and energy domains, including, for example, appropriate voltage and / or synchronization settings depending on the different silicon technologies performed by the chips.

[0107] Figure 7 schematically represents a DNN 700 accelerator implementing, for example, one of the 602 computing groups of the fragmented chip 110 of Figure 6. According to the example in Figure 7, the DNN 700 accelerator is a DNN core or accelerator (from the English "deep neural network") comprising a DNN core 702, which includes, for example, an array of arithmetic logic units (ALUs). The DNN 700 accelerator further includes a memory (SRAM) 704, which is, for example, volatile memory such as SRAM. The DNN 700 accelerator further includes, for example, the network chip interface circuit 610, which includes, for example, a network chip interface system bus (3D PLUG SYS BUS) 706, an input / output memory management unit (I0MMU) 708, and an interrupt request module 710 configured to receive interrupts via the network chip 108 that are intended for the computing group 702.According to one variant to a DNN, the 700 accelerator could, according to another variant, implement another type of network or artificial intelligence processor, or another type of application-specific accelerator, such as an FPGA (field programmable gate array, pre-broadcast pro- . (grammable by the user).

[0108] Fig. 8 schematically represents a computing group 800 implementing, for example, one of the computing groups 602 of the fragmented chip 110 of Fig. 6. According to the example in [Fig. 8], the computing group 800 is a CPU (Central Processing Unit), and includes, for example, a 64-bit CPU (64b CPU) 802, and, in some cases, one or more other processing circuits, such as a Vector Processor (VECT.) 804 and a Floating-Point Unit (FPU) 806. The computing group 800 further includes one or more cache memories, such as a Level 1 Instruction Cache (L11$) 808, a Level 1 Data Cache (L1D$) 810, and a Level 2 Cache (L2$) 812, which is, for example, common to both instructions and data. The computing group 800 further includes, for example, the Network Chip Interface Circuit 610, which is, for example, similar to the 610 circuit in [Fig. 8].[7], except that the I0MMU 708 is replaced in the 800 computing group by an MMU 814. Instead of a CPU, the 800 computing group could, according to one variant, implement a graphics processing unit (GPU).

[0109] As previously stated, an MMU defines a relationship (in terms of address translation) between the logical and physical addresses of memory locations. An MMU is directly managed by a processor, which effectively allocates memory and maintains a record in its MMU. An I0MMU is commonly linked to a slave of an accelerator, such as the DDN 702 core, which also relies on its address translation. The accelerator may not allocate memory itself, but may, for example, access a memory location pointed to by the main processor. Furthermore, the I0MMU allows, for example, a CPU that wishes to use an accelerator to drive the accelerator directly using logical (or user) addresses, because the I0MMU, in synchronization with the CPU's MMU, will handle the translation. Without an I0MMU, the host CPU would have to use only physical addresses when passing a memory pointer to the accelerator.This translation could become very resource-intensive for the CPU, as it requires context switching to perform the task. The I0MMU, for example, handles this address translation automatically in hardware.

[0110] Some or all of the fragmented chips 110 of the computing device 100 may, for example, comprise only computing groups 610 of a single type, such as a general-purpose CPU like computing group 800 of [Fig. 8], or a specific hardware circuit such as the DNN accelerator 700 of [Fig. 7]. According to one embodiment, one, some, or all of the fragmented chips 110 of the computing device 100 may comprise computing groups of more than one type. Some examples will now be described in connection with Figures 9 and 10.

[0111] Figure 9 is a planar view of the computing device 100 according to an example embodiment in which each fragmented chip 110 comprises two types of computing groups. For example, as in the example in Figure 1B, the computing device 100 comprises four computing stacks 104, 106, 114, and 116. In the example in Figure 9, each computing stack comprises a single fragmented chip 110 mounted on the corresponding network chip 108. Each fragmented chip 110 comprises, for example, nine computing groups arranged in three columns and three rows, each computing group being connected to a corresponding NoC router 202 (not shown in Figure 9) of the NoC 201 of the corresponding network chip 108.As represented by hatched cells, the upper left and upper center computing group of each fragmented chip 110 is, for example, implemented by a general-purpose CPU 800, and the other computing groups are, for example, specific hardware circuits such as accelerators, one example of which is the DNN 700 accelerator.

[0112] Figure 10 is a planar view of the computing device 100 according to an example embodiment in which each fragmented chip 110 comprises a single type of computing group. Each computing group is, for example, connected to a corresponding NoC router 202 of the NoC 201 (not shown in Figure 10) of the corresponding network chip 108. For example, as in the example in Figure 1B, the computing device 100 comprises four computing stacks 104, 106, 114, and 116.

[0113] The computer stack 104 includes, for example, a single fragmented chip 110 mounted on the corresponding network chip 108 and comprising four computing groups corresponding to general-purpose CPUs in a two-by-two arrangement.

[0114] The computing stack 106 includes, for example, a single fragmented chip 110 mounted on the corresponding network chip 108 and comprising nine computing groups corresponding to specific hardware circuits, such as DNN 700 accelerators, arranged three by three.

[0115] The computer stack 114 includes for example two fragmented chips 110 mounted on the corresponding network chip 108, each of the fragmented chips 110 comprising two general-purpose CPUs, such as the CPU core 800 of [Fig.8].

[0116] The computer stack 116 includes, for example, a single fragmented chip 110 mounted on the corresponding network chip 108 and comprising six general-purpose CPUs, such as the CPU core 800 of [Fig.8].

[0117] The computing device 100 as described herein has advantages in terms of flexibility and configurability, since it is possible for a designer to assemble a number of network chips 108 and a number and type of fragmented chips that satisfy the constraints of a given application, including processing capacity, power consumption and memory storage capacity.

[0118] In order for the computing device 100 to be functional, each of the NoC routers 202 in the NoC is, for example, programmed to correctly route data packets to and from the various fragmented chips 110. This information is, for example, defined in a routing table stored by some or all of the NoC routers 202, and / or by the chip-to-chip interfaces. In some embodiments, the first time the computing device 100 is powered on after its manufacture, an automatic configuration procedure is triggered so that the system automatically discovers the available resources and generates the routing table. An example of such a procedure will now be described with reference to Figures 11 and 12.

[0119] Figure 11 is a flowchart representing an example of the steps in a configuration process for the computer device 100 described herein. This process is implemented, for example, by the network chips 108, and, for example, by the configuration processor 216 implemented in the network chips 108.

[0120] In a step 1101 (FIRST POWER ON), the computing device 100 is, for example, powered on for the first time. For example, the computing device 100 has been assembled with at least one network chip 108, and one or more of the fragment chips 110 mounted on one, some, or all of the network chips 108. It would also be possible that some network chips 108 do not have any fragment chips 110 mounted on them. In addition, the bus interface 228 of one of the network chips 108 has, for example, been connected to a system bus of a computing system in which the computing device 100 is to be integrated. In some embodiments, a host processor, such as the host processor 404 of [Fig. 4], is accessible via this system bus. Furthermore, in some embodiments, one or more external memories, such as the memories 402 of [Fig. 4], are also connected to the system bus.4], were connected to external memory interfaces 218 of one or more network chips 108. .

[0121] In a step 1102 (START AUTO-CONFIG), an automatic configuration procedure is triggered, for example. If the computer device 100 comprises a plurality of network chips 108, one of these network chips is designed, for example, as the network chip that first triggers and manages the automatic configuration process. This network chip 108 will be designated as the primary network chip. For example, the network chip 108 having its bus interface 218 connected to the system bus is the primary network chip, and, for example, detects this bus and triggers the automatic configuration procedure.According to one variant, each 108 network chip includes a configuration input pin (not shown) and the primary 108 network chip is identified by connecting this configuration input pin to a given voltage level, such as a VDD supply voltage, while the pin of each other 108 network chip is connected to another level such as ground.

[0122] In a step 1103 (DETECT NETWORK CHIP ORIENTATIONS), the primary network chip triggers, for example, a detection procedure to detect the presence and orientations of the network chips 108 in the computing device 100. For example, the primary network chip is configured to detect whether any network chip is connected to any of its chip-to-chip interfaces 206, 208, 210, 212, and the orientations of these chips, and then to request that each new network chip discovered perform a similar check and report, this step being repeated until no more new network chips are discovered.

[0123] Considering the example in [Fig. 4], the network chip 108A is the primary network chip, and transmits signals from each of its chip-to-chip interfaces 206, 208, 210, 212 to detect additional chips and to request their orientations. Thus, it determines, for example, that its north and west interfaces 206, 212 are not connected to any other chip, that its east chip-to-chip interface 208 is connected to a south chip-to-chip interface 210 of the network chip 108B, and that its south chip-to-chip interface 208 is connected to an east chip-to-chip interface 210 of the network chip 108D. In some embodiments, the network chips 108B and 108D also communicate their identifier numbers, which are unique identifiers, to the primary network chip, at least among the network chips 108 of the device 100, thus enabling the primary network chip 108A to determine that the network chips 108B and 108D are separate chips.The primary network chip 108A then requests, for example, that each of the network chips 108B and 108D perform a similar detection via their chip-to-chip interfaces and report it. For example, network chip 108B reports that its chip-to-chip interface 208 is connected to the south chip-to-chip interface 210 of network chip 108C, and network chip 108D reports that its south chip-to-chip interface 210 is connected to the east chip-to-chip interface 208 of network chip 108C. The primary network chip 108A can thus determine, by the identifier of chip 108C, that the same chip is connected to both network chips 108B and 108D. In some embodiments, the primary network chip 108A is then configured to request, via the network chip 108B or 108D, the network chip 108C to perform a similar detection via its chip-to-chip interfaces, and to report.This time, for example, no new chips are discovered, and thus step 1103 is completed. In the case of a large number of network chips, this procedure continues, for example, until all network chips and their orientations have been discovered.

[0124] In a step 1104 (DETECT PRESENCE OF CHIPLETS / RESOURCES), each network chip 108 of the device 100 is, for example, configured to detect the presence of one or more fragmented chips mounted or placed on it, and of any additional resources, such as memory or peripheral circuits, connected to it. For example, the primary network chip performs this detection at each of its NoC routers and requests that each of the other discovered network chips perform a similar check and report back. The presence of peripheral circuits, or external resources, is detected, for example, using the corresponding interfaces 218, 224, and 226 described in relation to [Fig. 2]. In some embodiments, the presence of a fragmented chip is detected by a dedicated circuit, as will be described below in relation to [Fig. 12].

[0125] Figure 12 schematically represents a fragmented chip detection circuit 1200 according to one embodiment. Each network chip 108 includes, for example, in association with each of its NoC routers 202, an interconnect pad 170A dedicated to fragmented chip detection. For example, each fragmented chip 110 includes, for example, for each NoC router 202 with which it must communicate, an interconnect pad 170B also dedicated to fragmented chip detection.

[0126] The connection pin 170B is, for example, connected in the fragmented chip 110 to a power supply rail (VDD) via a resistor RL. The connection pin 170A is, for example, connected in the network chip 108 to a ground voltage via a resistor R2, and to the input of a buffer 1202, implemented, for example, by an inverter. The buffer 1202 generates a detection signal Sd indicating when a fragmented chip 110 is present. The resistance of resistor R2 is, for example, greater than the resistance of resistor RL. For example, resistor RI has a resistance in the range of 30 to 100 ohms, and resistor R2 has a resistance in the range of 1 kΩ to 500 kΩ. Thus, when no fragmented chip 110 is present, the voltage at the 170A pin is for example kept low by resistor R2, and inverter 1202 provides a high value.When a fragmented chip 110 is present, the connection pads 170A and 170B are in electrical contact with each other, and the voltage at pad 170A thus increases to a relatively high level, causing the Sd signal to go down, and thus indicating the presence of the fragmented chip 110.

[0127] Depending on the chip-to-chip interface technology, the 170A, 170B pads could be made by micro-bumps or other types of chip-to-chip connections.

[0128] Of course, the circuit in [Fig. 12] provides just one example of a mechanism for detecting the presence of a fragmented chip, other solutions being possible.

[0129] In some embodiments, for each fragmented chip detected, a security procedure is applied before allowing the fragmented chip to be integrated into the computing device 100. For example, this involves a procedure authentication, based for example on the verification of one or more keys, which may include a shared key in the case of symmetric cryptography, or a key from a private and public key pair in the case of asymmetric cryptography.

[0130] Again in relation to [Fig. 11], in a step 1105 (CONFIGURE CACHE / SCRATCH PAD MEMORIES AND GENERATE / COMPLETE ROUTING TABLE), the primary network chip configures, for example, the cache and working memories and generates / populates a routing table. In particular, the primary network chip, for example under the direction of the host processor, is arranged to configure the memory resources of each of the network chips to define memories that must provide cache memory, and / or memories that must provide working memory. During the same step, or in a subsequent step, the routing table is generated or populated. The routing table describes, for example, the addresses of each of the NoC routers 202 of each network chip 108, the addresses of each fragmented chip 110, and also the addresses of other resources, such as peripheral circuits and / or external memory.For example, as described earlier in relation to [Fig. 4], router addresses are assigned not only based on the relative positions of the NoC 202 routers within each network chip 108, but also based on the relative positions and orientations of the network chips 108. Thus, the routing table is generated based on the presence and orientation of the network chips. The routing table is stored in a distributed manner within the NoC. For example, each NoC 202 router stores its routing information so that it can correctly forward packets across the network.

[0131] Fig. 13 schematically represents an example of a design system 1300 for the design of the computer device 100 described herein.

[0132] The design system 1300 allows, for example, the design of one or more fragmented chips compatible with the network chip design. However, the fragmented chip design is, for example, developed independently of the network chip design procedure 108, and, for example, no modification of the network chip design is made. This has advantages, in that it leads to a relatively rapid design of the fragmented chips.

[0133] The system 1300 includes, for example, stored in a database, a network chip model 1302, defining, for example: - a fast functional model 1304 of the network chip 108, intended to simulate, or co-simulate, the RTL (Register) description Transfer Level (register transfer level) of the fragmented chip assembled on a network chip, but using a relatively fast functional model, for example a description in C++, System C, or TLM (Transaction Level Modelling), rather than a full network chip database, which would be much heavier to process; - a model of electrical and synchronization constraints (.lib) 1306, for example in the form of a library file, which allows, for example, synchronization checks at the boundary between the fragmented chip 110 and the network chip 108; and - a physical view 1308 of the network chip 108, defining for example the physical model defining the physical constraints, for example the footprint, of the network chip 108, for example in the form of an LEF (Library Exchange Format) or GDSII (Graphics Design System II) file, which can be used to define the structure of the fragmented chip 110.

[0134] In addition, the database also stores, for example, software and drivers (SW & DRIVERS) 1310 associated with the network chip 108. The software and drivers include, for example, firmware for the network chip 108 implementing its functions, including drivers for the various input / output interfaces and a startup code intended to be executed during the startup sequence of the network chip 108.

[0135] The system 1300 includes, for example, a fragmented chip synthesis and development (RTL D&S) module 1312, which is configured, for example, to develop and synthesize, based partly on the network chip model 1302 and also on a fragmented chip specification, an RTL (Register Transfer Level) representation of the fragmented chip. Furthermore, the module 1312 is configured, for example, to perform an RTL verification (RTL VERIF.) 1316, and to generate a physical implementation (CHIPLET PH Y. IMPLEMENTATION) 1314 of the fragmented chip, defining, for example, the structure and other physical design features.

[0136] A high-level system (S / E) simulation and / or emulation module 1318 is for example configured to receive the network chip model 1302 and the software and drivers 1310, and to perform high-level simulation and / or emulation of the RTL design of the fragmented chip in combination with the network chip model 1302 in order to validate the design.

[0137] Modules 1312 and 1318 are, for example, implemented by software executed in a suitable data processing environment.

[0138] One advantage of the embodiments described herein is that, by providing a network chip capable of communicating with other network chips and having one or more interfaces for connecting a fragmented chip, it constitutes a versatile and relatively low-cost building block for forming a computing device. Furthermore, by assembling one or more fragmented chips onto network chips, the fragmented chips comprising computing groups, a different technology can be used for the fragmented chips than for the network chip technology. For example, an advanced technology can be used for the fragmented chips, providing high performance. Moreover, the resulting computing device has, for example, relatively high efficiency due to relatively short chip-to-chip links between the network chips, and between each network chip and its corresponding fragmented chips.Another advantage is the flexibility and modularity of the solution, as it is possible to increase processing resources simply by adding one or more fragmented chips to the device, possibly with a new network chip, and / or by adding network chips and / or external memories to increase memory resources. Furthermore, an advantage of the close proximity of the NoC memories to the compute groups of the fragmented chips is that these memories can be configured as additional cache memory or as additional working memory.

[0139] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to those skilled in the art. For example, although some embodiments have been described based on network chips comprising a network-on-chip, in other embodiments other types of programmable infrastructure could be used, in which routers are more generally any access point capable of being connected to a processing element.

[0140] Furthermore, although examples have been described in which each network chip 108 has at least one fragmented chip 110 placed on it, in alternative embodiments, one or more network chips 108 may have no fragmented chip 110 placed on it. Such a network chip 108 provides, for example, only memory resources.

[0141] Furthermore, although examples based on external DDR memories have been described, it will be obvious to those skilled in the art that the use of single data rate (SDR) memories would also be possible. In addition, other types of memory can be implemented instead of or in addition to DDR memories, such as non-volatile memories, for example FLASH memories, with their interface specific, for example a serial FLASH interface, containing for example the binary code of the system firmware.

[0142] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Network chip (108) comprising: - a programmable infrastructure (201) having a plurality of access points (202); - at least one fragmented chip communication interface (3D PLUG) adapted to interface with at least one fragmented chip (110) when the fragmented chip is placed on the network chip, each fragmented chip communication interface (3D PLUG) being connected to a corresponding point among the access points (202); and - a plurality of network-to-network communication interfaces (206, 208, 210, 212) each adapted to interface with another network chip (108).

2. Network chip according to claim 1, further comprising a memory circuit (204) connected to each router (202).

3. Network chip according to claim 2, wherein at least one of the memory circuits (204) is reconfigurable as either a cache memory (204') or a working memory (204") of the first processing element, the first processing element (602, 700, 800) comprising for example a memory management unit defining an allocation of cache memory and / or working memory to the first processing element.

4. Network chip according to claim 2 or 3, wherein at least one of the memory circuits (204) is non-volatile memory.

5. Network chip according to any one of claims 1 to 4, wherein the programmable infrastructure is a network-on-chip (201), and the access points are NoC routers (202) of the network-on-chip.

6. Computer device comprising: the network chip according to any one of claims 1 to 5 mounted on a substrate (102).

7. Computer device according to claim 6, further comprising at least one additional network chip (108) according to any one of claims 1 to 5 mounted on the substrate (102), the network chip and said at least one additional network chip being interconnected by network-to-network communication interfaces (206, 208, 210, 212).

8. Computer device according to claim 7, wherein the network chips (108) are identical to each other, at least one of the network chips having a different orientation from that of at least one other of the network chips.

9. Computer device according to claim 8, wherein each of the access points (202) of each network chip (108) is assigned and stores an address based on its location in its programmable infrastructure (201) and based on the orientation of the network chip (108) relative to the other network chips (108).

10. A computer device according to claim 8 or 9, wherein each network chip (108) comprises, at a first of its edges, an external memory interface (218), and wherein a first of the network chips (108A) is oriented so that its first edge is adjacent to a first edge of the computer device, and a second of the network chips (108B) is oriented so that its first edge is adjacent to a second edge of the computer device, the first and second edges of the computer device being, for example, perpendicular edges, or opposite edges, of the computer device.

11. A computer device according to any one of claims 6 to 10, further comprising: - at least one fragmented chip (110) placed on the network chip (108), each fragmented chip (110) comprising at least one first processing element (602, 700, 800) connected, via a fragmented chip communications interface (3D PLUG), to a first of the access points (202) of the network chip (108) on which the fragmented chip (110) is placed.

12. Computer device according to claim 11, wherein each fragmented chip (110) is configured to operate asynchronously with respect to the network chip (108) on which it is placed.

13. Computer device according to claim 11 or 12, wherein said at least one fragmented chip (110) is placed on the network chip (108) in a face-to-face arrangement.

14. Computer device according to any one of claims 11 to 13, wherein said at least one fragmented chip (110) is placed on the network chip (108) in a face-to-back arrangement.

15. Method of designing the computer device according to any one of claims 11 to 14, comprising designing said at least one fragmented chip (110) based on a network chip model (1302) representing the network chip (108).

16. A method for configuring a computer device comprising a or several network chips (108) mounted on a substrate (102), the method comprising: - the detection, by a first of the network chips (108), of the number and orientation of the network chips (108) of the computer device, in which each network chip (108) implements a programmable infrastructure (201) having a plurality of access points (202); and - the detection, by the first network chip (108), of the presence or absence of at least one fragmented chip (110) placed on each network chip (108) and connected, via a fragmented chip communication interface (3D PLUG), to at least one first of the access points (202) of the network chip (108) on which the fragmented chip (110) is placed.

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