Electronic device comprising transistors

Abstract

Electronic device comprising transistors. This description relates to an electronic device (100) comprising a semiconductor substrate (102) and transistors whose gates (120) are contained in trenches (110) extending into the semiconductor substrate, each transistor comprising a semiconductor casing (130) doped with a first type of conductivity, the casing being buried in the semiconductor substrate and in contact with two adjacent trenches, among said trenches, a first semiconductor region (152) doped with a second type of conductivity, covering the casing, in contact with the casing, and in contact with the two adjacent trenches, a second semiconductor region (150) doped with the second type of conductivity more heavily doped than the first semiconductor region, extending into the first semiconductor region, and a third semiconductor region (132) doped with the first type of conductivity.more heavily doped than the box, covering the box, in contact with the first region, and extending into the semiconductor substrate in contact with the box. Figure for the abbreviation: Fig. 2,

Description

Description Title of the invention: Electronic device comprising transistors technical field

[0001] — This description generally relates to electronic devices, and more specifically electronic devices including transistors. Previous technique

[0002] — In certain electronic devices, field-effect transistors are used to a non-conducting state to block high voltages, typically above 10 V, for example, on the order of 40 V, or even exceeding 100 V. Such transistors with a magnetic effect Fields are generally suitable for blocking high drain-source voltages only when the drain-source voltage is positive. To achieve a blockage of a Since voltage can be positive or negative, it may be necessary to have two Field-effect transistors in antiparallel. This can present a space requirement. important and costly. Summary of the invention

[0003] = An object of an embodiment is to provide an electronic device including transistors that overcome all or part of the drawbacks of the devices existing transistor-based electronics.

[0004] — According to an object of an embodiment, the surface occupied by the effect transistors The field of view is reduced.

[0005] According to an object of an embodiment, the manufacturing cost of the effect transistors The field of view is reduced.

[0006] One embodiment provides an electronic device comprising a substrate se- semiconductor having a first face and transistors whose gates are contained in trenches extending into the semiconductor substrate, each transistor comprising, within the semiconductor substrate, a doped semiconductor casing first type of conductivity, in which the channel of the transistor, the casing being buried in the semiconductor substrate and in contact with two adjacent trenches among said trenches, a first semi-con- a doped conductive material of a second type of conductivity, opposite to the first type of conductivity, covering the casing, in contact with the casing, and in contact with the two adjacent trenches, a second type-doped semiconductor region of conductivity more strongly doped than the first semiconductor region, extending into the first semiconductor region and exposed on the first face, and a third semiconductor region doped with the first type of conductivity, plus heavily doped than the box, covering the box, exposed on the first face, in contact with the first region, and extending into the semiconductor substrate in contact with the box. According to one embodiment, the second semiconductor region is in contact with the two adjacent trenches. According to one embodiment, the third semiconductor region is in contact with the two adjacent trenches. According to one embodiment, the first semiconductor region comprises a first semiconductor subregion containing the second semiconductor region and at least one second semiconductor subregion exposed on the first face and connecting the first semiconductor subregion to the third semiconductor region, the maximum depth of the first semiconductor subregion being greater than the maximum depth of the second semiconductor subregion. According to one embodiment, each transistor comprises, in the trench containing the transistor gate: - a first electrically insulating layer between the transistor gate and the semiconductor casing, forming the transistor gate insulator; - an electrically conductive element located in the trench; - a second electrically insulating layer between the electrically conductive element and the semiconductor substrate; and - a third electrically insulating layer between the electrically conductive element and the grid. According to one embodiment, the second semiconductor regions of the transistors are electrically connected together and the third semiconductor regions of the transistors are electrically connected together. According to one embodiment, the semiconductor substrate comprises a second face opposite the first face, each transistor further comprising, in the semiconductor substrate, a fourth doped semiconductor region of the second type of conductivity, covered by the casing, in contact with the casing, and a fifth doped semiconductor region of the second type of conductivity, more strongly doped than the fourth semiconductor region, and exposed on the second face. According to one embodiment, the electronic device comprises several transistors for each pair of adjacent trenches, with at least some of the third semiconductor regions of the transistors being alternated with the second semiconductor regions of the transistors. According to one embodiment, the housings of two adjacent transistors are joined. One embodiment also provides a method for manufacturing the electronic device as defined above, in which the formation of the first The semiconductor region comprises a step of formation, by epitaxy, of a doped semiconductor layer of the second type of conductivity, and a step of implantation of dopants of the second type of conductivity into the semiconductor layer. Brief description of the drawings These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: [Fig.1 A] is a partial and schematic side-sectional view of a method of implementing an electronic device comprising transistors; [Fig.1B] is another partial and schematic lateral cross-sectional view of the device in [Fig.1A]; [Fig.1C] is another partial and schematic lateral cross-sectional view of the device in [Fig.1A]; [Fig.1D] is a partial and schematic top view of the device in [Fig.1A]; [Fig.2] is a partial and schematic perspective view with cross-section of the device in figures 1A to ID; [Fig.3A] is a partial and schematic side section view, analogous to [Fig.1A] illustrating one embodiment of the connections of the sources and the housings of the transistors; [Fig.3B] is another partial and schematic side-section view, analogous to [Fig.1B] illustrating one embodiment of the transistor gate connections; [Fig.4] is a partial and schematic top view illustrating one method of making transistor connections; Figure 5 is a partial, schematic top view illustrating another embodiment of the transistor connections: [Fig.6] illustrates a step in an embodiment of a manufacturing process for the device shown in Figures 1A to ID and 2; [Fig.7] illustrates another step in the process; [Fig.8] illustrates another step in the process; [Fig.9] illustrates another step in the process; [Fig.10] illustrates another step in the process; [Fig.11] illustrates another step in the process; [Fig.12] illustrates, through three views, another stage of the process; [Fig.13] illustrates, through three views, another stage of the process; [Fig.14] illustrates, through three views, another stage of the process; Figure 15 is a perspective view with a cross-section of the device shown on the... figures 1A to 1D illustrating an example of the evolution of dopant concentration; [Fig.16] is a view analogous to [Fig.15] from another direction; [Fig.17] represents curves showing the evolution of dopant concentrations obtained at the manufacturing stages implemented to obtain the dopant concentrations illustrated in Figures 15 and 16; [Fig.18] represents a curve of evolution of the resistance in the on state Ron of a transistor of the device shown in figures 1A to ID; [Fig.19] is a cross-sectional view of the device shown in Figures LA to 1D illustrating the evolution of the current density in a first usage configuration; [Fig.20] is a perspective view with cross-section of the device shown in Figures 1A to 1D illustrating the evolution of the current density in the first configuration of use; [Fig.21] is a view analogous to [Fig.19] in a second usage configuration; [Fig.22] is a view analogous to [Fig.20] in the second usage configuration; Figure 23 is a view analogous to Figure 19 in a third usage configuration; and [Fig.24] is a view analogous to [Fig.20] in the third usage configuration. Description of the implementation methods The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may possess identical structural, dimensional, and material properties. For clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, mask fabrication steps, doping steps, and fabrication steps for terminals electrically connected to doped areas are not detailed, as the described embodiments are compatible with such standard steps. Unless otherwise specified, when referring to two connected elements, this means directly connected without any intervening elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the terms "insulator" and "conductor" are understood here to mean "electrically insulating" and "conductive," respectively. “electrically conductive”. In the description that follows, when referring to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or relative positional qualifiers, such as the terms “above”, “below”, “superior”, “inferior”, etc., or to orientational qualifiers, such as the terms “horizontal”, “vertical”, etc., unless otherwise specified, reference is made to the orientation of the figures or to a display screen in a normal operating position. Unless otherwise specified, the expressions 'approximately', 'roughly', 'significantly', and 'in the order of' mean within 10%, preferably within 5%. Unless otherwise specified, ordinal numeral adjectives, such as 'first', 'second', etc., are used only to distinguish elements from one another. In particular, these adjectives do not restrict the described realizations to a specific order of these elements. Figures 1A, 1B, 1C, and 1D represent, partially and schematically, respectively, cross-sectional views and a top view, and [Fig. 2] is a perspective view of an embodiment of a device 100 comprising several transistors T. The cross-sectional views 1B and 1C have parallel planes 1B-1B and 1C-1C, respectively. The transistors T are partially shown in Figures 1A to 1D and 2. The device 100 is typically an electronic integrated circuit chip, defined by a semiconductor substrate 102 comprising a front face 104 and a rear face 106, not visible in Figures 1A to 1D and 2 and visible in Figures 3A and 3B described later, opposite the front face 104, and transistors T located in and on the substrate 102. The T transistors are delimited by trenches 110, four parallel trenches 110 being shown as an example in Figures 1B to 1D and 2. Each trench 110 extends into the substrate 102 from the front face 104 over a portion of the thickness of the substrate 102. Each transistor T includes, in particular: - a grid 120 located in one of the trenches 110; - a semiconductor box 130 doped with a first type of conductivity, buried in the substrate 102, separated from the gate 120 by a gate insulator 124, and in which the channel of the transistor T is formed during operation. The box 130 is connected to the front face 104 by a semiconductor contact area 132 extending into the substrate 102 from the front face 104; - Doped semiconductor zones 140 and 150 of drain / source, doped with a second type of conductivity, opposite to the first type of conductivity, and located on either side of the 130 box. The doped zone 140, also called the drain region, not visible in Figures 1A to 1D and 2, but visible in Figures 3A and 3B described below, is in contact with the rear face 106 of the substrate 102, and the doped area 150, also called the source region, is in contact with the front face 104 of the substrate 102: and - Semiconductor regions 142, 152, called drift regions, doped with the second type of conductivity and less strongly doped than doped areas 140 and 150. Drift region 142 is interposed between doped area 140 and box 130 and semiconductor region 152 is interposed between doped area 150 and box 130. Each transistor T defined by the elements described above thus constitutes a field-effect transistor, that is to say an electronic component capable, depending on a control voltage applied between the gate 120 and the source region 150, of forming, in the casing 130, a conductive channel electrically connecting the drain and source regions 140 and 150. The gate 120 of each transistor T includes at least one electrically conductive region extending into one of the trenches 110, such as, for example, a metal and / or doped polycrystalline silicon. A side wall of the trench 110 forms a side face of the housing 130 of the transistor T. The gate insulator 124, covering the side wall of the trench 110, is in contact with the housing 130 and with the conductive region of the gate 120. The gate insulator 124 is typically made of one or more dielectric layers; for example, the gate insulator is made of a layer of silicon oxide. The thickness of the gate insulator 124 is typically less than 15 nm, preferably between 20 nm and 40 nm. The number and dimensions of the trenches 110 depend on the intended application. The depth of each trench 10 can be between 1.7 µm and 2.5 µm, for example, approximately 2 µm. As an example, each trench 110 can have a width between 0.1 µm and 1 µm, for example, 0.6 µm. Preferably, the trenches 110 extend at least partially in directions parallel to a common direction, hereafter referred to as the longitudinal trench direction, and are evenly spaced. The direction perpendicular to the longitudinal trench direction is hereafter referred to as the lateral trench direction. The spacing of the trenches along the lateral trench direction can be between 0.9 µm and 1.2 µm. The number of trenches 110 can vary from 1000 to 3000. The length of each trench 110 according to the longitudinal direction of the trench can vary from 0.5 µm to 3 µm. According to one embodiment, as shown in Figures 1B and 2, each trench 110 of a set of adjacent and parallel trenches 110, possibly excluding the trenches 110 located at the two opposite edges of the set of trenches 110, delimits transistors T on either side of the trench 110. According to another embodiment, as shown in Figures 1D and 2, for each trench 110, the grids 120 contained in the trench 110 are connected to each other and form a common grid 120 for the transistors T which are delimited by this trench 110. According to one embodiment, for each trench 110, the semiconductor boxes 130 of the transistors T which are delimited by this trench 110 and located on the same side of this trench 110 are joined and form a continuous semiconductor box 130. In one example, the substrate 102 consists of a semiconductor wafer, for example, a silicon wafer. In another example, the substrate consists of a layer located on the surface of a semiconductor wafer, for example, an epitaxial layer on a semiconductor wafer. Preferably, the substrate 102 is single-crystal. According to one embodiment, as shown in Figures 1B and 1C, each box 130 located between the first and second adjacent trenches 110 extends from the first trench 110, in contact with the grid insulator 124 covering the side wall of the first trench 110, to the second trench, in contact with the grid insulator 124 covering the side wall of the second trench 110. The depth, measured from the front face 104, of the contact area 132 can be between 0.4 µm and 0.8 µm. The maximum depth, measured from the front face 104, of the box 130 can be between 0.8 µm and 1.2 µm. The thickness, measured along a direction orthogonal to the front face 104, of the box 130 under the drift region 152 can be between 0.5 µm and 0.8 µm. The maximum thickness, measured along a direction orthogonal to the front face 104, of the box 130 can be between 1 µm and 1.3 µm.The dimension along the longitudinal trench direction of the contact zone 132 can be between 0.5 µm and 1.5 µm. According to one embodiment, as shown in [Fig. 1D], each drift region 152 located between adjacent first and second trenches 110 extends from the first trench 110, in contact with the grid insulator 124 covering the side wall of the first trench 110, to the second trench, in contact with the grid insulator 124 covering the side wall of the second trench 110. The drift region 152 comprises a first drift subregion 154 and two second drift subregions 156, connected to the first drift subregion 154. The first drift subregion 154 is less heavily doped than the source region 150.The second drift subregions 156 are less heavily doped than the source region 150, and preferably less heavily doped than the first drift subregion 154. Each of the first drift subregion 154 and the second drift subregions 156 located between adjacent first and second trenches 110 extends from the first trench 110, in contact with the grid insulator 124 covering the side wall of the first trench 110, to the second trench, in contact with. The grid insulator 124 covers the side wall of the second trench 110. The source region 150 is contained within the first drift subregion 154. The first drift subregion 154 covers the entire bottom of the source region 150. The first drift subregion 154 covers the entire side walls of the source region 150 between the first and second trenches 110. The second drift subregions 156 are located on either side of the first drift subregion 154 along the longitudinal trench direction. Each second drift subregion 156 extends, along the longitudinal trench direction, from the first drift subregion 154 to the adjacent contact zone 132. Each second drift subregion 156 may be exposed on the front face 104 of the substrate 102.Preferably, the source region 150 extends from the first trench 110, in contact with the grid insulation 124 covering the side wall of the first trench 110, to the second trench, in contact with the grid insulation 124 covering the side wall of the second trench 110. The depth of the first drift subregion 154 can be between 0.4 µm and 0.6 µm. The depth of each subsequent drift subregion 156 can be between 0.3 µm and 0.6 µm. The maximum dimension along the longitudinal trench direction of the drift region 152 can be between 2 µm and 5 µm. The dimension along the longitudinal trench direction of the first drift subregion 154 can be between 1.5 µm and 4 µm. The dimension along the longitudinal trench direction of each subsequent drift subregion 156 can be between 0.5 µm and 1 µm. The depth, measured from the first face 104, of the source region 150 can be between 0.2 µm and 0.4 µm. For example, transistor T is an N-channel type. Thus, doped regions 140 and 150 are N-type doped. The housing 130 is P-type doped. However, in the described embodiments, the N and P conductivity types, or doping types, can be interchanged. Similar operation to that described is then obtained by reversing the signs of the voltages in the device. Preferably, the doping levels of zones 140 and 150 are high, i.e., greater than 5 × 10⁸ atoms / cm³, preferably greater than 10¹⁷ atoms / cm³. The contact 132, electrically connected to the housing 130, is a doped zone also having such a high doping level. The doping level of the housing 130 is preferably less than 10¹⁷ atoms / cm³, more preferably less than 5 × 10¹⁷ atoms / cm³. Each drift region 142, 152 has a doping level lower than that of the doped region 150. Preferably, each semiconductor region 142, 152 has a low doping level, i.e., less than 2 × 10⁻⁶ atoms / cm². This doping level is preferably greater than 5 × 10⁻⁶ atoms / cm². According to one embodiment, each first drift subregion 154 has a doping level between 2 × 10⁻⁷ atoms / cm* and 6*10' atoms / cm*. According to one embodiment, each second drift subregion 156 has a doping level between 3*10!6 atoms / em* and 1*10"7 atoms / cm*. The device 100 may further include, for each trench 110, an electrically conductive element 180 located in the trench 110. The conductive element 180 is connected to a terminal not shown in Figures 1A to 1D and 2. This terminal is preferably connected to the contact areas 132. The conductive element 180 is located opposite at least a portion of the semiconductor region 142, i.e., the conductive element 180 is located against an insulator 184 covering the lateral face of at least a portion of the semiconductor region 142. The insulating layer 184 separates the conductive element 180 from the semiconductor region 142. The distance between the conductive element 180 and the semiconductor region 142, corresponding to the thickness of the insulating layer 184, is, for example, between 100 nm and 200 nm, preferably between 120 nm and 180 nm. The insulating layer 184 preferably has a thickness greater than that of the grid insulator 124.For example, insulating layer 184 is made of silicon oxide or silicon nitride. At the bottom of the trench 110, an insulating portion, preferably a portion of the insulating layer 184, is located under the conducting element 180. This portion electrically isolates the conducting element 180 from the part of the substrate 102 located under the conducting element 180. In addition, insulating layers 186, preferably of the same material or materials as the grid insulator 124, electrically isolate the conducting element 180 from the grid 120. Preferably, the conductive element 180 consists of a conductive wall located in a central portion of the trench 110. The wall is elongated in the same direction as the trench. The wall extends into the substrate 102 orthogonally to the front face 104 of the substrate. By way of example, the wall comprises, preferably is made of, a metallic material or, preferably, doped polycrystalline silicon. The width of the conductive wall, measured in the transverse direction of the trench, is, for example, between 30 nm and 200 nm. The device 100 further comprises conductive tracks and conductive vias, not shown in Figures 1A to 1D and 2, of at least one metallization level formed on the front face 104 of the substrate 102 for connecting the sources, gates, and housings of the transistors T. In one embodiment, the source regions 150 of all the MOS transistors are connected together. In another embodiment, the gates 120 in the grooves 110 are connected together. In another embodiment, the contact areas 132 of the housings 30 are connected together. Figures 3A and 3B are views analogous respectively to figures 1A and 1B illustrating one embodiment of the connections of transistors T. As an example, device 100 is shown in figures 3A and 3B with two levels of metallization N1 and N2. The first metallization level N1 comprises an insulating layer 190 covering the front face 104 of the substrate 102, metallic tracks 192 extending over the insulating layer 190, and conductive vias 194 passing through the insulating layer 190 and connecting the metallic tracks 192 in particular to the grids 120, the source regions 150, and the contact areas 132. The second metallization level N2 comprises an insulating layer 200 covering the conductive tracks 192 and the insulating layer 190 between the conductive tracks 192, metallic tracks 202 extending over the insulating layer 200, and conductive vias 204 passing through the insulating layer 200 and connecting the metallic tracks 202 to at least some of the metallic tracks 192. The number of T transistors connected in parallel depends on the intended application. In one embodiment, the device 100 comprises from 3*105 to 3*106 T transistors. Figure 4 is a top view of an embodiment illustrating an arrangement of the conductive tracks 192 of the first metallization level, which are in the form of parallel strips and plates. Figure 4 also shows the boundaries of the trenches 110, the contact areas 132, and the source regions 150. The conductive vias 194 are further represented by squares, possibly crossed by a horizontal line. In the present embodiment, the trenches 110 are parallel and extend uninterrupted over the entire region where the transistors are formed. As shown in Figure 4, the conductive tracks 192 of the first metallization level are arranged in parallel strips and plates.[4], the conductive tracks 192 are divided into conductive plates 192_S connected to the source regions 150 by conductive vias 194_S, into conductive tracks 192_B connected to the contact areas 132 by vias 194_B, into a conductive track 192_G connected to the grids 120 by vias 194_G, and into a conductive track 192_M connected to the conductive elements 180 by vias 194_M. In the present embodiment, the plates 192_S are alternated with the strips 192_B. The conductive tracks 202 of the second metallization level, not shown in [Fig. 4], can be used for the connection of the conductive plates 192_S. Figure 5 is a top view of an embodiment illustrating an alternative arrangement of the conductive tracks 192 of the first metallization level, which are in the form of parallel strips and plates. Figure 5 also shows the boundaries of the trenches 110, the contact areas 132, and the source regions 150. In this embodiment, the trenches 110 are parallel and extend and are distributed in sets 112 of trenches over the region where the transistors are formed; each set 112 of trenches comprises first and second groups. 114, 116 of trenches 110, the trenches of the first group 114 being offset along the transverse trench direction relative to the trenches 110 of the second group 116 by half the trench spacing, the trenches of the first and second groups being connected at one end to a trench 118 extending along the transverse trench direction. The conductive vias 194 are represented by squares possibly crossed by a horizontal line. As shown in [Fig. 5], the conductive tracks 192 are divided into conductive plates 192_S connected to the source regions 150 by conductive vias 194_S, and into conductive tracks 192_MB connected to the contact areas 132 and the conductive elements 180 by vias 194_MB. The connection of the grids 120 can be made in an area outside [Fig. 5]. As an example, for an application in the field of high-power integrated relays, the drain of transistors T can be brought to operation at a potential of 40 V to 45 V. When the transistors T are in the conducting state, the voltage between the gate and the source of each transistor T is approximately 10 V and the potential at the source is approximately 40 V–45 V. When the transistors T are in the non-conducting state, the voltage between the gate and the source of each transistor T is approximately 0 V and the potential at the source is approximately 0 V. The contact areas 132 of the housings 130 are brought to 0 V and the conductive elements 180 are brought to 0 V. The presence of the conductive elements 180 advantageously reduces the intensity of the electric field present at the PN junctions during operation. This allows for an increase in the concentration of dopants in the drift region 142 and 152 while ensuring that the transistor is not damaged when maximum voltages are applied. Figures 6 to 14 are partial and schematic cross-sectional views of structures obtained at stages of an embodiment of a manufacturing process for device 100 in Figures 1A to 1D. For Figures 12, 13, and 14, three cross-sectional views A, B, and C have been shown, analogous to cross-sectional views 1A, 1B, and IC. Figure 6 represents the structure obtained after the formation in substrate 102 of the drain region 140 strongly of the second type of conductivity, for example N-type doped, and of a semiconductor layer 210 weaker than the drain region 140, whose dopant concentration corresponds substantially to the desired dopant concentration for the drift region 142. The substrate 102 can be fabricated by the formation, on a strongly doped silicon wafer, which corresponds to the drain region 140, of the weaker doped silicon semiconductor layer 210, for example by epitaxy. Fig. 7 represents the structure obtained after the formation of the trenches 110 in the layer 310 of the substrate 102. The trenches 110 can be made by an etching step. Figure 8 represents the structure obtained after the formation, on the walls and bottom of each trench 110, of an insulating layer 212. The process may include a conformal deposition of an insulating layer covering the structure resulting from the engraving of the trenches 110. The composition and thickness of the insulating layer 212 correspond to the desired composition and thickness for the insulating layer 184. As an alternative, the insulating layer 212 may be formed by a thermal oxidation step. Figure 9 represents the structure obtained after the formation in each trench 110 of a conductive core 214. The process may include the deposition of a conductive layer, for example of polycrystalline silicon, covering the insulating layer 212 and filling the remaining space of each trench 110, and the removal, for example by etching, of the parts of the conductive layer located outside the trenches 110. The composition of the conductive cores 214 corresponds to the desired composition of the conductive elements 180. Figure 10 represents the structure obtained after etching, over part of the depth of each trench 110, the insulating layer 212 and the conductive core 214. The conductive elements 180 and the insulating layers 184 of the transistors are thus formed. Figure 11 shows the structure obtained after the formation, in each trench 110, of the insulating layer 186, the grid insulator 124, and the grid 120. The grid insulator 124 can be formed by thermal oxidation. The process may include depositing a conductive layer covering the insulating layer and filling the remaining space in each trench 110, and removing, for example by etching, the portions of the conductive layer located outside the trenches 110. Figure 12 represents, in cross-sectional views 12A, 12B, and 12C, the structure obtained after a step of implanting dopants of the first type of conductivity, for example of type P, to form the housings 130 of the transistors, buried in the substrate 102. Fig. 13 represents, in cross-sectional views 13A, 13B, and 13C, the structure obtained after a first step of implantation of dopants of the second type of conductivity, to form, for each transistor T, the first drift subregion 154, and a second step of implantation of dopants of the second type of conductivity, to form, for each transistor T, the source region 150. Figure 14 represents, in cross-sectional views 14A, 14B, and 14C, the structure obtained after a step of implanting dopants of a first type of conductivity to form the contact areas 132. This further delimits, for each transistor T, the second drift subregions 156 of the drift regions 152. The transistors T are thus formed. The process continues with the formation of metallization levels. Figures 15 and 16 are perspective views with cross-sections in two different directions illustrating the evolution of dopant concentration in grayscale within the device 100 of Figures 1A to 1D, fabricated according to the embodiment of the manufacturing process described previously in relation to Figures 6 to 14, with the dopant concentration profiles illustrated in [Fig. 17]. In Figures 15 and 16, the shade of gray is darker as the concentration of N- or P-type dopants increases. In Figures 15 and 16, only the semiconductor substrate 102 is shown, and the elements of a single transistor T are partially represented. The outlines of the gate 120, the conducting element 180, and the vias 194 connected to the source region 150 and the contact area 132 of transistor T are also partially shown. On [Fig.17], curves C1, C2, C3, and C4 are profiles of dopant concentrations, expressed in atoms / cm*, in substrate 102 as a function of the depth measured from the front face 104 at the level of a source region 150. In particular, substrate 102 can be made by the formation, on a silicon wafer heavily doped with arsenic (N-type dopant), which corresponds to the drain region 140, and of the semiconductor layer 210 of silicon more weakly doped with phosphorus (N-type dopant), for example by epitaxy. Curve C1 is the curve of evolution of the concentration of arsenic (present in substrate 102) and curve C2 is the curve of evolution of the concentration of phosphorus from the formation of layer 210. Curve C3 is the curve of evolution of the concentration of boron (P-type dopant) obtained after the implantation step for the formation of cell 130.Curve C4 represents the evolution of phosphorus concentration after the implantation step for the formation of the first drift subregion 154. The evolution curve, not shown in [Fig. 5], of phosphorus concentration after the phosphorus implantation step for the formation of the source region 150 shows a peak at approximately 2*10⁻¹⁵ atoms / cm² at a depth of approximately 50 nm and drops to less than 1*10¹⁵ atoms / cm² at a depth greater than 350 nm. As shown in Figures 15 and 16, the concentration of N-type dopants evolves continuously between the first and second drift subregions 154, 156 and the source region 150. Simulations were performed on device 100, shown in Figures 11A to 1D, to highlight the properties of transistor T. For the simulations, device 100 included the dopant concentrations described previously in relation to Figures 15 to 17. The simulations correspond to normal operating conditions of transistor T and unfavorable potential conditions for the PN junctions of transistor T. The simulations were performed at a temperature of 25 °C. Figure 18 shows a current density curve (CD), expressed in A / cm², as a function of the drain voltage (Vd), expressed in volts, flowing through the drain region 140 of transistor T in the on-state. Figures 19, 21, and 23 are side-sectional views of a portion of a transistor T, and Figures 20, 22, and 24 are cross-sectional perspective views of a portion of a transistor T. Figures 19, 20, 22, and 24 illustrate the current density curve in grayscale under different operating configurations of transistor T. For Figures 19, 20, 22, and 24, the current density (CD) is expressed in A / cm². The shade of gray is darker as the current density reaches extremely high or extremely low values. For Figures 20, 22, and 24, the current density CD is expressed in A / cm². Figures 21 and 23 represent equipotential lines in different transistor T operating configurations.In figures 21 and 23, the concentration of dopants is further represented in shades of grey; the shade of grey is darker the higher the concentration of N- or P-type dopants. Figures 18 to 20 illustrate an initial simulation in which transistor T is in the forward-biased state. The drain of transistor T was at a potential of approximately 40 V, the gate-source voltage of transistor T was approximately 10 V, and the source potential of transistor T was approximately 40 V. A forward-biased resistance Ron of approximately 6.3 mΩ·mm was determined. The presence of the contact areas 132 does not result in excessive degradation of the forward-biased resistance Ron compared to a structure in which the source region extends along the entire length of the trench. Figures 21 and 22 illustrate a second simulation in which transistor T is in the off state and the biasing conditions of the PN junction between the housing 130 and the drift region 142 are the most unfavorable. The drain of transistor T is at a potential of approximately 40 V, the gate-source voltage of transistor T was approximately 0 V, and the source potential of transistor T was approximately 0 V. The PN junction formed between the housing 130 and the drift region 142 is reverse-biased and holds the applied potentials. Figures 23 and 24 illustrate a third simulation in which the T transistors are in the off state and the biasing conditions of the junction between the box 130 and the drift region 152 are the most unfavorable. The drain of each T transistor was at a potential of approximately 0V, the gate-source voltage of each T transistor was approximately 0V, and the source potential of each T transistor was approximately 17 V. The PN junction formed between the box 130 and the drift region 152 is reverse-biased and holds the applied potentials. The T transistors described above advantageously allow for a holding voltage in the non-conducting state for both a positive drain-source voltage and a negative drain-source voltage. Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to those skilled in the art. In particular, the T transistors have been described with a drain region 140 located on the rear side. As an alternative, the drift region 142 may be in contact with a more heavily doped contact area located on the front side. Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic device (100) comprising a semiconductor substrate (102) having a first face (104) and transistors (T) whose gates {120) are contained in trenches (110) extending into the substrate semiconductor, each transistor comprising, in the semiconductor substrate conductor, a semiconductor casing (130) doped with a first type of conductivity, in which the channel of the transistor, the casing being buried in the semiconductor substrate and at contact of two adjacent trenches among said trenches, a first semiconductor region (152) doped with a second type of conductivity, as opposed to the first type of conductivity, covering the caisson, in contact with the caisson, and in contact with the two trenches ad- underlying, a second semiconductor region (150) doped with second type of conductivity more strongly doped than the first semiconductor region, extending into the first semiconductor region conductive and exposed on the first face, and a third semi- conductive (132) doped with the first type of conductivity, more strongly doped that the box, covering the box, exposed on the first facing, in contact with the first region, and extending into the substrate se- semiconductor in contact with the casing.

2. An electronic device according to claim 1, wherein the second semiconducting region (150) is in contact with the two trenches ad- Jacentes.

3. Electronic device according to claim 1 or 2, wherein the The third semiconductor region (132) is in contact with the two adjacent trenches.

4. Electronic device according to any one of claims 1 to 3, in which the first semiconductor region (152) comprises a first semiconductor subregion (154) containing the second semiconductor region (150) and at least a second subregion se- miconductor (156) exposed on the first face (104) and connecting the first semiconductor subregion to the third semiconductor region ducting (132), the maximum depth of the first semi-subregion conductive being greater than the maximum depth of the second semiconductor subregion.

5. Electronic device according to any one of claims 1 to 4, in which each transistor (T) comprises, in the trench (110) containing the gate (120) of the transistor: - a first electrically insulating layer (124) between the grid (120) of the transistor and the semiconductor casing (130) and forming the insulator of transistor grid; - an electrically conductive element (180) located in the trench (110); - a second electrically insulating layer (184) between the element electrically conductive and the semiconductor substrate; and - a third electrically insulating layer (186) between the element electrically conductive and the grid.

6. Electronic device according to any one of claims 1 to 5, in which the second semiconductor regions (150) of the transistors (T) are electrically connected together and in which the third semiconductor regions (132) of the transistors (T) are electrically connected together.

7. Electronic device according to any one of claims | to 6, in which the semiconductor substrate (102) comprises a second face (106) opposite the first face (04), each transistor including, in the semiconductor substrate, a fourth semiconducting region (142) doped with the second type of conductivity, covered by the casing (130), in contact with the casing, and a fifth semiconducting region (150) doped with the second type of conductivity, more heavily doped than the fourth semiconductor region, and displayed on the second side.

8. Electronic device according to any one of claims 1 to 7, comprising several transistors (T) for each pair of trenches (110) adjacent, at least some of the third semi-con- regions conducting regions (132) of the transistors being alternated with the second regions semiconductors (150) of transistors.

9. Electronic device according to claim 8, wherein the boxes (130) of two adjacent transistors (T) are joined.

10. Method of manufacturing the electronic device (100) according to one any of claims 1 to 9, wherein the formation of the the first semiconductor region (152) includes a step of formation, by epitaxy, of a semiconductor layer (210) doped with a second type of conductivity, and a dopant implantation step of the second type of conductivity in the semiconductor layer.