METHOD FOR THE MANUFACTURE OF POLYCRYSTALLINE SILICON CARBIDE USABLE FOR THE MANUFACTURE OF INTEGRATED CIRCUIT SUBSTRATES, AND SILICON CARBIDE THUS OBTAINED

Abstract

A process for manufacturing a polycrystalline SiC plate by chemical vapor deposition on a graphite surface, in which a mixture of gases is introduced into a heated chamber so as to create a gaseous phase comprising: - at least one gaseous precursor of silicon and / or carbon, - at least one dopant gas comprising at least one nitrogen atom, - a carrier gas, said gas mixture decomposing on the graphite surface to form a layer of polycrystalline SiC, and said process being characterized in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar. The said plate is characterized in that: (i) its texture coefficient C422 is less than 30%, and (ii.a) its texture coefficient C220 is greater than 60%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 70%.

Description

Title of the invention: METHOD FOR MANUFACTURING USABLE POLYCRYSTALLINE SILICON CARBIDE FOR THE MANUFACTURE OF INTEGRATED CIRCUIT SUBSTRATES, AND SILICON CARBIDE THUS OBTAINED technical field

[0001] The invention relates to the field of materials science, and more particularly to the field of materials usable for the manufacture of substrates for integrated circuits, and to the processes for producing these materials. It relates more specifically to polycrystalline silicon carbide. This material, like all materials for microelectronic substrates, is used in the form of thin wafers (for which those skilled in the art often use the English term "wafer"), typically circular. SiC is particularly well-suited to the manufacture of substrates for use in power electronic components. The SiC wafers must meet very strict specifications regarding their flatness, the homogeneity of their properties, and the absence of defects.

[0002] The present invention presents a new type of polycrystalline SiC wafers usable for the manufacture of integrated circuit substrates; these wafers have particular crystallographic characteristics.

[0003] Since integrated circuits are generally deposited on the surfaces of a single-crystal semiconductor, in the case of a polycrystalline silicon carbide wafer, the electronically active surface (i.e., the surface on which the integrated circuits are deposited) must be specially prepared by transferring a layer of single-crystal SiC. This preparation method by transferring a layer of single-crystal SiC is not part of the present invention.

[0004] The present invention also relates to a new method for manufacturing such a polycrystalline silicon carbide wafer capable of receiving, in a subsequent manufacturing step, the transfer of a monocrystalline SiC layer. Prior art

[0005] Since the beginning of microelectronics, the vast majority of microelectronic circuits have been fabricated on a single-crystal silicon substrate. For certain specific applications, semiconductor silicon is not the ideal substrate, but it is used for lack of a better alternative. Silicon carbide (abbreviated SiC), on the other hand, is a remarkable semiconductor material. It possesses a wide band gap, a high breakdown field, high charge carrier mobility at saturation, and a strong Thermal conductivity. This combination of exceptional physical properties gives it excellent voltage resistance, as well as the ability to handle very high current densities, even at high temperatures. The article "Power Components in SiC - Technology" by D. Tournier, published in 2007 as part D-3120 in the Techniques de l'Ingénieur collection, provides an introduction to the subject.

[0006] SiC is therefore a material perfectly suited for manufacturing power components necessary for the efficient conversion of electrical energy in applications such as power distribution, renewable energies, and electric vehicles. The use of SiC makes it possible to advantageously replace silicon-based transistors such as IGBTs with power components such as MOSFETs, offering voltage withstand rates on the order of kilovolts and significantly lower switching energy losses. In these power components, voltage and temperature withstand can become limiting factors during the design of the electronic components and the circuit boards on which these components are mounted.The recent development of electric vehicles would greatly benefit from the use of such SiC power components to improve energy efficiency during the conversion of direct current from batteries into alternating current usable by the motor. However, the cost and availability of these components remain obstacles to the adoption of this technology, and for this reason, silicon is still widely used as a substrate in specific applications where SiC would offer technical advantages.

[0007] According to the prior art, silicon carbide substrates intended for the deposition of microelectronic circuits are in the form of wafers, generally circular in shape. They are manufactured industrially using the PVT (Physical Vapor Transfer) process, which consists of sublimating a SiC powder at high temperature (> 2200°C) and condensing the vapors onto a seed to obtain a single-crystal SiC ingot or "ball." Single-crystal SiC substrates (wafers) are then sliced ​​from this single-crystal ingot. A layer of crystalline SiC is deposited by epitaxy on one face of this substrate to obtain a crystal with as few defects as possible. After epitaxy, these wafers are ready for the fabrication of electronic components.

[0008] Improvements to the industrial PVT process over the past 30 years have significantly reduced the density of major crystalline defects in these substrates, such as dislocations and micropipes, which had a major impact on the reliability of SiC components. Furthermore, they have made it possible to increase the size of the substrates (wafers) to a standard diameter of 150 mm, with a target of 200 mm expected very soon. Despite these industrial efforts, the PVT process remains complex to control, has low productivity, and consumes a significant amount of energy because it requires maintaining a very hot furnace. high temperature for about a hundred hours.

[0009] Furthermore, for power components, the lowest possible on-mode resistance (Ron) is a determining factor for improving the system's energy efficiency by limiting Joule heating during current flow. In these applications, single-crystal SiC is doped both to enable the fabrication of the component's P / N junctions and to reduce its resistivity at the drain contact. The addition of nitrogen allows the substrate to be doped during crystal growth. Standard "n"-doped wafers have a resistivity on the order of 20 mOhm·cm. It becomes very difficult to reduce the resistivity below this threshold without degrading the crystal quality, because excessive doping creates stresses that promote further crystal dislocations.

[0010] A new technology under development would allow the combination of a low-cost SiC substrate (wafer) with improved electrical performance and a high-quality single-crystal SiC thin film in which the microelectronic component would be fabricated. The single-crystal SiC layer is deposited onto the substrate by a molecular bonding process as described in WO 01 / 18873 (French Atomic Energy Commission), which also ensures minimal contact resistance between the substrate and the deposited single-crystal layer. EP 3 018 696 A1 describes an embodiment of such a process, resulting in a single-crystal SiC layer deposited onto a polycrystalline SiC substrate (hereinafter referred to as "P-SiC" or "P-SiC Wafer").

[0011] These P-SiC substrates must meet strict requirements for electrical resistance, thermal conductivity, and flatness. Prototype "dummy wafers" are currently available on the market from companies such as Ferrotec. These wafers, with a standard diameter of 150 mm and a thickness of 750 µm, are used to balance a full load of single-crystal SiC wafers in certain processes to improve uniformity.

[0012] According to the prior art, P-SiC wafers are obtained by depositing polycrystalline SiC by CVD onto a cylindrical graphite substrate. After machining away the SiC layer deposited around the periphery of the cylinder until the graphite is exposed, two SiC disks can be separated from the two faces of the cylinder by oxidation of the graphite in air. This is described in patent applications JP 1994 340994 and JP 1997 296361.

[0013] However, it soon became apparent that the resulting wafers exhibited unacceptable deformation (Bow and Warp) for the intended application. The Bow and Warp parameters represent the flatness of a wafer intended for the semiconductor industry and are known to those skilled in the art of semiconductor substrates for microelectronics (only the English terms are used for these parameters, which we write here). (with a capital letter); they will be described in greater detail below and can be measured according to the SEMI MF 1390 standard. The processes described in the two Japanese documents cited above provide a solution to the problem through the repetition of several thin-layer deposition steps, less than 100 µm thick. Indeed, for a sufficiently thick deposit, the increase in grain diameter generates an internal compressive stress. The conical grains repel each other as they grow. This physical mechanism is demonstrated by P. Chaudhari in the publication "Grain growth and Stress relief in thin films," published in the Journal of Vacuum Science and Technology 9, 520 (1972), which is a fundamental document for any specialist in vapor deposition.The process described in JP 1994 340994 and JP 1997 296361 makes it possible to obtain thick layers of P-SiC of several hundred microns by limiting the increase of internal compressive stresses and therefore makes it possible to limit the deformations once detached from the graphite.

[0014] Japanese patent JP 3648 112 B2 describes a similar process that allows for the alternating deposition of layers exhibiting tensile and compressive stresses, in order to cancel the integrated stress moment over the entire thickness of the deposit. This mechanical moment is indeed the cause of the deformation observed when the P-SiC disk is removed from its graphite substrate.

[0015] It is important to note, however, that the processes described above are not suitable for achieving low resistivity and good thermal conductivity through the wafer thickness due to the multiple interfaces separating the layers within its thickness. A single-layer solution to the problem would be more advantageous.

[0016] US patent 10,934,634 B2 describes obtaining a P-SiC wafer with excellent flatness from a single layer of SiC deposited by CVD on a graphite substrate. A sufficiently thick deposit, typically 2 mm, has an upper portion where the variation in grain diameter is stabilized. Since the compressive stress no longer changes in this portion (as demonstrated in the cited publication by Chaudhari), it is then possible to machine a 350 µm thick slice that exhibits a near-zero stress gradient, similar to the grain size gradient throughout the thickness, and thus integrates a near-zero mechanical moment over the thickness. The expected effect is very low wafer deformation.However, the cost and energy expended by such a process is probably unfavorable, since approximately 1.65 mm of the 2 mm layer deposited by CVD must be removed by grinding and polishing to obtain the wafer at the desired thickness of 350 µm with the desired flatness.

[0017] To reduce manufacturing costs, it would be optimal to grow by CVD at high speed a P-SiC layer of thickness as close as possible to the final thickness with a grain size very quickly stabilized after the start of layer growth, to avoid any unnecessary overthickness which would become necessary to reduce or eliminate the grain size gradient.

[0018] At the Transducers & Eurosensors 2007 conference, XA Fu et al. published a paper entitled "Nitrogen-doped polycrystalline 3C-SiC films deposited by LPCVD for MEMS applications." In this paper, the authors studied the deposition of SiC with dopant gas levels (NH3) ranging from 2% to 12% as a mole fraction of the silicon precursor (dichlorosilane). To obtain a resistivity below 20 mΩ·cm under these conditions, the dopant concentration must exceed 5%. A higher dopant concentration leads to an increase in residual stress without increasing the stress gradient. In this study, the deposition was carried out at a low temperature (900°C) and low pressure, favoring crystal growth exclusively along the (111) axis, but with an extremely slow deposition rate of 0.6 pm / h.Significant doping does not appear to alter the crystalline orientation of the deposited thin film under these conditions, as measured by X-ray diffraction (XRD) analysis.

[0019] In the publication by HKE Latha et al. published in 2014 in the journal Mater. Res. Express 1 015902, the effects of high doping of 3C-SiC obtained by CVD using methyltrichlorosilane (MTCS) as a silicon and carbon precursor, and NH3 as a doping agent, are studied. The deposition conditions are 1040°C at low pressure. The growth rate of the deposit reaches approximately 5 pm / h, much higher than the previous case, but still far too low to produce large thicknesses (several hundred microns) in an economically viable manner. An influence of the doping level on the crystal orientation and grain size is observed under these conditions. A high doping level is accompanied by an increase in grain size, and their crystal orientation axis is modified according to X-ray diffraction (XRD) analysis.

[0020] Patent application WO 2021 / 060515 (Tokai Carbon) proposes a process for obtaining a P-SiC substrate with a thickness between 500 µm and 6 mm, at a high deposition temperature close to 1500°C. The deposition time is between 5 h and 15 h, resulting in deposition rates exceeding 100 µm / h, which are particularly well-suited to industrial production. The P-SiC is doped by adding nitrogen to the mixture. To obtain a sufficiently flat substrate, the patent proposes a process that varies the concentration of the SiC precursor during deposition, in order to reduce the excessively pronounced grain size gradient in the deposit. This process is proposed for nitrogen mass concentrations between 200 ppm (2.8 x 10¹⁹ atm / cm³) and 1000 ppm (1.38 x 10²⁰ atm / cm³). Above 1000 ppm, it is noted that an excessive concentration of nitrogen in P-SiC would generate significant defects in the crystals and a deformation of the substrate.

[0021] Thus, a high concentration of nitrogen dopant in the P-SiC material is potentially a limiting factor for obtaining good flatness, but it is desirable for obtaining low electrical resistivity. These contradictory tendencies must be taken into account when attempting to fabricate a P-SiC raw substrate by CVD with low resistivity (e.g., <10 mOhm.cm) and sufficient flatness to allow grinding of a P-SiC wafer by removing as little material as possible. With regard to the flatness of the raw substrate obtained by CVD, it must be borne in mind that grinding a surface as hard as SiC is a lengthy and expensive process, and furthermore, any material removed by grinding represents lost material.Indeed, the manufacturing cost of the P-SiC wafer must reach a sufficiently low level to be able to serve as a substrate combined with a thin film of polycrystalline SiC in power electronics applications.

[0022] According to the prior art, the nominal thickness of the finished P-SiC wafer is 350 µm for a nominal diameter of 150 mm. A thicker raw product (rough blank) is manufactured by a CVD deposition process on a graphite substrate. For economic reasons, once detached from the graphite, the P-SiC rough blank must not exceed a thickness of 1 mm; typically 750 µm and preferably 600 µm are targeted, in order to obtain a reasonable CVD deposition time and to reduce the thickness to be removed by grinding and polishing, to a maximum of 650 µm, typically 400 µm, and preferably 250 µm, respectively.

[0023] The warp of a 350 µm thick wafer with a six-inch diameter must be less than 50 µm after grinding and polishing to comply with microelectronics standards. To achieve this, an intermediate blank must first be prepared by grinding from the rough blank detached from the graphite. This intermediate blank will then serve as a starting point for preparing, by fine grinding followed by polishing, the P-SiC wafer onto which a single-crystal layer of SiC will subsequently be transferred. The difference between the initial thickness of the rough blank and the deformation measured on said rough blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the rough blank (see [Fig. 1]).

[0024] In the present invention, the inventors sought to optimize the fabrication of a raw SiC substrate having a high N-dopant content, typically greater than 5 x 10¹⁹ atoms / cm³, preferably greater than 10²⁰ atoms / cm³, to typically achieve a material resistivity of less than 15 mΩ·cm and preferably less than 10 mΩ·cm. The thermal conductivity of the material should typically be greater than 200 W / mK, but a value greater than 250 W / mK is preferred. m / K, despite a high N-dopant content which can affect thermal conductivity by generating additional crystalline defects detrimental to phonon propagation. We are also looking for a substrate with excellent surface homogeneity of grain size, and preferably a fine grain. Objects of the invention

[0025] It follows from the work carried out by the inventors of the present application that a massive plate of polycrystalline SiC (hereinafter referred to as "P-SiC") can be obtained by chemical vapor deposition (CVD) operating in a temperature range of about 1300 K to about 1800 K on a substrate comprising a graphite surface.In this process, which forms the first object of the present invention, a gas mixture is introduced into a heated chamber so as to create a gaseous phase comprising at least one gaseous precursor of silicon and / or carbon, at least one doping gas comprising at least one nitrogen atom, and a carrier gas. This gas mixture decomposes on the surface of the graphite substrate to form a layer of polycrystalline SiC on the graphite surface of the substrate. The process is characterized in that the temperature in the reactor is between 1450 K and 1650 K and the total partial pressure of the gaseous precursors is less than 350 mbar, and preferably less than 300 mbar. This deposition is carried out on the graphite surface of a substrate comprising a graphite surface; the substrate may be a graphite plate.This substrate, and more specifically this graphite plate, is advantageously circular, so as to allow the direct production of a circular SiC disk.

[0026] According to an advantageous embodiment, said gas phase comprises trichloromethylsilane as a silicon and carbon precursor, and preferably does not comprise any other silicon and / or carbon precursors. Said dopant gas is advantageously selected from the group consisting of: NH3, N2H4, N2, H2NCH3.

[0027] This product allows the deposition of a layer of polycrystalline silicon carbide (P-SiC) which can then be separated from the graphite surface on which it was formed; thus a P-SiC disc is obtained whose thickness can be reduced by grinding, then polishing both faces.

[0028] Thus, a polycrystalline SiC wafer can be produced, which represents another object of the present invention. This wafer can be a rough blank, which can then undergo grinding steps to become an intermediate blank for the fabrication of a polycrystalline SiC substrate suitable for receiving a transfer of a single-crystal SiC layer to form a wafer usable for the fabrication of a substrate for the deposition of integrated circuits. Said wafer, said rough blank, and said intermediate blank represent other objects of the present invention, as will be explained later. They advantageously have a microstructure and a particular crystallographic texture, as will be explained below.

[0029] Said polycrystalline SiC plate has a particular crystallographic texture, which can be obtained for specific doping and conductivity characteristics. Thus, a second object of the invention is a polycrystalline SiC plate, characterized in that: (i) its texture coefficient C422 is less than 30%, and (ii.a) its texture coefficient C220 is greater than 60% and preferably greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 70%; and preferably greater than 80%. Advantageously, its texture coefficient C422 is less than 20%, preferably less than 15%, and preferably less than 10%.

[0030] Advantageously, the electrical resistivity of this polycrystalline SiC plate is less than 20 mOhm.cm, preferably less than 15 mOhm.cm, and even more preferably less than 10 mOhm.cm, and / or its nitrogen content is greater than 5 x 10¹⁹ atoms / cm³, preferably greater than 1 x 10²⁰ atoms / cm³, and even more preferably greater than 1.5 x 10²⁰ atoms / cm³. As is customary in the field of microelectronic substrates, the doping level (in this case, the nitrogen content) can be determined by secondary ion mass spectrometry (SIMS).

[0031] A particularly preferred embodiment of this second object of the invention is a polycrystalline SiC plate, doped with nitrogen with a nitrogen content, measured by secondary ion mass spectrometry, greater than 5 x 1019 atoms / cm3, said plate having an electrical resistivity of less than 15 mOhm.cm and a preferred crystal orientation, said plate being characterized in that: (i) its texture coefficient C422 is less than 20%, and (ii.a) its texture coefficient C220 is greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 80%.

[0032] Said polycrystalline SiC plate typically has the shape of a circular disk. It is characterized by good flatness, and advantageously has either a diameter between 140 mm and 165 mm or a diameter between 185 mm and 210 mm; these two diameter ranges include the sizes currently common in the semiconductor industry, namely 6 inches and 8 inches.

[0033] Said polycrystalline SiC plate may be a rough blank obtained from a vapor deposition process. It may also be an intermediate blank for the manufacture of a wafer obtained by grinding such a rough blank. In one embodiment, the polycrystalline SiC plate according to the invention has a thickness of less than 550 µm, preferably less than 500 µm, more preferably less than 450 µm, and even more preferably between 355 µm and 420 µm; this embodiment is particularly suitable for plates with a diameter between 140 mm and 165 mm. In another embodiment, the SiC plate polycrystalline according to the invention has a thickness of less than 850 pm, preferably less than 800 pm, more preferably less than 750 pm, and even more preferably between 510 pm and 650 pm; this embodiment is particularly suitable for plates with a diameter between 185 mm and 210 mm.

[0034] In another embodiment, the polycrystalline SiC plate according to the invention has a diameter between 140 mm and 165 mm, a thickness between 350 µm and 450 µm, and a deformation characterized by a warp of less than 50 µm, preferably less than 40 µm, and even more preferably less than 30 µm. Its thickness is preferably between 350 µm and 400 µm. By way of example, said plate may have a thickness between 350 µm and 400 µm and a warp of less than 40 µm (and preferably less than 30 µm), or its thickness may be between 400 µm and 450 µm and its warp may then be less than 50 µm (and preferably less than 40 µm).

[0035] In yet another embodiment, the polycrystalline SiC plate according to the invention has a diameter between 185 mm and 210 mm, a thickness between 500 µm and 650 µm, and a deformation characterized by a warp of less than 70 µm, preferably less than 50 µm, and even more preferably less than 40 µm. Its thickness is preferably between 500 µm and 600 µm. By way of example, said plate may have a thickness between 500 µm and 600 µm and a warp of less than 50 µm (and preferably less than 40 µm), or its thickness may be between 600 µm and 650 µm and its warp may then be less than 70 µm (and preferably less than 50 µm). Figures

[0036] Figures 1 to 12 illustrate different aspects of the invention.

[0037] [Fig.1] schematically shows the measurement of the parameter called "Warp" which expresses a particular aspect of the flatness defect of a semiconductor wafer.

[0038] [Fig.2] shows an image obtained by scanning electron microscopy of backscattered electrons of a cross-section of a P-SiC layer obtained by a process according to Example 1.

[0039] [Fig.3] shows an image obtained by direct mode scanning electron microscopy, of a cross-section of a P-SiC layer similar to Example 1.

[0040] [Fig.4] shows an image obtained by scanning electron microscopy of backscattered electrons of a cross-section of a P-SiC layer obtained by a process according to Example 2.

[0041] [Fig.5] shows an image obtained by direct mode scanning electron microscopy, of a cross-section of a P-SiC layer similar to Example 2.

[0042] [Fig.6] shows an image obtained by scanning electron microscopy of backscattered electrons of a cross-section of a P-SiC layer obtained by a process according to Example 3.

[0043] [Fig.7] shows an image obtained by direct mode scanning electron microscopy, of a cross-section of a P-SiC layer similar to Example 3.

[0044] [Fig.8] shows an image obtained by scanning electron microscopy of backscattered electrons of a cross-section of a P-SiC layer obtained by a process according to Example 4.

[0045] [Fig.9] shows an image obtained by direct mode scanning electron microscopy, of a cross-section of a P-SiC layer similar to Example 4.

[0046] [Fig. 10] shows an image obtained by scanning electron microscopy of backscattered electrons of a cross-section of a P-SiC layer obtained by a process according to Example 5.

[0047] [Fig. 11] shows an image obtained by direct mode scanning electron microscopy, of a cross-section of a P-SiC layer similar to Example 5.

[0048] [Fig. 12] schematically and in a simplified manner shows a vertical cross-section through a reactor according to the invention which makes it possible to manufacture a blank for a polycrystalline SiC substrate according to the invention.

[0049] The following numerical references are used on [Fig. 12] and in the description:

[0050] 1: Reactor according to the invention

[0051] 2: Enclosure

[0052] 3: Reaction space

[0053] 4: Heating space

[0054] 5: Evacuation space

[0055] 6: Heating element

[0056] 7: Graphite susceptor

[0057] 8: Inlet of precursor gases

[0058] 9: Reaction gas outlet

[0059] 10: Outlet nozzle

[0060] 11: Injector

[0061] 12: Graphite discs (substrates) Detailed description

[0062] Those skilled in the art of semiconductor substrates for microelectronics are familiar with the various ways to characterize the overall flatness of wafers: these different parameters are known by the terms or acronyms Bow (the distance between the surface and the plane corresponding to the best fit to the center of the unfixed wafer, see ASTM F534 "Standard Test Method for Bow of Silicon Wafers" section 3.1.2), Warp (the sum of the maximum positive and negative deviations from the plane corresponding to the best fit for an unfixed wafer, see ASTM F1390 "Standard test Method for Measuring Warp on Silicon Wafers by Automated Non-Contact Scanning"), TTV (Total Thickness Variation, i.e., the difference between the maximum and minimum thickness values ​​for a fixed wafer, see ASTM F657 "Standard Test Method for Measuring Warp and Total Thickness Variation on Silicon Slices and Wafers by a Non-contact Scanning Method"), TIR (Total Indicated Reading, i.e., the sum of the maximum positive and negative deviations from the plane corresponding to the best fit for a fixed wafer), SRAD (Spherical Reference Measurement, expressing a radius of curvature for the sphere corresponding to the best fit); other acronyms express parameters to characterize the local flatness of wafers, in particular: LFPD (Local Focal Plane Deviation, i.e.the maximum distance between the wafer surface and the plane corresponding to the best fit (above or below the unfixed wafer surface), for a given area) and LTV (Local Thickness Variation, i.e. the difference between the maximum and minimum thickness values ​​of the unfixed wafer, for a given area).

[0063] In the context of the present invention, the flatness of the wafers is characterized by the parameter commonly called "Warp". This parameter refers to the algebraic difference of the wafer's deviations from a reference plane. Figure 1 schematically illustrates the determination of this parameter from a surface profile by the algebraic difference of the ordinates B and C of the disk placed on a base plane.

[0064] One could also determine a median plane from the surface profile (typically using an algorithm implementing a least-squares method) and calculate the warp from the deviations from the median plane, which gives the same result as long as the median plane is parallel to the base plane. If the median plane is not parallel to the base plane, then the measurement method with respect to the base plane is superior to the method with respect to the median plane.

[0065] We now describe the method according to the invention which makes it possible to solve the problem posed.

[0066] The process according to the invention uses the chemical vapor deposition (CVD) technique, carried out in a heated chamber. The process involves a gaseous mixture comprising at least one silicon precursor gas (such as a silane or a chlorosilane) and / or at least one carbon precursor gas (such as an alkane or an alkene), and / or at least one silicon and carbon precursor gas (such as methyltrichlorosilane, abbreviated MTCS), and at least one dopant gas comprising nitrogen (for example, NH3, N2H4, or N2). This dopant gas may also be a carbon and / or silicon precursor (for example, an amine such as H2NCH3). These gases may be diluted in a carrier gas, which may be a gas reducing agent such as hydrogen and / or an inert gas such as argon.

[0067] By way of example, a gaseous composition for implementing the process according to the invention may comprise a carbon precursor, a silicon precursor, a doping gas, and the carrier gas. Another example is a gaseous composition that comprises a silicon and carbon precursor, a silicon precursor, a carbon precursor, a doping gas, and the carrier gas.

[0068] This gaseous mixture is admitted into a high-temperature reactor where the precursor gases are decomposed and react at the surface to form the 3C-SiC polytype. This material is particularly well-suited for combination with a single-crystal SiC layer due to its mechanical and thermal resistance properties, its compatibility with thermal expansion, and its purity. Furthermore, it can be doped with nitrogen to very high levels, typically 1020 atoms / cm³, and exhibit a resistivity well below 20 Ohm·cm, without any degradation of substrate quality that would be detrimental to the manufacture of power components. Finally, it is a material capable of withstanding the subsequent high-temperature processes that the wafer will undergo during the fabrication of the electronic component.

[0069] The reactor temperature during CVD deposition of SiC should be between approximately 1300 K and approximately 1800 K, and preferably between approximately 1350 K and approximately 1700 K, more preferably between approximately 1400 K and approximately 1650 K, and even more preferably between approximately 1450 K and approximately 1650 K. The total pressure in the reactor advantageously does not exceed 350 mbar, and preferably does not exceed 300 mbar.

[0070] In an advantageous embodiment of the P-SiC wafer manufacturing process according to the invention, a substrate is depositioned by CVD onto a graphite surface. Advantageously, said substrate is a fine-grained, purified isostatic graphite substrate, to avoid any contamination and outgassing of impurities during deposition. For example, to obtain a wafer with a diameter of 150 mm, the deposition is carried out on a disc-shaped graphite cylinder with a nominal diameter approaching 150 mm and a thickness greater than 2 mm to ensure sufficient flatness of the substrate. The reactor may comprise a plurality of these discs, which may have the same or different diameters. Preferably, both faces of the discs have a flatness <15 µm, obtained by sufficiently precise machining.The coefficient of thermal expansion of isostatic graphite is judiciously chosen to be compatible with the SiC layer during cooling after deposition. A substrate marketed by MERSEN under the designation "grade 2303" can be used.

[0071] We now describe the sequence of events in a typical embodiment of the process according to the invention, and first, in relation to [Fig. 12], we describe by way of example a reactor in which the process according to the invention can be carried out. The process according to the invention takes place in a reactor 1 of a particular type. It comprises a reaction chamber 2, which contains a reaction space 3, a heating space 4, and a reaction gas exhaust space 5. Said chamber 2 is designed to be able to achieve low pressures down to a minimum of a few tens of millibars by pumping the gases to an effluent treatment device (not shown in the figure). The precursor gases are admitted into the reaction space 3 of reactor 1 through a plurality of injectors 11 supplied by a gas line 8 referred to as the precursor gas inlet. The reaction gases leave the reaction space 3 into the exhaust space 5, from where they are drawn through an outlet nozzle 10 into the gas line 9 referred to as the reaction gas outlet. The heating space 4 comprises a plurality of heating elements 6, typically solenoids.Graphite cylinders or discs 12, also called substrates here, are loaded into enclosure 2; for simplicity, [Fig. 12] does not show the supports which hold said substrates 12 in reactor 1.

[0072] The deposition chamber 2 is heated by induction of a magnetic field in a graphite susceptor 7 inside which the precursor gases (for example silanes, alkanes and / or methyl-chlorosilanes), carrier gases (for example hydrogen and / or argon), and dopant gas (for example NH3, amines and / or N2) will circulate. The graphite substrates 12 are in thermal equilibrium inside the reaction space 3 heated by the susceptor 7 at a temperature generally between 1300 K and 1700 K (measured by a thermocouple), and more preferably between 1350 K and 1650 K. The gas mixture is introduced by nozzles or injectors 11 allowing a homogeneous distribution of the gas flow in the chamber 2. In this temperature range, the deposition rates can vary over fairly wide ranges, from pm / h to more than 100 pm / h.The total partial pressure of said gaseous precursors is advantageously less than 350 mbar, and preferably less than 300 mbar.

[0073] To achieve a minimum P-SiC deposition thickness of approximately 600 µm, the gas injection time can vary from a few hours to several tens, or even hundreds, of hours depending on the conditions chosen. The control parameters indicated above can be adjusted to obtain the product according to the invention, as will be explained in greater detail with reference to the examples. Thus, it is possible to obtain high-quality P-SiC wafers under economically satisfactory conditions, enabling their use in electronic applications as a substitute for single-crystal SiC produced by the traditional PVT process.

[0074] When the desired coating thickness on the surface of the graphite substrate 12 is reached, the injection of precursor gases into the furnace is stopped and the chamber is cooled to ambient temperature for unloading. The graphite discs 12 coated by A thick layer of SiC deposit is then machined and subsequently oxidized in air, typically at 900°C, to remove any graphite residue. A raw SiC disk is recovered for each face.

[0075] The deformation of the rough disc is measured using a confocal white light sensor that scans the surface of the SiC disc that was in contact with the graphite. To perform this measurement, the CVD-coated side of the disc is placed on a support. The difference between the maximum and minimum elevation of the surface scanned by the sensor relative to the support plane of the measuring tool is measured. The graphite-facing surface was a flat reference before being detached from the graphite. After detachment, this surface becomes warped due to the relaxation of stresses in the deposited layer. This warped surface can be interpolated by a median plane using the least-squares method. If this median plane is parallel to the support plane, the deformation measurement is equal to the warp. This deformation measurement method generally overestimates the warp measurement.

[0076] If the deformation measurement on the rough blank is in accordance with the objective set below, it can be ground to a thickness slightly greater than the nominal 350 pm and to obtain a final warp of less than 50 pm for a standard size wafer of 6 inches.

[0077] Indeed, it is first necessary to prepare an intermediate blank by grinding from the rough blank detached from the graphite. This intermediate blank will then serve as a starting point for preparing, by fine grinding followed by polishing, the P-SiC wafer onto which a single-crystal layer of SiC will subsequently be transferred. The difference between the initial thickness of the rough blank and the deformation measured on said rough blank must not be less than the thickness of the intermediate blank. This means that the volume of the ground intermediate (cylindrical) blank must be included in the volume of the rough blank (see [Fig. 1]). The grinding step will also aim to remove a sufficient thickness on the side of the face in contact with the graphite. This removes the initial crystal growth zone, thus eliminating the strong stresses generated by this depositional evolution.

[0078] Over the temperature range of 1373 K to 1673 K, the orientation of P-SiC crystal growth was studied by So and Chun in the article “Growth and structure of Chemical vapor deposited Silicon Carbide from methyltrichlorosilane and hydrogen in the temperature range of 1100 to 1400°C” (Journal of Vacuum Science & Technology A 6, 5 (1988)). Figure 4 of this document shows, for this temperature range, a transition in the texture coefficient from the preferred (111) orientation at low temperature to the (220) orientation at high temperature. The texture coefficient was measured using the method described in the publication by G.B. Harris (1952) “X. Quantitative measurement of preferred orientation in rolled uranium bars.” , published in the journal Philosophical Magazine Series 7, 43:336, 113-123.

[0079] The product obtained by the process according to the invention not only exhibits excellent flatness (characterized by a low value of the Warp parameter), low electrical resistance and good thermal conductivity, but also exhibits on its high surface (i.e. the surface far from the growth substrate, obtained by material removal by polishing) a small grain size and good grain size homogeneity. Examples

[0080] Examples 1 to 5 illustrate certain aspects of the invention, but do not limit its scope.

[0081] In these examples, diffraction peaks were collected by a PANalytical X'Pert PRO MPD type X-ray diffractometer using the 0-20 method over an angle range from 10° to 135° (scale 20). Within this range, the ten diffraction peaks listed in Table 1, ranked according to increasing Miller indices (hkl), were considered for SiC 3C:

[0082] Table 1: Diffraction peaks taken into account hkl Peak Position 20 [°] Theoretical Intensity I [%] (Source ICDD) 111 [34.940° - 36.345°] 100,200 [41.230° - 41.584°] 23,220 [59.494° - 60.452°] 57,311 [71.167° - 72.348°] 48,222 [75.303° - 75.749°] 10,400 [89.575° - 90.298°] 12,331 [100.250° - 101.537°] 25,420 [104.045° - 104.885°] 13,422 [119.276° - 120,418°] 14,511 [132,367° - 134,021°] 15

[0083] A texture coefficient Chki (for N=10pics) is calculated from the intensity of the peak I^iproportional to the area under the peak of the sample and the theoretical intensity IOhki of a powder which can be obtained from the theoretical % published by 1TCDD (International Centre for Diffraction Data).

[0084] Chki = (Ihki / Io hki) / (1 / N xS (Ihkl / lohkl))-

[0085] The texture coefficient in this case varies over a range from 0 to 10. We can also express it as a percentage. It allows us to quantify the average preferential orientation of the crystallites in the deposited layer relative to the normal to the surface of the sample.

[0086] In these examples, the carbon source and the silicon source were the same molecule, namely methyl trichlorosilane (abbreviated MTCS). The nitrogen-source dopant gas was NH3. By modifying a few key parameters of the CVD process (temperature, precursor partial pressure, % dopant gas), it is possible to change the orientation and texture of the deposited layer. This will impact the intrinsic stress gradient of the deposit, allowing a warp on the rough blank to be obtained that meets the objective.

[0087] Example 1: Coarse conical grain texture with preferred orientation (422)

[0088] A 650 pm layer was deposited on a graphite substrate by operating at a temperature temperature of 1550 K, a partial pressure of 23 mbar of MTCS and a mole fraction of NH3 of 3%.

[0089] Figure 2 shows the backscattered electron scanning electron microscopy image of a cross-section of the obtained P-SiC layer; the substrate is at the bottom and the black bar represents a length of 100 pm. At the bottom is the texture triangle on which, for information purposes, certain facets marked with four different white symbols are indicated. Figure 3 shows a similar image obtained by direct scanning electron microscopy at a higher magnification; the white bar represents a length of 20 pm. In both of these micrographs, the substrate is at the bottom.

[0090] The observed orientation is a preferentially oriented (422) texturing with texture coefficients gathered in Table 2:

[0091] Table 2: Texture coefficients of P-SiC according to example 1 C111+C222+C511 C220 C422 9% 1% 80%

[0092] Figures 2 and 3 show a continuous increase in grain diameter over the first 200 microns. This increase in grain size can be evaluated for each ordinate of the coordinate system by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0093] The resulting layer contains a nitrogen concentration, measured by SIMS, of 8 x 10¹⁹ nitrogen atoms per cm³ and an electrical resistivity of 16 mΩ·cm, measured by the four-point method. The thermal conductivity of the layer was deduced from the result of a thermal diffusivity measurement using the laser flash method. The value obtained was 210 W / m / K.

[0094] Despite physical properties conforming to the intended objective, the deformation measured on the raw disk is much greater than the intended objective. Out of a total of 16 disks For products, the average deformation is 850 pm with a standard deviation of 140 pm. It will not be possible to produce a P-SiC wafer by grinding from a raw disk with a thickness less than 1000 pm.

[0095] After several depositions under these conditions, the observed texturing is very preferentially oriented (422) with a texture coefficient C422 >75%.

[0096] Example 2: Oriented fine grain texture (111)

[0097] A 650 pm layer was deposited on a graphite substrate at a temperature of 1550 K, a partial pressure of 8 mbar MTCS, and an NH3 molar fraction of 6%. Figures 4 and 5 are micrographs analogous to Figures 2 and 3 of Example 1 (the white bar in [Fig. 5] corresponds to a length of 50 pm).

[0098] The observed orientation is a preferentially oriented (111) texturing with texture coefficients gathered in Table 3.

[0099] Table 3: Texture coefficients of P-SiC according to example 2 C111+C222+C511 C220 C422 86% 1% 8%

[0100] Figure 5 shows grains whose size does not increase as the P-SiC layer grows; these grains are in the form of thin rods, highly oriented along the normal to the substrate plane. The grain size can be estimated for each coordinate point by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0101] The resulting deposit contains a nitrogen concentration, measured by SIMS, of 7 x 10²⁰ nitrogen atoms per cm³ and an electrical resistivity of 1.1 mΩ·cm, measured by the four-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. A value of 52 W / m / K is obtained, which is well below the target. The fine-grained structure appears to significantly limit the thermal conductivity.

[0102] The deformation measured on the raw disk is, however, very good. Over a total of 16 disks produced, the average deformation is 190 pm with a standard deviation of 72 pm. This would make it possible to produce P-SiC wafers by grinding from a raw disk less than 1000 pm thick at a reasonable cost.

[0103] After several depositions under these conditions, the observed orientation is a highly preferentially oriented (111) texturing with the sum of texture coefficients C111+C222 +C5n>80%.

[0104] Example 3: Oriented fine grain texture (220)

[0105] A 650 pm layer was deposited on a graphite substrate by operating at a temperature of 1550 K, a partial pressure of 16 mbar of MTCS and a mole fraction of NH3 of 4%.

[0106] Figures 6 and 7 are micrographs analogous to figures 2 and 3 of example 1.

[0107] The observed orientation is a preferentially oriented (220) texturing with texture coefficients gathered in Table 4:

[0108] Table 4: Texture coefficients of P-SiC according to example 3 C111+C222+C511 C220 C422 2% 93% 3%

[0109] The resulting deposit contains a nitrogen concentration, measured by SIMS, of 1.8 x 10²⁰ nitrogen atoms per cm³ and an electrical resistivity of 5 mΩ·cm, measured by the four-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. A value of 270 W / m / K is obtained, which is above the target. Despite the small grain size, the tree-like texture appears to promote good thermal conductivity, even with high doping.

[0110] The deformation measured on the raw disc is also very good. Over a total of 16 discs produced, the average deformation is 210 µm with a standard deviation of 82 µm. This makes it possible to produce P-SiC wafers by grinding from a raw disc less than 1000 µm thick at a reasonable cost.

[0111] After several depositions under these conditions, the observed texture is highly preferentially oriented (220) with the texture coefficient C220 > 90% and C422 < 10%

[0112] Example 4: Texture with predominantly fine grain oriented (220) mixed with coarse grain oriented (422)

[0113] Figures 8 and 9 are micrographs analogous to figures 2 and 3 of example 1.

[0114] An 800 pm layer was deposited on a graphite substrate at a temperature of 1600 K, a partial pressure of 16 mbar MTCS, and an NH3 molar fraction of 4%. A preferentially (220) oriented texture is observed, exhibiting large grains preferentially (422) oriented according to the texture coefficients summarized in Table 5:

[0115] Table 5: Texture coefficients of P-SiC according to example 4 C111+C222+C511 C220 C422 8% 65% 18%

[0116] Figure shows two populations of grains of different sizes. The oriented grains (220) have a diameter between 1 pm and 10 pm. The other predominantly oriented grains (422) have a conical shape whose diameter can increase up to 50 µm. Grain size can be assessed for each coordinate system by counting the number of intersections of a horizontal line with a constant ordinate and grain boundaries on the EBSD image. Here, the average grain size increases rapidly, as large grains remain in the minority in the texture.

[0117] The resulting deposit contains a nitrogen concentration, measured by SIMS, of 2.2 x 10²⁰ nitrogen atoms per cm³ and an electrical resistivity of 3.3 mΩ·cm, measured by the four-point method. The thermal conductivity of the layer is deduced by a thermal diffusivity measurement using the laser flash method. A value of 215 W / m / K is obtained, which is above the target.

[0118] The deformation measured on the raw disc is also very good. Over a total of 16 discs produced, the average deformation is 235 µm with a standard deviation of 90 µm. This makes it possible to produce P-SiC wafers by grinding from a raw disc less than 1000 µm thick at a reasonable cost.

[0119] After several depositions under these conditions, the observed texture remains preferentially oriented (220) with the texture coefficient C220 > 60% and C422 < 20%

[0120] Example 5: Texture with predominantly coarse grains oriented (422) mixed with a fine texture of small grains oriented (220)

[0121] An 800 pm layer was deposited on a graphite substrate by operating at a temperature of 1600 K, a partial pressure of 16 mbar MTCS and an NH3 mole fraction of 6%.

[0122] Figures 10 and 11 are micrographs analogous to figures 2 and 3 of example 1.

[0123] A preferentially oriented (422) texture is observed, exhibiting very large grains oriented according to the texture coefficients gathered in Table 6:

[0124] Table 6: Texture coefficient of P-SiC according to example 5 C111+C222+C511 C220 C422 20% 7% 54%

[0125] The figure shows very large grains oriented predominantly (422) or secondarily (111), with a conical shape and diameters up to 100 pm. A few small grains (220) smaller than 10 pm are very rare. The figure shows a continuous increase in grain diameter over the first 500 microns. This increase in grain size can be evaluated for each ordinate of the coordinate system by counting the number of intersections of a horizontal line of constant ordinate with the grain boundaries on the EBSD image.

[0126] The resulting deposit contains a nitrogen concentration measured by SIMS of 6.8 x 10²⁰ nitrogen atoms per cm³ and an electrical resistivity measured at 0.9 mΩ·cm by the four-point method, well below the upper limit targeted. It is also deduced the thermal conductivity of the layer by measuring thermal diffusivity using the laser flash method. A value of 130 W / m / K is obtained, which is below the target.

[0127] Out of a total of 16 discs produced, the average deformation is 650 pm with a Standard deviation of 178 pm. It will not be possible to produce a P-SiC wafer by rectification from a raw disk with a thickness of less than 1000 pm.

[0128] After several depositions under these conditions, the observed texture remains preferentially oriented (422) with the texture coefficient C422 > 50% and Chi+C222+C5ii > 15% and C22o < 10% Comparison of examples 1 to 5

[0129] The main results obtained in relation to the examples presented above are summarized in Table 7 below:

[0130] Table 7: Main results from examples 1 to 5 above Ex Temp [K] MTCS [mbar] nh3 [%] %c 220 %cm+ C222+C511 %c 422 N [atm / cm3] Res [mOhm. cm] TC [W / m / K] Deformation 1 1550 23 3 1 9 80 8xl019 16 210 NOK 2 1550 8 6 1 86 8 7 xlO20 1.1 52 OK 3 1550 16 4 93 2 3 1.8 xlO20 5 270 OK 4 1600 16 4 65 8 18 2.2xl020 3.3 215 OK 5 1600 16 6 7 20 54 6.8xl020 0.9 130 NOK

[0131] Examples 2, 3, and 4 show a texture highly oriented along the two possible axes (111) and (220) (C220 > 60% or C111+C222+C511 > 80%). It consists of a succession of fine, elongated grains. The grain diameter stabilizes at a maximum of 10 pm for a length that can reach up to 100 pm.

Claims

Claims

1. Polycrystalline SiC plate having a preferential crystalline orientation, said plate being characterized in that: (i) its texture coefficient C422 is less than 30%, and (ii.a) its texture coefficient C220 is greater than 60%, and preferably greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 70%, and preferably greater than 80%.

2. Polycrystalline SiC plate according to claim 1, characterized in that its electrical resistivity is less than 20 mOhm.cm, preferably less than 15 mOhm.cm, and even more preferably less than 10 mOhm.cm.

3. Polycrystalline SiC plate according to any one of claims 1 to 2, characterized in that it is doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy, greater than 5 x 1019 atoms / cm3, preferably greater than 1 x 1020 atoms / cm3, and even more preferably greater than 1.5 x 1020 atoms / cm3.

4. Polycrystalline SiC plate according to any one of claims 1 to 3, characterized in that its texture coefficient C422 is less than 20%, preferably less than 15%, and even more preferably less than 10%.

5. Polycrystalline SiC plate according to any one of claims 1 to 4, doped with nitrogen with a nitrogen content, measured by secondary ion mass spectroscopy, greater than 5 x 1019 atoms / cm3, said plate having an electrical resistivity of less than 15 mOhm.cm and a preferential crystalline orientation, and said plate being characterized in that: (i) its texture coefficient C422 is less than 20%, and (ii.a) its texture coefficient C220 is greater than 60%, and preferably greater than 80%, or (ii.b) the sum of the texture coefficients C111+C222+C511 is greater than 80%.

6. Polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is a raw blank resulting from a vapor deposition process.

7. A polycrystalline SiC plate according to any one of claims 1 to 5, characterized in that it is an intermediate blank for the manufacture of a wafer obtained by grinding a raw blank according to claim 6.

8. Polycrystalline SiC plate according to claim 7, characterized in that its thickness is less than 550 pm, preferably less than 500 pm, more preferably less than 450 pm, and even more preferably between 355 pm and 420 pm.

9. Polycrystalline SiC plate according to any one of claims 1 to 8, characterized in that it has a diameter of between 140 mm and 165 mm, a thickness of between 350 pm and 450 pm and a deformation characterized by a Warp of less than 50 pm, preferably less than 40 pm and even more preferably less than 30 pm.

10. Polycrystalline SiC plate according to claim 9, characterized in that it has a thickness of between 350 pm and 400 pm.

11. Polycrystalline SiC plate according to any one of claims 1 to 7, characterized in that it has a diameter of between 185 mm and 210 mm, a thickness of between 500 pm and 650 pm and a deformation characterized by a Warp of less than 70 pm, preferably less than 50 pm and even more preferably less than 40 pm.

12. Polycrystalline SiC plate according to claim 11, characterized in that it has a thickness of between 500 pm and 600 pm.

13. Polycrystalline SiC plate according to any one of claims 1 to 13, characterized in that it has been obtained by a CVD process.

14. A method of manufacturing a polycrystalline SiC plate according to any one of claims 1 to 13 comprising a step of chemical vapor deposition of a layer of polycrystalline SiC on the graphite surface of a substrate (12) comprising a graphite surface, wherein a gas mixture is introduced into a heated enclosure (2) so as to create a gas phase comprising: - at least one gaseous precursor of silicon and / or carbon, - at least one doping gas comprising at least one nitrogen atom, - a carrier gas, said gas mixture decomposing on the surface of said graphite substrate (12) to form a layer of polycrystalline SiC on said graphite surface of said substrate, and said method being characterized in that the temperature in said heated enclosure (2) is between 1450 K and 1650 K and the total partial pressure of said gaseous precursors is less than 350 mbar, and preferably less than 300 mbar.

15. A method according to claim 14, characterized in that said gas phase comprises trichloromethylsilane, and preferably does not comprise other precursors of silicon and / or carbon.

16. Method according to any one of claims 14 and 15, characterized in that said doping gas is selected from the group formed by: NH 3, n2h4, n2, h2nch3.

Images