INTEGRATED CIRCUIT COMPRISING A CIRCUIT FOR ADAPTING THE VOLTAGE SUPPLIED TO THE GATE OF A POWER TRANSISTOR

Abstract

The invention relates to an integrated circuit comprising: an enhancement power transistor (P2), and a circuit for adapting the voltage supplied to the gate of said enhancement power transistor, said adaptation circuit comprising at least one branch (101) connected between an input terminal (INPUT) and the second terminal (SOURCE), said branch comprising a depletion head transistor (M1), a depletion tail transistor (M2) connected to a first dipole (R1), a connecting quadrupole (10) and an enhancement foot transistor, the source of which is connected to the second terminal (SOURCE) and the gate of which is connected to its drain, said drain being connected to a second dipole (15), said driving circuit being connected, by the source of the head transistor (M1), to the gate of the power transistor (P2). Figure for the abstract: Fig 3

Description

Title of the invention: INTEGRATED CIRCUIT COMPRISING A CIRCUIT FOR ADAPTING THE VOLTAGE SUPPLIED TO THE GATE OF A POWER TRANSISTOR Technical field

[0001] The invention relates to the field of power electronics.

[0002] The invention relates in particular to a circuit for adapting the voltage supplied to the gate of the power transistors.

[0003] The invention advantageously makes it possible to drive the gate of the power transistors with higher voltages than in the state of the art, without damaging the power transistors. The invention further proposes a more robust and compact adaptation circuit than the circuits of the prior art. STATE OF THE ART

[0004] Power electronics is a branch of electronics dedicated to high-power energy transfers, for which it is important to minimize energy losses. It is mainly based on the use of controlled power switches. To do this, many switches in Silicon technology (IGBT, MOSFET) as well as wide bandgap semiconductor components (SiC, GaN) can be used. The transistors can be controlled by a driver circuit. The purpose of this driver circuit is to control the charging and / or discharging of the gate of the power component in order to allow changes of state of the power transistor.

[0005] Generally, the gate of the transistors is limited in the voltage values ​​that it can be applied without being damaged. Typically, depending on the models of GaN transistors, this voltage can be a maximum of 3, 6 or 9V.

[0006] The drivers, for their part, can provide voltages between 6 and 20V. In order to adapt the voltage provided by the driver, an adaptation circuit can be interposed between the driver and the gate of the power transistor.

[0007] To do this, it is possible to use circuits formed from discrete components such as those shown in [Fig.l].

[0008] Typically, the adaptation circuit 200 of the prior art receives at input INPUT a pulse width modulation signal, alternating between a high state and a low state, also called PWM signal or “Pulse-width modulation” in the English literature. The input INPUT is connected to a first interconnection point A1 of three branches of the adaptation circuit 200.

[0009] A first branch comprises a resistor R4 connected in series with the cathode of a Schottky diode D4, whose anode is connected to a second interconnection point A2.

[0010] A second branch, mounted in parallel with the first branch, comprises a resistor R3.

[0011] The third branch comprises, among other things, two Schottky diodes D2, D3. The first Schottky diode D2 is connected to the first interconnection point A1 by its cathode, while the second diode D3 is connected to the first interconnection point A1 by its anode. The cathode of the second Schottky diode D3 is connected, on the one hand, to a capacitor C1 and on the other hand to the cathode of a Zener diode D1, the capacitor C1 and the Zener diode D1 being connected in parallel. The anode of the first diode D2 is connected to a resistor R2, the other terminal of which is connected, on the one hand, to ground and on the other hand to the anode of the Zener diode D1 and to the second terminal of the capacitor C1.

[0012] The adaptation circuit 200 supplies the gate of a power transistor P2.

[0013] Such a circuit has the disadvantage of comprising a large number of components and consequently of occupying a large surface area, which does not allow the circuit to be integrated into spaces with reduced dimensions.

[0014] Another solution of the prior art consists of using an integrated circuit, such as that of patent US 2020 / 0357906 illustrated in [Fig.2].

[0015] The integrated circuit 300 also receives a pulse width modulated signal as input. The input is connected to the drain of a transistor T1. The gate of the transistor T1 is connected to the cathode of a Zener diode D7, the anode of which is connected to ground. A resistor R7 is connected between the drain and the gate of the transistor T1. The source of the transistor T1 is connected to the gate of a power transistor whose voltage is to be regulated.

[0016] This circuit is commonly called a "clamp circuit" in English literature. Thanks to the presence of the Zener diode D7, it allows the voltage delivered to the gate of the power transistor, not shown in the figure, and connected to the point called "clamped signal", to be limited.

[0017] Although this circuit is more compact than that of [Fig.l], it is very sensitive to temperature variations and variations in the manufacturing parameters of the transistors, also called “process corners” in the English literature.

[0018] The problem that the invention aims to solve is to provide an adaptation circuit that is more compact than the circuits of the prior art and whose sensitivity to temperature variations and to variations in the manufacturing parameters of the transistors is limited. Statement of the invention

[0019] To solve this problem, the Applicant has developed an integrated circuit comprising: - an enhancement-mode power transistor whose drain is connected to a first terminal of the integrated circuit and whose source is connected to a second terminal of the integrated circuit, and - a circuit for adapting the voltage supplied to the gate of an enhancement power transistor comprising at least one branch connected between an input adapted to receive a signal capable of adopting a low state and a high state, and the second terminal.

[0020] This branch includes: - a depletion head transistor, whose drain is connected to the input, - a depletion tail transistor whose source is connected to one terminal of a first dipole, and whose gate is connected to the second terminal of the first dipole, - a connecting quadrupole whose first terminal is connected to the gate of the head transistor, whose second terminal is connected to the source of the head transistor, whose third terminal is connected to the source of the tail transistor and whose fourth terminal is connected to the drain of the tail transistor, and - an enhancement-mode foot transistor whose source is connected to the second terminal and whose gate is connected to its drain, said drain being connected to a second terminal of a second dipole, whose first terminal is connected to the second terminal of the first dipole.

[0021] Said adaptation circuit is connected, by the source of the head transistor, to the gate of the power transistor.

[0022] According to the invention, a signal capable of adopting a low state and a high state is, for example, a pulse width modulated signal.

[0023] Such an adaptation circuit has very few components compared to the prior art of [Fig.l]. It is therefore easier to integrate into integrated circuits. In addition, fewer parasites, linked to the interactions of the components between them, appear on the control signal of the power transistor, due to the limited number of components. In addition, the circuit can be described as quasi-passive, in the sense that it only has one input connected to a driver and one output connected to the gate of a power transistor, and that it does not require any other source of energy than that provided by the driver to adapt the voltage.

[0024] Furthermore, it is known that depletion-mode transistors have a negative threshold voltage, and enhancement-mode transistors have a positive threshold voltage.

[0025] By observing the threshold voltages of the enhancement-mode and depletion-mode transistors during variations in the manufacturing parameters, it is sometimes possible to compensate for the effects of these variations on the performance of the circuit using its transistors.

[0026] Thus, for the circuit of the invention, an enhancement transistor makes it possible to compensate for a pair of depletion transistors when the lower part and the upper part of the circuit are combined.

[0027] The direct consequence is that fluctuations linked to variations in temperature and variations in the manufacturing process of a given transistor are compensated by the presence of the other transistors in the circuit.

[0028] The circuit is therefore more robust than the circuits of the prior art.

[0029] According to a first embodiment, the connecting quadrupole mentioned above consists of two short circuits respectively connecting the first and third terminals and the second and fourth terminals.

[0030] Advantageously, the second dipole is then a short circuit.

[0031] This embodiment is the simplest. The circuit comprises only two depletion transistors, one enhancement transistor and one dipole, i.e. four components in total. Such a circuit is therefore particularly easy to implement and integrate into integrated circuits.

[0032] The number of enhancement transistors and the number of depletion transistors is chosen as a function of the maximum voltage value that one wishes to apply to the gate of the enhancement power transistor.

[0033] Thus, the adaptation circuit of this first embodiment delivers a maximum voltage of 3V.

[0034] According to a second embodiment, the connecting quadrupole comprises two depletion transistors: a high transistor and a low transistor, the source of the high transistor being connected to the drain of the low transistor and to the first terminal of the connecting quadrupole, the drain of the high transistor being connected to the second terminal of the connecting quadrupole, the gate of the low transistor being connected to the third terminal of the connecting quadrupole and the gate of the high transistor and the source of the low transistor being connected to the fourth terminal of the connecting quadrupole.

[0035] Advantageously, the second dipole then comprises an enhancement transistor whose source is connected to the second terminal of the second dipole and whose gate is connected to its drain, said drain being connected to the first terminal of the second dipole.

[0036] In this embodiment, the circuit then comprises two enhancement transistors, the threshold voltages of which compensate with the two pairs of depletion transistors.

[0037] The adaptation circuit of this second embodiment then delivers a maximum voltage of 6V.

[0038] According to a third embodiment, the connecting quadrupole is made up of n elementary quadrupoles, with n > 1, each elementary quadrupole comprising two depletion transistors: a high transistor and a low transistor, the source of the high transistor being connected to the drain of the low transistor and to a first terminal of the elementary quadrupole, the drain of the high transistor being connected to a second terminal of the elementary quadrupole, the gate of the low transistor being connected to a third terminal of the elementary quadrupole and the gate of the high transistor and the source of the low transistor being connected to a fourth terminal of the elementary quadrupole; the elementary quadrupoles being connected in series, with two consecutive elementary quadrupoles connected so that the first terminal of the elementary quadrupole is connected to the third terminal of the elementary quadrupole and the second terminal of the elementary quadrupole is connected to the fourth terminal of the elementary quadrupole;the first and second terminals of the elementary quadrupole forming the first and second terminals of the connecting quadrupole and the third and fourth terminals of the elementary quadrupole forming the third and fourth terminals. ;

[0039] Advantageously, the second dipole then comprises n enhancement transistors, each of said transistors having its gate connected to its drain, said transistors being connected in series, two consecutive transistors being connected by the source of one and the drain of the other and, the drain of the first transistor forming the first terminal of the second dipole and the source of the last transistor forming the second terminal of the second dipole.

[0040] According to the embodiments, the first dipole may for example be an enhancement transistor whose gate is connected to its drain. The transistor then behaves like a diode. Preferably, the first dipole is a resistor, which makes it possible to better compensate for variations within the circuit. The sizing of the transistor or the value of the resistor does not in principle have a significant impact on the value of the voltage reference. However, the sizing of these components can be adapted in order to limit the energy consumption of the adaptation circuit.

[0041] The adaptation circuit of this third embodiment then delivers a maximum voltage of 3V multiplied by n.

[0042] In order to increase the value of the current transmitted to the power transistor, it is possible to connect several branches as described previously in parallel.

[0043] The adaptation circuit then comprises m branches connected in parallel, each branch being connected by the source of its head transistor, to the gate of the power transistor. The current available at the output is thus increased by a ratio m, while maintaining the performance of the original branch. Description of figures

[0044] The manner of carrying out the invention, as well as the advantages which result therefrom, will emerge clearly from the description of the embodiments which follow, in support of the attached figures in which:

[0045] [Fig-1] is an electrical diagram of a prior art matching circuit comprising discrete components,

[0046] [Fig.2] is an electrical diagram of another adaptation circuit of the prior art, achievable in an integrated circuit,

[0047] [Fig.3] is an electrical diagram of the adaptation circuit of the invention according to a first embodiment,

[0048] [Fig.4] is an electrical diagram of a variant of the embodiment of [Fig.3],

[0049] [Fig.5] is an electrical diagram of the adaptation circuit of the invention according to a second embodiment,

[0050] [Fig.6] is an electrical diagram of the adaptation circuit of the invention according to a third embodiment,

[0051] [Fig.7] is an electrical diagram of the adaptation circuit of the invention according to a fourth embodiment,

[0052] [Fig.8] is an electrical diagram of the adaptation circuit of the invention according to a fifth embodiment,

[0053] [Fig.9] is an electrical diagram of the adaptation circuit of the invention according to a sixth embodiment, and

[0054] [Fig. 10] is a comparative graph between the input signal and the output signal of the circuit of the invention for different transistors whose manufacturing process varies. Detailed description of the embodiments

[0055] As illustrated in Figures 3 to 9, the integrated circuit of the invention comprises a matching circuit connected to the gate of an enhancement power transistor P2-P8. The integrated circuit has three terminals. An input terminal INPUT, a first terminal DRAIN connected to the drain of the enhancement power transistor P2-P8, and a second terminal SOURCE connected to the source of the enhancement power transistor P2-P8.

[0056] The adaptation circuit comprises at least one branch 101-108. Each branch comprises a head transistor M1, M11, M21, M31, M41, M51, M61, M71 whose drain is connected to the input terminal INPUT intended to receive a pulse width modulated signal, alternating between a high state and a low state. This signal is for example provided by a control circuit or "driver" in the English literature. The input signal INPUT can for example adopt a high state between 8 and 12 V and a low state equal to 0 V.

[0057] The source of the head transistor Ml, Mil, M21, M31, M41, M51, M61, M71 is connected to the gate of the enhancement power transistor P2-P8.

[0058] Each branch 101-108 of the adaptation circuit of the invention also comprises a tail transistor M2, M14, M26, M36, M44, M54, M64, M74.

[0059] The two head transistors M1, Mil, M21, M31, M41, M51, M61, M71 and tail transistors M2, M14, M26, M36, M44, M54, M64, M74 are connected to each other by a connecting quadrupole 10, 20, 30, 40.

[0060] In the first embodiment of Figures 3 and 4, the connecting quadrupole 10 corresponds to two short circuits. A first short circuit connects the terminals Q1 and Q3 of the connecting quadrupole 10 and the second short circuit connects the terminals Q2 and Q4 of the connecting quadrupole 10.

[0061] Thus, the head transistor M1 is connected, by its source, to the drain of the tail transistor M2 via the short circuit connecting the terminals Q2 and Q4. In addition, the source of the tail transistor M2 is connected to the gate of the head transistor M1 via the short circuit connecting the terminals Q1 and Q3.

[0062] In the second embodiment of [Fig. 5], the connecting quadrupole 20 comprises two depletion transistors M12, M13 in series: a high transistor M12 and a low transistor M13. The source of the high transistor M12 is connected to the drain of the low transistor M13 and to the first terminal Q1 of the connecting quadrupole 20. The first terminal Q1 is also connected to the gate of the head transistor M11. The drain of the high transistor M12 is connected to the second terminal Q2 of the connecting quadrupole 20. The second terminal Q2 is also connected to the source of the head transistor M11. The gate of the low transistor M13 is connected to the third terminal Q3 of the connecting quadrupole 20. The third terminal Q3 is also connected to the source of the tail transistor M14. Finally, the gate of the high transistor M12 and the source of the low transistor M13 are connected to the fourth terminal Q4 of the connecting quadrupole 20, the latter also being connected to the drain of the tail transistor M14.

[0063] In the fourth embodiment of [Fig.7], the connecting quadrupole 30 is made up of two elementary quadrupoles QEi, QEi+1 connected in series, that is to say that the third terminal QEi-3 of the first elementary quadrupole QEi is connected to the first terminal QEi+1-1 of the second elementary quadrupole QEi+1 and the fourth terminal QEi-4 of the first elementary quadrupole QEi is connected to the second terminal QEi+1-2 of the second elementary quadrupole QEi+1. Each elementary quadrupole QEi, QEi+1 comprises two depletion transistors M32-M35: a high transistor M32, M34 and a low transistor M33, M35. The source of each high transistor M32, M34 is connected to the drain of each low transistor M33, M35 and to a first terminal QEi-1, QEi+1-1 of each elementary quadrupole QEi, QEi+1.The drain of each high transistor M32, M34 is connected to a second terminal QEi-2, QEi+1-2 of each elementary quadrupole QEi, QEi+1, the gate of each low transistor M33, M35 is connected to a third terminal QEi-3, QEi+1-3 of each elementary quadrupole QEi, QEi+1 and the gate of each high transistor M32, M34 and the source of each low transistor M33, M35 are connected to a fourth terminal QEi-4, QEi+1-4 of . each elementary quadrupole QEi, QEi+1. The terminals QEi-1 and QEi-2 respectively form the terminals Q1 and Q2 of the connecting quadrupole 30 and the terminals QEi+1-3 and QEi+1-4 respectively form the terminals Q3 and Q4 of the connecting quadrupole 30.

[0064] In the third embodiment of [Fig.6], the connecting quadrupole 40 is made up of n elementary quadrupoles QEl-QEn, with n > 1. Each elementary quadrupole comprises two depletion transistors: a high transistor M22, M24 and a low transistor M23, M25, connected in the same way as for the elementary quadrupoles QEi, QEi+1 described with reference to [Fig.5]. The elementary quadrupoles QEl-QEn are connected in series, with two consecutive elementary quadrupoles QEi, QEi+1 connected so that the first terminal QEi+1-1 of the elementary quadrupole QEi+1 is connected to the third terminal QEi-3 of the elementary quadrupole QEi and the second terminal QEi+1-2 of the elementary quadrupole QEi+1 is connected to the fourth terminal QEi-4 of the elementary quadrupole QEi.The first and second terminals QE1-1, QEI-2 of the elementary quadrupole QEI form the first and second terminals Ql, Q2 of the connecting quadrupole 40 and the third and fourth terminals QEn-3, QEn-4 of the elementary quadrupole QEn form the third and fourth terminals Q3, Q4 of the connecting quadrupole 40.

[0065] The head and tail transistors are depletion transistors. They can belong to the category of GaN transistors or MOS transistors.

[0066] The tail transistor M2, M14, M26, M36, M44, M54, M64, M74 is connected by its source to one terminal of a first dipole. The gate of the tail transistor M2, M14, M26, M36, M44, M54, M64, M74 is connected to the second terminal of the first dipole. The first dipole may for example be a resistor RI, R11, R21, R31, R41, R51, R61, R71 as illustrated in Figures 3 and 5-9, or a diode. For example, the first dipole is an enhancement transistor M4, mounted as a diode, that is to say that its gate is connected to its drain, as illustrated in [Fig.4].

[0067] The second terminal of the first dipole is connected in series with a second dipole 15, 25, 35, 45.

[0068] In the first embodiment of Figures 3 and 4, the second dipole 15 corresponds to a short circuit.

[0069] In the second embodiment of [Fig.5], the second dipole 25 comprises an enhancement transistor M15 whose source is connected to the second terminal of the second dipole 25 and whose gate is connected to its drain. The latter is also connected to the first terminal of the second dipole 25.

[0070] In the fourth embodiment of [Fig.7], the second dipole 35 comprises 2 enhancement transistors M37, M38. Each transistor M37, M38 has its gate connected to its drain. The transistors M37, M38 are connected in series, that is to say the source of the first transistor M37 is connected to the drain of the second transistor M38. The drain of the first transistor M37 then forms the first terminal A3 of the second dipole 45 and the source of the second transistor M38 forms the second terminal A4 of the second dipole 45.

[0071] In the third embodiment of [Fig.6], the second dipole 35 comprises n enhancement transistors M27, M28. Each transistor M27, M28 has its gate connected to its drain. The transistors M27, M28 are connected in series, that is to say that two consecutive transistors M27, M28 are connected by the source of one and the drain of the other. The drain of the first transistor M27 then forms the first terminal A3 of the second dipole 35 and the source of the last transistor M28 forms the second terminal A4 of the second dipole 35.

[0072] The second terminal of the second dipole 15, 25, 35, 45 is connected to a non-linear component. In practice, the non-linear component is a foot transistor M3, M16, M29, M39. The foot transistor M3, M29, M39 is advantageously an enhancement transistor, the gate of which is connected to its drain. The foot transistor M3, M29, M39, M46, M56, M66, M76 is connected to the second terminal SOURCE, which is generally itself connected to ground, by its source.

[0073] The maximum voltage value supplied to the gate of the power transistor P2-P8 is determined by the number of enhancement transistors M3, M15, M16, M27-M29, M37-M39, M45, M46, M55, M56 in the circuit.

[0074] Thus, the first embodiment comprises a single enhancement transistor M3 and makes it possible to limit the voltage supplied to the gate of the power transistor P2 to a value substantially equal to 3V. The second embodiment comprises two enhancement transistors M15, M16 and makes it possible to limit the voltage supplied to the gate of the power transistor P4 to a value substantially equal to 6V. The fourth embodiment comprises three enhancement transistors M37-M39 and makes it possible to limit the voltage supplied to the gate of the power transistor P6 to a value substantially equal to 9V. The third embodiment comprises n enhancement transistors M37-M39 and makes it possible to limit the voltage supplied to the gate of the power transistor P5 to a value substantially equal to n times 3V.

[0075] According to the fifth and sixth embodiments illustrated in Figures 8 and 9, it is possible to connect two identical branches 101-108 in parallel in order to increase the signal current supplied to the gate of the power transistor P2-P8, while maintaining an identical voltage. Thus, the fifth and sixth embodiments comprise two branches 105-108 each comprising two enhancement transistors M45, M46, M65, M66 and make it possible to limit the voltage supplied to the gate of the power transistor P7, P to a value substantially equal to 6V.

[0076] Thus, in the case of a circuit comprising only one branch, the current flowing in the circuit from the INPUT input to the gate of the power transistor to be en- change P2-P8 is of the order of IA.

[0077] When several branches are connected in parallel, the current can reach several Amperes. The invention is therefore well suited to a wide range of power transistors.

[0078] To do this, as illustrated in [Fig.8], branches 105 and 106 are connected in parallel between the input INPUT and the second terminal SOURCE. Branch 105 is connected to branch 106 by the source of its head transistor M41, which is connected to the source of the head transistor M51 of branch 106. The sources of the two head transistors M41, M51 are thus connected to the gate of the power transistor P7.

[0079] Alternatively, as illustrated in [Fig.9], it is possible to share the lower part of the adaptation circuit, comprising the enhancement transistors M75, M76. Thus, the branches 105 and 106 are connected in parallel between the input INPUT and the second terminal of the first dipole R71.

[0080] The adaptation circuit obtained is therefore not very sensitive to fluctuations in the supply voltage, temperature and variations in the transistor manufacturing process.

[0081] Indeed, the Applicant has carried out numerical simulations, the results of which are illustrated in [Fig. 10]. Thus, for an input signal 120 having a high state equal to 12V and a low state equal to 0V, the signal supplied to the gate of the power transistor P2-P8 varies very little depending on the transistor manufacturing process. In the worst case, i.e. for slow-slow (SS) transistors, the signal 140 has a slight delay in the rise, but which remains entirely satisfactory. For all other combinations of transistors, the signal 130 is faithfully reproduced and has a low state at 0V and a high state at 6V.

Claims

Claims

1. Integrated circuit comprising: - an enhancement power transistor (P2-P8), the drain of which is connected to a first terminal (DRAIN) of the integrated circuit and the source of which is connected to a second terminal (SOURCE) of the integrated circuit, - a circuit for adapting the voltage supplied to the gate of said enhancement power transistor (P2-P8), said adaptation circuit comprising at least one branch (100-108) connected between an input terminal (INPUT) adapted to receive a signal capable of adopting a low state and a high state, and the second terminal (SOURCE), said at least one branch (100-108) comprising: - a depletion head transistor (Ml, Mil, M21, M31, M41, M51, M61, M71), whose drain is connected to the input (INPUT), - a depletion tail transistor (M2, M14, M24, M34, M46, M56) whose source is connected to a terminal of a first dipole (RI, RI 1, R21, M4), and whose gate is connected to the second terminal of the first dipole (RI, Rll, R21, R31, R41, R51, R61, R71, M4), - a connecting quadrupole (10, 20, 30, 40) whose first terminal (Ql) is connected to the gate of the head transistor (Ml, Mil, M21, M31, M41, M51, M61, M71), whose second terminal (Q2) is connected to the source of the head transistor (Ml, Mil, M21, M31, M41, M51, M61, M71), whose third terminal (Q3) is connected to the source of the tail transistor (M2, M14, M26, M36, M44, M54, M64, M74) and whose fourth terminal (Q4) is connected to the drain of the tail transistor (M2, M14, M26, M36, M44, M54, M64, M74), and - an enhancement foot transistor (M3, M16, M29, M39, M46, M56, M76) whose source is connected to the second terminal (SOURCE) and whose gate is connected to its drain, said drain being connected to a second terminal (A4) of a second dipole (15, 25, 35), whose first terminal (A3) is connected to the second terminal of the first dipole (RI, Rll, R21, R31, R41, R51, R61, R71, M4), said matching circuit being connected, by the source of the head transistor (Ml, Mil, M21, M31, M41, M51, M61, M71), to the gate of the power transistor (P2-P8).

2. Integrated circuit according to claim 1, characterized in that the connecting quadrupole (10) consists of two short circuits respectively connecting the first and third terminals (Q1, Q3) and the second

3.

4. and fourth terminals (Q2, Q4). Integrated circuit according to claim 1, characterized in that the connecting quadrupole (20) comprises two depletion transistors (M12, M13, M42, M52, M43, M53, M62, M63, M72, M73): a high transistor (M12, M42, M52, M62, M72) and a low transistor (M13, M43, M53, M63, M73), the source of the high transistor (M12, M42, M52, M62, M72) being connected to the drain of the low transistor (M13, M43, M53, M63, M73) and to the first terminal (Q1) of the connecting quadrupole (20), the drain of the high transistor (M12, M42, M52, M62, M72) being connected to the second terminal (Q2) of the connecting quadrupole (20), the gate of the low transistor (M13, M43, M53, M63, M73) being connected to the third terminal (Q3) of the connecting quadrupole (20) and the gate of the high transistor (M12, M42, M52, M62, M72) and the source of the low transistor (M13, M43, M53, M63, M73) being connected to the fourth terminal (Q4) of the connecting quadrupole (20). Integrated circuit according to claim 1, characterized in that the connecting quadrupole (40) is made up of n elementary quadrupoles (QE1, QEi, QEi+1, QEn), with n > 1, each elementary quadrupole (QEi) comprising two depletion transistors: a high transistor (M42, M52, M44, M54) and a low transistor (M23, M33, M25, M35), the source of the high transistor (M22, M24) being connected to the drain of the low transistor (M23, M25) and to a first terminal (QEi-1) of the elementary quadrupole (QEi), the drain of the high transistor (M22, M24) being connected to a second terminal QEi-2 of the elementary quadrupole (QEi), the gate of the low transistor (M23, M25) being connected to a third terminal (QEi-3) of the elementary quadrupole (QEi) and the gate of the high transistor (M22, M24) and the source of the low transistor (M23, M25) being connected to a fourth terminal (QEi-4) of the elementary quadrupole (QEi);the elementary quadrupoles being connected in series, with two consecutive elementary quadrupoles (QEi, QEi+1) connected so that the first terminal (QEi+1-1) of the elementary quadrupole (QEi+1) is connected to the third terminal (QEi-3) of the elementary quadrupole (QEi) and the second terminal (QEi+1-2) of the elementary quadrupole (QEi+1) is connected to the fourth terminal (QEi-4) of the elementary quadrupole (QEi); the first and second terminals (QE1-1, QEI-2) of the elementary quadrupole (QEI) forming the first and second terminals (Ql, Q2) of the connecting quadrupole (40) and the third and fourth terminals (QEn-3, QEn-4) of the elementary quadrupole (QEn) forming the third and fourth terminals; (Q3, Q4).

5. Integrated circuit according to claim 1, characterized in that the depletion transistors (M1, M2, M11-M14, M21-M26, M31-M36, M41-M46, M51-M54, M61-M64, M71-M74) and enhancement transistors (M3, M15, M27-M29, M37-M39, M45, M46, M55, M56, M75, M76) are GaN transistors or MOS transistors.

6. Integrated circuit according to claim 1, characterized in that the first dipole is a resistor (RI, Rll, R21, R31, R41, R51, R61, R71).

7. Integrated circuit according to claim 1, characterized in that the first dipole is an enhancement transistor (M4) whose gate is connected to its drain.

8. Integrated circuit according to claim 2, characterized in that the second dipole (15) is a short circuit.

9. Integrated circuit according to claim 3, characterized in that the second dipole (25) comprises an enhancement transistor (M15) whose source is connected to the second terminal of the second dipole (25) and whose gate is connected to its drain, said drain being connected to the first terminal (A3) of the second dipole (25).

10. Integrated circuit according to claim 4, characterized in that the second dipole (35) comprises n enhancement transistors (M27, M28), each of said transistors (M27, M28) having its gate connected to its drain, said transistors (M27, M28) being connected in series, two consecutive transistors (M27, M28) being connected by the source of one and the drain of the other and, the drain of the first transistor (M27) forming the first terminal (A3) of the second dipole (35) and the source of the last transistor (M28) forming the second terminal (A4) of the second dipole (35).

11. Integrated circuit according to claim 1, characterized in that A comprises m branches (101-108) connected in parallel, each branch being connected by the source of its head transistor (Ml, Mil, M21, M31, M41, M51, M61, M71), on the gate of the power transistor (P2-P8).

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