Electronic circuit based on RRAM cells

Abstract

Electronic circuit based on RRAM cells This electronic circuit performs binary calculation operations, and comprises word, bit and source lines, and memory cells organized in rows and columns, the cells of the same row being selectable by at least one word line, those of the same column being connected to a pair of complementary bit lines and at least one source line. Each memory cell comprises at least one pair of memristors and at least one pair of switches, each memristor of a cell being connected to a switch and connected to the same source line during each calculation operation, each pair of memristors storing a binary value; the switches being connected, for their activation, to a word line and to a pair of complementary bit lines, the two switches of a pair being connected to the same word line.It comprises a reading module, used during each calculation operation and comprising: - a logic unit for each column, each comprising an input terminal connected to a source line to receive an input value, called column value, the logic unit switching between low and high values, depending on a comparison of the column value with a switching threshold value; and - a modification unit, for at least one logic unit and depending on the calculation operation, of a difference between the column value and said threshold value.

Description

Title of the invention: Electronic circuit based on RRAM cells

[0001] The present invention relates to an electronic circuit capable of implementing calculation operations each providing a binary output.

[0002] The invention relates to any type of application using operations applied to binary operands, in particular applications using binary artificial neural networks, also called BNN (Binary Neural Network).

[0003] A neural network is generally composed of a succession of layers of neurons, each of which takes its inputs from the outputs of the previous layer. More precisely, each layer comprises neurons taking their inputs from the outputs of the neurons in the previous layer. Each layer is connected to the next by a plurality of synapses. A synaptic weight is associated with each synapse. It is a number, such as a binary number, or a distribution, which takes both positive and negative values. In the case of a dense layer, the input of a neuron is the weighted sum of the outputs of the neurons in the previous layer, the weighting being done by the synaptic weights and followed by activation via an activation function.

[0004] It is therefore desirable to develop dedicated hardware architectures, intermixing memory and calculation, to create fast, low-power neural networks capable of learning in real time.

[0005] Such dedicated hardware architectures more generally aim to efficiently perform operations applied to binary operands.

[0006] A neural network based on optical-type technologies is known.

[0007] Another field of research concerns the production of neurons and synapses of neural networks based on CMOS (Complementary Metal-Oxide-Semiconductor) technology. The acronym CMOS refers to both a manufacturing process and a component obtained by such a manufacturing process.

[0008] However, according to each of these technologies, each neuron occupies several tens of micrometers on each side. In addition, each synapse also occupies several tens of micrometers on each side. As a result, on a limited surface corresponding for example to an electronic chip, the number of neurons and synapses that can be integrated is limited, which results in a reduction in the performance of the neural network.

[0009] Therefore, to reduce the size, architectures are specifically studied in which the synapses are memristive.

[0010] Memristive synapses are synapses using memristors. In electronics, the memristor (or memristor) is a passive electronic component. The name is a portmanteau word formed from the two English words memory and resistor. A memristor is a non-volatile memory component, the value of its electrical resistance changing with the application of a voltage over a certain period of time and remaining at that value in the absence of voltage.

[0011] Examples of such an implementation are proposed in the following articles:

[0012] - “A Fully Integrated Analog ReRAM Based 78.4TOPS / W Compute-ln-Memory Chip with Fully Parallel MAC Computing” by Q. Liu et al. (2020);

[0013] - “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors” by C. Xue et al. (2019);

[0014] - “A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS / W for Tiny AI Edge Devices” by C. Xue et al. (2021);

[0015] - « A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme » de W. Chen et al. (2017); et

[0016] - « Embedded 1-Mb ReRAM-Based Computing-in-Memory Macro With Multibit Input and Weightfor CNN-Based Al Edge Processors » de C. Xue et al. (2019).

[0017] According to these articles, the approach consists of storing the weights of a neuron within a column of RRAM or ReRAM (Resistive Random-Access Memory) memory cells, and applying the inputs (activations) to the word lines, generally denoted WL (Word Line), of this column (a positive voltage being applied to an associated bit line), generally denoted BL (Bit Line). The input voltages can be binary (open or closed access transistors), or take several possible values ​​in the case of multi-bit inputs. A weight equal to 1 is generally coded by a low resistance state, denoted LRS (Low Resistance State), and a weight equal to 0 by a high resistance state, denoted HRS (High Resistance State). If the input corresponding to a given weight is equal to 1, this will result - by Ohm's law - in a current within the cell carrying the multiplication between the input and the weight.If the weight is 1, the current is high (because the resistance is low), and if the weight is 0, the current is low.

[0018] Since the cells are connected via source lines, usually denoted SL (Source Line), the currents add up via Kirchhoff's law, resulting in a MAC (Multiply And Accumulate) operation well known for neural network inference. A comparator circuit calculates the actual output of the neuron by comparing the result of the MAC operation to a reference value.

[0019] However, these neuromorphic circuits today suffer from the excessive variability of resistive memory cells, due to the low maturity of their fa brication. Therefore, these approaches are limited in terms of the number of operands of a MAC operation, typically to 9 inputs. In addition, still due to the high variability of memory cells, these approaches require complex circuitry for comparing the MAC operation to the different possible threshold values, resulting in significant area and consumption.

[0020] Another approach is presented in the article “Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control” by L. Wang et al. (2021). It consists of performing the accumulation via a resistive bridge and not a current accumulation. This approach uses columns of RRAM memory cells resulting from the fusion of the source line SL of two columns (2T2R structure for 2 Transistors and 2 Resistors, a pair of switches and a pair of memristors). Each column thus has a pair of complementary bit lines BL, BLb and a source line SL. Two resistors are used to encode each weight in differential (HRS-LRS or LRS-HRS). A voltage is then applied between the complementary bit lines BL, BLb of the column, thus creating a resistive bridge between the resistors on the left and right sides of the column.The resulting voltage corresponds to the result of the MAC operation. Although allowing greater robustness against neuron variability, this approach has the same drawbacks as the previous one in terms of complexity and surface area of ​​the comparators required at the bottom of the column, and still seems limited to 9 inputs.

[0021] Finally, a last approach is presented in the article “Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges” by M. Ezzadeen et al. (2021). It consists of applying the inputs differentially to the complementary bit lines BL, BLb (and no longer to the word lines WL), by activating a respective word line of the memory cell array. The weights are differentially encoded in 2T2R cells. This results in a resistive bridge structure within each 2T2R cell, resulting in an exclusive-or, or XOR, operation at the output of each SL source line. Since the binary multiplication operation is equivalent to a not-exclusive-or, or XNOR, operation, a simple inverter at the end of the SL source line makes it possible to produce the result of the XNOR operation.The accumulation is performed by a capacitive bridge, connecting each inverter output to a capacitor, and connecting all the capacitors on the other hand together to form the bridge. This approach has the advantage of being extremely robust against cell variability (thanks to the use of capacitors, mature technology) despite a low surface impact (single inverter per column). Due to its robustness, it also allows the implementation of very large neurons (up to 513 inputs), by performing in one go (a single calculation cycle) the summation of the . contributions from a large number of inputs since all columns are activated at the same time to perform the calculation for a neuron associated with a row of the matrix. In addition, the memory cells encoding the weights are in practice more compact, since it is sufficient to have a single 2T-2R cell and a single word line per row. However, only one neuron can perform a calculation during a given cycle, since only one row of the memory cell matrix is ​​activated for each calculation. Depending on the application context, the “one neuron per row” or “one neuron per column” solution will be preferred, in particular depending on the number of inputs of each neuron, the number of neurons per layer, the available surface area, etc.

[0022] There is therefore a need for an electronic circuit making it possible in particular to produce a binary neural network which is less bulky and has better integrability in a set of memory cells.

[0023] To this end, the invention relates to an electronic circuit capable of implementing calculation operations each providing a binary output, the circuit comprising:

[0024] - word lines;

[0025] - pairs of complementary bit lines;

[0026] - source lines;

[0027] - a set of memory cells organized according to a matrix comprising rows and columns, the memory cells of the same row being selectable by at least one word line, the memory cells of the same column being connected to a pair of complementary bit lines and at least one source line;

[0028] each memory cell comprising at least one pair of memristors and at least one pair of switches, each memristor of a respective memory cell being connected to a respective switch and connected to the same source line during each calculation operation, each pair of memristors respectively storing a binary value by respectively having different first and second resistance values; the switches being connected, for their activation, to a respective word line and connected respectively to a pair of complementary bit lines, the two switches of a respective pair being connected to the same word line;

[0029] - a reading module implemented during each calculation operation, the module of reading including:

[0030] + one logical unit for each column, each logical unit comprising at least an input terminal connected to a respective source line for receiving an input value called a column value, the logic unit being capable of performing a logic operation having a switch between a low value and a high value as a function of a comparison of the column value with respect to a switch threshold value, during the calculation operation, and

[0031] + a modification unit suitable for modifying, for at least one logical unit and in depending on the desired calculation operation, a difference between the column value and the tipping threshold value.

[0032] With the electronic circuit according to the invention, the reading module comprising a logic unit for each column and the modification unit capable of modifying, for at least one logic unit and depending on the calculation operation, the difference between the column value and the threshold value, makes it possible to more efficiently determine a resulting value corresponding to the voltage of the respective source line.

[0033] Preferably, each memory cell comprises two pairs of memristors and two pairs of switches, with a first pair of switches connected to a first word line assigned to an input, and respectively a second pair of switches connected to a second word line assigned to the inverse of said input; and with a first pair of memristors associated with the first pair of switches and storing a synaptic weight, and respectively a second pair of memristors associated with the second pair of switches and storing the inverse of the same synaptic weight.

[0034] According to this clever implementation, each memory cell then allows to directly perform a non-exclusive-or, or XNOR, operation between an input and the corresponding synaptic weight of a respective neuron, and an inference value of said neuron is then obtained directly from the resulting value corresponding to the voltage of the respective source line, or from the resulting values ​​corresponding to the voltages of the respective source lines when the synaptic weights of said neuron are encoded on several columns of the set of memory cells in matrix form.

[0035] According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following characteristics, taken in isolation or in all technically possible combinations:

[0036] - the modification unit is suitable for modifying the difference between the column value and the toggle value for a respective logical unit, by controlling a modification of the complementary voltages applied on the pair of complementary bit lines for the column associated with said logical unit;

[0037] - the modification unit is suitable for modifying the difference between the column value and the threshold value for a respective logical unit, by commanding a change in the threshold value of said logical unit;

[0038] said threshold value preferably being modified via a change in the supply voltage of said logic unit and / or via a change in the bias voltage of a back gate of at least one transistor of said logic unit;

[0039] - the modification unit is capable of modifying, incrementally according to a step predefined increment, said difference between the column value and the switching threshold value, to determine - from a plurality of predefined possible values ​​- a resulting value corresponding to the voltage of the respective source line corresponding to said column value; the increment step depending on said plurality of possible values;

[0040] - the reading module further comprises a storage unit for at least a column, each storage unit being adapted to store the resulting value determined for the respective column, pending the determination of all the resulting values ​​for a respective group of several columns;

[0041] each storage unit preferably comprising a bit register for storing said determined resulting value in binary form;

[0042] - the reading module further comprises an extinction unit for each column, each extinction unit being suitable - after determination of the resulting value for the respective column and pending the determination of all the resulting values ​​for a respective group - for controlling the application of the same voltage to the pair of complementary bit lines for the circulation of a substantially zero current in the source line of the respective column;

[0043] - each memory cell has two pairs of memristors and two pairs of com mutators;

[0044] - a first pair of switches is connected to a first assigned word line to an input, and respectively a second pair of switches is connected to a second word line assigned to the inverse of said input; and in which a first pair of memristors is associated with the first pair of switches and storing a binary value, and respectively a second pair of memristors is associated with the second pair of switches and storing the inverse of the same binary value;

[0045] - each memory cell has a single pair of memristors and a single pair of switches, each pair of memristors respectively storing a syn-naptic weight;

[0046] - the logical operation performed by the logic unit is an inversion, and the operation of associated calculation is chosen from: a neural computation operation, such as the MAC operation; an AND operation; an OR operation; a Majority operation;

[0047] - the value of the switching threshold depends on the associated calculation operation;

[0048] when the associated calculation operation is the AND operation or the OR operation, the value the switching threshold preferably being at a voltage step of a corresponding bit line voltage, the corresponding bit line voltage being one of the complementary bit line voltages for the AND operation and the other of said voltages for the OR operation, the voltage step satisfying the following equation:

[0049] p = 1 OPD+Ï

[0050] where P represents the voltage step;

[0051] ABL represents the voltage differential between the bit line voltage and the complementary bit line voltage, and

[0052] OPD represents the number of operands to which the calculation operation is applied;

[0053] when the associated calculation operation is the Majority operation, the value of the switching threshold preferably being a median value of the complementary bit line voltages;

[0054] - the reading module further comprises a combination unit for at least a column, each combination unit being capable of combining the results of logical operations performed successively by a respective logical unit, to implement a combined logical operation;

[0055] each combination unit preferably comprising a flip-flop connected to the output of the respective logic unit;

[0056] the combined logical operation being preferably further chosen from the group consisting of: an exclusive-or operation and a not-exclusive-or operation;

[0057] - each memory cell of a respective column comprises at least one pair of sub-cells, each sub-cell comprising a memristor and a switch, each memristor of a respective sub-cell being connected to a respective source line and switch, the memristors of each pair of sub-cells respectively storing a binary value by having respectively first and second different resistance values; the switches being connected, for their activation, to a respective word line and connected respectively to a pair of complementary bit lines, the two switches of a respective pair of sub-cells being connected to the same word line; the two source lines associated with a respective pair of sub-cells being connected to each other via an auxiliary switch during each calculation operation and then forming the same source line to which each memristor of a respective memory cell is connected during each calculation operation;

[0058] - the electronic circuit is a neuromorphic circuit suitable for implementing a binary output neural network, each memory cell being associated with a respective synaptic weight of a neuron, and the word lines being capable of receiving input voltages during a neural calculation operation;

[0059] - the electronic circuit comprises a first controller making it possible to select the memory cells of a row which are connected to the same word line, and comprising a second controller connected to the pairs of bit lines and allowing to apply to each pair of bit lines different and symmetrical voltages with respect to an average voltage, the voltage applied to a bit line being higher or lower than that applied to the associated complementary bit line;

[0060] - the electronic circuit comprises several distinct sets of memory cells suitable for operating in parallel. - each logic unit performs an inverter-type logic function;

[0061] - each logic unit preferably being a simple inverter;

[0062] the simple inverter preferably still comprising only two transistors.

[0063] These characteristics and advantages of the invention will appear more clearly on reading the description which follows, given solely by way of non-limiting example, and made with reference to the appended drawings, in which:

[0064] [Fig-1] [Fig.l] is a schematic representation of an electronic circuit, according to the invention, suitable for implementing calculation operations each providing a binary output, the circuit comprising word lines, pairs of complementary bit lines, source lines, a set of memory cells organized according to a matrix comprising rows and columns, each memory cell comprising at least one pair of memristors and at least one pair of switches, and a reading module implemented during each calculation operation, the reading module comprising a logic unit for each column, each logic unit performing a logic operation with switching between a low value and a high value as a function of a comparison of a column value with respect to a switching threshold value, and a modification unit, for at least one logic unit and as a function of the calculation operation, of a difference between the column value and the switching threshold value;

[0065] [Fig.2] [Fig.2] is a schematic representation of a memory cell respective according to a first exemplary embodiment, where it comprises two pairs of memristors and two pairs of switches;

[0066] [Fig.3] [Fig.3] is a graph showing the effect of variability of the values ​​of the re resistances of the states of a memristor;

[0067] [Fig.4] [Fig.4] is a schematic view illustrating an XNOR operation performed via the memory cell of [Fig.2];

[0068] [Fig.5] [Fig.5] is a schematic representation of a respective logical unit of [Fig.l], and the output voltage of said logic unit taking into account the variability effect represented in [Fig.3], for an example with five rows of memory cells;

[0069] [Fig.6] [Fig.6] is a schematic representation illustrating the modification, for the logical unit of [Fig.5], of the difference between the column value and the switching threshold value;

[0070] [Fig.7] [Fig.7] is a representation of the electronic circuit according to the invention with the memory cells of [Fig.2], in an example where the electronic circuit forms a neuromorphic circuit implementing a binary output neural network, each memory cell being associated with a respective synaptic weight of a neuron, and the word lines being capable of receiving input voltages during a neural calculation operation;

[0071] [Fig.8] [Fig.8] is a schematic representation of the electronic circuit according to the invention with a particular implementation of a controller of the pairs of complementary bit lines, capable of resetting a respective column value after detection by the logic unit of a switch for said column;

[0072] [Fig.9] [Fig.9] is a schematic representation of the electronic circuit according to the invention and an associated timing diagram, the circuit further comprising a register at the output of each logic unit, each register being capable of transcribing in binary form the result of the calculation operation for the column, by recording - until the resulting value corresponding to the result of the calculation operation is reached - each successive value at the output of the corresponding logic unit, as illustrated in the timing diagram;

[0073] [Fig. 10] [Fig. 10] is a schematic representation of a respective memory cell according to a second exemplary embodiment, where it comprises a single pair of memristors and a single pair of switches;

[0074] [Fig. 11] [Fig. 11] is a view similar to that of [Fig.5], further representing examples of switching threshold, when the calculation operation performed is the logical AND operation, or respectively the logical OR operation; and

[0075] [Fig. 12] [Fig. 12] is a schematic representation of the electronic circuit according to the invention, the circuit further comprising a flip-flop at the output of each logic unit, each flip-flop being capable of carrying out a combination of results of logic operations carried out successively by a respective logic unit, to implement a combined logic operation, such as an exclusive-or operation or a not-exclusive-or operation.

[0076] It should be noted that the expression "specific to" followed by a verb is considered equivalent to the expression "configured for" followed by the same verb. The expression "specific to" will then be replaceable, if necessary, by the expression "configured for", without this modifying the content and tenor of the present invention.

[0077] In [Fig. 1], an electronic circuit 10 is capable of implementing calculation operations each providing a binary output. The calculation operations carried out by the electronic circuit 10 are for example neural calculation operations, such as operations for counting the number of 1s in a series of bits (from the English popcounf), or even MAC operations (from the English Multiply And Accumulate) well known for neural network inference; AND operations on binary operands; OR operations on binary operands; Majority operations among binary operands.

[0078] The electronic circuit 10 comprises a set of memory cells 12, that is to say a plurality of memory cells 12, the memory cells 12 being organized according to a two-dimensional matrix 14 comprising rows 16 and columns 18.

[0079] In addition, the electronic circuit 10 comprises several distinct sets of memory cells 12 capable of operating in parallel, as illustrated in particular in the example of [Fig.7].

[0080] The matrix 14 will be referred to as the cell matrix 14 in the remainder of the description. A memory cell 12 has the coordinates (i,j) when said memory cell 12 is positioned at the intersection of the i-th row 16; and the j-th column 18j with i and j two integers.

[0081] In the example of [Fig.l], the number of rows 16 and columns 18 is equal to N, so that the indices i and j are between 1 and N. In the example of [Fig.l], a matrix of cells 14 has been represented for which N is equal to 9. As a variant, the number of rows 16 and columns 18 can of course be different.

[0082] More generally, in the example of [Fig.7], the number of rows 16 is equal to n and respectively the number of columns 18 is equal to m, so that the index i is between 1 and n, and respectively the index j is between 1 and m.

[0083] The electronic circuit 10 also comprises word lines WL (visible in FIGS. 2, 7 and 10), pairs of complementary bit lines BL and BLb, source lines SL and two controllers 20 and 22.

[0084] The electronic circuit 10 also comprises a reading module 24 implemented during each calculation operation, which will be described in more detail in the remainder of the description.

[0085] In the preceding notations, a word line is referenced WL (from the English Word Line); the complementary bit lines BL and BLb use the acronym BL (from the English Bit Line) and the source lines are referenced with the acronym SL (from the English Source Line).

[0086] In the example of [Fig.l], each memory cell 12 is connected to a respective input line IN, a respective source line SL and a respective pair of complementary bit lines BL and BLb.

[0087] Each input line IN is suitable for receiving or selecting an operand to which the calculation operation is to be applied. Each input line IN is for example suitable for receiving an input value for the calculation operation.

[0088] Each input line IN is itself connected to a respective word line WL or to a respective pair of complementary word lines WL and WLb, depending on the topology of the memory cells 12. In the examples of Figures 2, 4 and 7, each input line IN is connected to a respective pair of complementary word lines WL and WLb. In the example of [Fig.10], each input line IN is connected to a single respective word line WL.

[0089] Each memory cell 12 of the same row 16 shares the same input line IN, itself connected to a respective word line WL or to a respective pair of complementary word lines WL and WLb, so that the input lines IN, and respectively the word lines WL, WLb, can also be indexed with the index i. Thus, the first input line IN, that is to say the one which connects the memory cells 12 of the first row 16, is referenced INi; and the, or respectively the, word line(s) associated with this first input line INi are referenced WLi, or respectively WLi and WLb.

[0090] The memory cells 12 of the same column 18 share the same pair of complementary bit lines BL and BLb and the same source line SL. These three lines can therefore also be indexed with the index j.

[0091] For the sake of clarity, all of the source lines SL are shown but only the complementary bit line pairs BL and BLb of the first column 18i, the fifth column 185 and the ninth column 189 are shown in dot-dash lines in [Fig.l].

[0092] The memory cells 12 of the same row 16 are then selectable by at least one word line WL, and the memory cells 12 of the same column 18 are connected to a pair of complementary bit lines BL, BLb and a source line SL.

[0093] The first controller 20 makes it possible to select the memory cells 12 of a row 16 which are connected to the same word line WL.

[0094] The first controller 20 is capable of controlling each input line IN, and by transitivity each word line WL, WLb. Indeed, when each input line IN is connected to a respective pair of complementary word lines WL and WLb, the input line IN is connected directly to one WL of the word lines, and via an inverter 26, hereinafter called word line inverter 26, to the other WLb of the word lines; and the control of the value applied to the input line IN also causes the control of the value applied to the respective pair of complementary word lines WL and WLb.Indeed, the person skilled in the art will of course understand that the value applied to the input line IN is then the same as that applied to the word line WL which is connected directly to the input line IN, and as a corollary that the value applied to the input line IN is then the inverse of that which is applied to the complementary word line WLb which is connected to the input line. IN via the word line inverter 26. Of course, when each input line IN is connected directly to a single respective word line WL, as in the example of [Fig. 10], then the value applied to the input line IN is the same as that applied to said word line WL connected directly to the input line IN.

[0095] By "inverse" of a binary value is meant the value complementary to 1 of said binary value. In other words, if a binary value is equal to 0, the inverse of this binary value is equal to 1; and respectively if a binary value is equal to 1, the inverse of this binary value is equal to 0.

[0096] The second controller 22 is capable of controlling the pairs of complementary bit lines BL and BLb and the source lines SL.

[0097] The second controller 22 is connected to the pairs of bit lines BL, BLb and makes it possible to apply different voltages to each pair of bit lines BL, BLb, the voltages applied during the calculation operation being advantageously symmetrical with respect to a middle voltage, the voltage applied to a bit line BL being higher or lower than that applied to the associated complementary bit line BLb.

[0098] The first controller 20 and the second controller 22 are configured to be driven in a coordinated manner to control the memory cells 12 using the lines that they control according to the desired operation.

[0099] In particular, the first controller 20 is configured to bring the input values ​​circulating on each of the input lines IN. It is these input values ​​which will for example feed the neural network produced where appropriate by the electronic circuit 10.

[0100] The inverter 26 is an element capable of receiving an incident signal on an input 26E and performing a logic inversion calculation to emit on an output 26S an output signal which is the inverse of the incident signal. Here, the input 26E of the inverter 26 is connected to the input line IN, and the output 26S of the inverter 26 is connected to the complementary word line WLb.

[0101] Each memory cell 12 is capable of storing at least one binary value, such as a binary weight, in particular a respective binary synaptic weight of the neural network when the calculation operation carried out is a neural calculation operation.

[0102] The structure of a memory cell 12 is represented more precisely in [Fig.2] for the case of the memory cell 12 having the coordinates (i,j).

[0103] Each memory cell 12 comprises at least one pair of memristors 28, 30, the or each pair of memristors being formed of two memristors, namely a first memristor 28 and a second memristor 30, and at least one pair of switches 32, 34, the or each pair of switches being formed of two switches, namely a first switch 32 and a second switch 34.

[0104] In the examples of figures 2, 4 and 7, each memory cell 12 comprises two pairs of memristors 28, 30, i.e. two first memristors 28 and two second memristors 30, and two pairs of switches 32, 34, i.e. two first switches 32 and two second switches 34.

[0105] In the example of [Fig. 10], each memory cell 12 comprises a single pair of memristors 28, 30, i.e. a single first memristor 28 and a single second memristor 30, and a single pair of switches 32, 34, i.e. a single first switch 32 and a single second switch 34.

[0106] Because memristors 28 and 30 are present, such a memory cell 12 is a resistive random-access memory cell. The memory cell 12 is more often referred to by the acronym RRAM or ReRAM (Resistive random-access memory).

[0107] Furthermore, such an arrangement is generally referred to as a 4T4R structure with reference to the presence of the four switches (designated 4T) and four memristors (designated 4R) in the examples of FIGS. 2, 4 and 7. By analogy, such an arrangement is generally referred to as a 2T2R structure with reference to the presence of the two switches (designated 2T) and two memristors (designated 2R) in the example of [Fig. 10]. The memory cell 12 is also sometimes referred to as a 4T4R cell in the examples of FIGS. 2, 4 and 7, or respectively as a 2T2R cell in the example of [Fig. 10].

[0108] Each memristor 28, 30 of a respective memory cell 12 is connected to the same source line SL and to a respective switch 32, 34, and each pair of memristors 28, 30 is configured to respectively store a binary value by respectively having different first and second resistance values. Those skilled in the art will observe that the source line SL to which the memristors 28, 30 of the respective memory cell 12 are connected is likely to be formed of two separate source lines connected together during the calculation operation.

[0109] Each memristor 28, 30 is a component whose electrical resistance value changes permanently when a current is applied. Thus, data can be recorded and rewritten by a control current. Such behavior is observed in particular in phase change materials, ferroelectric tunnel junctions or oxide-based redox memories, such as HfOx or TiO2 x. The change in resistance of a memristor depends on the amplitude and duration of the voltage pulses applied across the memristor, as well as the maximum current value that can pass through the memristor, for example for a “SET” operation, i.e. the transition from a high resistance to a low resistance.

[0110] Each memristor 28, 30 thus has two states, namely a high state and a low state low. The high state corresponds to high resistance and is generally abbreviated HRS. The high state is therefore referred to as the HRS high state in the following. The low state corresponds to low resistance and is generally abbreviated LRS. The low state is therefore referred to as the LRS low state in the following.

[0111] However, due to the variability of the memristors 28, 30 in operation, it turns out that the resistance in the high state HRS can be lower than the resistance in the low state LRS, which generates errors if the information (weight) is coded in a single memristor 28, 30.

[0112] This variability is shown schematically in [Fig.3]. In this figure, the probability that a memristor 28, 30 in practice exhibits the resistance value as a function of the state of the memristor is proposed. More precisely, the first curve, the curve noted 36, schematically represents the probability for all the values ​​observed in practice for the low state LRS while the second curve 38 represents the same curve for the high state HRS.

[0113] The graph in [Fig.3] shows that there is an overlap zone 40. In this overlap zone 40, distinguishing the low LRS and high HRS states may be impossible. This overlap may be greater with the long-term time drifts of the memristors 28, 30.

[0114] To overcome this problem, the information is coded by the ratio between the two resistances of the two states thanks to a differential configuration of the two memristors 28 and 30. Also, the memristors 28 and 30 are series and complementary memristors respecting the same logic coding. By complementary, it is understood here that the memristors 28 and 30 have a different state, a low state LRS for one and a high state HRS for the other.

[0115] According to the examples of figures 2, 4, 7 and 10, a high weight, that is to say a logic “1”, is represented by a high state HRS of the first memristor 28, and respectively a low state LRS of the second memristor 30. As a corollary, a low weight, that is to say a logic “0”, is represented by a low state LRS of the first memristor 28, and respectively a high state HRS of the second memristor 30.

[0116] Furthermore, in the examples of Figures 2, 4 and 7 where each memory cell 12 comprises two pairs of memristors 28, 30, the pairs of memristors 28, 30 are preferably coded in a complementary manner from one pair to the other. In other words, within each memory cell 12, one pair of memristors 28, 30 is preferably configured to code a binary value, while the other pair of memristors 28, 30 is preferably configured to code the inverse of said binary value.

[0117] Also, in the example of coding logic mentioned above, if the binary value to be encoded is equal to 1 for the first pair of memristors 28, 30, the left memristor, i.e. the first memristor 28, is coded in high resistance (high state HRS), and the memristor on the right, i.e. the second memristor 30, is coded in low resistance (low state LRS), while for the second pair of memristors 28, 30 encoding the inverse of said binary value, i.e. 0, the memristor on the left, i.e. the first memristor 28, is coded in low resistance (low state LRS) and the memristor on the right, i.e. the second memristor 30, is coded in high resistance (high state HRS).

[0118] A first pair of switches 32, 34 is connected to a first word line assigned to an input IN, namely the word line WL directly connected to the input line IN, and respectively a second pair of switches 34, 32 is connected to a second word line assigned to the inverse of said input IN, namely the complementary word line WLb connected to the input line IN via the word line inverter 26. The first pair of memristors 28, 30 is associated with the first pair of switches 32, 34 and stores a binary value w; and respectively the second pair of memristors 28, 30 is associated with the second pair of switches 34, 32 and stores the inverse of the same binary value w.

[0119] Further, as previously described, the first pair of memristors 28, 30 and the associated first pair of switches 32, 34 will have their word line WL assigned to the input corresponding to the binary value, while the second pair of memristors 28, 30 and the associated second pair of switches 32, 34 will have their complementary word line WLb assigned to the inverse of the same input, by the word line inverter 26.

[0120] The switches 32, 34 are connected, for their activation, to a respective word line WL, WLb and connected respectively to a pair of complementary bit lines BL, BLb, the two switches 32, 34 of a respective pair being connected to the same word line WL, WLb.

[0121] Each of the two switches 32 and 34 is for example a transistor, such as a field-effect transistor, also called FET (from the English Field-Effect Transistor)•

[0122] Thus, each switch 32 and 34 has three electrodes, a gate G, a source S and a drain D. Generally, for a transistor whose reference sign is X, where X designates the reference 32 or 34, the electrodes will be noted in the figures according to the following notation: the gate XG, the source XS and the drain XD.

[0123] This notation is chosen here to simplify the representation, knowing that the positions of the source XS and the drain XD are defined with respect to the main polarization direction, that is to say the most used for the assembly. Of course, if the polarization is reversed, the person skilled in the art knows that the roles and positions of the source XS and the drain XD are exchanged.

[0124] According to the example described, the two switches 32 and 34 are insulated gate field effect transistors, also called MOSFET (from the English Metal Oxide Semi- conductor Field Effect Transistor).

[0125] Each gate 32G and 34G of the two switches 32 and 34 is connected to the word line WL. Depending on the voltage level present on the word line, the switches 32 and 34 are made conducting or on the contrary not conducting, i.e. blocked. The first controller 20 will in practice choose to select one or more rows 16 of memory cells 12 by making the switches 32, 34 of the memory cells 12 of this or these rows 16 conductive.

[0126] Each first switch 32 is connected to a respective first memristor 28, and each second switch 34 is connected to a respective second memristor 30. The drain 32D of the first switch 32 is then connected to one terminal of the first memristor 28, the other terminal of the first memristor 28 being connected to the common source line SL. The drain 34D of the second switch 34 is connected to one terminal of the second memristor 30, the other terminal of the second memristor 30 being connected to the common source line SL. The source 32S of the first switch 32 is connected to the bit line BL while the source 34S of the second switch 34 is connected to the complementary bit line BLb.

[0127] The second controller 22 will control the power supply of the pairs of bit lines, so that the voltage presented on a bit line BLj is different and complementary to the voltage presented on the complementary bit line BLbj. Thus, when a memory cell 12 of coordinate i,j, in particular a pair of memristors 28, 30, is selected (its switches being turned on by the activation voltage presented on the associated word line WL; or WLb;), the memristors 28 and 30 of this pair are in series and constitute a resistive bridge between the bit lines BLj and BLbj.

[0128] In the present case, the memristors 28 and 30 of this pair are thus supplied by voltages present on the bit lines BLj and BLbj symmetrical with respect to a voltage equal to [V(BL)+V(BLb)] / 2, called the middle voltage, where V(BL) represents the voltage of the bit line BL, and V(BLb) represents the voltage of the complementary bit line BLb.

[0129] In the examples of Figures 2, 4 and 7, with the coding logic defined above, if the binary value, such as a weight, in particular a synaptic weight of a binary neural network, stored in a given memory cell 12 is equal to 0, then for the first pair of memristors 28, 30, the first memristor 28 (corresponding to the one on the top left among the four memristors of the memory cell 12) is the low state LRS and the second memristor 30 (corresponding to the one on the top right) is in the high state HRS; and conversely, for the second pair of memristors 28, 30, the first memristor 28 (corresponding to the one at the bottom left) is in the high state HRS and the second memristor 30 (corresponding to the one at the bottom right) is in the low state LRS.

[0130] Those skilled in the art will of course understand that the coding is reversed if the value binary stored in the memory cell 12 is equal to 1, and for the first pair of memristors 28, 30, the first memristor 28 (corresponding to the one at the top left) is the high state HRS and the second memristor 30 (corresponding to the one at the top right) is in the low state LRS; and conversely, for the second pair of memristors 28, 30, the first memristor 28 (corresponding to the one at the bottom left) is in the low state LRS and the second memristor 30 (corresponding to the one at the bottom right) is the high state HRS.

[0131] Those skilled in the art will further observe that in the examples of FIGS. 2, 4 and 7 and by the word line inverter 26, only one pair of memristors 28, 30 among the two pairs of memristors 28, 30 can be activated at a time.In particular, in these examples, and given that the word line inverter 26 is connected to the complementary word line WLb associated with the second pair of memristors 28, 30, if the input value received on the input line IN is equal to 1, then the first pair of memristors 28, 30 is activated since the value on the word line WL directly connected to the input line IN is also equal to 1 and the switches 32, 34 associated with this first pair are therefore on, while the second pair of memristors 28, 30 is not activated since the value on the complementary word line WLb is then equal to 0, the word line inverter 26 inverting the input value equal to 1 into the value 0, and the switches 32, 34 associated with this second pair are therefore off, i.e. blocked.Conversely, if the input value received on the input line IN is equal to 0, then the first pair of memristors 28, 30 is not activated since the value on the word line WL is also equal to 0 and the switches 32, 34 associated with this first pair are therefore non-conducting, while the second pair of memristors 28, 30 is in this case activated since the value on the complementary word line WLb is then equal to 1, the word line inverter 26 inverting the input value equal to 0 into the value 1, and the switches 32, 34 associated with this second pair are therefore conducting.

[0132] Furthermore, when a voltage is applied between the bit line BL and the complementary bit line BLb, with a higher potential VH for the bit line BL than that VL for the complementary bit line BLb, this results in a resistive bridge between the first and second memristors 28, 30 of the pair of memristors 28, 30 which is activated, as explained previously. The memristor 28, 30 which is in the high state HRS then systematically pushes the midpoint voltage, i.e. that of the source line SL, towards the bit line BL, BLb which is connected to the memristor 28, 30 in the low state LRS.

[0133] Also, in the examples of figures 2, 4 and 7, with this clever implementation of the two pairs of memristors 28, 30 coupled to the two complementary word lines WL, WLb, one of the word lines being connected to the input line IN via the word line inverter 26, each memory cell 12 then allows to directly perform a not-exclusive-or, or XNOR, operation between the binary input received on the input line IN and the binary value, such as the corresponding synaptic weight of a respective neuron, stored in the memory cell 12, and the result of the XNOR operation is then obtained via the comparison of the voltage of the source line SL with the middle voltage.

[0134] In the example of [Fig.4], with the coding logic defined above, if the voltage of the source line SL is lower than the midpoint voltage [V(BL)+V(BLb)] / 2, then the result of the XNOR operation is equal to 1; if the voltage of the source line SL is higher than the midpoint voltage [V(BL)+V(BLb)] / 2, then the result of the XNOR operation is equal to 0.

[0135] The four possible situations depending on whether the binary input value, also called binary input, received on the input line IN; is equal to 0 or 1, and whether the binary value Wji stored in the memory cell 12 is equal to 0 or 1, are then represented in a synthetic manner on the right part of [Fig.4].

[0136] In the first situation where the binary input received on the input line IN; is equal to 0 and the binary value Wji stored in the memory cell 12 is equal to 0, the second pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is in the high state HRS while the second memristor 30 (corresponding to the one on the right) is in the low state LRS. The first memristor 28 in the high state HRS then pushes the voltage of the source line SLj towards the complementary bit line BLbj connected to the second memristor 30 in the low state LRS, as represented by the arrow FL The voltage of the source line SLj is then closer to the low potential VL for the complementary bit line BLbj than to the high potential VH of the bit line BLj, and is therefore lower than the middle voltage [V(BL)+V(BLb)] / 2, so that the result of the XNOR operation is equal to 1. This therefore verifies XNOR(0,0) = 1.

[0137] In the second situation where the binary input received on the input line IN; is equal to 1 and the binary value wj; stored in the memory cell 12 is equal to 1, the first pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is the high state HRS, the second memristor 30 (corresponding to the one on the right) being in the low state LRS. The first memristor 28 in the high state HRS then pushes the voltage of the source line SLj towards the complementary bit line BLbj connected to the second memristor 30 in the low state LRS, as represented by the arrow FL The voltage of the source line SLj is then lower than the middle voltage [V(BL)+V(BLb)] / 2, and the result of the XNOR operation is therefore equal to 1. This therefore verifies XNOR(1,1) = 1.

[0138] In the third situation where the binary input received on the input line IN; is equal to 1 and the binary value wj; stored in the memory cell 12 is equal to 0, the first pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is in the low state LRS, while the second memristor 30 (corresponding to the one on the right) is in the high state HRS. The second memristor 30 in the high state HRS then pushes the voltage from the source line SLj to the bit line BLj connected to the first memristor 28 in the low state LRS, as represented by the arrow F2. The voltage of the source line SLj is then closer to the high potential VH of the bit line BLj than to the low potential VL for the complementary bit line BLbj, and is therefore greater than the middle voltage [V(BL)+V(BLb)] / 2, so that the result of the XNOR operation is equal to 0. This therefore verifies XNOR(1,0) = 0.

[0139] In the fourth and final situation where the binary input received on the input line IN; is equal to 0 and the binary value wj; stored in the memory cell 12 is equal to 1, the second pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is in the low state LRS, while the second memristor 30 (corresponding to the one on the right) is the high state HRS. The second memristor 30 in the high state HRS then pushes the voltage from the source line SLj to the bit line BLj connected to the first memristor 28 in the low state LRS, as represented by the arrow F2. The voltage of the source line SLj is then greater than the middle voltage [V(BL)+V(BLb)] / 2, and the result of the XNOR operation is therefore equal to 0. This therefore verifies XNOR(0,1) = 0.

[0140] Those skilled in the art will of course understand that also with an inverted coding logic where the binary value 1 stored in the memory cell 12 is encoded in the form of the first memristor 28 in the low state LRS and the second memristor 30 in the high state HRS, and as a corollary the binary value 0 is encoded in the form of the first memristor 28 in the high state HRS and the second memristor 30 in the low state LRS, each memory cell 12 of the examples of FIGS. 2, 4 and 7 still allows the XNOR operation to be performed, and that the result of the XNOR operation is then equal to 0 if the voltage of the source line SL is lower than the middle voltage [V(BL)+V(BLb)] / 2, and conversely equal to 1 if the voltage of the source line SL is higher than the middle voltage [V(BL)+V(BLb)] / 2, this always assuming that the high potential VH is applied to the bit line BL, while the low potential VL is applied to the complementary bit line BLb.

[0141] Of course, assuming that the potentials would be applied to the complementary bit lines BL, BLb in an inverse manner with respect to the above, with the high potential VH applied to the complementary bit line BLb and the low potential VL applied to the bit line BL, then the logic for comparing the voltage of the source line SL with the middle voltage to determine the result of the XNOR operation would also be inverted.

[0142] [Fig.5] then concerns the voltage distributions obtained overall on the source line SLj, that is to say at the bottom of the source line SLj in the examples of figures 1 and 7, when several input lines IN; are used simultaneously, the graph of the voltage distributions represented in [Fig.5] illustrating the case where five input lines IN; are used simultaneously.

[0143] This example in [Fig.5] concerns in particular the case of the inference of a binary neural network. To understand what follows, it can be observed that a binary neural network presents a specificity in the inference compared to a classic neural network.

[0144] When a classical neural network is applied to an input vector to calculate an output vector, each neuron receives input values ​​corresponding to output values ​​of neurons of a previous layer ai and performs a weighted sum y jy. ; a and the neuron then applies a non-linear function f to the J ' I result of the weighted sum.

[0145] In contrast, in a binary neural network, the weighted sum is obtained by performing the following operation:

[0146] [Math.l] a, - sign^popcount (XNOR(wjb x^ ) -

[0147] where ai represents the output value calculated by the neuron,

[0148] xi represent the input values ​​for said neuron,

[0149] wji represent the respective binary weights associated with said neuron for each of the inputs;

[0150] XNOR is the logical operation of not-exclusive-or;

[0151] popcount. is the function that counts the number of 1s in a series of bits, when i varies between 1 and the number n of entries;

[0152] Tj is a predefined threshold, and

[0153] Slgn is a function associating the value 1 with a positive input and associating it with a negative value.

[0154] When the input values ​​are applied to the n input lines IN;, where n represents the number of input lines IN;, n word lines are activated among the 2n complementary word lines WL;, WLb;. This then forms a divider bridge between the bit line BLj and the complementary bit line BLbj, as shown in the upper part of [Fig.5], where a first equivalent resistance RBL corresponds to the equivalent resistance for the divider bridge portion connected between the bit line BLj and the source line SLj, and a second equivalent resistance RBLb corresponds to the equivalent resistance for the divider bridge portion connected between the bit line

[0155]

[0156]

[0157]

[0158]

[0159]

[0160]

[0161]

[0162]

[0163]

[0164]

[0165]

[0166]

[0167] complementary BLbj and source line SLj. From the above, especially in view of the example in [Fig.4], if the result of the XNOR operation is equal to 1, then the first memristor 28 to the left of the source line SLj is in the high state HRS and the second memristor 30 to the right of the source line SLj is in the low state LRS. Conversely, if the result of the XNOR operation is equal to 0, then the first memristor 28 to the left of the source line SLj is in the low state LRS and the second memristor 30 to the right of the source line SLj is in the high state HRS. For the first equivalent resistance RBL corresponding to the portion of the divider bridge to the left of the source line SLj, the number of memristors in the high state HRS, noted #HRS in [Fig.5], is then equal to pop, where pop is equal to the result of the popcount function in the previous equation (1) when the input values ​​x; are the input values ​​applied to the n input lines IN;, and for the first equivalent resistance RBL the number of memristors in the low state LRS, noted #LRS in [Fig.5], is then equal to n-pop, n representing the number of input lines IN;. In the example of [Fig.5], the first equivalent resistance RBL then verifies the following equation: [Math.2] j _ pop t n-pop _ pL+H(np) _ p(LH)+nH R^ “ HRS + “ERST “ ÏIL “ HL where Rbl represents the first equivalent resistance, pop, or the abbreviated notation p, is equal to the result of the popcount function in equation (1) above, n representing the number of input lines IN;, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or abbreviated notation L, represents the resistance of memristor 28, 30 in the low LRS state. As a corollary, for the second equivalent resistance RBLb corresponding to the portion of the divider bridge to the right of the source line SLj, the number #LRS of memristors in the low state LRS is then equal to pop, the number #HRS of memristors in the high state HRS is then equal to n-pop. In the example of [Fig.5], the second equivalent resistance RBLb then verifies the following equation: [Math.3] 1 pop (:n-pop pH+L(np) ~ LRS + HRS ~ HL “ p(HL)+nL HL where RBLb represents the second equivalent resistance,

[0168]

[0169]

[0170]

[0171]

[0172]

[0173] pop, or the abbreviated notation p, is equal to the result of the popcount function in equation (1) above, n representing the number of input lines IN;, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or abbreviated notation L, represents the resistance of memristor 28, 30 in the low LRS state. From the previous equations (2) and (3), the source line voltage SL then verifies the following equation: [Math.4] V(SL)-V(BLb) RBLb RBL+RBLb *ABL = HL * 1 p(HL)+nL —+--¾— 1 p(H4.)+nL p(L <H)+nH +

[0174]

[0175]

[0176]

[0177]

[0178]

[0179]

[0180]

[0181]

[0182]

[0183]

[0184]

[0185]

[0186]

[0187] where V(SL) represents the source line voltage SL, V(BLb) represents the voltage of the complementary bit line BLb, and ABL represents the voltage differential between the voltage of bit line BL and the voltage of complementary bit line BLb according to the following equation: [Math.5] ABL = |V(BL) -V(BLb)| After simplification, the voltage of the source line SL then verifies the following equation: [Math.6] V(SL)= * ABL + V ( BLb ) where V(SL) represents the source line voltage SL, V(BLb) represents the voltage of the complementary bit line BLb, ABL represents the voltage differential between the voltage of bit line BL and the voltage of complementary bit line BLb according to equation (5), pop is equal to the result of the popcount function of equation (1) above, n representing the number of input lines INi, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or abbreviated notation L, represents the resistance of memristor 28, 30 in the low LRS state. The skilled person will observe that the preceding equation (6) depends on the pop value, that is, on the result of the popcount function of the preceding equation (1). The larger the pop value, the larger the term |pop* ( LRS - HRS ) j will be, and since the term pop*( LRS - HRS ) is negative because HRS>LRS, the smaller the term n*HRS + pop*(LRS - HRS). Therefore, the larger the pop value will be The larger the voltage, the lower the voltage of the source line SL will be, and closer to the voltage of the complementary bit line BLb.

[0188] Due to the variability of the memristors in operation, as described previously with regard to [Fig. 3], a distribution 40 of the voltages of the source line SL according to the preceding equation (6) comprises a plurality of lobes 42, each lobe 42 representing a probability density of the voltage of the source line SL for a given pop value. The number of lobes 42 contained in the distribution 40 is then equal to the number of possible values ​​of the pop value, i.e. n+1, with n representing the number of input lines IN;.

[0189] The number of threshold values ​​necessary to determine the value of the voltage of the source line SL among these n+1 lobes 42 is then equal to n, these values ​​of a threshold th being noted respectively th=0 to th=nl in the example of [Fig.5], with n=5.

[0190] The reading module 24 will now be described in more detail, with reference to FIGS. 5 to 9.

[0191] The reading module 24 comprises a logic unit 50 for each column 18, each logic unit 50 comprising at least one input terminal 52 connected to a respective source line SL to receive an input value called column value, and an output terminal 54. The logic unit 50 is capable of performing a logic operation having a switch between a low value and a high value, as a function of a comparison of the column value with respect to a switch threshold value INVth, during the calculation operation, the result, noted a, of the logic operation being delivered at the output terminal 54.

[0192] According to the invention, the reading module 24 further comprises a modification unit 60 capable of modifying, for at least one logical unit 50 and depending on the desired calculation operation, a difference between the column value and the INVth switching threshold value. In other words, the modification unit is capable of modifying, for at least one logical unit 50 and depending on the desired calculation operation, the INVth switching threshold value with respect to the column value.

[0193] The logic operation performed by the logic unit 50 is preferably an inversion, the logic unit 50 typically being a simple inverter. The logic unit 50 is then capable of receiving an incident signal on its input terminal 52 and of performing a logic inversion calculation to emit on its output terminal 54 an output signal which is the inverse of the incident signal.

[0194] Those skilled in the art will then observe that if the reading module 24 only comprises the modification unit 60 in the form of a simple inverter, then the reading module 24 can compare the voltage of the source line SL with a single switching threshold value INV*, as shown as an example of the state of the art in the lower part of [Fig.5]. In this example, the single threshold value switching threshold INVth, also called inversion threshold, or switching threshold, is chosen equal to 0.6 V, i.e. the middle between the voltage of the complementary bit line BLb chosen equal to 0.3 V and the voltage of the bit line BL chosen equal to 0.9 V. In this example, if the value pop, i.e. the result of the popcount function, is greater than a middle threshold, i.e. equal to 3, 4 or 5, then the voltage of the source line SL is less than 0.6 V, and the logic unit 50 will give the value 1 at its output terminal 54, the voltage U50 at the output terminal 54 represented by a dotted line then being at VDD. If the pop value is lower than the middle threshold, i.e. equal to 0, 1 or 2, then the voltage of the source line SL is higher than 0.6V, and the logic unit 50 will give the value 0 at its output terminal 54, the voltage U50 at the output terminal 54 then being 0.

[0195] Thus, with a simple inverter, it is possible to perform the comparison of the pop value with a threshold, such as the middle threshold. However, this is insufficient to perform a neural operation, where the threshold value is not fixed to the average value. This is the reason why the state of the art generally uses a complete comparator at the bottom of the column to compare the pop value with any threshold defined during training. However, the use of a comparator at the bottom of the column requires a large surface area (much larger than a simple inverter), significant power consumption and low parallelism due to the multiplexing at the bottom of the column.

[0196] According to the invention, the modification unit 60 then makes it possible to modify, for at least one logical unit 50 and depending on the desired calculation operation, the difference between the column value and the switching threshold value INV*, i.e. to modify the switching threshold value INVth with respect to the column value.

[0197] The modification unit 60 then makes it possible in particular to compare the pop value, that is to say the result of the popcount function, with any threshold value, by having at the bottom of the column only the logic unit 50, typically in simple inverter form, as illustrated in Figures 7 to 9.

[0198] The modification unit 60 is, for example, capable of modifying the difference between the column value and the INVth switching value for a respective logic unit 50, by controlling a modification of the complementary voltages applied to the pair of complementary bit lines BL, BLb for the column 18 associated with said logic unit 50.

[0199] In the example of [Fig.6], to obtain the first threshold th=0 of [Fig.5], the voltage of the complementary bit line BLb is controlled to the value INVth-5*Ath, i.e. for example 0.1 V, and the voltage of the bit line BL is controlled to the value INVth+Ath, i.e. for example 0.7 V, while the switching threshold value INV th, is unchanged, remaining equal to 0.6 V in this example. To obtain the second threshold th=l of [Fig.5], the voltage of the complementary bit line BLb is controlled to the value INVth-4*Ath, for example 0.2 V, and the voltage of the bit line BL is controlled to the value INVth+2*Ath, for example 0.8 V, while the switching threshold value INVth, is unchanged, for example 0.6 V. To obtain the third threshold th=2 of [Fig.5], the voltage of the complementary bit line BLb is controlled to the value INVth-3*Ath, for example 0.3 V, and the voltage of the bit line BL is controlled to the value INVth+3*Ath, for example 0.9 V, while the switching threshold value INVth, is unchanged, for example 0.6 V. To obtain the fourth threshold th=3 of [Fig.5], the voltage of the complementary bit line BLb is controlled to the value INVth-2*Ath, for example 0.4 V, and the voltage of the bit line BL is controlled to the value INVth+4*Ath, for example 1 V, while the switching threshold value INVth, is unchanged, for example 0.6 V. Finally, to obtain the fifth threshold th=4 of [Fig.5], the voltage of the complementary bit line BLb is controlled to the value INVth-Ath, for example 0.5 V, and the voltage of the bit line BL is controlled to the value INVth+5*Ath, for example 1.1 V, while the switching threshold value INVth, is unchanged, for example 0.6 V.

[0200] Those skilled in the art will observe that in this example of [Fig.6], the modification of the complementary voltages of the pair of complementary bit lines BL, BLb is carried out with a variation according to a variation step Ath from one threshold to the next.

[0201] The variation step Ath verifies for example the following equation:

[0202] [Math.7] = _ Pj±Hl£glWABL = JtL *AbL \ n(L+H) n(L+H) / n(L+H)

[0203] where ABL represents the voltage differential between the voltage of the bit line BL and the voltage of the complementary bit line BLb according to equation (5),

[0204] pop, or the abbreviated notation p, is equal to the result of the popcount function of the previous equation (1),

[0205] n representing the number of input lines INi,

[0206] HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and

[0207] LRS, or the abbreviated notation L, represents the resistance of the memristor 28, 30 in the low state LRS.

[0208] As a variant, not shown, the modification unit 60 is capable of modifying the difference between the column value and the INVth switching threshold value for a respective logical unit 50, by commanding a modification of the INVth switching threshold value of said logical unit 5.

[0209] According to this variant, the INVth switching threshold value is for example modified via a change in the supply voltage of said logic unit 50, or via a change in the bias voltage of a back gate of at least one transistor of said logic unit 50, or via both the change in the supply voltage and the change in the bias voltage.

[0210] As an optional addition, the modification unit 60 is capable of modifying, incrementally according to a predefined incrementation step, said difference between the column value and the switching threshold value INVth, to determine - among a plurality of predefined possible values ​​- a resulting value corresponding to the voltage of the respective source line SL, i.e. corresponding to said column value. The incrementation step depends on said plurality of possible values. According to this optional addition, the incrementation step is for example equal to the variation step Ath defined previously.

[0211] When the calculation operation performed is a neural calculation operation, such as the MAC operation, the electronic circuit 10 according to the invention with the set of memory cells 12 organized according to the matrix 14 comprising n rows 16 and m columns 18, then makes it possible to implement a neural network 65 with n inputs and m outputs, such as a fully connected neural network, as shown in [Fig.7]. In the example of [Fig.7], the electronic circuit 10 then comprises n*m memory cells 12, each comprising two pairs of memristors 28, 30 and two pairs of switches 32, 34, i.e. n*m 4T4R type cells; as well as n pairs of complementary word lines WL, WLb, i.e. 2*n word lines WL, WLb; m source lines SL; and m pairs of complementary bit lines BL, BLb, or 2*m bit lines BL, BLb.

[0212] Due to the high variability of the memristors 28, 30, the electronic circuit 10 is preferably limited to 9 simultaneously activated inputs, i.e. n equal to 9. In the case where the neural networks used require neurons larger than 9 inputs (which is very frequent), it is then advantageous to divide the global neuron into portions of 9 inputs, and to sum the results of the MAC of each portion to obtain the global popcount, which will be compared to the threshold specific to the neuron. This division of the global neuron into portions of 9 inputs is known in itself, and even has a practical aspect, because the usual convolution filters have a size of 3 by 3, i.e. 9 inputs in total.

[0213] Consequently, the generation of the voltages of the pairs of complementary bit lines BL, BLb is advantageously shared for all the columns 18 of the matrix 14, thus reducing the complexity of the generation of the offsets of the voltages of the pairs of complementary bit lines BL, BLb, described previously to successively modify the switching threshold value INVth with respect to the column value. All the thresholds th=0 to th=nl are then preferentially tested successfully. sively in ascending order, or alternatively in descending order, resulting at the output of each logical unit 50 in a sequence of bits which corresponds to the value of the partial MAC with 9 inputs. This sequence of bits can also be interpreted by a thermometric type coding, close to one-hot coding. This sequence of bits contains a sequence of 1 which corresponds to thresholds lower than the pop value (result of the popcounf function).

[0214] As an optional addition, the reading module 24 further comprises an extinction unit 70 for each column 18, each extinction unit 70 being capable - after determination of the resulting value for the respective column 18 and pending the determination of all the resulting values ​​for a respective group of columns 18 - of controlling the application of the same voltage to the pair of complementary bit lines BL, BLb for the circulation of a substantially zero current in the source line SL of the respective column 18.

[0215] Each extinction unit 70 then makes it possible to limit the current consumption at the output of the corresponding source line SL, by “switching off” the corresponding column as soon as its first “1” is obtained at the output of the logic unit 50. In addition, a complete one-hot coding is then obtained, as shown in [Fig.8], without the unnecessary sequence of 1s.

[0216] The second controller 20 suitable for controlling the pairs of complementary bit lines BL, BLb generally contains two two-input multiplexers 72, one for each bit line BL, BLb, each multiplexer 72 being useful for conventional write and read operations. These multiplexers 72 are controlled by control bits stored in registers. Each extinction unit 70 is then for example obtained by connecting the output of each logic unit 50 to the clear or reset signal clr of a flip-flop 74 controlling its respective complementary bit line BLb, this via an AND logic gate 76, which is also connected to a global clear signal CLR_G, as shown in the example of [Fig.8]. In the example of [Fig.8], the other flip-flop 78 is a flip-flop controlling the respective bit line BL.

[0217] In the example of [Fig.8], at the end of each shift of the voltages of the pairs of complementary bit lines BL, BLb, if the output of the logic unit 50 is a “1”, this output will clear the control flip-flop 74 of the respective complementary bit line BLb in the following cycle, thus setting the two voltages of the pairs of complementary bit lines BL, BLb to the voltage of the bit line BL, i.e. to the high voltage VH, and thus resulting in a zero current within the column 18 concerned, then in a “0” at the output of the corresponding logic unit 50. In this example, it is simply necessary to start with the highest threshold, decreasing towards the lowest threshold. In [Fig.8], the direction of the time evolution for the sequence of bits at the output of each logical unit 50 is represented by the arrow F3.

[0218] As an optional addition, the successive outputs of the logic units 50 are stored in registers specific to each column 18.

[0219] As an optional addition, the reading module 24 further comprises a storage unit 80 for each column 18, each storage unit 80 being capable of storing the resulting value determined for the respective column 18, pending the determination of all the resulting values ​​for a respective group of several columns 18.

[0220] Each storage unit 80 preferably comprises a bit register 82 for storing said determined resulting value in binary form. Each storage unit 80 is advantageously in the form of the bit register 82.

[0221] According to this optional addition, in the example of [Fig.9], each logic unit output 50 is connected to a respective bit register 82, each output driving the “enable” signal 84 of the associated register 82. This register 82 typically contains 4 bits, since 4 bits are sufficient to code a MAC operation whose value varies between 0 and 9. The registers 82 further have a clock input 85 receiving a clock signal CLK and an input 86 common and parallel to all the registers 82. This common input 86 is driven by an up (or down) counter 88. The up (or down) counter 88 is advantageously the same as that used in the control of the pairs of complementary bit lines BL, BLb.

[0222] [Fig.9] illustrates the overall operation of such storage units 80, with a timing diagram showing two cases: in dark gray a column with a MAC equal to 9, and in light gray a column with a MAC equal to 3.

[0223] After selecting the input lines IN corresponding to the inputs of the neurons, the voltages of the pairs of complementary bit lines BL, BLb corresponding to the first desired threshold (for example here the highest threshold) are first applied to the pairs of complementary bit lines BL, BLb. The output, noted inv[0], of the logic unit 50 of the hatched column sets to 1, because its MAC operation, noted MAC[0], is maximum and is equal to 9. Consequently, when the clock CLK of the registers 82 goes to 1, the register 82 of the hatched column captures the binary code of the counter 88, which corresponds to the value 9.Subsequently, at the edge of the global clear signal CLR_G, the flip-flop 74 controlling the complementary bit line BLb of the hatched column is cleared, equalizing - for example at the high potential VH - the voltages of the pairs of complementary bit lines BL, BLb of this column 18, to "turn it off" in the rest of the calculations with the remaining thresholds, setting the output of its logic unit 50, denoted inv[0], to 0. As for the column filled with points, the output, denoted inv[l], of its logic unit 50 remains at 0 until the threshold cycle. “3”, where it flips to 1 because its MAC operation, noted MAC[1], is equal to 3, and then follows the same sequence as the hatched column.

[0224] Simulations carried out on this 9-input neuron show excellent results. Indeed, when the variability of the transistors forming the switches 32, 34 is not simulated, the output error rate of the logic unit 50 is zero for all cases, i.e. whatever the pop value resulting from the popcount function and whatever the threshold value. When said variability of the transistors is simulated, the output error rate of the logic unit 50 is similar to that of a conventional approach, while observing that the power consumption with the electronic circuit 10 according to the invention is then significantly lower, typically more than 80 times lower, than that of the circuit of the state of the art, for better or equivalent latency.

[0225] Those skilled in the art will then observe that the electronic circuit 10 according to the invention then makes it possible to efficiently carry out the neural calculation operation, such as the MAC operation according to the preceding equation (1), and by requiring a small surface area for the components implementing said operation, while also having low consumption, and by offering an increased possibility of parallelism, as represented in [Fig.7] in particular.

[0226] In the example of [Fig. 10], each memory cell 12 comprises a single pair of memristors 28, 30, i.e. a single first memristor 28 and a single second memristor 30, and a single pair of switches 32, 34, i.e. a single first switch 32 and a single second switch 34.

[0227] According to the example of [Fig.10], each memory cell 12 is also capable of storing at least one binary value, such as a binary weight, in particular a respective binary synaptic weight of the neural network when the calculation operation carried out is a neural calculation operation.

[0228] The coding of each memory cell 12 is for example that described in the article “Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control” by L. Wang et al. (2021). Each column 18 also has a pair of complementary bit lines BL, BLb and a source line SL. Each row 16 then has a single word line WL. The first and second memristors 28, 30 are used to code each weight in differential (HRS-LRS or LRS-HRS), in a manner analogous to what was described previously. A voltage is then applied between the complementary bit lines BL, BLb of column 18, creating a resistive bridge between the memristors on the left and right sides of column 18. The resulting voltage corresponds to the result of the MAC operation, this time performed with an AND operation rather than the XNOR operation described previously.

[0229] To avoid sometimes having an even number of memory cells 12 activated, a parity word line WL_p is added, and this parity word line WL_p is configured to activate the memory cells 12 of type 2T2R (coded in HRS, LRS), which would activate if the number of inputs IN is even. Therefore, the voltage distributions will always be on either side of the threshold of the logic unit. This parity word line WL_p is advantageous especially when the calculation operation is the Logic Majority operation.

[0230] Once this symmetry problem is solved, the number of threshold shifts via the variations in the voltages of the pairs of complementary bit lines BL, BLb is adapted to the number of activated word lines WL. The maximum value of the counter (or down counter) 88 is then equal to the number of activated word lines WL plus one. The voltages of the pairs of complementary bit lines BL, BLb which are symmetrical with respect to the threshold of the inverter correspond to the middle threshold, an upward shift will correspond to a lower threshold, and a downward shift will correspond to a higher threshold. In the case where the number of word lines WL is even, the person skilled in the art will understand that the lowest threshold should not be considered, which simply corresponds to the memory cell 12 associated with the parity word line WL_p.

[0231] The advantage of this example of [Fig.10] is that by activating only the necessary word lines WL, the current in the columns 18 is greatly reduced. The memory cell 12 used is also a 2T2R cell, rather than a 4T4R memory cell in the examples of figures 2, 4 and 7. In addition, this example of [Fig. 10] also makes it possible to reduce the number of threshold shifts via variations in the voltages of the pairs of complementary bit lines BL, BLb, this number adapting according to the number of activated word lines WL.

[0232] Alternatively, no parity word line is added, and the electronic circuit 10 then further comprises a control unit configured to analogically adapt the voltages of the pairs of complementary bit lines BL, BLb in the case where the number of activated word lines WL is odd.

[0233] In the example of [Fig. 11], the calculation operation performed by the electronic circuit 10 is an AND operation on binary operands, or an OR operation on binary operands, or even a Majority operation among binary operands.

[0234] In the example of [Fig. 11], the distribution 40 of the voltages of the source line SL is similar to that of [Fig. 5], described previously, and comprises the plurality of lobes 42, each lobe 42 representing a probability density of the voltage of the source line SL for a given pop value. The number of lobes 42 contained in the distribution 40 is then equal to the number of possible values ​​of the voltage of the source line S(VL), i.e. n+1, with n representing the number of input lines IN;.

[0235] The number of threshold values ​​necessary to determine the value of the voltage of the source line SL among these n+1 lobes 42 is then equal to n, these values ​​of a threshold th being noted respectively th=0 to th=nl in the example of [Fig.l 1], with n=5.

[0236] However, when the calculation operation performed is the AND operation on binary operands, or the OR operation on binary operands, or the Majority operation among binary operands, the person skilled in the art will observe that only one threshold is necessary each time.

[0237] Indeed, the AND operation on the plurality of binary operands is equal to 1 if and only if all the binary operands are equal to 1, and equal to 0 in all other cases. The threshold is then positioned so as to be able to detect this voltage probability density lobe corresponding to the case where all the operands are equal to 1, and then determine whether all the operands are equal to 1 or not, then deduce the result of the AND operation.

[0238] Conversely, the OR operation on the plurality of binary operands is equal to 0 if and only if all the binary operands are equal to 0, and equal to 1 in all other cases. The threshold is then positioned so as to be able to detect this voltage probability density lobe corresponding to the case where all the operands are equal to 0, and then determine whether all the operands are equal to 0 or not, then deduce the result of the OR operation.

[0239] In the above-mentioned coding logic example where the binary value is encoded equal to 1, with for the first pair of memristors 28, 30 (or the only pair in the example of [Fig. 10]), the left memristor, i.e. the first memristor 28, is coded in high resistance (high state HRS), and the right memristor, i.e. the second memristor 30, is coded in low resistance (low state LRS), the only threshold used is then the lowest threshold to implement the AND operation, and respectively the highest threshold to implement the OR operation, and respectively again the middle threshold for the Majority operation, as shown in [Fig.l 1].

[0240] The calculation operation then makes it possible to perform a logical AND, or a logical OR, or even a logical Majority for each column 18 separately for all the rows 16 of the matrix 14, and this only for the rows whose word lines WL are activated. The electronic circuit 10 according to this example of the invention then makes it possible to activate several rows 16 in parallel to perform the Boolean calculation - namely logical AND, or logical OR, or even a logical Majority - bit by bit on several inputs in parallel.

[0241] Generally, the value of the INV* switching threshold depends on the associated calculation operation.

[0242] In the example of [Fig. 11], when the associated calculation operation is the operation AND or OR operation, the value of the switching threshold INVth is typically one voltage step away from a corresponding bit line voltage BL, BLb, the corresponding bit line voltage BL, BLb being one of the complementary bit line voltages BL, BLb for the AND operation and the other of said voltages for the OR operation.

[0243] The voltage step typically verifies the following equation:

[0244] [Math. 8] n_ dBL

[0245] where P represents the voltage step;

[0246] ABL represents the voltage differential between the voltage of the bit line BL and the voltage of the complementary bit line BLb, and

[0247] OPD represents the number of operands to which the calculation operation is applied.

[0248] In the example of [Fig. 11], when the associated calculation operation is the Majority operation, the value of the switching threshold INVth is typically the median value of the complementary bit line voltages BL, BLb. All cases where the result of the Majority operation is equal to 1 then correspond to voltage probability density lobes 42 arranged on the same side of this median threshold; and all cases where the result of the Majority operation is equal to 0 then correspond to voltage probability density lobes 42 arranged on the other side of said median threshold.

[0249] As an optional addition, the reading module 24 further comprises a combination unit 90 for at least one column 18, each combination unit 90 being capable of combining the results of logical operations carried out successively by a respective logical unit 50, to implement a combined logical operation. The combined logical operation is typically chosen from the group consisting of: an exclusive-or operation and a not-exclusive-or operation.

[0250] Each combination unit 90 preferably comprises a flip-flop 92 connected to the output of the respective logic unit 50. Each combination unit 90 is advantageously in the form of the flip-flop 92.

[0251] According to this optional addition, in the example of [Fig.12], each logic unit output 50, denoted inv[0] for the first column 18, then inv[l] for the second column 18, and so on, is connected to a respective flip-flop 92, each output inv[i] driving the “enable” signal 94 of the associated flip-flop 92, with i an integer index between 0 and the number of columns 18 minus one. The flip-flops 92 further have a clock input 95 receiving a clock signal CLK and an input 96 common and parallel to all the flip-flops 82. This common input 96 is driven by a control unit 98. The control unit 98 is advantageously common with that used in the control of complementary bit line pairs BL, BLb. (To be verified by the inventor)

[0252] [Fig. 12] illustrates the overall operation of such combination units 90, for example with a three-step sequence.

[0253] In a first initial step, marked by a circled 1, the contents of all flip-flops 92 are reset to 0 via the application of a clear signal, as known per se.

[0254] In a second step, marked with a circled 2, the two operands of each column 18 to which the combined logical operation, such as an exclusive-or operation, or XOR, is to be applied are first selected via the corresponding word lines WL.

[0255] In the example of [Fig. 12], during this second step, an OR operation is then performed with the two operands of each column 18, and via each respective logic unit 50, in the manner described previously with respect to [Fig.l 1]. The result of each OR operation is then applied to the Enable input of the corresponding flip-flop 92 and during a next edge of the clock signal CLK, by applying the value 1 to the common input 96 of the flip-flops 92. As a result, the flip-flops 92 whose Enable input is at “1” take the value “1” and the other flip-flops 92 whose Enable input is at “0” keep the value “0” corresponding to the previous reset step.

[0256] In a third step, marked by a circled 3, a new logical operation is performed with the two operands of each column 18, and via each respective logical unit 50.

[0257] In the example of [Fig. 12], during this third step, an AND operation is then performed with the two operands of each column 18, and via each respective logic unit 50, in the manner described previously with respect to [Fig.l 1]. An AND operation between the result of the previous OR operation and the inverse result of each AND operation (i.e. the 1-complemented result of each AND operation) is then obtained in the flip-flop 92 corresponding to the next edge of the clock signal CLK, by applying the value 0 to the common input 96 of the flip-flops 92. Indeed, during the next edge of the clock signal CLK, the value 0 on the common input 96 will be forced into the flip-flops 92 for which the “enable” signal 94 is at 1, i.e. those for which the result of the AND operation performed during the third step is equal to 1.In other words, if the NAND operation applied with the two operands of each column 18 is equal to 1, then the "enable" signal 94 is at 0, and the result of the OR operation of the second stage is then kept in the corresponding flip-flop 92.

[0258] In other words, in the example of [Fig. 12], the combination unit 90 then allows an exclusive-or operation to be performed, noted XOR, with the two operands of each column 18, taking into account the following equation:

[0259] [Math.9] XOR(a, b) = (a OR b) AND {a AND b) = (a + b) ■ (ab)

[0260] where XOR denotes the exclusive-or operation;

[0261] a and b represent the two operands;

[0262] OR, or “+”, denotes the logical operation OR;

[0263] AND, or “.”, denotes the logical operation AND; and

[0264] “ represents the NOT operator.

[0265] In the example of [Fig. 12], the result of the combined logic operation, obtained in each flip-flop 92 at the end of the sequence is then noted OP[i], with i integer index between 0 and the number of columns 18 minus one, that is to say OP[0] for the first column 18, then OP[1] for the second column 18, and so on.

[0266] Those skilled in the art will then understand that the flip-flops 92 more generally make it possible to implement any type of combination of AND or OR logic operations to perform combined logic operations, the AND or OR logic operations being performed via the logic units 50, as described previously with regard to [Fig.11].

[0267] Those skilled in the art will further observe that, if only the first two steps identified by the circled 1 and 2 are implemented, the flip-flops 92 then form a means of storing the result of the logical operations carried out by the logical units 50.

[0268] According to an optional complementary aspect, the electronic circuit 10 according to the invention further comprises additional switches, not shown, configured to connect together the source lines SL of a group of several columns 18, and then carry out the logic operations by group of columns 18, rather than by group of rows 16.

[0269] According to this complementary aspect, the logic unit 50 used to perform the logic operation for said group of columns 18 is preferably that connected to the source line SL which is capable of being connected to all the other source lines SL of the columns 18 of the group.

[0270] According to this complementary aspect, all the source lines SL are optionally connected to each other via the additional switches, which are then advantageously configured to all be closed during each calculation operation. If necessary, the second controller 22 inhibits the column(s) 18 not belonging to the group of columns 18 for which the logic operation is to be performed, by applying a high impedance potential to the pairs of complementary bit lines BL, BLb of said column(s) 18 not belonging to the group of columns 18. This then simplifies the control of additional switches.

[0271] It will be noted that it is possible in practice to combine, at the same time, the two possibilities of “combining operands” in columns 18 or in rows 16 by selecting operands on several rows 16 and by connecting the columns 18 as described above via a connection between their source lines SL.

[0272] In the examples of Figures 2, 4, 7 and 10, each memristor 28, 30 of a respective memory cell 12 is connected to the same source line SL and to a respective switch 32, 34.

[0273] Those skilled in the art will understand that, as a variant, not shown, each memory cell 12 of a respective column 18 comprises at least one pair of sub-cells, not shown, each sub-cell comprising a memristor 28, 30 and a switch 32, 34, each memristor 28, 30 of a respective sub-cell being connected to a source line and to a respective switch 32, 34. Similarly, the memristors 28, 30 of each pair of sub-cells then respectively store a binary value by respectively having different first and second resistance values. Similarly, the switches 32, 34 are connected, for their activation, to a respective word line WL and connected respectively to a pair of complementary bit lines BL, BLb, the two switches 32, 34 of a respective pair of sub-cells being connected to the same word line WL.

[0274] According to this variant, the two source lines associated with a respective pair of sub-cells are then connected to each other during each calculation operation via an auxiliary switch, not shown, to then form the same source line SL, also called source line common to the memory cells 12 of the same column 18, to which each memristor 28, 30 of a respective memory cell 12 is connected during each calculation operation.

[0275] It is thus understood that the electronic circuit 10 according to the invention makes it possible to determine more efficiently a resulting value corresponding to the voltage of the respective source line SL, by virtue of its reading module 24 comprising a logic unit 50 for each column 18 and the modification unit 60 capable of modifying, for at least one logic unit 50 and as a function of the calculation operation, the difference between the column value and the switching threshold value INVth of the corresponding logic unit 50.

Claims

1. Claims Electronic circuit (10) capable of implementing calculation operations each providing a binary output, the circuit comprising: - word lines (WL); - pairs of complementary bit lines (BL, BLb); - source lines (SL); - a set of memory cells (12) organized according to a matrix (14) comprising rows (16) and columns (18), the memory cells (12) of the same row (16) being selectable by at least one word line (WL), the memory cells (12) of the same column (18) being connected to a pair of complementary bit lines (BL, BLb) and at least one source line (SL); each memory cell (12) comprising at least one pair of memristors and at least one pair of switches, each memristor of a respective memory cell (12) being connected to a respective switch and connected to the same source line (SL) during each calculation operation, each pair of memristors respectively storing a binary value by respectively having first and second different resistance values; the switches being connected, for their activation, to a respective word line (WL) and connected respectively to a pair of complementary bit lines (BL, BLb), the two switches of a respective pair being connected to the same word line (WL); - a reading module (24) implemented during each calculation operation, the reading module (24) comprising: + a logic unit (50) for each column (18), each logic unit (50) comprising at least one input terminal (52) connected to a respective source line (SL) to receive an input value called column value, the logic unit (50) being capable of performing a logic operation having a switch between a low value and a high value as a function of a comparison of the column value with respect to a switch threshold value (INVth), the logic operation performed by the logic unit (50) being an inversion during the calculation operation, and + a modification unit (60) capable of modifying, for at least one logical unit (50) and depending on the desired calculation operation, a difference between the column value and the switching threshold value (INVth).

2. Electronic circuit (10) according to claim 1, wherein the modification unit (60) is adapted to modify the difference between the column value and the flip value (INVth) ​​for a respective logic unit (50), by controlling a modification of the complementary voltages applied on the pair of complementary bit lines (BL, BLb) for the column (18) associated with said logic unit (50).

3. An electronic circuit (10) according to claim 1 or 2, wherein the modification unit (60) is adapted to modify the difference between the column value and the threshold value for a respective logic unit (50), by controlling a modification of the threshold value of said logic unit (50); said threshold value preferably being modified via a change in the supply voltage of said logic unit (50) and / or via a change in the bias voltage of a back gate of at least one transistor of said logic unit (50).

4. Electronic circuit (10) according to any one of the preceding claims, wherein the modification unit (60) is adapted to modify, incrementally according to a predefined incrementation step, said difference between the column value and the switching threshold value (INVth), to determine - from among a plurality of predefined possible values ​​- a resulting value corresponding to the voltage of the respective source line (SL) corresponding to said column value; the incrementation step depending on said plurality of possible values.

5. Electronic circuit (10) according to claim 4, wherein the reading module (24) further comprises a storage unit (80) for at least one column (18), each storage unit (80) being adapted to store the resulting value determined for the respective column (18), pending the determination of all the resulting values ​​for a respective group of several columns (18); each storage unit (80) preferably comprising a bit register (82) for storing said determined resulting value in binary form.

6. Electronic circuit (10) according to claim 4 or 5, wherein the reading module (24) further comprises an extinction unit (70) for each column (18), each extinction unit (70) being specific - after determination of the resulting value for the respective column (18) and pending determination of all the re- resulting for a respective group - to control the application of the same voltage to the pair of complementary bit lines (BL, BLb) for the circulation of a substantially zero current in the source line (SL) of the respective column (18).

7. An electronic circuit (10) according to any preceding claim, wherein each memory cell (12) comprises two pairs of memristors and two pairs of switches.

8. Electronic circuit (10) according to claim 7, wherein a first pair of switches (32, 34) is connected to a first word line (WL) assigned to an input (IN), and respectively a second pair of switches (34, 32) is connected to a second word line (WLb) assigned to the inverse of said input (IN); and wherein a first pair of memristors (28, 30) is associated with the first pair of switches (32, 34) and storing a binary value (w), and respectively a second pair of memristors (30, 28) is associated with the second pair of switches (34, 32) and storing the inverse of the same binary value (w).

9. Electronic circuit (10) according to any one of claims 1 to 6, in which each memory cell (12) comprises a single pair of memristors and a single pair of switches, each pair of memristors respectively storing a synaptic weight.

10. Electronic circuit (10) according to any one of the preceding claims, in which the logical operation performed by the logic unit (50) is an inversion, and the associated calculation operation is chosen from: a neural calculation operation, such as the MAC operation; an AND operation; an OR operation; a Majority operation.

11. Electronic circuit (10) according to claim 11, wherein the value of the switching threshold (INVth) ​​depends on the associated calculation operation; when the associated calculation operation is the AND operation or the OR operation, the value of the switching threshold (INVth) ​​preferably being at a voltage step of a corresponding bit line voltage (BL, BLb), the corresponding bit line voltage (BL, BLb) being one of the complementary bit line voltages (BL, BLb) for the AND operation and the other of said voltages for the OR operation, the voltage step satisfying the following equation: p_ ÆL ' OPM where P represents the voltage step; ABL represents the voltage differential between the bit line voltage (BL) and the complementary bit line voltage (BLb), and OPD represents the number of operands to which the computation operation is applied; when the associated computation operation is the Majority operation, the value of the switching threshold (INVth) ​​preferably being a median value of the complementary bit line voltages (BL, BLb).

12. Electronic circuit (10) according to claim 10 or 11, wherein the reading module (24) further comprises a combination unit (90) for at least one column (18), each combination unit (90) being capable of combining the results of logical operations carried out successively by a respective logical unit (50), to implement a combined logical operation; each combination unit (90) preferably comprising a flip-flop (92) connected to the output of the respective logical unit (50); the combined logical operation being more preferably chosen from the group consisting of: an exclusive-or operation and a not-exclusive-or operation.

13. Electronic circuit (10) according to any one of the preceding claims, wherein each memory cell (12) of a respective column (18) comprises at least one pair of sub-cells, each sub-cell comprising a memristor and a switch, each memristor of a respective sub-cell being connected to a respective source line and a respective switch, the memristors of each pair of sub-cells respectively storing a binary value by respectively having different first and second resistance values; the switches being connected, for their activation, to a respective word line (WL) and connected respectively to a pair of complementary bit lines (BL, BLb), the two switches of a respective pair of sub-cells being connected to the same word line (WL);the two source lines associated with a respective pair of sub-cells being connected to each other via an auxiliary switch during each calculation operation and then forming the same source line (SL) to which each memristor of a respective memory cell (12) is connected during each calculation operation.;

14. An electronic circuit (10) according to any preceding claim, wherein the electronic circuit (10) is a neuro- morphic suitable for implementing a binary output neural network, each memory cell (12) being associated with a respective synaptic weight of a neuron, and the word lines (WL) being capable of receiving input voltages during a neural calculation operation.

15. Electronic circuit (10) according to any one of the preceding claims, comprising a first controller (20) making it possible to select the memory cells (12) of a row (16) which are connected to the same word line (WL), and comprising a second controller (22) connected to the pairs of bit lines (BL, BLb) and making it possible to apply to each pair of bit lines (BL, BLb) different and symmetrical voltages with respect to a middle voltage, the voltage applied to a bit line (BL) being higher or lower than that applied to the associated complementary bit line (BLb).

16. Electronic circuit (10) according to any one of the preceding claims, in which the electronic circuit (10) comprises several distinct sets of memory cells (12) capable of operating in parallel.

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