ASSEMBLY OF INTEGRATED CIRCUIT BOARDS

Abstract

According to one aspect, a method for assembling two integrated circuit boards (W1, W2) is proposed, the method comprising: - removing by abrasion a portion of an assembly face (FINT1) of a first integrated circuit board from a periphery of the first board, and - bonding the assembly face (FINT1) of the first board to an assembly face (FINT2) of a second integrated circuit board (W2). Figure for the abstract: Fig 1

Description

Title of the invention: Integrated circuit board assembly

[0001] Some embodiments and implementation methods relate to the manufacture of integrated circuits, in particular the assembly of integrated circuit boards.

[0002] Integrated circuit board assembly allows two integrated circuit boards to be assembled by stacking them one on top of the other.

[0003] In particular, each integrated circuit board (generally referred to by the Anglo-Saxon term "wafer") is intended to contain several analogous integrated circuits, or electronic chips, mutually separated by cutting lines.

[0004] In the rest of the text, the term "plate" may sometimes be used for the sake of simplicity instead of "integrated circuit plate".

[0005] Each integrated circuit board comprises a first "FEOL" (Front End Of Line) section in which the electronic components of the integrated circuits are formed. This semiconductor board can be made of silicon.

[0006] Each wafer also includes a second "BEOL" portion (an acronym for "Back End Of Line") comprising an interconnection network integrated into one or more dielectric layers. This "BEOL" portion extends from the FEOL portion to an assembly face of the wafer. The interconnection network includes conductive tracks and / or conductive contacts on the assembly face of the wafer. The interconnection network allows the transmission of electrical signals between the electronic components of the wafer to the conductive tracks and / or conductive contacts on the assembly face of the wafer.

[0007] When the integrated circuit boards are assembled, these boards have their assembly faces assembled against each other.

[0008] The assembly of the integrated circuit boards then presents so-called 3D electronic structures, each comprising a chip from a first board assembled with a chip from a second board. The different 3D structures are mutually separated by the cutting lines.

[0009] Such a 3D structure makes it possible to reduce the lengths of electrical interconnections between the different chips in order to improve its performance in terms of speed.

[0010] The assembly of integrated circuit boards can then be cut to obtain the different 3D structures, each comprising two electronic chips stacked one on top of the other.

[0011] The use of different integrated circuit boards allows the functions of each chip in a 3D structure to be distributed. A first board can, in particular, be used to implement integrated circuits carrying out an analog part of the electronic structures, and a second board can be used to implement integrated circuits carrying out a digital part of the structures. For example, the first integrated circuit board can be used to implement image sensor detector arrays, and the second board can be used to implement integrated circuits that perform digital processing of the data generated from these detector arrays.

[0012] In particular, it is possible to achieve a hybrid bonding between the two plates. The hybrid bonding allows for the creation of dielectric-dielectric and metal-metal bonds between the bonding faces of the two plates.

[0013] Each integrated circuit board has a perimeter that defines its lateral boundaries. In particular, each board has a main area and a peripheral area extending from the main area to the perimeter of the board. The main area of ​​the board contains all the functional elements of the board, that is, the various chips. The peripheral area, on the other hand, is devoid of functional elements.

[0014] The perimeter of each plate can be rounded so that each plate has an edge roll off (known in English as "edge roll off") on its peripheral area. The edge roll off corresponds to a decrease in the height of the assembly face in the peripheral area of ​​the plate compared to the main area of ​​the plate.

[0015] The edge drop of each plate prevents satisfactory bonding of the plates because the peripheral areas of the plates are not in contact when the plates are placed against each other.

[0016] To eliminate the edge run-off of a board, it is common practice to cut a portion of the board's peripheral area to its edge. This peripheral cut, which corresponds to a mechanical contouring of the integrated circuit board in its peripheral area, is typically performed using cutting tools such as cutting blades or wheels. This cut thus creates a right-angled shoulder at the cut. However, this cut generates defects on the board's assembly face at the cut. These defects may be fragments of the board that protrude from the assembly face. These defects prevent the two boards from being bonded immediately. Indeed, these defects may leave gaps between the two assembly faces of the boards. Bonding cannot then be performed correctly in these gaps.

[0017] To eliminate defects generated by peripheral cutting, chemical mechanical polishing (CMP) can be performed. However, such chemical mechanical polishing results in a slight edge drop at the shoulder obtained after cutting. In particular, chemical mechanical polishing creates a chamfer on the shoulder obtained after cutting.

[0018] In order to eliminate this edge drop, it is common to glue the two plates together on their assembly face and then perform thermocompression to deform the integrated circuit plate at the chamfer so that it presses against the other integrated circuit plate.

[0019] The assembly process may then include an annealing process to seal the assembly.

[0020] Once annealing has been completed, an inspection of the assembly can be carried out. However, at this stage of the process, if assembly defects are identified, the plates cannot be separated and are therefore discarded. Thus, assembly defects can prove costly.

[0021] In addition, such an assembly process has the disadvantage of involving many steps, and is therefore relatively long to implement.

[0022] Furthermore, mechanical routing of the integrated circuit board is only compatible with certain types of boards. In particular, mechanical routing is not suitable for integrated circuit boards with an interconnect section having extremely low dielectric constants (usually designated by the acronym "ULK BEOL", which stands for "Ultra Low-K Back-End Of Line").

[0023] Thus, there is a need to propose solutions allowing two integrated circuit boards to be assembled in a simple and quick manner.

[0024] According to one aspect, a method for assembling two integrated circuit boards is proposed, the method comprising: - the removal by abrasion of a portion of an assembly face of a first integrated circuit board on a periphery of the first board, and - a bonding of the assembly face of the first board to an assembly face of a second integrated circuit board.

[0025] Abrasive removal is carried out in such a way as to hollow out the perimeter of the integrated circuit board to limit, or even eliminate, edge drooping on a peripheral area of ​​the first integrated circuit board. Abrasive removal may, for example, correspond to polishing an edge on the assembly face of the first board.

[0026] Unlike a conventional cut or contouring used to eliminate a With the edge removed, the abrasion removal does not generate surface defects on the plate.

[0027] The absence of surface defects on the plate allows the two plates to be bonded directly after said abrasion removal. Furthermore, the bond between the two plates is improved.

[0028] Such a process therefore makes it possible to reduce the number of steps to be carried out to assemble two integrated circuit boards.

[0029] In an advantageous embodiment, said abrasion removal makes it possible to form a peripheral hollow having a surface extending from the assembly face to the periphery of the first plate, the surface of the hollow having a rounded shape from the assembly face of the first plate to a depth in the first plate and then being flat and parallel to the assembly face from this depth to the periphery of the integrated circuit plate.

[0030] The depth is such that the hollow extends partially in the first part and extends in the second part of this first plate.

[0031] In particular, the recess is formed in a peripheral area of ​​the first integrated circuit board extending to its periphery. This peripheral area extends around a main area of ​​the first integrated circuit board. The main area of ​​the first integrated circuit board contains functional elements of the first integrated circuit board, including electronic components and an interconnection network. The peripheral area is devoid of functional elements of the first board.

[0032] Preferably, the surface of the hollow has, at the intersection between this surface and the assembly face, a tangent oriented with respect to the assembly face at an angle between 5 and 20 degrees.

[0033] Advantageously, the hollow extends from the periphery of the integrated circuit board over a distance of between 1 and 4 mm.

[0034] In an advantageous embodiment, the hollow is formed over a depth of between 50 and 150 pm.

[0035] Preferably, the rounded shape of the hollow has a radius of curvature between 1 and 10 mm, in particular on the order of 5 mm.

[0036] Advantageously, the removal by abrasion of the portion of the first integrated circuit board is carried out using at least one abrasive strip placed against the assembly face on the periphery of the first integrated circuit board while rotating the first integrated circuit board.

[0037] In an advantageous embodiment, the surface of the abrasive ribbons has an abrasive face comprising abrasive diamonds.

[0038] Preferably, the bonding is a molecular adhesion bonding.

[0039] Advantageously, the method further comprises a conformity check of the collage.

[0040] Furthermore, checking the bonding at this stage of the process avoids the need for post-bonding thermocompression. Indeed, the thermocompression typically used to improve the bond between the two plates is unnecessary here because the bond quality has already been checked.

[0041] In an advantageous embodiment, the process further includes annealing after bonding.

[0042] Annealing also seals the assembly of the two plates. The plates can no longer be disassembled after this annealing.

[0043] In particular, annealing can create covalent bonds between the conductive traces on the assembly face of the first integrated circuit board and the conductive traces on the assembly face of the second integrated circuit board. The two integrated circuit boards are then electrically connected.

[0044] Advantageously, annealing is carried out after checking the conformity of the bonding.

[0045] Checking the bonding at this stage of the process makes it possible to detect defects in the bonding while it is still possible to separate the two integrated circuit boards before re-bonding. Thus, detecting bonding defects at this stage of the process makes it possible to avoid discarding the two bonded boards.

[0046] Preferably, the method further includes an inspection of the assembly of the two integrated circuit boards after annealing. This inspection verifies the conformity of the assembly after annealing.

[0047] In an advantageous embodiment, each integrated circuit board comprises a first part comprising electronic components and a second part comprising interconnection networks integrated in one or more dielectric layers, the interconnection networks extending from said electronic components to the assembly face of the corresponding board, the interconnection networks of the two integrated circuit boards being adapted to be electrically connected via the two assembly faces once the two integrated circuit boards are assembled.

[0048] According to another aspect, an assembly of integrated circuit plates is proposed, obtained by implementing an assembly process as described above.

[0049] According to yet another aspect, an assembly of two integrated circuit boards is proposed, comprising a first integrated circuit board having an assembly face and a peripheral recess having a surface extending from the assembly face to the periphery of the first board, the surface of the recess having a rounded shape from the assembly face of the first board to a depth in the first board and then being flat and parallel to the assembly face from this depth to the periphery of the first board. integrated circuits.

[0050] The assembly also includes a second integrated circuit board having an assembly face glued to the assembly face of the first board.

[0051] According to one embodiment, the surface of the hollow has, at the intersection between this surface and the assembly face, a tangent oriented with respect to the assembly face at an angle between 5 and 20 degrees.

[0052] According to one embodiment, the hollow extends from the periphery of the first integrated circuit plate over a distance of between 1 and 4 mm.

[0053] According to one embodiment, the depth of the peripheral hollow is between 50 and 150 pm.

[0054] According to one embodiment, the rounded shape of the hollow has a radius of curvature between 1 and 10 mm, in particular on the order of 5 mm.

[0055] According to one embodiment, each integrated circuit board comprises a first part comprising electronic components and a second part comprising interconnection networks integrated in one or more dielectric layers, the interconnection networks extending from said electronic components to the assembly face of this integrated circuit board, the interconnection networks of the two integrated circuit boards being electrically connected via the two assembly faces.

[0056] According to one embodiment, said depth is such that the hollow extends partially in the first part and extends in the second part of the first plate.

[0057] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings in which:

[0058] [Fig.l];

[0059] [Fig.2] ;

[0060] [Fig.3] ;

[0061] [Fig.4] ;

[0062] [Fig.5] ; and

[0063] [Fig.6] schematically illustrate methods of implementation and realization of the invention.

[0064] Fig. 1 illustrates an implementation of a method for assembling two integrated circuit boards W1, W2. Such an assembly method is used to assemble two integrated circuit boards W1, W2 stacked one on top of the other so as to obtain in the end an example of assembly such as that illustrated in Fig. 6.

[0065] The assembly of the W1, W2 plates can be permanent or temporary. In particular, a permanent assembly can be implemented to obtain an electronic structure. in which the plates are stacked. These plates W1, W2 then respectively present assembly faces FINT1, FINT2 assembled against each other ([Fig.6]).

[0066] The assembly can be carried out so that the plates W1, W2 are electrically connected to each other via their assembly faces, as schematically illustrated in the lower part of [Fig. 2]. In particular, each plate W1, W2 may have electrically conductive tracks and / or electrically conductive contacts on its assembly face. In order to electrically connect the two plates W1, W2, they are assembled by placing the conductive tracks and / or conductive contacts of one plate opposite and in contact with the conductive tracks and / or conductive contacts of the other plate.

[0067] The assembly of the integrated circuit boards is then a 3D assembly which presents so-called 3D ("three-dimensional") electronic structures, each comprising a chip from a first board assembled with a chip from a second board. The different 3D structures are mutually separated by the cutting lines.

[0068] Such a 3D structure makes it possible to reduce the lengths of the electrical interconnections between the two chips that compose it, in order to improve its performance in terms of speed.

[0069] The assembly of integrated circuit boards can then be cut to obtain the different 3D structures, each comprising two electronic chips stacked one on top of the other.

[0070] As mentioned above, the use of different integrated circuit boards allows functions to be distributed across each chip of a 3D structure. A first board can be used to implement integrated circuits carrying out an analog part of the electronic structures, and a second board can be used to implement integrated circuits carrying out a digital part of the structures. For example, the first board, W1, can be used to implement image sensor detector arrays, and the second board, W2, can be used to implement integrated circuits carrying out digital processing of the data generated from these detector arrays.

[0071] Figures 3 to 6 schematically represent all or part of the two integrated circuit boards W1 and W2 without detailing the individual 3D structures.

[0072] More specifically, as illustrated in [Fig.2], each plate includes a first part "FEOL" (acronym for the Anglo-Saxon expression "Front End Of Line") in which the electronic components of the chips are formed.

[0073] Each integrated circuit board also includes a second part "BEOL" (acronym for the Anglo-Saxon expression "Back End Of Line") comprising interconnection networks integrated into one or more layers electrical. This second part, "BEOL," extends from the first part, FEOL, to the assembly face of the integrated circuit board. In particular, the interconnection networks of the second BEOL extend from the electronic components of the first FEOL to the respective assembly face of the integrated circuit boards.

[0074] More particularly, the first plate W1 comprises a first part FEOL1 and a second part BEOL1 which extends to the assembly face FINT1 of the first plate Wl.

[0075] The second integrated circuit plate W2 comprises a first part FEOL2 and a second part BEOL2 up to the assembly face FINT2 of the second plate W2 ([Fig.6]).

[0076] Furthermore, each plate has a perimeter that laterally delimits the plate. In particular, the first plate W1 has ([Fig. 3]) a main area ZC and a peripheral area ZP extending around the main area to the perimeter of the plate. [Fig. 3] illustrates only a cross-sectional view of the first plate W1, so only one side of the integrated circuit plate is shown. The main area ZC of the first plate W1 includes all the functional elements of the first plate, i.e., the electronic components and the interconnect networks. The peripheral area ZP, on the other hand, does not contain any functional elements of the first plate. The peripheral area ZP can extend, for example, over a distance DI of between 1 and 4 mm from the perimeter of the plate W1, for example, on the order of 3 mm.

[0077] The perimeter of each plate can be rounded so that each plate has an edge roll off (known in English as "edge roll off") on its peripheral area. The edge roll off corresponds to a decrease in the height of the assembly face in the peripheral area of ​​the plate compared to the main area of ​​the plate.

[0078] The assembly process is used to perform a hybrid bonding process to create bonds between the dielectric layers of the BEOL1 and BEOL2 parts of the Wl, W2 integrated circuit boards and bonds between the conductive tracks on the FINT1 assembly face of the Wl board and the conductive tracks on the FINT2 assembly face of the W2 board.

[0079] As illustrated in [Fig.1], the process includes obtaining 100 of the first integrated circuit board W1 and the second integrated circuit board W2.

[0080] The process then includes removing material by abrasion 101 from a portion of the periphery of the assembly face of the first plate WL. The material removal by abrasion 101 makes it possible to hollow out the assembly face FINT1 from the periphery of the first plate WL so as to hollow out the assembly face FINT1 in the peri-zone The peripheral area ZP of the first plate Wl is removed from its periphery. Thus, material removal by abrasion 101 creates a peripheral hollow EDG in the peripheral area ZP of the integrated circuit plate Wl, as illustrated in [Fig. 4]. The hollow extends partially into the first part FEOL1 and into the second part BEOL1 of the plate Wl.

[0081] In particular, the EDG cavity has a surface S_BVL extending from the assembly face FINT1 to the periphery of the plate W1. The surface S_BVL of the cavity has a rounded shape from the assembly face FINT1 of the first plate W1 to a given depth in the first plate W1, then is flat and parallel to the assembly face FINT1 from this depth to the periphery of the first integrated circuit plate FINT1.

[0082] More specifically, the EDG depression is formed over a depth DEVD of between 50 and 150 µm, in particular on the order of 100 µm. The EDG depression extends into the peripheral zone ZP of the WL plate. The EDG depression therefore extends from the periphery of the WL plate over a distance DZP of between 1 and 4 mm, in particular on the order of 3 mm.

[0083] Furthermore, the surface S_BVL of the EDG cavity has, at the intersection between this surface S_BVL and the assembly face FINT1, a tangent at least substantially orthogonal to the assembly face FINT1. For example, the angle between this tangent and the assembly face FINT1 is between 5 and 20 degrees.

[0084] In particular, the rounded shape of the hollow has a radius of curvature between 1 and 10 mm, in particular on the order of 5 mm.

[0085] The removal 101 can be carried out by a polishing machine. The polishing machine includes a support platform (not shown) that can be rotated about itself around an axis orthogonal (Y) to this support platform and passing through its center.

[0086] As illustrated in [Fig. 5], the polishing machine includes at least one ribbon FLM abrasive configured to be applied against the perimeter of the FINT1 assembly face of the first WL plate

[0087] In particular, each FLM strip has an abrasive face. This abrasive face can be placed against the periphery of the FINT assembly face of the first plate WL. To give it an abrasive property, diamonds are bonded to the abrasive face. These diamonds allow material to be removed from the first plate W1 when the strip is set in motion.

[0088] Each FLM strip is configured to be unwound, i.e., driven in translation along its longitudinal direction, against the periphery of the first plate W1 on the assembly face FINT1 of the peripheral zone ZP so as to hollow out the first plate WL

[0089] To form the peripheral hollow EDG, each abrasive strip FLM is brought into contact with the periphery of the assembly face FINT1 and unrolled while rotating the first plate W1, causing the support platform to rotate.

[0090] Removing a portion of the FINT1 assembly face in the peripheral zone ZP of the first plate W1 by abrasion eliminates the edge droop of the first plate W1. Furthermore, the abrasion removal creates the peripheral recess EDG with a rounded profile, which limits, or even prevents, the appearance of defects at the periphery of the main zone ZC, such as those that can appear at the abrupt cut made during mechanical trimming in the prior art.

[0091] The process then includes a molecular adhesion bonding 102 (also known by the Anglo-Saxon expression "fusion bonding") of the assembly face FINT1 of the first plate of W1 to the assembly face FINT2 of the second plate W2.

[0092] As illustrated in [Fig.6], the 102 molecular adhesion bonding allows BND bonds to form between the dielectric layer of the second part BEOL1 of the first plate W1 and the dielectric layer of the second part BEOL2 of the second plate W2.

[0093] The absence of a defect in the periphery of the main zone ZC of the plate W1 following the removal 101 by abrasion of a portion of the peripheral zone ZP carried out to eliminate the edge drop of the plate W1 makes it possible to improve the bonding 102 by molecular adhesion.

[0094] The process then includes a control 103 of the molecular adhesion bonding 102 of the two plates W1, W2. This control 103 verifies that the molecular adhesion bonding 102 of the two plates W1, W2 has been performed correctly. This control is carried out, for example, by analyzing the assembly using acoustic waves in an aqueous medium. In particular, if the control 103 detects that the assembly is non-compliant, then the plates can be separated to perform the retraction 101 again before re-bonding the two integrated circuit plates by molecular adhesion.

[0095] This control 103 can be easily carried out following the molecular adhesion bonding 102 due to the shape of the peripheral cavity EDG, which prevents moisture from the aqueous environment from penetrating between the plates W1, W2, which could lead to bonding defects. In particular, as seen previously, the surface S_BVL of the peripheral cavity EDG has, at the intersection between this surface S_BVL and the assembly face FINT1, a tangent at least substantially orthogonal to the assembly face FINT1 of the integrated circuit plate W1. This tangent is also at least substantially orthogonal to the assembly face FINT2 of the integrated circuit plate W2 once the molecular adhesion bonding 102 has been carried out. From the Thus, the periphery of the main zone ZC of plate W1 is in good contact with plate W2. Therefore, moisture from the aqueous environment cannot penetrate between the two plates W1 and W2 during test 103.

[0096] Checking the bonding 102 by molecular adhesion at this stage of the process makes it possible to detect defects in the bonding while it is still possible to separate the two integrated circuit boards W1, W2 before repeating the bonding. Thus, detecting bonding defects at this stage of the process makes it possible to avoid discarding the two bonded integrated circuit boards.

[0097] Furthermore, checking the bonding 102 at this stage of the process avoids the need for thermocompression following molecular adhesion bonding. Indeed, the thermocompression typically used to improve the bonding of the two integrated circuit boards is unnecessary here because the quality of the molecular adhesion bonding 102 has already been checked.

[0098] The process then includes an annealing step 104 (also known by the English term "anneau"). Annealing step 104 creates BND covalent bonds between the conductive tracks on the assembly face FINT1 of the W1 board and the conductive tracks on the assembly face FINT2 of the W2 board. The two integrated circuit boards W1 and W2 are then electrically connected. Annealing step 104 also seals the assembly of the two W1 and W2 boards. The W1 and W2 boards cannot be disassembled after this annealing step 104. The annealing can be carried out at a temperature between 200°C and 450°C, particularly around 350°C, for a duration of between 1 and 4 hours, particularly around 2 hours.

[0099] The process then includes a check 105 to verify the conformity of the assembly of the plates W1, W2. In particular, the check 105 makes it possible to verify the conformity of the BND bonds formed during the annealing 104.

[0100] The assembly of the integrated circuit boards W1, W2 can then be cut to obtain the different 3D electronic structures, each comprising several superimposed integrated circuits.

[0101] Such a method for assembling integrated circuit boards has the advantage of being faster than known assembly methods. Indeed, such a method does not require heat compression between the molecular adhesion bonding 102 and the annealing 104. Furthermore, since the adhesion bonding 102 is improved, it is possible to more quickly check the conformity of the assembly of the integrated circuit boards W1, W2.

[0102] Such an assembly process also has the advantage of reducing the scrapping of integrated circuit boards due to irreversible assembly defects. This assembly process therefore reduces the manufacturing costs of stacked electronic chips.

[0103] The assembly process described above makes it possible to obtain an assembly of a first plate W1 and a second plate W2 of integrated circuits stacked one on top of the other, as illustrated in [Fig.6].

[0104] The following are recalled characteristics of an assembly of integrated circuit boards W1 and W2 according to an embodiment of the invention, as illustrated in this [Fig.6]

[0105] The first plate W1 and the second plate W2 each comprise a first portion FEOL1, FEOL2 which includes electronic components and a second portion BEOL1, BEOL2 which includes interconnection networks integrated into one or more dielectric layers. The plates W1 and W2 also each comprise an assembly face FINT1 and FINT2. The interconnection networks of the second portions BEOL1, BEOL2 extend, in each of the plates W1, W2, from the electronic components to the respective assembly face of each plate W1, W2.

[0106] The FINT2 assembly face of the second board W2 is bonded to the FINT1 assembly face of the first board WL. The interconnect networks of the first board WL and the second board W2 are electrically connected via the FINT1 and FINT2 assembly faces, in particular through BND covalent links between conductive traces on the FINT1 assembly face of the integrated circuit board WL and conductive traces on the FINT2 assembly face of the integrated circuit board W2.

[0107] The first integrated circuit board W1 further comprises a peripheral recess EDG. The peripheral recess EDG extends into a peripheral area ZP of the first integrated circuit board and, in particular, from the periphery of the first integrated circuit board W1 over a distance DZP of between 1 and 4 mm. In addition, the recess EDG has a depth DEVD of between 50 and 150 µm, for example, on the order of 100 µm.

[0108] The peripheral hollow EDG has a surface S_BVL which extends from the assembly face FINT1 to the periphery of the first plate WL. The surface S_BVL of the hollow has a rounded shape from the assembly face FINT1 of the first plate W1 to a depth in the first plate WL. In particular, the rounded shape of the hollow EDG has a radius of curvature between 1 and 10 mm, in particular on the order of 5 mm.

[0109] The S_BVL surface of the EDG cavity is, moreover, flat and parallel to the assembly face FINT1 from this depth to the periphery of the first integrated circuit board WL. The S_BVL surface of the cavity also has, at the intersection between this S_BVL surface and the assembly face FINT1, a tangent oriented with respect to the assembly face FINT1 at an angle between 5 and 20 degrees.

Claims

Demands

1. Method for assembling two integrated circuit boards (Wl, W2), the method comprising: - removing by abrasion a portion of an assembly face (FINT1) of a first integrated circuit board (Wl) on a periphery of the first board (Wl), and - bonding by molecular adhesion of the assembly face (FINT1) of the first board (Wl) to an assembly face (FINT2) of a second integrated circuit board (W2), the method further comprising checking the conformity of the bonding.

2. A method according to claim 1, wherein said abrasion removal makes it possible to form a peripheral hollow (EDG) having a surface (S_BVL) extending from the assembly face (FINT1) to the periphery of the first plate (Wl), the surface (S_BVL) of the hollow having a rounded shape from the assembly face (FINT1) of the first plate (Wl) to a depth in the first plate (W1) and then being flat and parallel to the assembly face from this depth to the periphery of the first integrated circuit plate (Wl).

3. Method according to claim 2, wherein the surface (S_BVL) of the hollow (EDG) has, at the intersection between this surface (S_BVL) and the assembly face (FINT1), a tangent oriented with respect to the assembly face (FINT1) at an angle between 5 and 20 degrees.

4. A method according to any one of claims 2 or 3, wherein the hollow (EDG) extends from the periphery of the first integrated circuit plate (Wl) over a distance (DZP) of between 1 and 4 mm.

5. A method according to any one of claims 2 to 4, wherein the hollow (EDG) is formed over a depth (DEVD) of between 50 and 150 pm.

6. A method according to any one of claims 2 to 5, wherein the rounded shape of the hollow (EDG) has a radius of curvature between 1 and 10 mm, in particular of the order of 5 mm.

7. A method according to any one of claims 1 to 6, wherein the removal by abrasion of the portion of the first integrated circuit board (Wl) is carried out using at least one abrasive strip (FLM) placed against the assembly face (FINT1) around the periphery of the first integrated circuit board (Wl) while simultaneously removing the first integrated circuit board (Wl) rotating.

8. A method according to claim 7, wherein the surface of the abrasive ribbons (FLM) has an abrasive face comprising abrasive diamonds.

9. A method according to any one of claims 1 to 8, further comprising annealing after gluing.

10. Method according to claim 9, annealing is carried out after checking the conformity of the bonding.

11. A method according to any one of claims 9 or 10, further comprising checking the assembly of the two integrated circuit boards (W1, W2) after annealing.

12. A method according to any one of claims 1 to 11, wherein each integrated circuit board (Wl, W2) comprises a first part (FEOL1, FEOL2) having electronic components and a second part (BEOL1, BEOL2) having interconnect networks integrated in one or more dielectric layers, the interconnect networks extending from said electronic components to the assembly face (FINT1, FINT2) of this integrated circuit board, the interconnect networks of the two integrated circuit boards (Wl, W2) being adapted to be electrically connected via the two assembly faces (FINT1, FINT2) once the two integrated circuit boards (Wl, W2) have been assembled.

Images