Connection circuit for memory access

Abstract

Connection circuit for memory access The present description relates to a connection circuit (116, 118) connecting a first circuit (112, 114) of a device (100) to a bus (110) configured to allow access to an addressable memory space (106, 108) of the device, the connection circuit being configured to:- receive an input address, transmitted by the first circuit, the input address corresponding to an address in a first or in a second address range of the addressable memory space, the addressable memory space further comprising a third address range, not addressable by the first circuit; - compare the input address with a threshold address; - based on the comparison, generate a part of an output address, the output address belonging to the second or the third address range of the addressable memory space; and- provide the part of the output address to the bus (110). Figure for abstract: Fig. 1

Description

Title of the invention: Connection circuit for memory access Technical field

[0001] The present description generally relates to access to a memory space by a circuit such as a peripheral circuit of the device or a direct memory access circuit. Prior art

[0002] Certain electronic devices comprise an addressable memory space, at least a portion of which is not addressable by certain peripheral circuits.

[0003] Indeed, some devices include, for example, 64-bit processors having access to a memory space of more than 4 Gigabytes. However, these devices may also include 32-bit peripherals or direct memory access circuits (in English "Direct Memory Access Circuits" or "DMA Circuits"), which are limited and do not have the possibility of addressing all the address ranges of the memory space.

[0004] There is a need to make address ranges accessible to a peripheral circuit, and / or another circuit, which are not directly addressable by this circuit. Summary of the invention

[0005] One embodiment provides a connection circuit connecting a first circuit of a device to a bus configured to provide access to an addressable memory space of the device, the connection circuit being configured to: - receiving an input address, transmitted by the first circuit, the input address corresponding to an address in a first or in a second address range of the addressable memory space, the addressable memory space further comprising a third address range, not addressable by the first circuit; - compare the input address with a threshold address; - based on the comparison, generating a portion of an output address, the output address belonging to the second or third address range of the addressable memory space; and - provide the output address part to the bus.

[0006] According to one embodiment, the part of the output address comprises one or more additional address bits, and the connection circuit is configured to provide the bus with said one or more additional address bits as the most significant bits of the output address.

[0007] According to one embodiment, the above circuit is further configured to: - if the input address belongs to the second address range, generate one or several most significant bits of the output address to the binary value "0"; and - if the input address belongs to the first address range, generate one or more most significant bits of the output address to the binary value "1".

[0008] One embodiment provides a device comprising: - one or more memory circuits defining an addressable memory space comprising a first, a second and a third address range; - a first circuit not being capable of generating an address forming part of the third address range; - the connection circuit above connecting the first circuit to the addressable memory space.

[0009] According to one embodiment, the above device further comprises a processor, wherein the connection circuit further comprises a register, programmable by the processor, the register being configured to store a first bit whose value is defined if the circuit is in a first state or in a second state, the second state being a state in which the connection circuit is deactivated.

[0010] According to one embodiment, the register is configured to store a second bit, programmable by the processor and the programming of which locks the state of the connection circuit to the state defined by the value of the first bit.

[0011] According to one embodiment, the processor is a 64-bit processor and the first circuit is a 32-bit peripheral circuit.

[0012] According to one embodiment, the memory space comprising the second and third address ranges is implemented by a volatile memory, the third address range being addressable by the processor.

[0013] According to one embodiment, the first circuit is a peripheral circuit of the device.

[0014] According to one embodiment, the first circuit is a direct memory access circuit, the direct memory access circuit being configured to send, based on the contents of a register, an activation signal to the connection circuit, the activation signal programming the connection circuit in the first state.

[0015] According to one embodiment, the first circuit is configured to transmit the input address to the bus connected to the addressable memory space and in which the output address corresponds to the concatenation of the input address with the part of the output address provided by the connection circuit.

[0016] According to one embodiment, the memory space comprising the first address range is implemented by an internal memory of the device.

[0017] One embodiment provides a method comprising: - the transmission, by a first circuit of a device, of an input address, to a connection circuit of the device, the connection circuit connecting the first circuit to a bus configured to provide access to an addressable memory space of the device, the input address corresponding to an address in a first or second address range of an addressable memory space, the addressable memory space further comprising a third address range, not addressable by the first circuit; and - the comparison by the connection circuit of the input address with a threshold address; and - based on the comparison, generating, by the connection circuit, a part of an output address, the output address belonging to the second or third address range of the addressable memory space; and - provide the output address part to the bus.

[0018] According to one embodiment, the above method further comprises: - transmit, by the first circuit, the input address to the bus connected to the addressable memory space, the output address corresponding to the concatenation of the input address with the part of the output address provided by the connection circuit. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] is a block diagram of an electronic device according to an embodiment of the present description;

[0021] [Fig.2] illustrates an example of memory space addressable by a 32-bit peripheral circuit;

[0022] [Fig.3] illustrates an example of memory space addressable by a 64-bit processor;

[0023] [Fig.4] is a block diagram illustrating a connection circuit connecting a peripheral circuit to an addressable memory space;

[0024] [Fig.5] illustrates an example of memory space addressable by a 32-bit peripheral circuit according to an embodiment of the present description;

[0025] [Fig.6] is an example illustrating a configuration register of the connection circuit;

[0026] [Fig.7] is a block diagram illustrating a connection circuit connecting a direct memory access circuit to an addressable memory space; and

[0027] [Fig.8] is a flowchart illustrating steps of a method of accessing addressable memory space. Description of the embodiments

[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0033] [Fig.l] is a block diagram of an electronic device 100 comprising a processing device 102 according to an embodiment of the present description.

[0034] The electronic device 100 is for example an electronic card such as a microcircuit card, hardware for computer use, a microprocessor circuit, etc.

[0035] The processing device 102 comprises for example a processor 104 (CPU) connected to memories 106 (NV MEM) and 108 (MEM) via a bus 110. By way of example, the memory 106 is a non-volatile memory, for example an internal memory of the device. The memory 108 is a volatile memory, for example of the DDR SDRAM type (from the English "Double Data Rate Synchronous Dynamic Random Access Memory"). In another example, the memory 106 is a Flash type memory connected via a connector to the bus 110.

[0036] The processing unit 102 comprises for example a peripheral circuit 112 (PERIPH). For example, the peripheral circuit is a graphics card, a communication interface, or another type of circuit capable of accessing at least part of the memory space defined by the memories of the device. According to one embodiment, the peripheral circuit 112 does not have access to the entire addressable memory space formed by the memories 106 and 108. For example, the peripheral circuit 112 is configured to manipulate words of length strictly less than the words manipulated by the processor 104, and therefore to generate addresses which are also of length strictly less than the addresses generated by the processor 104. The addressable memory space formed by the memories 106 and 108 is for example sized according to the addressing capabilities of the processor 104, and is then not entirely directly addressable by the peripheral circuit 112. For example, an address range of the memory space is not directly addressable by the peripheral circuit 112. In another example, the size of the words manipulated by the peripheral circuit 112 is for example adapted, by the processor 104, in order to be supported by the memories 106 and 108. Nevertheless, an area of ​​the addressable memory space remains inaccessible for the peripheral circuit 112. For example, the memory area inaccessible by the peripheral circuit 112 is a memory area included in the memory 108.

[0037] In one example, the processor 104 is for example a 64-bit processor, configured to handle words having a size of up to 64 bits. For example, the memory space formed by the memories 106 and 108 is larger than 4 Gigabytes, for example 6 Gigabytes. For example, the memory 106 is 2 Gigabytes in size and the memory 108 is 4 Gigabytes in size.

[0038] The processor 104 is for example capable of addressing the entire addressable memory space corresponding to the memories 106 and 108. The peripheral circuit 112 is for example a 32-bit address peripheral. For example, a portion of the memory 108 is not addressable by the peripheral circuit 112.

[0039] The processing unit 102 comprises, for example, in addition to, or instead of, the peripheral circuit 112, a direct memory access (DMA) circuit 114. For example, the direct memory access circuit 114 is a 32-bit circuit, and this circuit therefore has the same limitations in terms of addressing capabilities as the peripheral circuit 112.

[0040] According to one embodiment, the peripheral circuit 112 is connected to the bus 110 via a connection circuit 116 and / or the direct memory access circuit 114 is connected to the bus 110 via a connection circuit 118.

[0041] According to one embodiment, the connection circuit 116 is configured to generate an output address based on an input address provided by the peripheral circuit 112, and to provide it to the bus 110. Similarly, the connection circuit 116 is configured to generate an output address based on an input address provided by the direct memory access circuit 114, and to provide it to the bus 110. For example, the input address provided by the circuits 112 and 114 are 32-bit addresses, and the output address is a 33-bit address. In some cases, the connection circuits 116 and 118 are configured to generate only the most significant bit(s), for example the 33rd bit, of the output address.

[0042] [Fig.2] illustrates an example of memory space directly addressable by the peripheral circuit 112 and / or the direct memory access circuit 114. By way of example, the peripheral circuit 112 and / or the direct memory access circuit 114 are 32-bit circuits.

[0043] For example, the memory 106 is addressable via addresses having hexadecimal values ​​0x00000000 to the neighboring value less than 0x80000000 and the memory 108 comprises an area 200 (LOW DRR) which is addressable via addresses having hexadecimal values ​​0x80000000 to the neighboring value less than 0x100000000. The memory 106 is then, for example, a memory of size 2 Gigabytes and the memory area 200 is also a memory of size 2 Gigabytes. The peripheral circuit 112 and / or the direct memory access circuit 114 is then capable of accessing the 4 Gigabytes formed by the memory 106 and the memory area 200.

[0044] The address ranges defining the memory 106 as well as the memory area 200 are given as an example and are of course not limiting, either by their size or by their values.

[0045] [Fig.3] illustrates an example of memory space addressable by the processor 104. For example, the processor 104 is a 64-bit processor.

[0046] By way of example, the memory space addressable by the processor 104 comprises the address ranges associated with the memory 106. By way of example, as described in relation to [Fig. 2], the memory 106 is addressable via addresses having a hexadecimal value between 0x00000000 and the neighboring value less than 0x80000000. The memory space addressable by the processor 104 further comprises the address ranges associated with the area 200 of the memory 108. By way of example, as described in relation to [Fig. 2], the memory 106 is addressable via addresses having a hexadecimal value between 0x80000000 and the neighboring value less than 0x100000000.

[0047] For example, the memory 108 further comprises an area 300 (HIGH DDR). For example, the area 300 is addressable via addresses having a hexadecimal value between 0x100000000 and the neighboring value less than 1x180000000. The area 300 is for example addressable by the processor 104 and is not directly addressable by the peripheral circuit 112 and / or by the direct memory access circuit 114.

[0048] [Fig. 4] is a block diagram illustrating a portion of the device 100 of [Fig. 1], and in particular the connection circuit 116 connecting the peripheral circuit 112 to the addressable memory space associated with the memories 106 and 108.

[0049] For example, the peripheral circuit 112 is a 32-bit circuit. For example, the addressable memory space comprises the address ranges described in relation to [Fig. 3]. The area 300 of the memory 108 is then not directly entirely addressable by the peripheral circuit 112.

[0050] According to one embodiment, the peripheral circuit 112 is connected to the circuit of connection 116 and to the bus 110 via a bus 400. For example, the peripheral circuit 112 provides, via the bus 400, the same addresses to the connection circuit 116 and to the bus 110. The connection circuit 116 is then connected to the bus 110 via a bus 402.

[0051] The buses 400 and 110 illustrated in [Fig.4] are for example address buses used to communicate access addresses to the memories 106, 108 during accesses, for example of the write and / or read type. Although they are not illustrated in the figures, data buses are also present between the peripheral circuit 112 and the memories, allowing data to be written to be communicated during write accesses, and / or allowing data to be read to be communicated during read accesses.

[0052] According to one embodiment, the processor 104 is configured to activate, or to deactivate, the connection circuit 116 during a startup phase. For example, an instruction of software executed by the processor 104 causes the activation of the connection circuit 116 depending on the memory that this software is configured to access. For example, when the processing unit 102 starts, the peripheral circuit 112 is capable of accessing the address ranges associated with the memory 106 and the connection circuit 116 is for example deactivated. For example, once the startup of the circuit 104 is complete, a software instruction allows the activation of the connection circuit 116 and the peripheral circuit 112 for example no longer has access to the memory 106. For example, when the startup sequence is complete, access to the memory 106 is for example no longer useful.When, for example, software executed by the processor 104 is configured to access a memory space of a size greater than the space associated with the zone 200, a software instruction allows the activation of the connection circuit 116. Thus, the peripheral circuit 112 has, for example, access to the entire memory 108.

[0053] According to one embodiment, when the connection circuit 116 is deactivated, it does not provide, for example, any output bits on the bus 402. In another embodiment, when the connection circuit 116 is deactivated, it provides, for example, only one or more bits of binary value "0" as output on the bus 402. The peripheral circuit 112 transmits for example directly to the bus 110 one or more addresses. The address(es) then belong(s) to the address ranges associated with the memory 106 or to the memory area 200 of the memory 108. For example, the address(es) transmitted by the peripheral circuit 112 are coded on 32 bits. The area 300 of the memory 108 is then not accessible by the peripheral circuit 112 when the connection circuit 116 is deactivated.

[0054] Thus, the addresses programmed by the processor 104 are not recalculated. Indeed, the processor 104 always gives the order to the peripheral circuit 112 to access an address belonging for example to memory 106 or to zone 200. The translation of the address is carried out by the connection circuit 116 and not by the processor 112.

[0055] According to one embodiment, when the connection circuit 116 is activated, the peripheral circuit 112 transmits an input address to the connection circuit 116. The connection circuit 116 is then configured to check whether the address is, for example, greater than a threshold address. As an example, the connection circuit 116 checks whether the address is greater than 0x80000000, which corresponds, in the example described in relation to [Fig. 3], to checking whether the address transmitted by the peripheral circuit 112 is an address of the zone 106 or of the zone 200. In another example, the connection circuit 116 is configured to determine whether the address belongs to an address range, for example associated with an area of ​​the memory 106 or of the memory 108. According to one embodiment, the connection circuit 116 is configured to generate one or more bits, for example the most significant bits of an output address on the basis of the comparison.

[0056] For example, if the input address provided by the peripheral circuit 112 is greater than the threshold address, for example equal to or greater than 0x80000000, the connection circuit 116 is configured to provide no output bits on the bus 402, or to provide only one or more bits of binary value "0" as output on the bus 402. The address of the memory access, which will be called "output address" in the present description, and which is the combination of the addresses provided by bus 402 and by bus 400, in order to execute an access to the memory, is therefore equal to the input address provided by the peripheral circuit 112 on the bus 400. In the example described in relation to [Fig. 3], if the input address provided by the peripheral circuit 112 is greater than the threshold address, it belongs to the zone 200, and in this case, nothing is not modified and the peripheral circuit 112 accesses zone 200 as requested.

[0057] For example, when the processor 104 gives the order to the peripheral circuit 112 to access the memory 106, for example by indicating an address associated with the address range associated with the memory 106, and the connection circuit 116 is activated, then the peripheral circuit 112 accesses the zone 300, although the ordered address belongs to the address range defining the memory 106.

[0058] For example, if the input address provided by the peripheral circuit 112 is lower than the threshold address, for example lower than 0x80000000, the output address provided to the bus 110 is a new address, provided in part by the connection circuit 116. For example, in this case, the output address, provided to the bus 110, is an output address belonging for example to the zone 300 of the memory 108. For example, the output address is composed of the input address provided on the bus 400, and a part provided by the connection circuit 116. This part consists for example of a or more additional address bits, which are for example the most significant bit(s) of the output address. For example, the 32 least significant bits of the output address generated by the connection circuit 116 correspond to the 32 bits of the input address and the connection circuit further generates a 33rd bit, being the most significant bit, of binary value "1". Thus, an address belonging to the address range associated with the memory 106 is modified, or translated, into an address belonging to the area 300.

[0059] As an example, the connection circuit 116 is configured to program the 33rd bit to the binary value "0" when the input address belongs to the address range associated with the zone 200 and to program it to the binary value "1" when the input address belongs to the address range associated with the memory 106.

[0060] [Fig.5] illustrates an example of the memory space addressable by the peripheral circuit 112 when the connection circuit 116 is activated.

[0061] For example, the connection circuit 116 is configured to program a 33rd address bit with the value 1 when the value of the input address, provided by the peripheral circuit 112, belongs to the address range 0x00000000 to the neighboring address lower than 0x80000000, for example when the input address is an address of the memory 106. The area 300 of the memory 108 is then accessible by the peripheral circuit 112. For example, the connection circuit 116 is further configured to program the 33rd bit of the output address with the binary value "0" when the input address belongs to the address range from 0x80000000 to the neighboring address lower than 0x100000000, in other words when the peripheral circuit 112 wishes to access the zone 200. The input address is, in this case, not modified and the peripheral circuit 112 accesses zone 200.

[0062] [Fig.6] illustrates an example of a configuration register of the connection circuit 116.

[0063] According to one embodiment, the connection circuit 116 comprises a register 600. For example, the register 600 is at least 2 bits long, and in the example of [Fig. 6], is 32 bits long, comprising bits ranging from a bit 0 (Bit 0) to a bit 31 (Bit 31). For example, bit 0 is programmable, for example by the processor 104. For example, when the processor 104 starts up, the processor 104 determines whether the connection circuit 116 is to be activated or deactivated. For example, the software executed by the processor 104 comprises an instruction allowing the programming of bit 0 and / or bit 31. For example, the programming of bit 0 and / or bit 31 is carried out on the basis of the size of the memory 108 and / or on the allocation of memory functions carried out by the software.For example, the software includes one or more indications of the memory areas that the peripheral circuit 112 is configured to access and the programming of bit 0 and / or . of bit 31 is carried out on the basis of these indications. For example, when bit 0 (EN) of register 600 is programmed to the value 1, the connection circuit 116 is activated and when bit 0 is programmed to the value 0, the connection circuit 116 is deactivated. This programming configuration is given as an example, programming bit 0 to state 0 can, in another example, make the connection circuit 116 active.

[0064] For example, bit 31 of the register is further programmable, for example by the processor 104, when it is started. For example, the state of bit 31 indicates whether the state of the connection circuit 116, i.e., activated or deactivated, is locked (LOCK) or not. For example, programming bit 31 to state 1 implies locking, in the state indicated by the state of bit 0, of the connection circuit 116 and programming to state 0 indicates its unlocking. The locked state of the connection circuit 116 implies, for example, that bit 0 is not reprogrammable by the processor 104. For example, when the connection circuit is locked, bit 0 is reprogrammable only when the processing unit 102 is restarted.

[0065] [Fig. 7] is a block diagram illustrating a part of the device 100 of [Fig. 1], and in particular the connection circuit 118 connecting the direct memory access circuit 114 to the addressable memory space formed for example by the memories 106 and 108.

[0066] For example, the direct memory access circuit 114 comprises registers 700 (SRC ADDR) and 702 (SRC T AG). The register 700 is for example configured to store, for example temporarily, a source address. For example, the source address corresponds to an address of the addressable memory space at which there is data that the direct memory access circuit 114 is configured to access, for example in reading. For example, the direct memory access circuit 114 is a 32-bit circuit and the source address contained in the register 700 is a 32-bit address. In the example described in relation to [Fig. 3], the source address is an address belonging to the address ranges associated with the memory 106 or with the zone 200 of the memory 108. In particular, the direct memory access circuit 114 is not capable of addressing the zone 300 of the memory 108.

[0067] For example, the register 702 is configured to store an indication value, for example in the form of data of at least two bits. For example, the indication value is programmed following the execution of an instruction of software executed by the processor 104 on the basis of the source address and / or the destination address. The indication value is for example an additional indication to the source address, identifying the memory, or the memory area, which the direct memory access circuit 114 wishes to access.

[0068] The direct memory access circuit 114 further comprises registers 704 (DST ADDR) and 706 (DST TAG). For example, the register 704 is configured to store a destination address, for example coded on 32 bits. For example, the destination address corresponds to an address of the memory 106 or of the memory 108 to which the direct memory access circuit 114 wishes, for example, to write the data identified by the source address. For example, the register 706 is configured to store an indication value indicating which memory area the direct memory access circuit 114 is configured to access, for example in writing.

[0069] For example, for registers 702 and 706, a binary indication value equal to "00" indicates that the direct memory access circuit 114 will access a first area of ​​memory 106, for example reserved for storage associated with the peripheral circuit. For example, a binary indication value equal to "01" indicates that the direct memory access circuit 114 will access a second area of ​​memory 106, for example reserved for internal storage of the device 100. According to one embodiment, when the indication value indicates that the direct memory access circuit 114 wishes to access memory 106, the connection circuit 118 is deactivated. For example, an indication value equal to 10 indicates that the memory access circuit 114 wishes to access memory 108.

[0070] According to one embodiment, the direct memory access circuit 114 further comprises a control circuit 708 (EN CTRL) configured to activate the connection circuit 118. For example, the registers 702 and 704 are connected to the control circuit 708, and the control circuit 708 is configured to send an EN SIGNAL signal to the connection circuit 118 when the indication value stored in the register 702, or in the register 706, indicates that the direct memory access circuit 114 wishes to access the memory 108.

[0071] According to one embodiment, the registers 702 and 706 are configured to transmit the source address, respectively the destination address, that they contain to the bus 110, for example via a bus 710. By way of example, the 32 bits composing the source address, or the destination address, are transmitted to the bus 110 via the bus 710.

[0072] The buses 710 and 110 illustrated in [Fig.7] are for example address buses used to communicate access addresses to the memories 106, 108 during accesses, for example of the write and / or read type. Although they are not illustrated in the figures, data buses are also present between the circuit 114 and the memories, allowing data to be written to be communicated during write accesses, and / or allowing data to be read to be communicated during read accesses.

[0073] According to one embodiment, when the connection circuit 118 is activated, the circuit connection circuit is configured to compare the source address, or the destination address, with a threshold address, or with a range of addresses. For example, the connection circuit 118 is configured to determine whether the source address, or the destination address, belongs to the range of addresses associated with the memory 106. If this is the case, the connection circuit 118 is for example configured to program a 33rd address bit of the source address, or of the destination address, with the binary value "1". In this way, an address belonging to the memory 106 is translated to an address belonging to the area 300 of the memory 108. For example, if the connection circuit 118 determines that the source address, or the destination address, belongs to the address range defining the area 200 of the memory 108, then the connection circuit 118 is configured to program the 33rd address bit of the source address or the destination address to the binary value "0".In this way, the source address, or the destination address, is not modified. For example, the connection circuit 118 is configured to transmit the value of the 33rd address bit to the bus 110 via a bus 712.

[0074] The use of the indication values, in the registers 702 and 706, makes it possible to activate and deactivate, dynamically, the connection circuit 118, so it is for example possible, initially, to read data in the zone 200 or in the memory 106, when the connection circuit 118 is deactivated and for example to write it in the zone 300 of the memory 108 after having activated the connection circuit 118.

[0075] [Fig.8] is a flowchart describing steps of a method for accessing an addressable memory space, formed for example by the memories 106 and 108. By way of example, the method is implemented via the connection circuit 116 or 118. The addressable memory space is for example not entirely addressable by the peripheral circuit 112 or by the direct memory access circuit 114.

[0076] In a step 800 (PERIPH ACCESS TO MEM), the peripheral circuit 112 or the direct memory access circuit 114 initiates a request for access to the addressable memory space. For example, the input address is an address included either in the address range associated with the memory 106, or in that associated with the zone 200. In particular, the peripheral circuit 112 or the direct memory access circuit 114 is not capable of addressing the zone 300 of the memory 108.

[0077] In a step 801 (CONNECTOR ACTIVATED?), subsequent to step 800, it is checked whether the connection circuit 116 or 118 is activated. For example, during the performance of step 801, the peripheral circuit 112 or the direct memory access circuit 114 transmits the input address to the bus 400 or 710.

[0078] If the connection circuit 116 or 118 is deactivated (branch N), the peripheral 112 or the direct memory access circuit 114 the method continues in a step 806 (OUTPUT ADDR=INPUT ADDR). For example, when performing step 806, an output address is generated by the processor 104, for example by adapting the input address. For example, the input address is a 32-bit address and the processor 104 converts it to a 33-bit address. The generated output step then allows the peripheral circuit to access the desired memory address. In other words, the output address corresponds to the input address. The generated output address therefore belongs, for example, to the memory area 106 or 200.

[0079] Following step 806, the peripheral circuit 104 accesses, in a step 802 (MEM ACCESS), for example the memory 106 or the zone 200 of the memory 108, by the output address, which is transmitted to the bus 110.

[0080] If the connection circuit 116 or 118 is activated (branch Y at the output of step 801), the method continues in a step 803 (INPUT ADDR>REF ADDR?). The connection circuit 116 or 118 compares, for example, the input address, previously transmitted by the peripheral circuit 112 or by the direct memory access circuit 114, with a threshold address. For example, the connection circuit 116 or 118 determines whether the input address is, for example, greater than the address 0x80000000, which corresponds to checking whether the input address belongs to the zone 200 of the memory 108. The address 0x80000000 is given as an example and is of course not limiting. Other addresses, or address ranges associated with memories 106 and 108 or other memories can of course be used.

[0081] If the input address is for example greater than the threshold address (Y branch), the method continues in a step 804 (OUTPUT ADDR=INPUT ADDR), in which an output address supplied to the bus 110 is identical to the input address. In one example, the input address, for example coded on 32 bits, is transmitted to the bus 110 and the connection circuit 116 or 118 programs for example a 33rd bit to zero which it supplies to the bus 110. Thus the output address is identical to the input address.

[0082] If the input address is, for example, not greater than the threshold address (branch N), the connection circuit 116, or 118, is configured to modify the input address in a step 805 (OUTPUT ADDR =INPUT ADDR+Ox 100000000). For example, if the input address is less than the threshold address, this means that the input address belongs to the memory 106. For example, the modification of the address consists of a translation to an address belonging to the zone 300. For example, the 32 least significant bits of the output address are identical to the 32 bits of the input address and the connection circuit 116 or 118 programs a 33rd, as the most significant bit of the output address to the binary value "1". The output address, corresponding to the concatenation of the input address with the part of the output address supplied by the connection circuit 116 or 118, is then supplied to bus 110. Thus the output address corresponds for example to an address in zone 300.

[0083] Following the performance of step 804 or step 805, the method terminates in an embodiment of step 802, in which the peripheral circuit 112 or the direct memory access circuit 114 accesses the entry address in the addressable memory space.

[0084] An advantage of the described embodiments is that they allow a peripheral circuit, or another circuit, to access memory areas that it cannot address directly.

[0085] Another advantage of the described embodiments is that they allow a peripheral circuit to expand its capabilities. For example, a peripheral circuit configured to generate 32-bit addresses has the ability to address a memory in which at least a portion of the addresses are 33-bit.

[0086] Another advantage of the described embodiments is that they do not require any configuration of the peripheral circuits. Thus, any peripheral circuit connected to the connection circuit benefits from the advantages provided by the connection circuit.

[0087] Another advantage of the described embodiments is that the processor does not have to be reprogrammed. Indeed, the addresses ordered by the processor do not have to be recalculated, for example by means of a translation table.

[0088] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the size of the addressable memory may vary and thus the address ranges defining the different memories and / or memory areas may vary. Similarly, the indication values ​​stored in association with the source or destination addresses in the direct memory access circuit may vary.

[0089] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A connection circuit (116, 118) connecting a first circuit (112, 114) of a device (100) to a bus (110) configured to provide access to an addressable memory space (106, 108) of the device, the connection circuit being configured to: - receive an input address, transmitted by the first circuit, the input address corresponding to an address in a first or second address range (106, 200) of the addressable memory space, the addressable memory space further comprising a third address range (300), not addressable by the first circuit; - compare the input address with a threshold address; - based on the comparison, generate a portion of an output address, the output address belonging to the second or third address range (200, 300) of the addressable memory space; and - provide the output address part to the bus (110).

2. A connection circuit according to claim 1, wherein the portion of the output address comprises one or more additional address bits, and the connection circuit (116, 118) is configured to provide the bus (110) with said one or more additional address bits as most significant bits of the output address.

3. Connection circuit according to claim 1 or 2, further configured to: - if the input address belongs to the second address range (200), generate the one or more most significant bits of the output address at the binary value "0"; and - if the input address belongs to the first address range (106), generate the one or more most significant bits of the output address at the binary value "1".

4. Device comprising: - one or more memory circuits (106, 108) defining an addressable memory space comprising a first, a second and a third address range (106, 200, 300); - a first circuit (112, 114) not being capable of generating an address forming part of the third address range; - the connection circuit (116, 118) according to any one of claims 1 to 3 connecting the first circuit to the addressable memory space.

5. The device of claim 4, further comprising a processor (104), wherein the connection circuit (116) further comprises a register (600), programmable by the processor, the register being configured to store a first bit whose value is defined if the circuit is in a first state or in a second state, the second state being a state in which the connection circuit is deactivated.

6. Device according to claim 5, in which the register (600) is configured to store a second bit, programmable by the processor and the programming of which locks the state of the connection circuit (116) to the state defined by the value of the first bit.

7. The device of claim 5 or 6, wherein the processor (104) is a 64-bit processor and the first circuit (112, 114) is a 32-bit peripheral circuit.

8. A device according to any one of claims 5 to 7, wherein the memory space comprising the second and third address ranges is implemented by a volatile memory (108), the third address range (300) being addressable by the processor (104).

9. A device according to any one of claims 5 to 8, wherein the first circuit is a peripheral circuit (112) of the device.

10. The device of any one of claims 5 to 8, wherein the first circuit is a direct memory access circuit (114), the direct memory access circuit (114) being configured to send, based on the contents of a register (702, 706), an activation signal to the connection circuit, the activation signal programming the connection circuit in the first state.

11. Device according to any one of claims 4 to 10, in which the first circuit is configured to transmit the input address to the bus (110) connected to the addressable memory space and in which the output address corresponds to the concatenation of the input address with the part of the output address provided by the connection circuit (118).

12. A device according to any one of claims 4 to 11, wherein the memory space comprising the first address range is implemented by an internal memory (106) of the device.

13. Method comprising: - transmitting, by a first circuit of a device, an input address, to a connection circuit of the device, the connection circuit connecting the first circuit to a bus (110) configured to allow access to an addressable memory space (106, 108) of the device, the input address corresponding to an address in a first or in a second address range of an addressable memory space, the addressable memory space further comprising a third address range, not addressable by the first circuit; and - the comparison by the connection circuit of the input address with a threshold address; and - based on the comparison, generating, by the connection circuit, a part of an output address, the output address belonging to the second or third address range (200, 300) of the addressable memory space; and - provide the output address part to the bus (110).

14. The method of claim 13, further comprising: - transmit, by the first circuit, the input address to the bus (110) connected to the addressable memory space, the output address corresponding to the concatenation of the input address with the part of the output address provided by the connection circuit.

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