Memory management method to save energy

Abstract

TITLE: Energy-Saving Memory Management Method This description relates to a system (1) comprising a memory (8), the memory (8) comprising a plurality of readable and writable memory units. Each memory unit comprises a memory cell array and a peripheral circuit for accessing said memory cells. Each memory unit is configurable in a first or second operating mode. The memory cell array is configured, in both the first and second operating modes, to retain data until the memory unit is subsequently powered off. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode.The system further includes a controller (10) configured to configure in the second operating mode any memory unit that has not undergone any read or write access for a specified period. Figure for the abbreviation: 1.

Description

Title of the invention: Memory management method for saving energy Technical field

[0001] The present description relates to the field of memory management for the purpose of saving energy. Prior art

[0002] A volatile memory is a computer memory that requires continuous electrical power to retain the information stored in it. When the electrical power is interrupted, the information contained in the volatile memory is almost immediately lost. It may be a RAM of a microprocessor or a microcontroller in which a processor is configured to write data to or read data from the memory.

[0003] In certain applications, the entire volatile memory may not be used permanently during operation of the microprocessor or microcontroller. For example, the processor may access only a portion of the volatile memory during one operating phase and only another portion of the volatile memory during another operating phase. However, it is necessary for the volatile memory to remain permanently powered so that no data stored in the volatile memory is lost. Part of the electrical power consumed by the volatile memory then corresponds to the static consumption of the portions of the volatile memory that are not used.

[0004] One aim is to control a memory so as to reduce its energy consumption, without losing any data that it might store. Summary of the invention

[0005] An object of an embodiment is to overcome all or part of the disadvantages of known volatile memories.

[0006] One embodiment provides a system comprising a memory, the memory comprising a plurality of writable and readable memory units, each memory unit comprising an array of memory cells and peripheral circuitry for accessing said memory cells, each memory unit being configurable in a first or a second mode of operation, the array of memory cells being configured, in the first and second modes of operation, to retain data until a subsequent power-down of the memory unit, the peripheral circuitry being powered in the first mode of operation and not being powered in the second mode of operation, the system comprising further a controller configured to configure in the second operating mode any memory unit of the memory which has not undergone any write or read access for a determined period.

[0007] According to one embodiment, the controller is configured to configure in the first operating mode any memory unit of the memory for which write or read access is performed.

[0008] According to one embodiment, for each memory unit, the peripheral circuit of the memory unit is powered by a source of a high reference potential via a controllable switch, the controller being configured to control the closing of the controllable switch when the memory unit is in the first operating mode and to control the opening of the controllable switch when the memory unit is in the second operating mode.

[0009] According to one embodiment, the controller comprises, for each memory unit, a register and the controller comprises a processing unit configured to store a first value in the register when the corresponding memory unit is in the first operating mode or a second value in the register when the corresponding memory unit is in the second operating mode.

[0010] According to one embodiment, the controller comprises a counter for each memory unit, each counter being incremented at each pulse of a clock signal, the processing unit being configured to reset the counter when a read or write access to the corresponding memory unit is performed.

[0011] According to one embodiment, for each memory unit, the processing unit is configured to store the second value in the corresponding register when the corresponding counter exceeds a threshold.

[0012] According to one embodiment, the memory is a volatile memory, for example a RAM memory.

[0013] According to one embodiment, the system is a system on a chip.

[0014] An embodiment also provides a method for controlling a memory, comprising a plurality of memory units accessible in writing and in reading, each memory unit comprising an array of memory cells and a peripheral circuit for accessing said memory cells, the array of memory cells being configured, in the first and second operating modes, to retain data until a subsequent power-down of the memory unit, the peripheral circuit being powered in the first operating mode and not being powered in the second operating mode, the method comprising configuring in the second operating mode any memory unit of the memory which has not undergone any write or read access beyond a duration de- finished.

[0015] According to one embodiment, the method comprises configuring in the first operating mode any memory unit of the memory for which write or read access is performed. Brief description of the drawings

[0016] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0017] [Fig.l] illustrates, in a partial and schematic manner, an embodiment of an electronic system comprising a storage device;

[0018] [Fig.2] illustrates a more detailed embodiment of the storage device of [Fig.l];

[0019] [Fig.3] illustrates an embodiment of a memory unit of the storage device of [Fig.2]; and

[0020] [Fig.4] is a block diagram illustrating one embodiment of a method of operating the storage device of [Fig.2]. Description of the embodiments

[0021] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0022] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. Unless otherwise specified, ordinal numeral adjectives, such as "first", "second", etc., are used only to distinguish elements from one another. In particular, these adjectives do not limit the described embodiments to a particular order of these elements.

[0023] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements. In addition, a "binary signal" is a signal which alternates between a first constant state, for example a low state, noted "0", and a second constant state, for example a high state, noted "1". The high and low states of different binary signals of the same electronic circuit can be different. In practice, binary signals may correspond to voltages or currents that may not be perfectly constant in the high or low state.

[0024] [Fig.l] illustrates, in a partial and schematic manner, an embodiment of an electronic system 1, such as a system on chip, comprising at least one storage device 2, a command reception interface 4 and at least one master module 6.

[0025] According to one embodiment, the master module 6 is a processor configured to execute program code.

[0026] The storage device 2 comprises a memory 8 and a controller 10 for controlling the memory 8. The memory 8 is accessible in writing and / or reading by the master module 6 via the controller 10. According to one embodiment, the memory 8 is a volatile memory, that is to say a memory for which all data is lost when the memory 8 is powered down. The memory 8 is for example a random access memory (RAM), in particular a static random access memory (SRAM). The controller 10 is for example a circuit, programmable (FPGA) or not (ASIC).

[0027] [Fig. 2] represents, in a partial and schematic manner, a more detailed embodiment of elements of the system 1 of [Fig. 1], in particular of the storage device 2.

[0028] According to one embodiment, the memory 8 comprises a plurality of memory units 8a, 8b, 8c, 8d, 8e (in English memory eut) and the controller 10, five memory units 8a, 8b, 8c, 8d, 8e being represented by way of example in [Fig.2]. According to one embodiment, each memory unit 8a-8e has a size between 1 kilobyte and 128 kilobytes, for example equal to 64 kilobytes. The number of memory units 8a-8e of the memory 8 is for example between 1 and 40 (this number being five in the exemplary embodiment illustrated in [Fig.2]). The memory 8 has an overall size equal to the sum of the respective sizes of its memory units 8a-8e. For example, this overall size is 600 kilobytes.

[0029] [Fig. 3] shows, in a partial and schematic manner, an embodiment of the memory unit 8a, knowing that each memory unit 8a-8e of the memory 8 can have the structure shown in [Fig. 3]. The memory unit 8a comprises a MEM matrix of memory cells for storing data and peripheral circuits PER, in particular for accessing the memory cells of the MEM matrix of memory cells, transmitting data to be stored in the memory cells of the MEM matrix or transmitting data read from the memory cells of the MEM matrix. According to one embodiment, the MEM matrix of memory cells and the peripheral circuits PER comprise electronic components, for example field effect transistors, in particular gate field effect transistors isolated (MOSFET, English acronym for Metal Oxide Semiconductor Field Effect Transistor), subsequently called MOS transistors.

[0030] According to one embodiment, for each memory unit 8a-8e of the memory 8, the electronic components of the MEM matrix of memory cells and of the peripheral circuit PER are connected to a source gndm of a low reference potential, for example ground. The power supply of the electronic components of the MEM matrix of memory cells is provided by a first source vddma of a high reference potential. The power supply of the electronic components of the peripheral circuit PER is provided by a second source vddm of a high reference potential via a controllable switch SWa. The high reference potential of the first source vddma may be identical to or different from the high reference potential of the second source vddm. The controllable switch SWa is controllable by a control signal Sa, for example a binary signal.For example, the controllable switch SWa is closed when the control signal Sa is in a first state, for example the state "1", and is open when the control signal Sa is in a second state, for example the state "0". According to one embodiment, the controllable switch SWa may comprise a MOS transistor and the control signal Sa may correspond to the gate voltage of the MOS transistor.

[0031] As an example, a memory cell of the MEM matrix is ​​shown in [Fig. 3] comprising a first MOS transistor T1, for example P-channel, a second MOS transistor T2, for example N-channel, and a third MOS transistor T3, for example N-channel. The source of the MOS transistor T1 is connected, preferably connected, to the first source vddma of the high reference potential. The source of the MOS transistor T2 is connected, preferably connected, to the source gndm of the low reference potential. The drain of the transistor T1 is connected, preferably connected, to the drain of the transistor T2. The gate of the transistor T1 is connected, preferably connected, to the gate of the transistor T2. The source or drain of the transistor T3 is connected, preferably connected, to the drain of the transistor TL. According to one embodiment, the transistors T1, T2, and T3 are produced in an integrated manner.The N-type well of the transistor T1 is connected, preferably connected, to the first source vddma of the high reference potential. The P-type well of the transistor T2 is connected, preferably connected, to the source gndm of the low reference potential. The P-type well of the transistor T3 is connected, preferably connected, to the source gndm of the low reference potential.

[0032] As an example, the peripheral circuit PER is shown in [Fig. 3] comprising a fourth MOS transistor T4, for example P-channel, and a fifth MOS transistor T5, for example N-channel. The source of the MOS transistor T4 is connected to the second source vddm of the high reference potential. The source of the MOS transistor T5 is connected, preferably connected, to the source gndm of the low reference potential. The drain of transistor T4 is connected, preferably connected, to the drain of transistor T5. The gate of transistor T4 is connected, preferably connected, to the gate of transistor T5. According to one embodiment, transistors T4 and T5 are made in an integrated manner. The N-type well of transistor T4 is connected, preferably connected, to the first source vddma of the high reference potential. The P-type well of transistor T5 is connected, preferably connected, to the source gndm of the low reference potential.

[0033] Each memory unit 8a-8e of the memory 8 is configurable in two operating modes: a first mode called RUN mode, and a second mode called SLEEP mode. In the RUN mode and in the SLEEP mode, the MEM array of memory cells of each memory unit 8a-8e is powered by the first vddma source of the high reference potential. The memory unit 8a-8e is then capable of retaining data until a subsequent power-down of the memory unit. This means that data can be stored in the memory unit.

[0034] In the RUN mode, the peripheral circuit PER of the memory unit 8a-8e is powered by the second source vddm of the high reference potential. Operations for writing data into the array MEM of memory cells of the memory unit 8a-8e and operations for reading data stored in the array MEM of memory cells of the memory unit 8a-8e can be performed. The RUN mode is typically used during the execution of a program by the master module 6 in which the master module 6 is caused to write / read data into the memory unit. In the SLEEP mode, the peripheral circuit PER of the memory unit 8a-8e is not powered by the second source vddm of the high reference potential. Operations for writing data to the MEM array of memory cells of the memory unit 8a-8e and operations for reading data stored in the MEM array of memory cells of the memory unit 8a-8e cannot be performed.SLEEP mode is a low-power mode, compared to RUN mode. In SLEEP mode, the data stored in the memory unit 8a-8e are retained but read / write operations in the memory unit cannot be performed. The different memory units 8a-8e are configurable in either of these operating modes independently of each other. In other words, different memory units of the memory 8 can be configured in different operating modes.

[0035] The controller 10 has the function of configuring each memory unit 8a-8e of the memory 8 in one or other of the operating modes RUN or SLEEP.

[0036] Considering again [Fig.2], for each memory unit 8a-8b, the associated controllable switch SWa-SWb controlled by the corresponding control signal Sa-Se has been shown. The controller 10 comprises a plurality of registers 12, including, as illustrated in [Fig.2], a mode register 12a, 12b, 12c, 12d, 12e for each memory unit 8a-8e, five mode registers being shown as an example in [Fig.2]. Each mode register 12a-12e is intended to store the current operating mode of the associated memory unit 8a-8e. In other words, each memory unit 8a-8e is associated with a mode register 12a-12e of its own.

[0037] For example, a 12a-12e mode register can store: - a first value, such as logic state "0", to indicate SLEEP mode; or - a second value, such as logic state "1", to indicate RUN mode.

[0038] A mode register 12a-12e can thus be coded on a single bit. According to one embodiment, the control signal Sa-Se is obtained from the value stored in the mode register 12a-12e. According to one embodiment, a value "1" stored in the mode register 12a-12e corresponds to a control signal Sa-Se corresponding to the state "1" and a value "0" stored in the mode register 12a-12e corresponds to a control signal Sa-Se corresponding to the state "0".

[0039] The controller 10 further comprises a processing unit 14, configured to process requests for access to the memory 8 originating from the master module 6. The processing unit 14 is capable of relaying to the memory units 8a-8e the access requests sent by the master module 6 of the system 1. The processing unit 14 is further configured to modify the operating mode of each memory unit 8a-8e and is adapted to modify the value stored in each mode register 12a-12e.

[0040] The processing unit 14 may comprise a finite-state automaton or finite State machine (FSM) receiving the access requests sent by the master module 6 of the system 1. The processing unit 14 further receives a clock signal CLK supplied by a clock signal source 16. The controller 10 further comprises counters 18. According to one embodiment, the processing unit 14 comprises a counter 18a, 18b, 18c, 18d, 18e for each memory unit 8a-8e, five mode counters being shown as an example in [Fig.2]. Each counter 18a-18e is incremented at each pulse of the clock signal CLK.

[0041] [Fig.4] is a block diagram of an embodiment of a function method of the storage device 2.

[0042] In step 20, when the system 1 is powered up, the mode registers 12a-12e of the controller 10 are all set to the value "1" and the counters 18a-18e are all reset to zero. Each memory unit 8a-8e is then in the RUN mode.

[0043] In step 22, the processing unit 14 receives requests from the master module 6, for example a request to write data in the memory 8 or a request to read data stored in the memory 8. A write request typically comprises a write address in the memory 8 and the data to be written in the memory 8, these data occupying a size indicated in the write request or deducible from it. The processing unit 14 determines, on the basis of the write request, the memory unit(s) 8a-8b of the memory 8 targeted by the request, i.e. those whose content is updated by the writing. This determination can be implemented before, during or after writing in the memory 8. Similarly, a read request typically comprises a read address in the memory 8. The processing unit 14 determines, on the basis of the read request, the memory unit(s) 8a-8b of the memory 8 targeted by the request, i.e. those whose content must be read. This determination can be implemented before, during or after reading in the memory 8.

[0044] In step 24, the mode register 12a-12e associated with each memory unit 8a-8e targeted by the write / read request is set to the value "1" by the processing unit 14. For example, this setting to the value "1" is implemented once the writing or reading is performed. On the other hand, the mode registers 12a-12e of the memory units 8a-8e of the memory 8 which are not concerned by the write / read request are not modified in step 24. Furthermore, in step 24, the counter 18a-18e associated with each memory unit 8a-8e targeted by the write / read request is reset to zero. For example, this reset is performed once the writing or reading is performed. On the other hand, the counters 18a-18e associated with the memory units 8a-8e of memory 8 which are not concerned by the write / read request are not reset to zero in step 24.

[0045] In step 26, the processing unit 14 compares the contents of each counter 18a-18e to a threshold. For each memory unit 8a-8e, if the contents of the counter 18a-18e associated with the memory unit 8a-8e are greater than or equal to the threshold, the mode register 12a-12e associated with the memory unit 8a-8e is set to the value "0" by the processing unit 14. This causes the switch SWa-SWe associated with the memory unit 8a-8e to open. The memory unit 8a-8e is then put into SLEEP mode.

[0046] If the content of the counter 18a-18e associated with the memory unit 8a-8e is lower than the threshold, the mode register 12a-12e associated with the memory unit is not modified by the processing unit 14 in step 26, and the memory unit 8a-8e remains in the RUN mode. According to one embodiment, step 26 is implemented only for the memory unit 8a-8e whose associated mode register 12a-12e is at the value "1". According to one embodiment, the threshold corresponds to the elapse of a duration greater than 1 ms, preferably between 1 ms and 10 ms.

[0047] The operating embodiment of the controller 10 makes it possible to optimally reduce the energy consumption of the memory 8 when the latter is in the SLEEP operating mode, without loss of stored data.

[0048] The system 1 may comprise a plurality of storage devices 2 conforming to the preceding description. Each of these devices 2 comprises a memory 8 and a controller 10 for specifically controlling this memory 8. Otherwise, there are as many controllers 10 as there are memories 8 in the system 1. When the system 1 comprises several memories, these memories can be of variable sizes and / or be used for different purposes. For example, the system 1 can comprise: a first memory dedicated to the storage of execution data, in particular an execution stack, a second memory dedicated to the storage of security data, such as error-correcting codes, and a third memory constituting an extension of the first memory.

[0049] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will appear to those skilled in the art. In particular, in the embodiments described above, for each memory unit 8a-8e of the memory 8, the matrix MEM of memory cells of the memory unit is powered by a first source vddma of a high reference potential and the peripheral circuit PER of the memory unit is powered by a second source vddma of a high reference potential. As a variant, the second source vddm can be confused with the first source vddma, the peripheral circuit PER of the memory unit being connected to the first source vddma by the programmable switch SWa.

[0050] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. System (1) comprising a memory (8), the memory (8) comprising a plurality of memory units (8a, 8b, 8c, 8d, 8e) accessible in writing and in reading, each memory unit comprising an array (MEM) of memory cells and a peripheral circuit (PER) for accessing said memory cells, each memory unit being configurable in a first or a second operating mode, the array of memory cells being configured, in the first and second operating modes, to retain data until a subsequent power-down of the memory unit, the peripheral circuit being powered in the first operating mode and not being powered in the second operating mode, the system further comprising a controller (10) configured to configure in the second operating mode any memory unit of the memory having undergone no write or read access for a determined duration.

2. The system of claim 1, wherein the controller (10) is configured to configure in the first operating mode any memory unit (8a, 8b, 8c, 8d, 8e) of the memory (8) for which write or read access is performed.

3. System according to claim 1 or 2, in which, for each memory unit (8a, 8b, 8c, 8d, 8e), the peripheral circuit (PER) of the memory unit is supplied by a source (vddm) of a high reference potential via a controllable switch (SWa, SWb, SWc, SWd, SWe), the controller (10) being configured to control the closing of the controllable switch when the memory unit is in the first operating mode and to control the opening of the controllable switch when the memory unit is in the second operating mode.

4. A system according to any one of claims 1 to 3, wherein the controller (10) comprises, for each memory unit (8a, 8b, 8c, 8d, 8e), a register (12a, 12b, 12c, 12d, 12e) and wherein the controller (10) comprises a processing unit (14) configured to store a first value in the register when the corresponding memory unit is in the first operating mode or a second value in the register when the corresponding memory unit is in the second operating mode.

5. System according to claim 4, wherein the controller (10) comprises a counter (18a, 18b, 18c, 18d, 18e) for each memory unit (8a, 8b, 8c, 8d, 8e), each counter being incremented at each pulse of a clock signal (CLK), the processing unit (14) being configured to reset the counter when a read or write access to the corresponding memory unit is made.

6. System according to claim 5, wherein, for each memory unit (8a, 8b, 8c, 8d, 8e), the processing unit (14) is configured to store the second value in the corresponding register (12a, 12b, 12c, 12d, 12e) when the corresponding counter (18a, 18b, 18c, 18d, 18e) exceeds a threshold.

7. A system according to any one of claims 1 to 6, wherein the memory is a volatile memory, for example a RAM memory.

8. System according to any one of claims 1 to 7, of the system-on-chip type.

9. A method for controlling a memory (8), comprising a plurality of memory units (8a, 8b, 8c, 8d, 8e) accessible in writing and in reading, each memory unit comprising a matrix (MEM) of memory cells and a peripheral circuit (PER) for accessing said memory cells, the matrix of memory cells being configured, in the first and second operating modes, to retain data until a subsequent power-down of the memory unit, the peripheral circuit being powered in the first operating mode and not being powered in the second operating mode, the method comprising configuring in the second operating mode any memory unit of the memory which has not undergone any write or read access beyond a determined duration.

10. A method according to claim 9, comprising configuring in the first operating mode any memory unit (8a, 8b, 8c, 8d, 8e) of the memory (8) for which write or read access is performed.

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