Chip power supply network compensation method, device, equipment, storage medium and program

Abstract

The invention provides a chip power supply network compensation method and device, equipment, a storage medium and a program, relates to the technical field of integrated circuits, in particular to a chip and circuit design technology, can be applied to an application scene of chip test optimization, and the method comprises the following steps: determining a dynamic power consumption violation area of a current power supply network of a target chip; performing compensation priority classification on the dynamic power consumption violation area according to the voltage drop violation distribution information of the dynamic power consumption violation area to obtain a violation priority classification area; and determining a local power supply network compensation strategy of each violation priority classification area according to the compensation priority of the violation priority classification area. According to the embodiment of the invention, the efficiency and precision of chip power supply network compensation can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to chip and circuit design technology, and can be applied to chip testing and optimization application scenarios. Background Technology

[0002] The Power Delivery Network (PDN) is a core component of a chip's power supply system, and its design quality directly determines the severity of IR Drop (resistive voltage drop). IR Drop is the voltage loss caused by the combined resistance (R) of the power delivery network and the operating current (I). Chip IR Drop is divided into static and dynamic types. For large-scale chips using advanced processes, during the back-end design phase, the number of dynamic power violations in core computing modules is often far greater than the number of static power violations. Therefore, dynamic power IR Drop violations have become a bottleneck in the back-end implementation of the chip. Voltage fluctuations in the chip's power delivery network can cause timing distortion, further leading to the functional failure of chip physical units. In large-scale integrated chips, the failure of a single physical unit can cause the failure of the entire chip, resulting in significant losses for the entire chip design team. Therefore, how to address the weakness of the power delivery network in high dynamic power consumption areas within the chip and perform more precise power delivery network compensation to obtain a more stable chip power delivery network is a pressing issue that needs to be addressed in chip power delivery systems. Summary of the Invention

[0003] This disclosure provides a chip power network compensation method, apparatus, device, storage medium, and program, which can improve the efficiency and accuracy of chip power network compensation.

[0004] In a first aspect, embodiments of this disclosure provide a chip power network compensation method, including:

[0005] Identify the dynamic power consumption violation region of the target chip's current power network;

[0006] The dynamic power consumption violation region is classified into compensation priority categories based on the voltage drop violation distribution information of the dynamic power consumption violation region to obtain the violation priority classification region;

[0007] The local power network compensation strategy for each violation priority classification region is determined based on the compensation priority of the violation priority classification region.

[0008] Secondly, embodiments of this disclosure provide a chip power network compensation device, comprising:

[0009] The dynamic power consumption violation region determination module is used to determine the dynamic power consumption violation region of the current power network of the target chip.

[0010] The violation priority classification region classification module is used to classify the dynamic power consumption violation region according to the voltage drop violation distribution information of the dynamic power consumption violation region to obtain the violation priority classification region;

[0011] The local power network compensation strategy determination module is used to determine the local power network compensation strategy for each of the violation priority classification regions based on the compensation priority of the violation priority classification regions.

[0012] Thirdly, embodiments of this disclosure provide an electronic device, including:

[0013] At least one processor; and

[0014] A memory communicatively connected to the at least one processor; wherein,

[0015] The memory stores instructions that can be executed by the at least one processor, which, when executed, enables the at least one processor to perform the chip power network compensation method provided in the first aspect embodiment.

[0016] Fourthly, embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the chip power network compensation method provided in the first aspect embodiment.

[0017] Fifthly, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the chip power network compensation method provided in the first aspect embodiment.

[0018] This disclosure identifies dynamic power consumption violation regions in the current power network of a target chip. Based on voltage drop violation distribution information within these regions, compensation priorities are categorized to obtain violation priority classification regions. Then, a local power network compensation strategy is determined for each violation priority classification region based on its compensation priority. These local power network compensation strategies can be used to specifically compensate for matching violation priority classification regions within the target chip's current power network, addressing the issues of low efficiency and accuracy in existing chip power network compensation methods and improving both the efficiency and accuracy of chip power network compensation.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0020] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0021] Figure 1 This is a flowchart of a chip power network compensation method provided in an embodiment of this disclosure;

[0022] Figure 2 This is a flowchart of another chip power network compensation method provided in this embodiment of the disclosure;

[0023] Figure 3 This is a schematic diagram of an incremental optimization and verification process for chip power network compensation provided in an embodiment of this disclosure;

[0024] Figure 4 This is a structural diagram of a chip power network compensation device provided in an embodiment of this disclosure;

[0025] Figure 5 This is a schematic diagram of the structure of an electronic device used to implement the chip power network compensation method of the embodiments of this disclosure. Detailed Implementation

[0026] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0027] Currently, traditional power network enhancement methods include metal layer optimization and hierarchical adjustment methods. Metal layer optimization methods require increasing the width of power / ground lines in high-voltage power-saving modules within the chip, such as from 1x to 2x, and can also increase the number of vias to reduce vertical resistance, such as adding a via every 10μm. Hierarchical adjustment methods typically add a sparse, coarse grid to the upper layers of the chip's metal and a fine grid to the lower layers, forming a tiered power supply. Alternatively, manual adjustment can be used, where engineers manually select violation areas in the chip's power grid based on IR drop violations and compensate for the power network accordingly.

[0028] The prerequisite for using metal layer optimization methods to compensate for the power network of a chip is that the chip has sufficient wiring resources. In large-scale chips, chip designers often need to reduce chip area to achieve higher utilization and smaller size. Increasing the width of power and ground lines uniformly for modules with greater voltage drops may result in insufficient metal wiring resources for the modules.

[0029] The hierarchical adjustment method also relies on the density and wiring resources of the chip's physical standard cells. High-density standard cells in a chip require a large amount of underlying metal, and standard cell density is an important metric for measuring a chip's PPA (Performance Power Area). The denser the standard cells are arranged, the smaller the chip area and the higher the integration density. Modules with higher integration density will have denser underlying metal signal lines compared to ordinary modules. In this case, a large number of standard cells cannot meet design rule checks during the initial layout process. The inability of standard cells to find suitable positions at this step will lead to timing and more serious design rule violations.

[0030] Therefore, metal layer optimization and hierarchical adjustment methods are two uniform power network compensation methods. Both methods are uniform compensation, meaning they uniformly adjust the entire power network. However, both methods suffer from the following problems: insufficient compensation for hotspot areas of IR drop, while over-designing non-hotspot areas, such as increasing area overhead by 15%. Consequently, metal layer optimization and hierarchical adjustment methods struggle to capture local peaks in instantaneous dynamic power consumption within the chip's power network, resulting in high-risk areas not being specifically reinforced. Manual adjustment, unlike global compensation, involves engineers manually adjusting or globally reconstructing the power network after chip placement and routing. This requires multiple design-verification cycles, relying solely on manual iterative optimization, and consumes over 30% of the chip design cycle, extending chip development time. For these reasons, for core computing modules of chips with limited routing resources, a dynamic power consumption-driven and locally focused power network compensation optimization method is needed to accurately improve the chip's power integrity.

[0031] In one example Figure 1 This is a flowchart of a chip power network compensation method provided in this embodiment. This embodiment is applicable to situations where the power network of a chip is compensated in a targeted manner according to a priority division. This method can be executed by a chip power network compensation device, which can be implemented by software and / or hardware, and is generally integrated into an electronic device. The electronic device can be a terminal device or a server device, as long as it can execute the chip power network compensation method. This embodiment does not limit the specific device type of the electronic device.

[0032] Correspondingly, such as Figure 1 As shown, the method includes the following operations:

[0033] S110. Determine the dynamic power consumption violation area of ​​the current power network of the target chip.

[0034] The target chip can be any chip requiring power network compensation. For example, the target chip type can include, but is not limited to, various high-performance processors such as SoC (System on a Chip), TPU (Tensor Processing Unit), DPU (Deep Learning Processing Unit), NPU (Neural Network Processing Unit), GPU (Graphics Processing Unit), and CPU (Central Processing Unit), as long as there is a voltage drop assessment requirement. This disclosure does not limit the specific chip type or application scenario of the target evaluation chip. The dynamic power consumption violation region can be determined after performing dynamic IR Drop simulation on the target chip; it refers to the region in the current power network of the target chip where dynamic power consumption violations exist. A dynamic power consumption violation can be understood as the dynamic power consumption exceeding preset specifications or timing requirements in the circuit design of the power network, typically caused by excessively fast signal switching rates, excessive load capacitance, or abnormal supply voltage.

[0035] In this embodiment of the disclosure, after completing a round of placement and routing for the modules or subsystems of the target chip, dynamic power consumption simulation and hotspot extraction processes can be performed on the current power network of the target chip. Specifically, a corresponding dynamic power consumption simulation tool can be used to perform dynamic power consumption simulation on the target chip, thereby analyzing the dynamic power consumption simulation results of the target chip and identifying the regions in the current power network of the target chip that contain IR drop violations as dynamic power consumption violation regions.

[0036] S120. Based on the voltage drop violation distribution information of the dynamic power consumption violation region, the dynamic power consumption violation region is classified into compensation priorities to obtain the violation priority classification region.

[0037] The voltage drop violation distribution information can be the distribution of voltage drop violations within the dynamic power consumption violation region. The compensation priority can be the priority information configured for the dynamic power consumption violation region, used to determine different levels of compensation strategies corresponding to the dynamic power consumption violation region. The violation priority classification region can be the classification region obtained after classifying the dynamic power consumption violation region according to the compensation priority, resulting in various different compensation priorities.

[0038] Accordingly, after determining the dynamic power consumption violation region of the current power network of the target chip, the violation distribution characteristics in the dynamic power consumption violation region can be analyzed to determine the distribution of voltage drop violations in the dynamic power consumption violation region as voltage drop violation distribution information. Then, based on the voltage drop violation distribution information in the dynamic power consumption violation region, the dynamic power consumption violation region is classified into compensation priorities to obtain multiple violation priority classification regions. Each dynamic power consumption violation region can be configured with a corresponding compensation priority.

[0039] Understandably, the more voltage drop violations a local area within a dynamic power violation region contains, the higher the compensation priority for that local area, indicating a greater defect in the local power network corresponding to that area. Conversely, the fewer voltage drop violations a local area within a dynamic power violation region contains, the lower the compensation priority for that local area, indicating a smaller defect in the local power network corresponding to that area.

[0040] S130. Determine the local power network compensation strategy for each of the violation priority classification regions based on the compensation priority of the violation priority classification regions.

[0041] Among them, the local power network compensation strategy can be a power network compensation strategy applicable to the violation priority classification region, used to perform targeted compensation for local areas of the current power network of the target chip.

[0042] Accordingly, once the regional classification of dynamic power consumption violation areas is completed and the compensation priority corresponding to each dynamic power consumption violation area is determined, the local power network compensation strategy matching each violation priority classification area can be determined based on the compensation priority of the violation priority classification area. It is understood that the content of the local power network compensation strategy corresponding to violation priority classification areas with different compensation priorities will also be different; the content of the local power network compensation strategy corresponding to violation priority classification areas with the same compensation priority can be the same.

[0043] For example, when the compensation priority of a violation priority classification region is high, it can be determined that the violation priority classification region requires a stronger local power network compensation strategy. For instance, increasing the power / ground wire width of the upper layer metal and adjusting the density of the lower layer metal can be used as local power network compensation strategies for violation priority classification regions with higher compensation priority. When the compensation priority of a violation priority classification region is low, it can be determined that the violation priority classification region requires a weaker local power network compensation strategy. For instance, adjusting the density of the lower layer metal can be used as a local power network compensation strategy for violation priority classification regions with lower compensation priority.

[0044] Therefore, the above technical solution provides an automated method for local compensation enhancement of chip power networks based on the dynamic power consumption simulation results of the chip. This automated method identifies instantaneous power hotspots in chip operation through the dynamic power consumption results of chip modules or subsystems, and uses different compensation strategies to reinforce the local power network structure in a targeted manner, thereby improving the efficiency and accuracy of chip power network compensation. It can ensure the integrity of chip power while reducing resource waste.

[0045] This disclosure identifies dynamic power consumption violation regions in the current power network of a target chip. Based on voltage drop violation distribution information within these regions, compensation priorities are categorized to obtain violation priority classification regions. Then, a local power network compensation strategy is determined for each violation priority classification region based on its compensation priority. These local power network compensation strategies can be used to specifically compensate for matching violation priority classification regions within the target chip's current power network, addressing the issues of low efficiency and accuracy in existing chip power network compensation methods and improving both the efficiency and accuracy of chip power network compensation.

[0046] In one example Figure 2 This is a flowchart of another chip power network compensation method provided in this disclosure embodiment. Based on the technical solutions of the above embodiments, this disclosure embodiment has made optimizations and improvements, and provides methods for determining the dynamic power consumption violation area of ​​the current power network of the target chip, classifying the compensation priority of the dynamic power consumption violation area, and various specific implementation methods.

[0047] like Figure 2 The chip power network compensation method shown includes:

[0048] S210. Determine the dynamic power consumption violation area of ​​the current power network of the target chip.

[0049] In one optional embodiment of this disclosure, determining the dynamic power consumption violation region of the target chip may include: performing dynamic power consumption simulation on the target chip in multiple scenarios, extracting dynamic current density distribution data in spatial dimension based on the dynamic power consumption simulation results; mapping the dynamic current density distribution data to the physical layout of the target chip; and determining the dynamic power consumption violation region in the physical layout of the target chip based on the current density mapping result of the physical layout.

[0050] Among them, the dynamic current density distribution data can be determined by the dynamic power consumption simulation results of the target chip, which is the current density data dynamically distributed in the spatial dimension of the target chip.

[0051] Specifically, dynamic power consumption simulation tools can be used to perform dynamic power consumption simulations on the target chip under various scenarios, such as peak load, standby mode, and DVFS (Dynamic Voltage and Frequency Scaling) switching. Based on the simulation results, spatial dynamic current density distribution data can be extracted. However, the initially extracted spatial dynamic current density distribution data only reflects the dynamic current density characteristics of the target chip in a spatial dimension and cannot establish a correlation with the actual structure of the target chip. Therefore, after extracting the spatial dynamic current density distribution data, it is necessary to map the extracted dynamic current density distribution data to the physical layout of the target chip.

[0052] The physical layout of a chip transforms its circuit design into a manufacturable physical structure, serving as the direct basis for chip manufacturing. It defines the location and connection methods of components such as transistors and metal interconnects through precise geometric placement, ensuring the accuracy of signal transmission and the stability of electrical performance. Therefore, by mapping dynamic current density distribution data onto the physical layout of the target chip, the current density mapping result based on the physical layout can accurately reflect the current density distribution of the actual internal structure of the target chip. Consequently, the dynamic power consumption violation regions in the physical layout of the target chip, determined based on the current density mapping result, can accurately reflect the dynamic changes in power consumption within the target chip's internal structure, achieving precise location of dynamic power consumption violation regions.

[0053] S220. Divide the physical layout of the target chip into multiple grid regions.

[0054] The grid region can be a local area defined by the physical layout of the target chip. Optionally, the shape of the grid region can be any available shape, such as a triangle, rectangle, or square. This disclosure does not limit the shape type of the grid region.

[0055] Optionally, the physical layout of the target chip can be uniformly divided into multiple grid regions of the same size. Alternatively, the physical layout of the target chip can also be divided into multiple grid regions of different sizes. This disclosure does not limit the method of dividing the physical layout of the target chip into grid regions.

[0056] S230. Based on the voltage drop violation distribution information of the dynamic power consumption violation area, statistically analyze the voltage drop violation distribution information of the violation standard unit in each of the grid areas.

[0057] The violation standard cell can be a standard cell in the target chip that exhibits an IR drop violation. A standard cell in a chip is a pre-designed and verified circuit module with fixed size and function, reusable for building complex digital circuits. For example, a violation standard cell can be a standard cell whose voltage exceeds the supply voltage by 5%.

[0058] Specifically, based on the correspondence between the dynamic power consumption violation region and each grid region, the voltage drop violation distribution information of the dynamic power consumption violation region can be distributed to each grid region. The voltage drop violation status of the violation standard unit in each grid region can then be statistically analyzed as the voltage drop violation distribution information of the violation standard unit. The voltage drop violation distribution information of the violation standard units included in each grid region may differ.

[0059] In an optional embodiment of this disclosure, the step of statistically analyzing the voltage drop violation distribution information of the violation standard cells in each of the grid regions based on the voltage drop violation distribution information of the dynamic power consumption violation region may include: statistically analyzing the violation area, violation voltage drop target value, and violation voltage threshold of the violation standard cells in each of the grid regions based on the voltage drop violation distribution information of the dynamic power consumption violation region; calculating the violation area ratio based on the violation area of ​​the violation standard cells and the area of ​​the grid regions; and using the violation area ratio, violation voltage drop target value, and violation voltage threshold of the violation standard cells as the voltage drop violation distribution information of the violation standard cells.

[0060] The violation area can be the area occupied by the violation standard cell in the corresponding grid region. The violation voltage drop target value can be the maximum voltage drop of the violation standard cell. The violation voltage threshold can be the voltage threshold referenced in determining whether a standard cell is a violation standard cell. Its value can be configured according to the chip type and actual needs. This disclosure does not limit the specific value of the violation voltage threshold.

[0061] Specifically, for each grid region, based on the voltage drop violation distribution information of the dynamic power consumption violation region, the violation area occupied by the violation standard cell in each grid region, the maximum violation voltage drop of the grid region, and the violation voltage threshold referenced by the violation standard cell can be calculated. Furthermore, the violation area ratio is calculated based on the violation area of ​​the violation standard cell and the area of ​​the grid region. For example, for a grid region A, if the total area of ​​the violation standard cells included in grid region A is B, then the area of ​​grid region A is B. total Then the violation area ratio of grid region A is: r = B / B totalAfter determining the violation area ratio of each grid region, the violation area ratio, violation voltage drop target value, and violation voltage threshold of the violation standard cell in each grid region can be used as the voltage drop violation distribution information of the violation standard cell in that grid region. It is understandable that the violation voltage threshold may differ for different grid regions, because the standards used to determine violations may also differ in different areas of the target chip.

[0062] By statistically analyzing the violation area ratio, violation voltage drop target value, and violation voltage threshold of the violation standard unit in each grid area, the voltage drop violation distribution information of the violation standard unit in the grid area can be used to understand the specific situation of voltage drop violation distribution in each grid area. Thus, based on the actual violation situation in each grid area, targeted compensation priority classification processing can be carried out for each grid area, improving the accuracy of grid area compensation priority classification.

[0063] S240. Based on the voltage drop violation distribution information of the violation standard unit in each grid region, the compensation priority classification is performed on each grid region to obtain the violation priority classification region.

[0064] Correspondingly, after obtaining the voltage drop violation distribution information of the violation standard unit in each grid region, the voltage drop violation distribution information of the violation standard unit in each grid region can be used as a basis to treat each grid region as multiple local regions of the target chip, and the compensation priority of each grid region can be classified. Each grid region can be configured with a corresponding compensation priority. The grid region with the determined compensation priority is a violation priority classification region.

[0065] The above technical solution divides the physical layout of the target chip into multiple grid regions, uses each grid region as a local area, and determines the voltage drop violation distribution information of the violation standard cell in each grid region. This can truly reflect the dynamic power consumption violation situation of each grid region, thereby improving the accuracy of violation priority classification region classification.

[0066] In one optional embodiment of this disclosure, the step of classifying each grid region by compensation priority based on the voltage drop violation distribution information of the violation standard unit in each grid region to obtain the violation priority classification region may include: calculating a violation voltage reference value based on the violation voltage drop target value, the violation voltage threshold, and the standard operating voltage value of the target chip; and classifying each grid region by compensation priority based on the voltage reference value or the violation area ratio to obtain the violation priority classification region.

[0067] The violation voltage reference value can be a reference value calculated based on the power supply conditions of the violation standard unit, and can be used to classify different compensation priorities according to different ranges of the reference value.

[0068] Specifically, assume the target value of the violation pressure drop in the grid region is ΔV. max The violation voltage threshold is V. th V corresponding to different grid regions th The values ​​may differ; the standard operating voltage of the target chip is V. s Then, based on the target value ΔV for the violation pressure reduction, max Violation voltage threshold V th and the standard operating voltage value V of the target chip s The calculated reference value for the violation voltage is: After calculating the reference value of the violation voltage, the compensation priority of each grid area can be classified according to the voltage reference value or the violation area ratio of each grid area, so as to obtain the violation priority classification area with different compensation priorities.

[0069] In an optional embodiment of this disclosure, the step of classifying each grid region according to the voltage reference value or the violation area ratio to obtain the violation priority classification region may include: determining the grid region as a high-priority violation classification region when the voltage reference value is determined to be greater than a first preset threshold, or when the violation area ratio is determined to be greater than a second preset threshold; the compensation priority of the high-priority violation classification region is high priority; determining the grid region as a medium-priority violation classification region when the voltage reference value is determined to be greater than a third preset threshold and less than or equal to the first preset threshold, or when the violation area ratio is determined to be greater than a fourth preset threshold and less than or equal to the second preset threshold; the compensation priority of the medium-priority violation classification region is medium priority; determining the grid region as a low-priority violation classification region when the voltage reference value is determined to be less than or equal to the third preset threshold, or when the violation area ratio is determined to be equal to or equal to the fourth preset threshold; the compensation priority of the low-priority violation classification region is low priority.

[0070] The first preset threshold, the second preset threshold, the third preset threshold, and the fourth preset threshold can be set according to actual needs. The embodiments disclosed herein do not limit the specific values ​​of the first preset threshold, the second preset threshold, the third preset threshold, and the fourth preset threshold.

[0071] In a specific example, assuming the first preset threshold is 2, the second preset threshold is 0.7, the third preset threshold is 1.5, and the fourth preset threshold is 0.4, then if the voltage reference value of a grid region satisfies... If the violation area ratio satisfies r > 0.7, then the grid region can be determined as a high-priority violation classification region; if the voltage reference value of a grid region satisfies If the violation area ratio satisfies 0.4 < r ≤ 0.7, it can be determined that the grid area is a medium-priority violation classification area; if the voltage reference value of a grid area satisfies or the violation area ratio satisfies r ≤ 0.4, it can be determined that the grid area is a low-priority violation classification area. Among them, the compensation priority of the high-priority violation classification area is high priority, the compensation priority of the medium-priority violation classification area is medium priority, and the compensation priority of the low-priority violation classification area is low priority.

[0072] The above technical solution determines the compensation priorities of each violation priority classification area by comparing multi-dimensional reference factors such as voltage reference values and violation area ratios with various threshold boundaries of corresponding configurations, thereby improving the flexibility of the compensation priority classification processing of the violation priority classification area.

[0073] S250. Determine the local power network compensation strategy for each of the violation priority classification areas according to the compensation priority of the violation priority classification area.

[0074] In an optional embodiment of the present disclosure, the determining the local power network compensation strategy for each of the violation priority classification areas according to the compensation priority of the violation priority classification area may include: when it is determined that the compensation priority of the violation priority classification area is high priority, determining the local power network compensation strategy for the violation priority classification area as: increasing the width of the power line or ground line of the high-level metal, adjusting the density of the low-level metal according to the high-priority adjustment gradient, and increasing the DCAP (Decoupling Capacitor) unit; when it is determined that the compensation priority of the violation priority classification area is medium priority, determining the local power network compensation strategy for the violation priority classification area as: adjusting the density of the middle and low-level metals according to the medium-priority adjustment gradient; when it is determined that the compensation priority of the violation priority classification area is low priority, determining the local power network compensation strategy for the violation priority classification area as: adjusting the density of the middle and low-level metals according to the low-priority adjustment gradient.

[0075] Among them, the high-priority adjustment gradient, the medium-priority adjustment gradient, and the low-priority adjustment gradient can be configured according to actual needs, and can be the same or different. The embodiments of the present disclosure do not limit this.

[0076] Accordingly, if the compensation priority for the violation priority classification region is determined to be high priority, the local power network compensation strategy adopted for this high-priority violation priority classification region can be determined as follows: increasing the power or ground line width of the upper layer metals, adjusting the density of the lower layer metals according to the high-priority adjustment gradient, and adding DCAP cells. For example, the local power network compensation strategy adopted for the high-priority violation priority classification region can specifically be: increasing the width of the power / ground lines of the upper layer metals in the high-priority violation priority classification region, such as doubling the width of the upper layer power and / or ground lines; simultaneously adjusting the density of the lower layer metals in the high-priority violation priority classification region, such as adjusting the density of the metals in layers M1-M4 from 20% to 50%, and adding DCAP cells. Here, M1-M4 represent different metal layers. Layer M1 represents the metal layer closest to the standard cell.

[0077] If the compensation priority for the violation priority classification region is determined to be medium priority, the local power network compensation strategy adopted for this region can be determined as follows: adjust the density of the low- and middle-layer metals according to the medium priority adjustment gradient. For example, the specific local power network compensation strategy adopted for the medium-priority violation priority classification region can be: appropriately adjust the density of the low- and middle-layer metals in the region, such as increasing the density of the metals in layers M1-M4 from 20% to 50%.

[0078] If the compensation priority for the violation priority classification region is determined to be low, the local power network compensation strategy adopted for this low-priority violation priority classification region can be determined as follows: adjust the density of the middle and low-layer metals according to the low-priority adjustment gradient. For example, the local power network compensation strategy adopted for the low-priority violation priority classification region can be specifically as follows: appropriately adjust the density of the middle and low-layer metals in the low-priority violation priority classification region, such as increasing the density of the metals in layers M1-M4 from 20% to 40%.

[0079] The above technical solution determines an appropriate local power network compensation strategy for violation priority classification areas with different compensation priorities. For high-priority violation priority classification areas, it can not only meet the power network compensation needs of instantaneous high-risk areas, but also reduce the resource waste when performing power network compensation in non-high-risk areas such as medium- and low-priority violation priority classification areas, and effectively improve the resource utilization rate of global power network compensation.

[0080] In an optional embodiment of this disclosure, the above-described chip power network compensation method may further include: compensating the power network of the target chip in a simulation environment according to the local power network compensation strategy of each of the violation priority classification regions; performing dynamic voltage drop simulation based on the power network compensation result of the target chip to obtain voltage drop simulation result; and, if it is determined that the voltage drop simulation result meets the compensation termination condition, using the local power network compensation strategy of each of the violation priority classification regions as the target power network compensation strategy of the target chip.

[0081] The compensation termination condition can be a condition used to determine whether the target chip's power network needs further compensation processing. The target power network compensation strategy can be the power network compensation strategy that the target chip ultimately determines can be adopted. For example, the compensation termination condition can be that the number of IR drop violations of the target chip drops to a set threshold.

[0082] Understandably, once the local power network compensation strategy for each violation priority classification region is determined, a preliminary power network compensation process can be performed on each violation priority classification region of the target chip based on the local power network compensation strategy for each violation priority classification region. However, performing a compensation process on the power network of the target chip once may not completely solve the dynamic power consumption violation problem of the chip, so it is often necessary to iterate and verify the power network compensation process of the chip repeatedly.

[0083] Figure 3 This is a schematic diagram illustrating an incremental optimization and verification process for chip power network compensation provided in an embodiment of this disclosure. In a specific example, such as... Figure 3 As shown, an initial simulation environment for the target chip is constructed based on the initial data packet, and the module units of the target chip are laid out within this initial simulation environment. After the module unit layout is completed, the standard units of the module are further routed. After routing, the dynamic power consumption violation regions of the target chip's current power network can be determined in the simulation environment. Based on the voltage drop violation distribution information of the dynamic power consumption violation regions, the regions are classified into compensation priorities to obtain violation priority classification regions. Furthermore, the local power network compensation strategy for each violation priority classification region is determined based on its compensation priority.

[0084] After determining the local power network compensation strategy for each violation priority category region of the target chip, the power network of the target chip can be compensated in the simulation environment according to the local power network compensation strategy for each violation priority category region. This optimizes the routing of the target chip and verifies the effectiveness of the local power network compensation strategy through the simulation environment. In the simulation environment, the local power network compensation strategy for different violation priority category regions can be converted into corresponding simulation code, thereby executing virtual compensation for each violation priority category region of the target chip in the simulation environment through simulation code. After completing the compensation processing of the current round, the compensated data packets of the target chip can be used as input for iterative placement and routing in the subsequent simulation environment. After all routing is completed, the next step of timing and physical rule checking is performed. At the same time, dynamic voltage drop simulation is performed based on the power network compensation results of the target chip to obtain voltage drop simulation results. The IR Drop violation of the new data packets of the target chip module is verified based on the voltage drop simulation results. If the voltage drop simulation results determine that there are still a large number of violations in the corresponding mesh region of the target chip, it indicates that the target chip does not yet meet the compensation termination condition. At this point, violation priority classification regions that do not meet the compensation termination condition can be selected as target violation priority classification regions, and compensation priority classification is performed again on these target violation priority classification regions. Further, the local power network compensation strategy for each target violation priority classification region is re-determined based on the updated compensation priority of the target violation priority classification regions, and the local power network of each target violation priority classification region is iteratively compensated according to the local power network compensation strategy of each target violation priority classification region until the voltage drop simulation results of all violation priority classification regions of the target chip meet the compensation termination condition. Finally, the local power network compensation strategy determined for each violation priority classification region at the end of the incremental optimization and verification process can be used as the final usable target power network compensation strategy for the target chip.

[0085] The above technical solution, by adopting an incremental local power network compensation strategy combined with a rapid verification method, can significantly reduce the number of chip compensation design iterations, thereby improving the configuration efficiency of the local power network compensation strategy.

[0086] The aforementioned technical solution identifies instantaneous high-risk areas by leveraging the chip's dynamic power consumption characteristics and specifically reinforces the local power network structure, achieving precise optimization of the chip's power network and avoiding global resource waste. Simultaneously, employing an incremental local power network compensation strategy combined with rapid verification significantly reduces the number of chip compensation design iterations, enabling efficient simulation and iterative verification of chip power network compensation. This chip power network compensation method can significantly reduce local voltage drops and electromigration risks, making it suitable for high-performance chip designs using advanced processes below 7nm.

[0087] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information in this technical solution comply with relevant laws and regulations and do not violate public order and good morals.

[0088] It should be noted that any arrangement or combination of the technical features in the above embodiments also falls within the protection scope of this disclosure.

[0089] In one example Figure 4 This is a structural diagram of a chip power network compensation device provided in an embodiment of this disclosure. This embodiment is applicable to situations where the power network of a chip is compensated specifically according to a defined priority. The device is implemented through software and / or hardware and is specifically configured in an electronic device. This electronic device can be a terminal device or a server device, as long as it can execute the chip power network compensation method. This embodiment does not limit the specific type of electronic device.

[0090] like Figure 4 The chip power network compensation device 400 shown includes: a dynamic power consumption violation region determination module 410, a violation priority classification region classification module 420, and a local power network compensation strategy determination module 430. Among them,

[0091] Dynamic power consumption violation region determination module 410 is used to determine the dynamic power consumption violation region of the current power network of the target chip.

[0092] The violation priority classification region classification module 420 is used to classify the dynamic power consumption violation region according to the voltage drop violation distribution information of the dynamic power consumption violation region to obtain the violation priority classification region;

[0093] The local power network compensation strategy determination module 430 is used to determine the local power network compensation strategy for each of the violation priority classification regions based on the compensation priority of the violation priority classification regions.

[0094] This disclosure identifies dynamic power consumption violation regions in the current power network of a target chip. Based on voltage drop violation distribution information within these regions, compensation priorities are categorized to obtain violation priority classification regions. Then, a local power network compensation strategy is determined for each violation priority classification region based on its compensation priority. These local power network compensation strategies can be used to specifically compensate for matching violation priority classification regions within the target chip's current power network, addressing the issues of low efficiency and accuracy in existing chip power network compensation methods and improving both the efficiency and accuracy of chip power network compensation.

[0095] Optionally, the dynamic power consumption violation region determination module 410 is further configured to: perform dynamic power consumption simulation for the target chip in multiple scenarios, extract dynamic current density distribution data in spatial dimension based on the dynamic power consumption simulation results; map the dynamic current density distribution data to the physical layout of the target chip; and determine the dynamic power consumption violation region in the physical layout of the target chip based on the current density mapping result of the physical layout.

[0096] Optionally, the violation priority classification region classification module 420 is further configured to: divide the physical layout of the target chip into multiple grid regions; statistically analyze the voltage drop violation distribution information of the violation standard unit in each grid region based on the voltage drop violation distribution information of the dynamic power consumption violation region; and perform compensation priority classification on each grid region based on the voltage drop violation distribution information of the violation standard unit in each grid region to obtain the violation priority classification region.

[0097] Optionally, the violation priority classification region classification module 420 is further configured to: statistically analyze the violation area, violation voltage drop target value, and violation voltage threshold of the violation standard unit in each of the grid regions based on the voltage drop violation distribution information of the dynamic power consumption violation region; calculate the violation area ratio based on the violation area of ​​the violation standard unit and the area of ​​the grid region; and use the violation area ratio, violation voltage drop target value, and violation voltage threshold of the violation standard unit as the voltage drop violation distribution information of the violation standard unit.

[0098] Optionally, the violation priority classification region classification module 420 is further configured to: calculate a violation voltage reference value based on the violation voltage drop target value, the violation voltage threshold, and the standard operating voltage value of the target chip; and perform compensation priority classification on each of the grid regions based on the voltage reference value or the violation area ratio to obtain the violation priority classification region.

[0099] Optionally, the violation priority classification region classification module 420 is further configured to: determine the grid region as a high-priority violation classification region when it is determined that the voltage reference value is greater than a first preset threshold, or when it is determined that the violation area ratio is greater than a second preset threshold; the compensation priority of the high-priority violation classification region is high priority; determine the grid region as a medium-priority violation classification region when it is determined that the voltage reference value is greater than a third preset threshold and less than or equal to the first preset threshold, or when it is determined that the violation area ratio is greater than a fourth preset threshold and less than or equal to the second preset threshold; the compensation priority of the medium-priority violation classification region is medium priority; determine the grid region as a low-priority violation classification region when it is determined that the voltage reference value is less than or equal to the third preset threshold, or when it is determined that the violation area ratio is equal to or equal to the fourth preset threshold; the compensation priority of the low-priority violation classification region is low priority.

[0100] Optionally, the local power network compensation strategy determination module 430 is further configured to: when the compensation priority of the violation priority classification region is determined to be high priority, determine the local power network compensation strategy of the violation priority classification region as follows: increase the power line or ground line width of the upper layer metal, adjust the density of the lower layer metal according to the high priority adjustment gradient, and add DCAP units; when the compensation priority of the violation priority classification region is determined to be medium priority, determine the local power network compensation strategy of the violation priority classification region as follows: adjust the density of the middle and lower layer metals according to the medium priority adjustment gradient; when the compensation priority of the violation priority classification region is determined to be low priority, determine the local power network compensation strategy of the violation priority classification region as follows: adjust the density of the middle and lower layer metals according to the low priority adjustment gradient.

[0101] Optionally, the above-mentioned device further controls the compensation verification module, which is used to: compensate the power network of the target chip in a simulation environment according to the local power network compensation strategy of each of the violation priority classification regions; perform dynamic voltage drop simulation based on the power network compensation result of the target chip to obtain the voltage drop simulation result; and, if it is determined that the voltage drop simulation result meets the compensation termination condition, use the local power network compensation strategy of each of the violation priority classification regions as the target power network compensation strategy of the target chip.

[0102] The aforementioned chip power network compensation device can execute the chip power network compensation method provided in any embodiment of this disclosure, and has the corresponding functional modules and beneficial effects for executing the method. Technical details not described in detail in this embodiment can be found in the chip power network compensation method provided in any embodiment of this disclosure.

[0103] Since the chip power network compensation device described above is an apparatus capable of executing the chip power network compensation method in the embodiments of this disclosure, those skilled in the art can understand the specific implementation methods and various variations of the chip power network compensation device in this embodiment based on the chip power network compensation method described in the embodiments of this disclosure. Therefore, how the chip power network compensation device implements the chip power network compensation method in the embodiments of this disclosure will not be described in detail here. Any apparatus used by those skilled in the art to implement the chip power network compensation method in the embodiments of this disclosure falls within the scope of protection intended by this disclosure.

[0104] In one example, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0105] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0106] like Figure 5 As shown, device 500 includes a computing unit 501, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 502 or a computer program loaded from storage unit 508 into random access memory (RAM) 503. RAM 503 may also store various programs and data required for the operation of device 500. The computing unit 501, ROM 502, and RAM 503 are interconnected via bus 504. Input / output (I / O) interface 505 is also connected to bus 504.

[0107] Multiple components in device 500 are connected to I / O interface 505, including: input unit 506, such as keyboard, mouse, etc.; output unit 507, such as various types of monitors, speakers, etc.; storage unit 508, such as disk, optical disk, etc.; and communication unit 509, such as network card, modem, wireless transceiver, etc. Communication unit 509 allows device 500 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0108] The computing unit 501 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 501 performs the various methods and processes described above, such as chip power network compensation methods.

[0109] Optionally, the chip power network compensation method may include: determining the dynamic power consumption violation region of the current power network of the target chip; classifying the dynamic power consumption violation region into compensation priority regions based on the voltage drop violation distribution information of the dynamic power consumption violation region to obtain violation priority classification regions; and determining the local power network compensation strategy for each violation priority classification region based on the compensation priority of the violation priority classification regions.

[0110] For example, in some embodiments, the chip power network compensation method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by computing unit 501, one or more steps of the chip power network compensation method described above may be performed. Alternatively, in other embodiments, computing unit 501 may be configured to perform the chip power network compensation method by any other suitable means (e.g., by means of firmware).

[0111] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0112] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0113] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0114] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0115] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0116] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is established by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, also known as cloud computing servers or cloud hosts, which are hosting products within the cloud computing service ecosystem to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers integrated with blockchain technology.

[0117] This disclosure identifies dynamic power consumption violation regions in the current power network of a target chip. Based on voltage drop violation distribution information within these regions, compensation priorities are categorized to obtain violation priority classification regions. Then, a local power network compensation strategy is determined for each violation priority classification region based on its compensation priority. These local power network compensation strategies can be used to specifically compensate for matching violation priority classification regions within the target chip's current power network, addressing the issues of low efficiency and accuracy in existing chip power network compensation methods and improving both the efficiency and accuracy of chip power network compensation.

[0118] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0119] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip power network compensation method, comprising: Identify the dynamic power consumption violation region of the target chip's current power network; The dynamic power consumption violation region is classified into compensation priority categories based on the voltage drop violation distribution information of the dynamic power consumption violation region to obtain the violation priority classification region; The local power network compensation strategy for each violation priority classification region is determined based on the compensation priority of the violation priority classification region.

2. The chip power network compensation method according to claim 1, wherein, The determination of the dynamic power consumption violation region of the target chip includes: The target chip is subjected to dynamic power consumption simulation in multiple scenarios, and the dynamic current density distribution data in the spatial dimension is extracted based on the dynamic power consumption simulation results. The dynamic current density distribution data is mapped to the physical layout of the target chip; The dynamic power consumption violation region in the physical layout of the target chip is determined based on the current density mapping result of the physical layout.

3. The chip power network compensation method according to claim 1, wherein, The step of classifying the dynamic power consumption violation region according to the voltage drop violation distribution information of the dynamic power consumption violation region to obtain a violation priority classification region includes: The physical layout of the target chip is divided into multiple grid regions; Based on the voltage drop violation distribution information of the dynamic power consumption violation region, the voltage drop violation distribution information of the violation standard cell in each of the grid regions is statistically analyzed; Based on the voltage drop violation distribution information of the violation standard unit in each grid region, the compensation priority classification is performed on each grid region to obtain the violation priority classification region.

4. The chip power network compensation method according to claim 3, wherein, The step of statistically analyzing the voltage drop violation distribution information of the violation standard cells in each of the grid regions based on the voltage drop violation distribution information of the dynamic power consumption violation region includes: Based on the voltage drop violation distribution information of the dynamic power consumption violation region, the violation area, violation voltage drop target value, and violation voltage threshold of the violation standard cell in each of the grid regions are statistically analyzed. The violation area ratio is calculated based on the violation area of ​​the violation standard unit and the area of ​​the grid region; The violation area ratio, violation voltage drop target value, and violation voltage threshold of the violation standard unit are used as the voltage drop violation distribution information of the violation standard unit.

5. The chip power network compensation method according to claim 4, wherein, The compensation priority classification of each grid region is performed based on the voltage drop violation distribution information of the violation standard unit in each grid region to obtain the violation priority classification region, including: Calculate the violation voltage reference value based on the violation voltage drop target value, the violation voltage threshold, and the standard operating voltage value of the target chip; The compensation priority classification of each grid region is performed based on the voltage reference value or the violation area ratio to obtain the violation priority classification region.

6. The chip power network compensation method according to claim 5, wherein, The step of classifying each grid region according to the voltage reference value or the violation area ratio to obtain the violation priority classification region includes: If the voltage reference value is determined to be greater than a first preset threshold, or if the violation area ratio is determined to be greater than a second preset threshold, the grid area is determined to be a high-priority violation classification area; the compensation priority of the high-priority violation classification area is high priority. If the voltage reference value is determined to be greater than the third preset threshold and less than or equal to the first preset threshold, or if the violation area ratio is determined to be greater than the fourth preset threshold and less than or equal to the second preset threshold, the grid area is determined to be a medium-priority violation classification area; the compensation priority of the medium-priority violation classification area is medium priority. If the voltage reference value is determined to be less than or equal to the third preset threshold, or if the violation area ratio is determined to be equal to or equal to the fourth preset threshold, the grid area is determined to be a low-priority violation classification area; the compensation priority of the low-priority violation classification area is low priority.

7. The chip power network compensation method according to any one of claims 1-6, wherein, The step of determining the local power network compensation strategy for each violation priority classification region based on the compensation priority of the violation priority classification region includes: When the compensation priority of the violation priority classification region is determined to be high priority, the local power network compensation strategy for the violation priority classification region is determined as follows: increase the power line or ground line width of the upper layer metal, adjust the density of the lower layer metal according to the high priority adjustment gradient, and add decoupling capacitor DCAP unit. If the compensation priority of the violation priority classification region is determined to be medium priority, the local power network compensation strategy for the violation priority classification region is determined as follows: adjust the density of the low- and middle-layer metals according to the medium priority adjustment gradient. If the compensation priority of the violation priority classification region is determined to be low priority, the local power network compensation strategy for the violation priority classification region is determined to be: adjust the density of the middle and lower layer metals according to the low priority adjustment gradient.

8. The chip power network compensation method according to claim 7 further includes: The power network of the target chip is compensated in the simulation environment according to the local power network compensation strategy of each violation priority classification region. Dynamic voltage drop simulation is performed based on the power network compensation results of the target chip to obtain the voltage drop simulation results; If the voltage drop simulation results are determined to meet the compensation termination condition, the local power network compensation strategy of each violation priority classification region is taken as the target power network compensation strategy of the target chip.

9. A chip power network compensation device, comprising: The dynamic power consumption violation region determination module is used to determine the dynamic power consumption violation region of the current power network of the target chip. The violation priority classification region classification module is used to classify the dynamic power consumption violation region according to the voltage drop violation distribution information of the dynamic power consumption violation region to obtain the violation priority classification region; The local power network compensation strategy determination module is used to determine the local power network compensation strategy for each of the violation priority classification regions based on the compensation priority of the violation priority classification regions.

10. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the chip power network compensation method according to any one of claims 1-8.

11. A non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the chip power network compensation method according to any one of claims 1-8.

12. A computer program product comprising a computer program / instructions, wherein, When the computer program / instruction is executed by the processor, it implements the chip power network compensation method according to any one of claims 1-8.

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