Method for emulating an EEPROM memory

Abstract

Method for Emulating an EEPROM Memory This description relates to a method for emulating an EEPROM memory in a phase-change memory (104) of a circuit integrating a microprocessor, the method comprising the following steps: defining a write granularity in lines of the phase-change memory as a function of the size of the data packets to be written (EEelement1, EEelement2, EEelement3); associating with each data packet a first error-correcting code (ECC1, ECC2, ECC3) calculated by a program (SW) executed by said microprocessor; and storing the error-correcting codes of the data packets in the same line as the packets. Figure for the abstract: Fig. 3

Description

Title of the invention: Method for emulating an EEPROM memory technical field

[0001] This description relates generally to EEPROM memory emulation methods and memory circuits implementing these methods. Prior art

[0002] Many applications require non-volatile data storage during use. Electrically-Erasable Programmable Read-Only Memory (EEPROM) can be used for this purpose. These EEPROMs are often external to the integrated circuits that use them.

[0003] It has already been proposed to emulate the operation of an EEPROM memory in a flash memory integrated into a system-on-chip (System on Chip). These solutions are dedicated to flash memories and are not transferable to other memory technologies. Summary of the invention

[0004] There is a need for a device incorporating a memory that functions similarly to an EEPROM memory but is compatible with a memory technology other than flash memory. More specifically, there is a need for a solution to emulate an EEPROM memory in a phase-change memory.

[0005] One embodiment provides a method for emulating an EEPROM memory in a phase-change memory of a circuit integrating a microprocessor, the method comprising the following steps: - define a writing granularity in phase-change memory lines based on the size of data packets to be written; - to associate with each data packet a first error-correcting code calculated by a program executed by said microprocessor; and - store the error correction codes of the data packets in the same line as the packets themselves.

[0006] According to one embodiment, a phase-change memory line has the capacity to store at least two data packets associated with their first error-correcting codes.

[0007] According to one embodiment, each line of the phase-change memory comprises a data area and a storage area for a second error-correcting code calculated by a hardware operator for the corresponding line, the storage said second error-correcting code being disabled when the line is used in EEPROM emulation.

[0008] According to one embodiment, the data packets and their first error-correcting codes are stored in said data area.

[0009] According to one embodiment, each first error-correcting code is written following the data packet to which it corresponds.

[0010] According to one embodiment, the data packets and their respective first error-correcting codes are written one after the other.

[0011] According to one embodiment, the writing granularity depends on a parameter that can be modified by a user.

[0012] One embodiment provides for an integrated circuit, comprising a phase-change memory and a microprocessor, configured to implement such a process. Brief description of the drawings

[0013] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0014] [Fig.1] represents an example of an integrated circuit of the type to which the described embodiments apply;

[0015] [Fig.2] illustrates the implementation of an example of a common emulation method of an EEPROM memory in a phase-change memory;

[0016] Figure 3 illustrates the implementation of a method for emulating an EEPROM memory according to one embodiment; and

[0017] [Fig.4] illustrates the implementation of a method for emulating an EEPROM memory according to another embodiment. Description of the implementation methods

[0018] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0019] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0020] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.

[0021] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0022] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0023] Fig. 1 represents an example of an integrated circuit of the type to which the described embodiments apply.

[0024] More specifically, [Fig. 1] represents an example of an integrated circuit device 100 incorporating a phase-change memory 104 (PCM). The device 100 includes a phase-change memory 104 (PCM) capable of communicating, via a communication bus 114, with a driver circuit 106 configured to write or read data into or from the memory 102. The driver circuit 106 includes, for example, a dedicated hardware circuit which, when activated, is configured to calculate an error-correcting code (ECC) when writing each element into the memory 102.

[0025] The device 100 further includes, for example, a processing unit 110 (CPU) comprising one or more processors under the control of instructions stored in an instruction memory 112 (INSTR MEM). The instruction memory 112 is, for example, of the random access type (RAM). The processing unit 110 and the memory 112 communicate, for example, via a system bus 140 (data, address, and control bus). The memory 102 is connected to the system bus 140 via the driver circuit 106 and the communication bus 114. The device 100 further includes an input / output interface 108 (FO INTERFACE) connected to the system bus 140 for communication with the outside world.

[0026] The device 100 can integrate other circuits implementing other functions (for example, one or more volatile and / or non-volatile memories, other processing units), symbolized by a block 116 (FCT) in [Fig.1].

[0027] The described embodiments provide for emulating EEPROM-type memory operation in the phase-change memory 104 of the device 100. In other words, a portion of the phase-change memory of the integrated circuit 100 is allocated for data storage by emulating EEPROM-type operation.

[0028] Emulating EEPROM-type operation makes it possible, in particular, to make the device 100 compatible with applications or programs designed to work with EEPROM memories without having to adapt them to the nature of the phase-change memory integrated into the device, and to take advantage of a memory technology (phase-change memories) that is less expensive than the EEPROM technology. In particular, this allows applications designed for operation with EEPROM memory to function with a circuit integrating phase-change memory, thus avoiding the need for external memory.

[0029] Among the criteria that must be met when emulating EEPROM memory operation, one must note the need to respect the write granularity, that is, the size of the EEPROM data packets intended by the application. Typically, the word size is one or two bytes, and these words are grouped (encapsulated) into packets or elements of four, six, or eight bytes. For example, the write granularity depends on the size of the EEPROM memory lines with which the application is designed to operate.

[0030] Among the characteristics of a phase-change memory, it should be noted that it can be written with a granularity ranging from one byte to the size of a memory line, generally sixteen bytes or even more. The circuit 106 is therefore capable, depending on the size of the data to be written, of addressing only a portion of a line.

[0031] As with any memory write operation, it is necessary to associate an error-correcting code with each data write, stored in the same memory row. In a phase-change memory, this error-correcting code is calculated by the 106 circuit in hardware, typically through a combinational process. Furthermore, efforts are made to optimize the cycle time, that is, the number of write operations, since this determines the memory lifetime.

[0032] Fig. 2 illustrates the implementation of an example of a method for emulating an EEPROM memory in a phase-change memory.

[0033] The example in [Fig. 2] illustrates more specifically the content of a line of a phase-change memory after two steps A) and B) of writing EEPROM elements or packets. Although only one line 210 is shown, the memory 102 comprises several dozen, hundreds, or thousands of lines in all or part of which the writing process is implemented. In the example shown, each line of the phase-change memory has a 128-bit (16-byte) data area 202 and a 16-bit (2-byte) area for storing the error-correcting code for that data line. The number of bytes written simultaneously to the data area 202 is configurable at the circuit 106 level by one or more configuration or user option bytes.

[0034] In the example in [Fig.2], it is assumed that we wish to emulate, in memory 102, the writing of 64-bit EEPROM-type data packets. Data area 202 is therefore configured to write 8-byte sections.

[0035] Step A) illustrates the writing of a first element EEelementl into the first 64 bits of data area 202 via the driver circuit 106. The error-correcting code ECC associated with the content of data area 202 (element EElementl and content of the following 64 bits) is calculated by circuit 106 and stored in area 204. At the end of step A, half (in this example) of data area 202 is unused.

[0036] One solution would be to implement emulation in such a way as to allocate a line 210 of memory 102 to each EEPROM data packet. However, due to the size difference between the lines of memory 102 and the EEPROM elements, too much memory space would be wasted. Another possibility would have been to size the phase-change memory according to the size of the EEPROM elements. However, this would not allow for the emulation of EEPROM memory in existing circuits. Furthermore, the size of the EEPROM elements is likely to vary depending on the application being run and for which EEPROM operation is to be emulated.

[0037] The solution illustrated in [Fig. 2] (step B)) consists of using the remainder of data area 202 to store a second EEPROM element EEelement2. Thus, in the example of 8-byte elements and a 16-byte data area 202, the entire write area is used. However, the error-correcting code for area 202 must be recalculated, and a new ECC' code is written to area 204 of the line, replacing the previous ECC error-correcting code.

[0038] The need to rewrite the error-correcting code in the same area 204 when a second EEPROM element is written to the same line halves the number of possible cycles of the phase-change memory data area 204. This loss of memory lifetime is all the more significant when the difference between the size of the EEPROM packets and the size of line 210 is large. Furthermore, since the calculation of the error-correcting codes is performed by a dedicated hardware circuit, it is complex to modify its operation once in production to adapt it, if necessary, to the desired EEPROM behavior (number of detectable errors and number of correctable errors).

[0039] According to the described embodiments, when an EEPROM is to be emulated in a phase-change memory, the error-correcting codes for the EEPROM elements to be stored in the phase-change memory are calculated in software, and each pair of EEPROM elements and error-correcting codes is stored sequentially in the data area of ​​a line in the phase-change memory. This allows full use of the configurable write granularity of the phase-change memory to match this granularity to the size of the records (element + code) required for EEPROM emulation, depending on the application. Furthermore, thanks to the configurable write granularity in the phase-change memory, the error-correcting codes are written to the data area 202 once the EEPROM packet is complete. Writing it down is not a problem.

[0040] By proceeding in this manner, the hardware error-correcting code in area 204 is no longer needed, and its storage can be disabled in the portion of the phase-change memory allocated to EEPROM emulation. This prevents any reduction in the lifespan of the phase-change memory. The trade-off is a reduction in the total available size of a phase-change memory line in EEPROM emulation mode, corresponding to area 204, which cannot be used in EEPROM mode. Indeed, due to the circuit structure, this area is reserved for the hardware-calculated error-correcting code.

[0041] The size of the portion (number of lines) of the phase change memory allocated to data storage "EEPROM" depends on the application and the memory capacity that is to be reserved for program code in the remainder of the phase change memory and for data in the emulated portion. This configuration is performed using the usual configuration bytes or User Option Bytes.

[0042] Figure 3 illustrates the implementation of a method for emulating an EEPROM memory according to one embodiment.

[0043] The example in [Fig. 3] more specifically illustrates two steps, A') and B'), of writing EEPROM-type elements to the same line of the phase-change memory 104. Each line of the phase-change memory comprises, as in [Fig. 2], a data area 202 and an adjacent area 204 dedicated to the hardware error-correcting code. In the example in [Fig. 3], however, area 204 is no longer written to the portion of the memory allocated to EEPROM emulation. To achieve this, the user configuration bytes intended for the circuit 106 include one or more bits that condition the recording of the calculated code in area 204. It is thus possible to prevent the error-correcting code from being written to the phase-change memory lines allocated to EEPROM emulation.As mentioned previously, this allows you to take advantage of the configurable granularity of the records (element + associated error-correcting code) without impacting the lifetime of the phase-change memory. If necessary, the configuration bytes also disable the hardware error-correcting code operator.

[0044] In [Fig.3], we assume the need to store records (EEPROM elements + error-correcting code) of 64 bits, i.e. up to two EEPROM elements per line 210.

[0045] In a step A'), a first EEPROM element EEelementl is written to the first 48 bits of the write area 202 via the driver circuit 106. An error-correcting code ECC1 associated with the writing of the first EEPROM element EEelementl is calculated by an executable program (SW) by a microprocessor, for example the processing unit 110 or a microprocessor of the driver circuit 106, then written to area 202 of memory line 102 following the first EEPROM element EEelementl. The ECC1 error correction code, for example, is 16 bits in size.

[0046] In a step B'), a second 48-bit EEPROM element EEelement2 is written in the next 64 bits adjacent to the space where the error-correcting code ECC1 is written. An error-correcting code ECC2 associated with the writing of the second EEPROM element EEelement2 is calculated by the microprocessor-based executable program SW and then written to area 202 of the line following the error-correcting code ECC1 of the second EEPROM element EEelement2.

[0047] Figure 4 illustrates the implementation of a method for emulating an EEPROM memory according to another embodiment.

[0048] Compared to the embodiment of [Fig. 3], it is assumed that the application requiring the emulation of an EEPROM memory needs to store smaller packets or elements, for example, 4 bytes (32 bits). Their error-correcting code is then also smaller (for identical characteristics in terms of the number of detectable and correctable errors), for example, 12 bits. Three records (EEPROM element + error-correcting code) can then be stored per line 210 of the phase-change memory. The gain in terms of cycling compared to the solution of [Fig. 2], by avoiding rewriting area 204 three times, is then even greater than with the embodiment of [Fig. 3]. The three EEPROM elements EEelement1, EEelement2 and EEelement3 are written successively one after the other with interposition of their respective error correction codes ECC1, ECC2, ECC3, calculated by software.

[0049] More generally, the number of EEPROM elements that can be stored per line depends on the required size for the EEPROM records and the line size. The proposed solution provides a gain in terms of cycling as soon as at least two elements can be stored per phase-change memory line.

[0050] Another advantage is that using the microprocessor-executable program SW instead of the usual dedicated hardware circuit HW for calculating error-correcting codes offers flexibility in terms of parameterizing the error-correcting code (number of detectable errors and number of correctable errors).

[0051] Another advantage of the described solution is that its implementation does not require any hardware or structural modification of the circuit integrating the phase-change memory. Thus, it makes it possible to emulate EEPROM memory operation in existing integrated circuits that have phase-change memory.

[0052] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to the person skilled in the art. business. In particular, the sizes of the EEPROM elements (preferably 4, 6 or 8 bytes), of the software-calculated error-correcting codes (preferably 8, 12 or 16 bits respectively for 32, 48 or 64 bit data packets), of the 202 data areas (preferably 128 or 256 bits) of the phase-change memory lines, and of the portion (number of lines) of this memory allocated to EEPROM emulation depends on the application.

[0053] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, with regard to the arrangement of the EEPROM elements and their associated error-correcting codes in the memory lines 102, it is conceivable that all the error-correcting codes be grouped at the end of data area 202. A person skilled in the art may also consider one or more free spaces between one of the EEPROM elements and the associated error-correcting code. However, an advantage of storing each error-correcting code after the packet to which it is associated is that this simplifies memory addressing by avoiding, particularly during reading, the need to address the error-correcting codes separately from the packets to which they correspond.

Claims

Demands

1. Method of emulating an EEPROM memory in a phase-change memory (104) of a circuit integrating a microprocessor, the method comprising the following steps: - defining a write granularity in lines of the phase-change memory as a function of the size of data packets to be written (EEelement1, EEelement2, EEelement3); - associating with each data packet, a first error-correcting code (ECC1, ECC2, ECC3) calculated by a program (SW) executed by said microprocessor; and - storing the error-correcting codes of the data packets in the same line as the latter.

2. A method according to claim 1, wherein one line (210) of the phase-change memory has the capacity to store at least two data packets associated with their first error-correcting codes.

3. A method according to claim 1 or 2, wherein each phase-change memory line has a data area (202) and a storage area (204) for a second error-correcting code calculated by a hardware operator for the corresponding line, the storage of said second error-correcting code being disabled when the line is used in EEPROM emulation.

4. A method according to claim 3, wherein the data packets and their first error-correcting codes are stored in said data area.

5. A method according to any one of claims 1 to 4, wherein each first error-correcting code (ECC) is written following the data packet (EEelement1, EEelement2, EEelement3) to which it corresponds.

6. A method according to any one of claims 1 to 5, wherein the data packets (EEelement1, EEelement2, EEelement3) and their respective first error-correcting codes (ECC1, ECC2, ECC3) are written one after the other.

7. A method according to any one of claims 1 to 6, wherein the writing granularity depends on a user-modifiable parameter.

8. Integrated circuit, comprising a phase-change memory (102) and a microprocessor, configured to implement the method according to any one of claims 1 to 7.

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