Diffused resistor semiconductor device, associated control method and sensor

Abstract

Semiconductor device with diffused resistors, associated control method and sensor The present description relates to an electronic device (10) comprising first (12') and second (12) diffused resistors in contact with each other so as to form a PN junction, the device being configured so that the potential difference between the first and second resistors is constant at any point of the PN junction, the device being configured so that the PN junction is reverse biased. Figure for abstract: Fig. 1C

Description

Title of the invention: Diffused resistor semiconductor device, associated control method and sensor Technical field

[0001] The present description relates generally to electronic devices and more specifically to devices comprising resistors and their control methods. Prior art

[0002] A resistor is an electronic or electrical component whose main characteristic is to oppose a greater or lesser resistance to the circulation of an electric current.

[0003] In integrated circuit technology, two main categories of resistors are known: polycrystalline silicon resistors and diffused or implanted resistors, i.e. those using dopants of different types (typically P and N) in a semiconductor substrate (typically silicon).

[0004] The present description concerns the second category of resistors. Summary of the invention

[0005] One embodiment overcomes all or part of the drawbacks of devices comprising known diffused resistors.

[0006] One embodiment provides an electronic device comprising first and second diffused resistors in contact with each other so as to form a PN junction, the device being configured so that the potential difference between the first and second resistors is constant at any point of the PN junction, the device being configured so that the PN junction is reverse biased.

[0007] Another embodiment provides a method for controlling a device comprising first and second diffused resistors in contact with each other so as to form a PN junction, the potential difference between the first and second resistors being constant at any point of the PN junction, the device being configured so that the PN junction is reverse biased.

[0008] According to one embodiment, each of the first and second diffused resistors is made of doped semiconductor materials, the first and second diffused resistors being doped with opposite conductivity types.

[0009] According to one embodiment, the first resistor comprises a first layer buried in a substrate and first wells, the first regions extending from the periphery of the first layer towards a first face of the substrate, the first layer and the first wells being made of a doped semiconductor material of a first conductivity type; and the second resistor comprises a second layer resting on the first layer, the second layer being made of a doped semiconductor material of a second conductivity type.

[0010] According to one embodiment, the second resistor comprises a third semiconductor layer doped with a first conductivity type, the third layer being flush with an upper face of a substrate; and the first resistor comprises a second layer of a semiconductor material doped with a second conductivity type, the third layer resting on the second layer.

[0011] According to one embodiment, the device further comprises a third resistor, the third resistor comprising a first layer buried in the substrate and first wells, the first wells extending from the periphery of the first layer towards the first face of the substrate, the first layer and the first wells being made of a semiconductor material doped with a first conductivity type, the first layer and the first wells delimiting the second layer.

[0012] According to one embodiment, the PN junction between the first and third resistors is configured to be reverse biased.

[0013] According to one embodiment, the first resistor comprises a semiconductor well in a substrate, the well being doped with the type opposite to the doping type of the substrate; and the second resistor comprises a third semiconductor layer doped with the type opposite to the doping type of the well, the third layer being flush with an upper face of a substrate.

[0014] According to one embodiment, each of the resistors comprises a first end and a second end, each resistor comprising, at the first and second ends, a semiconductor region, more heavily doped than the rest of the resistor, constituting a terminal of said resistor.

[0015] According to one embodiment, each first and second resistor comprises first and second terminals, the second terminals of the first and second resistors being connected to the same first node for applying a reference voltage.

[0016] According to one embodiment, the device comprises a control circuit configured to provide the potentials on the terminals of the first and second resistors.

[0017] According to one embodiment, the control circuit comprises a first transistor connected in series with the first resistor between a second node for applying a supply voltage and the first node and a second transistor connected in series with the second resistor between the second node and the first node, the first and second transistors being mounted as a diode.

[0018] According to one embodiment, the first transistor has a channel width to length ratio equal to the channel width to length ratio of the second transistor multiplied by the quotient of the value of the second resistor to the value of the first resistor.

[0019] According to one embodiment, the device is configured so that the potential difference between the first and second resistors is zero at any point of the PN junction.

[0020] Another embodiment provides a sensor comprising a device as described above, the sensor being configured so that a measurement value of the sensor is dependent on the resistance value of the second resistor. Brief description of the drawings

[0021] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0022] [Fig.1A] is a top view of an embodiment of a device comprising a diffused resistor;

[0023] [Fig.lB] is a sectional view of the embodiment of [Fig.lA];

[0024] [Fig.lC] is another sectional view of the embodiment of [Fig.lA];

[0025] [Fig.2A] is a top view of another embodiment of a device comprising a diffused resistor;

[0026] [Fig.2B] is a sectional view of the embodiment of [Fig.2A];

[0027] [Fig.2C] is a sectional view of an embodiment of [Fig.2A];

[0028] [Fig.2D] is a sectional view of an embodiment of [Fig.2A];

[0029] [Fig.3] represents an example of a circuit comprising a diffused resistor;

[0030] [Fig.4] represents another circuit comprising a diffused resistor;

[0031] [Fig.5] represents an application of the embodiments described previously;

[0032] [Fig.6A] is a top view of another embodiment of a device comprising a diffused resistor;

[0033] [Fig.6B] is a sectional view of the embodiment of [Fig.6A]; and

[0034] [Fig.6C] is a sectional view of an embodiment of [Fig.6A]. Description of the embodiments

[0035] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0036] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0037] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0038] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0039] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0040] A diffused (or implanted) resistor is formed in a semiconductor substrate, for example silicon, of a generally elongated region in the manner of a bar of a first conductivity type (P or N) in a well, or the substrate, of a second conductivity type (N or P). Contact points at both ends of the bar define the terminals of the resistor and the well is biased so that the PN junction is reversed.

[0041] Among other things, due to the presence of a PN junction and the need to reverse-polarize this junction to obtain the resistive effect between the ends of the bar, diffused resistors suffer from a lack of stability of the resistance value with voltage variations. In other words, the resistance value varies with the voltage applied to its terminals.

[0042] The embodiments described provide for making the value of a diffused (or implanted) resistor voltage stable, that is to say making the value of the resistor independent of the potentials applied to its terminals.

[0043] According to the embodiments described, provision is made to polarize the region (the box and the buried region) surrounding the resistive bar to compensate for the voltage instability effect. More particularly, provision is made to carry out a particular polarization of the region surrounding the resistive bar such that the potential difference, at each point of the interface between the resistive bar and the region surrounding it, between the resistive bar and the region surrounding it is constant. Consequently, the voltage gradient which develops in the region surrounding the resistive bar in the longitudinal direction is the same as that developing in the resistive bar. A potential difference is then obtained between the bar and the region of opposite type which surrounds it which is constant whatever the longitudinal position between the two terminals of the bar.This amounts to exploiting the longitudinal resistance (in the direction of the resistive bar) of the region of the opposite conductivity type in which it is. finds the bar. This avoids the variation of the space charge area between the P and N regions in the longitudinal direction of the bar, which makes the value of the resistance independent of the voltages applied to each of its terminals. In other words, the resistance is independent of the potentials at its terminals, therefore of the potential difference between its terminals.

[0044] [Fig.lA] is a top view of an embodiment of a device 10 meeting the above objective. [Fig.lB] is a sectional view along line BB of [Fig.lA]. [Fig.lC] is a sectional view along line CC of [Fig.lA]. Note in response to comments relating to paragraph

[0037] : We will correct the arrows in [Fig.lA]. It is indeed intentional that there is less reference on one side than on the other and this has no effect on the protection. It is just so that one side is more visible than the other by having fewer references.

[0045] The device 10 comprises a substrate 14 (P-) made of a semiconductor material, for example silicon. The substrate 14 is doped, preferably of the P type.

[0046] The device 10 comprises a well 18 of conductivity type (N) opposite to that of the substrate 14, and a layer 16 or plate, of the same conductivity type (N) as the well, buried in the substrate 14 under the well 18. The well 18 is for example a rectangular ring. The well 18 and the buried region 16 delimit, on the front face side, a region 26 of the substrate of the first conductivity type (P-) forming a resistive bar 12. The well 18 and the region 16 form another resistor 12'.

[0047] The layer 16 forms, for example, a strip. The layer 16 has, for example, an approximate shape of a rectangular parallelepiped. The box 18 has the shape of a rectangular ring extending from the front or upper face of the substrate 14 to the buried layer 16. The box 18 comprises a first end 18a and a second end 18b. The first and second ends 18a, 18b preferably correspond to the two opposite sides furthest from each other of the box 18.

[0048] The front face of the substrate, therefore of the device 10, is covered with an insulating layer 15. More precisely, the layer 15 covers, preferably partially, an upper face of the substrate 14. The layer 15 is not shown in [Fig.1A] for greater clarity.

[0049] Contact recovery zones, respectively 20 and 24, are provided in the respective vicinity of the longitudinal ends of the box 18 and of the region 26. The zones 20 and 24 are respectively overdoped N+ and P+ and contacts 22 and 28 define electrical connection terminals of the respective zones 20 and 24.

[0050] An example of a method for forming the device 10 comprises the formation, in a semiconductor substrate, for example P-type doped, of the well 18. The formation of the well 18 is for example carried out by a doping step, for example through the openings of a mask located on the upper face of the substrate. The doping step is such that the wells extend from the upper face of the substrate. The method then comprises a step of forming the layer 16, for example by implanting a doping through the openings of another mask located on the upper face of the substrate. The layer 16 is formed so as to extend partially into the wells 18. There is thus electrical continuity between the layer 16 and the well 18.

[0051] The layer 15 is for example formed after the formation of the well 18. The layer 15 corresponds for example to a shallow insulating trench. The layer 15 is for example formed by a known method of forming a shallow insulating trench, for example comprising the formation of a mask uncovering the locations of the layer 15, the partial etching of the substrate, and the filling of the cavity obtained with an insulating material. Alternatively, the material of the layer 15 can be obtained from the material of the substrate, for example by oxidation.

[0052] At the ends 18a and 18b of the box 18, the layer 15 comprises openings 19a and 19b intended for the formation of the contact recovery zone 20 flush with the upper face of the substrate. Preferably, the thickness of the zones 20 is less than the height of the layer 15.

[0053] Similarly, the layer 15 is open in the vicinity of the ends of the region 26 for the formation of the contact recovery zones 24 and the contacts 28. In other words, the layer 15 comprises openings 19c and 19d intended for the formation of the contact recovery zone 24 flush with the upper face of the substrate. Preferably, the thickness of the zones 24 is less than the height of the layer 15.

[0054] The method for manufacturing the device 10 comprises, for example, a step of forming the regions 20, for example by doping the substrate through openings in another mask located on the upper face of the substrate. More precisely, the formation of the regions 20 comprises the doping of the part of the well 18 flush with the upper face of the substrate. Preferably, the openings in said mask completely uncover the openings 19a and 19b.

[0055] The well 18 and the layer 16 form the resistor 12'. The resistor 12' is a diffused resistor of conductivity type N. The region 20 located in the opening 19a constitutes a first terminal B1 of the resistor 12'. The region 20 located in the opening 19b constitutes a second terminal B2 of the resistor 12'. The contacts 22 are intended to contact the regions 20 so as to connect the resistor 12' to an electronic circuit. The value of the resistor 12' corresponds to the resistance between the terminals B1 and B2. The direction X extending from the terminal B1 to the terminal B2 corresponds to the main direction of the resistor 12' and is represented by an arrow in figures 1A and 1C.

[0056] The method of manufacturing the device 10 comprises for example a step of formation of the regions 24, for example by doping the substrate through openings in a mask located on the upper face of the substrate. Preferably, the openings in said mask completely uncover the openings 19c and 19d.

[0057] Region 26 forms resistor 12. Resistor 12 is a diffused resistor of conductivity type P. Region 24 located in opening 19c constitutes a first terminal A1 of resistor 12. Region 24 located in opening 19d constitutes a second terminal A2 of resistor 12. Contacts 28 are intended to contact regions 24 so as to connect resistor 12 to an electronic circuit. The value of resistor 12 corresponds to the resistance between terminals A1 and A2. The main direction of resistor 12 is the same direction X as the main direction of resistor 12'.

[0058] Resistor 12 is therefore separated from the rest of the P-doped substrate 14 by resistor 12'. Resistor 12 is separated from the rest of the P-doped substrate by a so-called triple well structure formed by well 18 and layer 16. Resistors 12 and 12' are in contact with each other. More precisely, resistor 12 rests on resistor 12'.

[0059] Resistors 12 and 12' are diffused resistors of opposite conductivity type. Resistors 12 and 12', and more precisely the interface between resistors 12 and 12', therefore form a PN junction.

[0060] By denoting VA a voltage applied between the terminals of the resistor 12, i.e. a potential difference VA1-VA2 between the terminals A1 and A2, and VB a voltage applied between the terminals of the resistors 12', i.e. a potential difference VB1-VB2 between the terminals B1 and B2, the voltage differences VB1 - VA1 and VB2 -VA2 are configured so that the PN junction formed between the resistors 12 and 12' is reverse-polarized. In other words, at each point P of contact between the resistor 12 and the resistor 12', the potential VAP of the resistor 12 at point P is less than or equal to the potential VBP of the resistor 12' at point P.

[0061] The device is further configured so that the difference between the potential of the resistor 12' and the potential of the resistor 12 is constant over the entire interface between the resistors 12 and 12' in the X direction. In other words, at any point P of the interface between the resistor 12 and the resistor 12', the difference between the potential VAP, i.e. the potential of the resistor 12 at the point P, and the potential VBP, i.e. the potential of the resistor 12' at the point P, is substantially equal to a constant value k. Thus, the device is configured so that the following equation is followed, in the X direction, over the entire interface between the resistor 12 and the resistor 12': VAP - VBP = k. The value k is a constant value, positive or zero and independent of the voltage values ​​VA and VB. In particular, this equation is followed at the terminals A1, A2, B1, B2. So the following equations are followed in the device: VA1- VB1 = VA2 - VB2 = k.

[0062] For example, the value k is substantially equal to zero. Thus, at any point P of the interface between the resistor 12 and the resistor 12', the potential VAP of the resistor 12 and the potential VBP of the resistor 12' are substantially equal.

[0063] The value of the resistor 12 is stable in voltage but not in temperature. The embodiment described above can therefore be used as a temperature sensor. The resistor 12 then corresponds to the variable element of the sensor, the variations in the resistance value of the resistor 12 being indicative of the variations measured by the sensor, for example indicative of variations in temperature. The sensor has for example an output on which an output signal is generated depending on the resistance value of the resistor 12.

[0064] An advantage of biasing resistors 12 and 12' in the manner described above is that this makes the value of the resistor independent of the voltages applied to each of its terminals. In particular, this avoids variations in the thickness of the space charge region, i.e., a region that is emptied of majority carriers and does not participate in the conduction of the resistor. In conventional diffused resistors, the greater the difference between voltage VAP and voltage VBP at a given point P of the interface between resistors 12 and 12', the larger the space charge region, which increases the value of the resistor. Such dependence on the voltages applied to each of the terminals is particularly problematic when the resistor is used as a sensor, for example a temperature sensor. This space charge region does not appear in Figures 1A to 1C and 2A to 2D.

[0065] [Fig.2A] is a top view of another embodiment of a device 30 in which another diffused resistor 32 is formed. [Fig.2B] is a sectional view of the embodiment of [Fig.2A] along line BB of [Fig.2A]. [Fig.2C] is a sectional view along line CC of [Fig.2A]. [Fig.2D] is a sectional view along a plane DD of [Fig.2A].

[0066] The device 30 comprises elements of the device 10 which will not be described again. In particular, the device 30 comprises: - substrate 14; - layer 15, comprising openings 19a, 19b, 19c and 19d; - resistor 12', i.e. layer 16, well 18 and regions 20; and - resistor 12, i.e. region 26 and regions 24.

[0067] The device 30 further comprises the resistor 32 produced by N-type diffusion in the bar 12 from the front face, of a strip or region 36, so as to obtain a rectangle surrounded (on the sides and below) by the region 26. The layer 15 then comprises an opening 34 located between the openings 19c and 19d. The opening 34 is separated from each of the openings 19c and 19d by a portion of the layer 15. The opening 34 is separated from each of the openings 19a and 19b by portions of the layer 15 and the opening 19c or 19d. The strip 36 is flush with the upper face of the substrate 14, in the opening 34.

[0068] The strip 36 has for example a rectangular parallelepiped shape. Thus, in the top view of [Fig.2A], the strip 36 has for example a rectangular shape. The strip 36 has a first end 36a and a second end 36b. The first and second ends 36a, 36b preferably correspond to the two opposite sides furthest from each other of the strip 36. Regions 38 at these ends 36a, 36b have the same type N of conductivity and define contact recovery zones 40 intended to be connected to an electronic circuit. The region 38 located at the end 36a constitutes a terminal C1 of the resistor 32. The region 38 located at the end 36b constitutes a terminal C2 of the resistor 32. Preferably, the strip 36 is not silicided outside the regions 38. The regions 38 are for example silicided.

[0069] The value of resistor 32 corresponds to the resistance between terminals C1 and C2.

[0070] We note VC a voltage applied between the terminals of the resistor 32, that is a potential difference VC1-VC2 between terminals Cl and C2, and VA a voltage applied between the terminals of resistors 12, i.e. a potential difference VA1-VA2 between terminals Al and A2. The device is configured so that the PN junction formed between resistors 12 and 32 is reverse biased. In other words, at each point P of contact between resistor 12 and resistor 32, potential VCP, i.e. the potential of resistor 32 at point P, is greater than potential VAP, i.e. the potential of resistor 12 at point P. Thus, the potential on terminal Cl is preferably greater than the voltage on terminal AL. Similarly, the potential on terminal C2 is preferably greater than the potential on terminal A2.

[0071] The device is further configured so that the difference between the potential of resistor 32 and the potential of resistor 12 is constant across the entire interface between resistors 12 and 32 in the X direction. In other words, at any point P of the interface between resistor 12 and resistor 32, the difference between the potential VAP of resistor 12 and the potential VCP of resistor 32 is substantially equal to a constant value k. Thus, the device is configured so that the following equation is followed in the X direction across the entire interface between resistor 12 and resistor 32: VAP - VCP = k. The value k is a constant value, positive or zero and independent of the voltage values ​​VA and VC.

[0072] For example, the value k is substantially equal to zero. Thus, at any point P of the interface between the resistor 12 and the resistor 32, the potential VAP of the resistor 12 and the potential VCP of the resistor 32 are substantially equal.

[0073] The device is configured so that the junction between resistors 12 and 12' is not not forward biased. The device is for example configured so that the junction between resistors 12 and 12' is reverse biased. For example, potentials VB1 and VB2 are equal to each other and at the maximum value between potentials VA1 and VA2.

[0074] [Fig. 3] represents an example of a circuit comprising a diffused resistor. More specifically, [Fig. 3] represents a delay generation circuit 42 comprising a diffused resistor 44.

[0075] Resistor 44 corresponds for example to resistor 12 of figures 1A to 1C or to resistor 32 of figures 2A to 2D.

[0076] The device 42 comprises a transistor 46. The transistor 46 is for example an insulated gate field effect transistor or MOSFET. The transistor 46 is for example a P-channel transistor.

[0077] The transistor 46 is connected in series with the resistor 44. The transistor 46 and the resistor 44 are connected in series between a node 48 for applying a supply voltage VDD and a node 50 for applying a reference voltage, for example the ground GND. The transistor 46 is connected between the node 48 and a node 52. The resistor is connected between the node 52 and the node 50. In other words, a conduction terminal of the transistor 46, for example the source, is connected, preferably connected, to the node 48. Another conduction terminal of the transistor 46, for example the drain, is connected, preferably connected, to the node 52.One terminal of resistor 44, for example terminal A2 in the case of resistor 12 or terminal C2 in the case of resistor 32, is connected, preferably connected, to node 52 and another terminal of resistor 44, for example terminal A1 in the case of resistor 12 or terminal C1 in the case of resistor 32, is connected, preferably connected, to node 50.

[0078] The transistor 46 is connected as a diode. In other words, the control terminal of the transistor 46, for example the gate, is connected, preferably connected, to the drain of the transistor 46, that is to say for example connected, preferably connected, to the node 52.

[0079] The circuit 42 further comprises a transistor 54 and a transistor 56. The transistor 54 is for example an insulated gate field effect transistor or MOSFET. The transistor 54 is for example a P-channel transistor. The transistor 56 is for example an insulated gate field effect transistor or MOSFET. The transistor 56 is for example an N-channel transistor.

[0080] Transistors 54 and 56 are connected in series between node 48 and node 50. More specifically, transistor 54 is connected between node 48 and a node 58 and transistor 56 is connected between node 58 and node 50. In other words, a conduction terminal of transistor 54, for example the source, is connected, preferably connected, to node 48. Another conduction terminal of transistor 54, for example the drain, is connected, preferably connected, to node 58. In addition, a conduction terminal of transistor 56, for example the drain, is connected, preferably connected, to node 58. Another conduction terminal conduction of transistor 56, for example, the source is connected, preferably connected, to node 50. Transistor 54 is connected so as to be crossed by a copy of the current passing through transistor 46.

[0081] The transistor 56 is connected as a diode. In other words, the control terminal of the transistor 56, for example the gate, is connected, preferably connected, to the drain of the transistor 56, that is to say for example connected, preferably connected, to the node 58. In addition, the control terminal of the transistor 54, for example the gate, is connected, preferably connected, to the node 52.

[0082] The circuit 42 further comprises a transistor 60 and a transistor 62. The transistor 60 is for example an insulated gate field effect transistor or MOSFET. The transistor 60 is for example a P-channel transistor. The transistor 62 is for example an insulated gate field effect transistor or MOSFET. The transistor 62 is for example an N-channel transistor.

[0083] Transistors 60 and 62 are connected in series between node 48 and node 50. More specifically, transistor 60 is connected between node 48 and a node 64 and transistor 62 is connected between node 64 and node 50. In other words, a conduction terminal of transistor 60, for example the source, is connected, preferably connected, to node 48. Another conduction terminal of transistor 60, for example the drain, is connected, preferably connected, to node 64. In addition, a conduction terminal of transistor 62, for example the drain, is connected, preferably connected, to node 64. Another conduction terminal of transistor 62, for example the source, is connected, preferably connected, to node 50.

[0084] A control terminal of the transistor 60, for example the gate, is connected, preferably connected, to the node 52. A control terminal of the transistor 62 is connected, preferably connected, to an output of an inverter 66. An input of the inverter 66 is connected, preferably connected, to an input node 68. An input signal IN is applied to the node 68. The transistor 60 is connected so as to be crossed by a copy of the current passing through the transistor 46.

[0085] The circuit 42 further comprises a transistor 70 and a transistor 72. The transistor 70 is for example an insulated gate field effect transistor or MOSFET. The transistor 70 is for example a P-channel transistor. The transistor 72 is for example an insulated gate field effect transistor or MOSFET. The transistor 72 is for example an N-channel transistor.

[0086] Transistors 70 and 72 are connected in series between node 48 and node 50. More precisely, transistor 70 is connected between node 48 and a node 74 and transistor 72 is connected between node 74 and node 50. In other words, a conduction terminal of transistor 70, for example the source, is connected, preferably connected, to node 48. Another conduction terminal of transistor 70, for example the drain, is connected, preferably connected, to node 74. In addition, a conduction terminal of the transistor 72, for example the drain, is connected, preferably connected, to node 74. Another conduction terminal of the transistor 72, for example the source, is connected, preferably connected, to node 50.

[0087] A control terminal of transistor 70, for example the gate, is connected, preferably connected, to node 64. Transistor 72 is connected so as to be crossed by a copy of the current passing through transistor 56.

[0088] Circuit 42 includes a capacitor 76. Capacitor 76 is connected between node 64 and node 50. In other words, one terminal of capacitor 76 is connected, preferably connected, to node 64 and another terminal of capacitor 76 is connected, preferably connected, to node 50.

[0089] The node 74 is connected to an output node 78, on which an output signal OUT is generated by the circuit 42. The output signal OUT corresponds to the input signal IN to which a delay has been applied. The node 74 is connected to the node 78 by an inverter 80. In other words, an input terminal of the inverter 80 is connected, preferably connected, to the node 74 and an output terminal of the inverter 80 is connected, preferably connected, to the node 78.

[0090] The circuit 42 further comprises a transistor 82 and a resistor 84. The resistor 84 is a diffused resistor. The resistor 84 corresponds to the resistor 12' in the case of the embodiment of Figures 1A to 1C or to the resistor 12 in the embodiment of Figures 2A to 2D. The transistor 82 is for example an insulated gate field effect transistor or MOSFET. The transistor 82 is for example a P-channel transistor.

[0091] Transistor 82 and resistor 84 are connected in series between node 48 and node 50. More specifically, transistor 82 is connected between node 48 and a node 86. Resistor 84 is connected between node 86 and node 50. In other words, a conduction terminal of transistor 82, for example the source, is connected, preferably connected, to node 48 and another conduction terminal of transistor 82, for example the drain, is connected, preferably connected, to node 86. One terminal of resistor 84, for example terminal B2 in the case of resistor 12' of Figures 1A to 1C or terminal A2 in the case of resistor 12 of the embodiment of Figures 2A to 2D, is connected, preferably connected, to node 86 and another terminal of resistor 84, for example terminal B1 ... IC or terminal A1 in the case of resistor 12 of the embodiment of Figures 2A to 2D, is connected, preferably connected, to node 50.

[0092] The transistor 82 is connected as a diode. In other words, the control terminal of the transistor 82, for example the gate, is connected, preferably connected, to the drain of the transistor 82, that is to say for example connected, preferably connected, to the node 58.

[0093] The size of the transistor 82, that is to say the width to length ratio of the channel, is configured so that the voltage across the resistor 84 is substantially equal to the voltage across the resistor 44. In other words, the size of the transistor 82 is configured so that the potential difference between the terminals of the resistor 84 is substantially equal to the potential difference between the terminals of the resistor 44. For example, the size of the transistor is equal to the size of the transistor 46 multiplied by the quotient Q of the resistance value of the resistor 44 over the resistance value of the resistor 84. For example, the transistor 46 is composed of one or more elementary transistors, the elementary transistors being identical. The transistor 82 is then composed of Q times more identical elementary transistors than the transistor 46.

[0094] The delay generation circuit 42 is configured to apply a delay T to a signal. In other words, when the signal IN takes a value at a time t, for example a binary value '1', the output signal OUT takes said value at a time t+T.

[0095] During operation of the circuit, the current flowing through transistor 46 is equal to (VDD - VtP) / R, VtP corresponding to the threshold voltage of transistor 46 and R corresponding to the value of resistor 44. The current flowing through transistor 60 is proportional to the current flowing through transistor 46 with a ratio of 1 / n, n being a positive integer, transistors 46 and 60 being connected as a current mirror.

[0096] If the input signal IN has a low value, i.e. a value corresponding to the binary value '0', the transistor 62 is on, and the capacitor 76 discharges via the transistor 62, the current flowing through the transistor 62 being greater than the current flowing through the transistor 60.

[0097] If the input signal IN has a high value, i.e. a value corresponding to the binary value '1', the transistor 62 is blocked. The capacitor 76 is therefore charged via the transistor 60. The voltage V across the capacitor 76 follows the following equation V(t) = t*(VDD - VtP) / (n*R*C), C being the capacitance value of the capacitor 76.

[0098] At the start of the charging of the capacitor 76, the voltage V is lower than VDD - VtP, the transistor 70 is thus conducting and the output signal OUT has the binary value '0'. When V reaches the value VDD-VtP, that is to say when t = T = n*R*C, the transistor 70 becomes blocked and the output signal OUT takes the binary value T'.

[0099] In the example of [Fig. 3], the circuit 42 is configured so that the potentials on terminals A1 and B1 are equal to each other and to the voltage VDD - VtP and that the potentials on terminals A2 and B2 are equal to each other and to a zero voltage. For this, terminals A2 and B2 are both connected to node 50. In order to ensure that the potentials on terminals A1 and B1 are equal, the current densities flowing through transistors 82 and 46 must be identical. More precisely, if transistors 46 and 82 each correspond to a plurality of elementary transistors identical to each other others, the current density in each of the elementary transistors must be the same. The potential difference between resistor 44 and resistor 84, which corresponds to the box in which resistor 44 is formed, is thus constant and zero at any point of the interface between resistors 44 and 84.

[0100] An advantage of using a resistor according to the described embodiments is that this makes the generated delay independent of variation in the voltage applied across the resistor, and therefore independent of the supply voltage.

[0101] More generally, an embodiment of a circuit for biasing diffused resistors such as those described in relation to FIGS. 1A to 2D comprises a resistor such as resistor 12 of the embodiment of FIGS. 1A to 1C or resistor 32 of the embodiment of FIGS. 2A to 2D connected in series with a diode-mounted transistor, such as transistor 46, and a resistor such as resistor 12' of the embodiment of FIGS. 1A to 1C or resistor 12 of the embodiment of FIGS. 2A to 2D connected in series with a diode-mounted transistor, such as transistor 82.

[0102] [Fig.4] shows another circuit including a diffused resistor. More precisely Specifically, [Fig.4] represents a circuit for ensuring that the voltages of the diffused resistors are as described previously.

[0103] The circuit 100 comprises diffused resistors 102 and 104. The resistor 102 corresponds for example to the resistor 12 of Figures 1A to 1C or to the resistor 32 of Figures 2A to 2D. The resistor 104 corresponds for example to the resistor 12' in the case of the embodiment of Figures 1A to 1C or to the resistor 12 in the embodiment of Figures 2A to 2D. The resistor 102 comprises a terminal 106, corresponding to the terminal A1 of the resistor 12 of Figures 1A to 1C or to the terminal C1 of the resistor 32 of Figures 2A to 2D, and a terminal 108, corresponding to the terminal A2 of the resistor 12 of Figures 1A to 1C or to the terminal C2 of the resistor 32 of Figures 2A to 2D.The resistor 104 comprises a terminal 110, corresponding to the terminal B1 of the resistor 12' in the case of the embodiment of Figures 1A to 1C or to the terminal A1 of the resistor 12 in the embodiment of Figures 2A to 2D, and a terminal 112 corresponding to the terminal B2 of the resistor 12' in the case of the embodiment of Figures 1A to 1C or to the terminal A2 of the resistor 12 in the embodiment of Figures 2A to 2D.

[0104] Terminal 106 is connected to terminal 110 by a voltage follower circuit. Similarly, terminal 108 is connected to terminal 112 by a voltage follower circuit.

[0105] In the example of [Fig.4], each follower circuit comprises an operational amplifier. More precisely, terminals 106 and 110 are connected by an operational amplifier 114 and terminals 108 and 112 are connected by an operational amplifier 116. Amplifier 114 comprises an output connected, preferably connected, to the terminal 110. Amplifier 114 comprises an input connected, preferably connected, to terminal 106. Amplifier 114 comprises another input connected, preferably connected, to the output of amplifier 114. Amplifier 116 comprises an output connected, preferably connected, to terminal 112. Amplifier 116 comprises an input connected, preferably connected, to terminal 108. Amplifier 116 comprises another input connected, preferably connected, to the output of amplifier 116.

[0106] [Fig. 5] represents an application of the embodiments described above. More specifically, [Fig. 5] represents a device 120 comprising a plurality of devices 10, four devices 10, referenced 10a, 10b, 10c and 10d, being represented in [Fig. 5].

[0107] Each device 10a, 10b, 10c, 10d is as described in relation to FIGS. 1A to 1C. Each device 10a, 10b, 10c, and 10d comprises a resistor 12 and a resistor 12'. More specifically, the devices 10a, 10b, 10c, and 10d respectively comprise a resistor 12a, 12b, 12c, or 12d and a resistor 12'a, 12'b, 12'c, or 12'd. Each resistor 12a, 12b, 12c, or 12d comprises terminals A1 and A2. Similarly, each resistor 12'a, 12'b, 12'c, or 12'd comprises terminals B1 and B2.

[0108] The devices 10a, 10b, 10c and 10 are connected in series. More specifically, the resistors 12a, 12b, 12c or 12d are connected in series so as to form a resistor of higher value. For example, the terminal A2 of the resistor 12a is connected, preferably connected, to the terminal A1 of the resistor 12b, the terminal A2 of the resistor 12b is connected, preferably connected, to the terminal A1 of the resistor 12c, the terminal A2 of the resistor 12c is connected, preferably connected, to the terminal A1 of the resistor 12d.

[0109] Furthermore, the resistors 12' are connected in series in the same way as the resistors 12. In other words, for each terminal of a resistor 12 connected, preferably connected, to a terminal of another resistor 12, the terminals B1, B2, of the resistors 12, closest to said terminals of the resistors 12 are connected, preferably connected, to each other. Thus, the terminal B2 of the resistor 12'a is connected, preferably connected, to the terminal B1 of the resistor 12'b, the terminal B2 of the resistor 12'b is connected, preferably connected, to the terminal B1 of the resistor 12'c, the terminal B2 of the resistor 12'c is connected, preferably connected, to the terminal B1 of the resistor 12'd.

[0110] The connection of the resistors makes it possible to ensure the constancy of the potential difference between each resistor 12 and the associated resistor 12'. The device 120 thus comprises, between the terminal A1 of the resistor 12a and the terminal A2 of the resistor 12d, a resistance equivalent to the sum of the resistance values ​​of the four resistors 12.

[0111] [Fig.6A] is a top view of another embodiment of a device 130 comprising a diffused resistor. [Fig.6B] is a sectional view, along a line BB, of the embodiment of [Fig.6A]. [Fig.6C] is a sectional view, along a line CC, of ​​an embodiment of [Fig.6A].

[0112] The device 130 comprises elements of the device 10 of FIGS. 1A to 1C which will not be described in detail again. The device 130 comprises: substrate 14, P-type doped; layer 15 comprising openings 19c, 19d; regions 24 in openings 19c and 19d; and contacts 28.

[0113] The device 130 comprises a well 132 in the substrate 14. The well 132 is on the front face of the substrate 14. The well 132 is of the second conductivity type (N). The well 132 forms a resistive bar. The well 132 extends at least from the region 24 in the opening 19c to the region 24 in the opening 19d. The well 132 is in contact with said regions 24. The regions 24 and the well 132 form a diffused resistor 136.

[0114] The device 130 further comprises a resistor 138, similar to the resistor 32 of FIGS. 2A to 2D, produced by P-type diffusion in the well 132 from the front face, of a strip or region 140, so as to obtain a rectangle surrounded (on the sides and below) by the well 132. The layer 15 then comprises an opening 142 located between the openings 19c and 19d. The opening 142 is separated from each of the openings 19c and 19d by a portion of the layer 15. The strip 140 is flush with the upper face of the substrate 14, in the opening 142.

[0115] The strip 140 is flush with the front face of the substrate 14. The strip 140 has, for example, the shape of a rectangular parallelepiped. Thus, in the top view of [Fig. 6A], the strip 140 has, for example, the shape of a rectangle. The strip 140 has a first end 140a and a second end 140b. The first and second ends 140a, 140b preferably correspond to the two opposite sides furthest from each other of the strip 140. Regions 144 at these ends 140a, 140b have the same type P of conductivity and define contact recovery zones intended to be connected to an electronic circuit. The region 144 located at the end 140a constitutes a terminal C1 of the resistor 138. The region 144 located at the end 140b constitutes a terminal C2 of the resistor 138. Preferably, the strip 140 is not silicided outside the regions 144. The regions 144 are for example silicided.

[0116] The value of resistor 138 corresponds to the resistance between terminals Cl and C2.

[0117] The resistors 136 and 138 of FIGS. 6A to 6C are for example configured to be polarized in the same way as the resistors 12' and 12 respectively of the device 10 of figures 1A to IC.

[0118] An advantage of the described embodiments is that the value of the resistance diffused is not dependent on the value of the voltages at each of the terminals of the resistor, and therefore on the supply voltage.

[0119] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0120] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An electronic device (10, 30) comprising first (12', 12, 84, 136) and second (12, 32, 44, 138) diffused resistors in contact with each other so as to form a PN junction, the device being configured so that the potential difference between the first and second resistors is positive and constant at any point of the PN junction, the device being configured so that the PN junction is reverse biased.

2. The device of claim 1, wherein each of the first (12', 12, 84, 136) and second (12, 32, 44, 138) diffused resistors is made of doped semiconductor materials, the first (12', 12, 84, 136) and second (12, 32, 44, 138) diffused resistors being doped with opposite conductivity types.

3. A device according to claim 1 or 2, wherein: - the first resistor (12', 84) comprises a first layer (16) buried in a substrate (14) and first wells (18), the first wells (18) extending from the periphery of the first layer (16) towards a first face of the substrate (14), the first layer (16) and the first wells (18) being made of a doped semiconductor material of a first conductivity type; and - the second resistor (12) comprises a second layer (26) resting on the first layer (16), the second layer (26) being made of a doped semiconductor material of a second conductivity type.

4. Device according to claim 1 or 2, wherein: - the second resistor (32) comprises a third semiconductor layer (36) doped with a first conductivity type, the third layer (36) being flush with an upper face of a substrate (14); and - the first resistor (12) comprises a second layer (26) of a semiconductor material doped with a second conductivity type, the third layer (36) resting on the second layer (26).

5. The device of claim 4, wherein the device further comprises a third resistor (12'), the third resistor (12') comprising a first layer (16) buried in the substrate (14) and first wells (18), the first wells (18) extending from the periphery of the first layer (16) toward the first face of the substrate (14), the first layer (16) and the first wells (18) being made of a doped semiconductor material of a first conductivity type, the first layer (16) and the first boxes (18) delimiting the second layer (26).

6. The device of claim 5, wherein the PN junction between the first (12) and third resistors (12') is configured to be reverse biased.

7. Device according to claim 1 or 2, in which: - the first resistor (136) comprises a semiconductor well (132) in a substrate (14), the well being doped with the type opposite to the doping type of the substrate; and - the second resistor (138) comprises a third semiconductor layer (36) doped with the type opposite to the doping type of the well, the third layer (36) being flush with an upper face of a substrate (14).

8. Device according to any one of claims 1 to 7, in which each of the resistors (12, 12', 32) comprises a first end (Al, B1 Cl) and a second end (A2, B2, C2), each resistor comprising, at the first and second ends, a semiconductor region (20, 24, 38), more heavily doped than the rest of the resistor, constituting a terminal of said resistor.

9. Device according to any one of claims 1 to 8, wherein each first (12', 12, 84, 136) and second (12, 32, 44, 138) resistor comprises first (A1, B1, C1) and second (A2, B2, C2) terminals, the second terminals (A2, B2, C2) of the first (12', 12, 84, 136) and second (12, 32, 44, 138) resistors being connected to the same first node (50) for applying a reference voltage.

10. A device according to any one of claims 1 to 9, wherein the device comprises a control circuit configured to provide the potentials across the terminals of the first (12', 12, 84, 136) and second (12, 32, 44, 138) resistors.

11. Device according to claims 8 and 10, in which the control circuit comprises a first transistor (82) connected in series with the first resistor (84) between a second node (48) for applying a supply voltage and the first node (50) and a second transistor (46) connected in series with the second resistor (44) between the second node and the first node, the first and second transistors being connected as a diode.

12. The device of claim 11, wherein the first transistor (82) has a channel width to length ratio equal to the channel width to length ratio of the second transistor (46) multiplied by the quotient of the value of the second resistor (12, 32, 44, 138) on the value of the first resistor (12', 12, 84).

13. A device according to any one of claims 1 to 12, wherein the device is configured so that the potential difference between the first and second resistors is zero at any point of the PN junction.

14. A method of controlling a device (10, 30) comprising first (12', 12, 84, 136) and second (12, 32, 44, 138) diffused resistors in contact with each other so as to form a PN junction, the potential difference between the first and second resistors being positive and constant at any point of the PN junction, the method comprising a step of reverse biasing the PN junction.

15. Method according to claim 14, applied to a device according to any one of claims 1 to 13.

16. A sensor comprising a device according to any one of claims 1 to 13, the sensor being configured such that a measurement value of the sensor is dependent on the resistance value of the second resistor (12, 32, 44, 138).

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