Method and circuit for emulating a read-only memory

Abstract

Method and circuit for emulating a read-only memory. This description relates to a circuit (112) configured to: - perform an operation between a memory (120) and a cryptographic circuit (116) in response to a write access request for one or more data items to the memory, the access request further including a storage address in the memory, the operation including: writing the data item(s); and for each data item, generating a write access request, in the cryptographic circuit, for the data item and generating a write access request, in the cryptographic circuit, for the storage address; - perform a check, in response to a read access request, from the processor, of a check value, the check including: comparing the check value with a reference value; and - based on the comparison, authorizing read-only access to the memory.Figure for the abridged version: Fig. 1.

Description

Title of the invention: Method and circuit for emulating a memory dead Technical field

[0001] The present description relates generally to a method and a circuit allowing the emulation of a read-only memory. Prior art

[0002] A read-only memory, such as a ROM (Read-Only Memory), has the advantage of storing data immutably. However, a read-only memory can have certain limitations. In particular, there are read-only memories that are not reprogrammable, which can be a constraint in certain applications. There are also reprogrammable read-only memories, which tend to be space and energy intensive.

[0003] One solution is to emulate a read-only memory with a random access memory. However, it is important, for security purposes, to guarantee the integrity of the stored data. It is also important to ensure that, when writing a sequence of data to the memory, the written data is correct. It may also be desirable to ensure that this data has been written to the correct addresses, that it has not been written multiple times and that the order of the sequence is respected.

[0004] There is a need to improve methods and circuits ensuring the integrity of data stored in a memory, such as a random access memory emulating a ROM type memory. Summary of the invention

[0005] One embodiment provides a coupling and chaining circuit configured to: - perform a coupling operation between a volatile memory and a cryptographic circuit, connected to the coupling and chaining circuit, in response to a request for write access to one or more data to the volatile memory, the write access request coming from a processor connected to the coupling and chaining circuit, the access request further comprising a storage address in the volatile memory, the coupling operation comprising: writing the data(s) to volatile memory; and for each of one or more data, the generation of a first access request for writing, in the cryptographic circuit, of the data and the generation of a second access request for writing, in the cryptographic circuit of the storage address; - perform a verification operation between the cryptographic circuit and the volatile memory, in response to an access request for reading, from the processor, of a verification value stored in the cryptographic circuit, the verification operation comprising: comparing the verification value with a reference value, stored in the coupling and chaining circuit; and - based on the comparison, permission to access volatile memory only for reading.

[0006] According to one embodiment, the above coupling and chaining circuit is further configured to, in response to the access request for reading the verification value, coming from the processor, return a default value to the processor.

[0007] According to one embodiment, the above coupling and chaining circuit is further configured to, if during the comparison it is determined that the verification value does not correspond to the reference value, delete the contents of the volatile memory.

[0008] According to one embodiment, the above coupling and chaining circuit comprises a register programmable by the processor allowing the configuration of the coupling and chaining circuit.

[0009] According to one embodiment, the above coupling and chaining circuit further comprises a second register configured to receive, from the processor, the reference value.

[0010] One embodiment provides an electronic device comprising: - the coupling and chaining circuit above; - the cryptographic circuit connected to the coupling and chaining circuit via a first bus; - the volatile memory connected to the coupling and chaining circuit via a second bus; and - the processor connected to the coupling and chaining circuit via a system bus and a third bus.

[0011] According to one embodiment, the cryptographic circuit is configured to generate the verification value by performing one or more cryptographic operations on each of the data values ​​and storage addresses and on the basis of a secret key, the secret key being only accessible in read mode by the cryptographic circuit.

[0012] According to one embodiment, the above electronic device further comprises a second cryptographic circuit connected to the coupling and chaining circuit and comprising the volatile memory.

[0013] One embodiment provides a method comprising: - the execution of a coupling operation, by a coupling and chaining circuit of an electronic device, on the basis of a reception, by the coupling and chaining circuit, of an access request for writing, from a processor of the device, of one or more data in a volatile memory of the device, each data being associated with a storage address in the volatile memory, the coupling operation comprising: the interception, by the coupling and chaining circuit, of the write access request; for each of the one or more data, the generation of a first access request for writing the data and a second access request for writing the associated storage address in a first cryptographic circuit; and for each of the one or more data, its writing in the volatile memory; - the execution of a verification operation, by the coupling and chaining circuit, on the basis of a reception, by the coupling and chaining circuit, of an access request, from the processor, for reading a verification value stored in the first cryptographic circuit, the verification operation comprising: the reading, by the coupling and chaining circuit, of the verification value and the comparison with a reference value stored in the coupling and chaining circuit; and - access authorization, only for reading, to the contents of the volatile memory, based on the comparison.

[0014] According to one embodiment, the coupling and chaining circuit is configured to return a default value, for example a series of zeros, to the processor in response to the access request for reading the verification value.

[0015] According to one embodiment, the first cryptographic circuit is configured to generate the verification value by applying, to each data item and to each storage address received, one or more cryptographic operations, the cryptographic operation(s) furthermore being carried out on the basis of a secret key.

[0016] According to one embodiment, the cryptographic operation(s) are hashing operations and / or operations of a cryptographic algorithm of the AES - GCM (Advanced Encryption Standard - Galois Counter Mode) type or of the AES - CCM (Advanced Encryption Standard - Counter with Encrypted Block Chaining Message authentication code) type comprising the generation of said verification value.

[0017] According to one embodiment, the processor is configured to transmit the reference value to the coupling and chaining circuit before transmitting the write access request.

[0018] According to one embodiment, the above method further comprises deleting of the contents of the volatile memory, controlled by the coupling and chaining circuit, when, during the comparison, it is determined that the verification value does not correspond to the reference value.

[0019] According to one embodiment, the above method further comprises, before the coupling operation, the writing, by the processor and in a register of the coupling and chaining circuit, of the reference value. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.l] is a block diagram of an electronic device according to an embodiment of the present description;

[0022] [Fig.2] is a block diagram illustrating a coupling operation implemented by a coupling and chaining circuit.

[0023] [Fig.3] is a block diagram illustrating a verification operation implemented by the coupling and chaining circuit; and

[0024] [Fig.4] is a flowchart illustrating steps of a method according to an embodiment of the present description. Description of the embodiments

[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0026] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the algorithms for generating message authentication codes (MAC - "Message Authentication Code"), for example involving hash operations and / or cryptographic functions, are known to the person skilled in the art and are not described in detail.

[0027] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0028] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., are referred to, unless otherwise specified, the orientation of the figures.

[0029] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0030] [Fig.l] is a block diagram of an electronic device 100 comprising an integrated circuit 102 according to an embodiment of the present description.

[0031] The electronic device 100 is for example a mobile electronic device, such as a mobile telephone, or an electronic card such as a microcircuit card.

[0032] The circuit 102 comprises for example a processor 104 (CPU) connected to a non-volatile memory 106 (NV MEM) and to a volatile memory 108 (RAM) via a system bus 110. By way of example, the memory 106 is a Flash type memory and the memory 108 is a RAM type memory (from the English "Random Access Memory").

[0033] According to one embodiment, the circuit 102 further comprises a coupling and chaining bridge 112 (CCB) connected to the bus 110 via a bus 114. The bus 114 is, for example, an AHB (Advanced High-performance Bus) type bus. In other examples, the bus 114 is an APB (Advanced Peripheral Bus) or AXI (Advanced External Interface) type bus.

[0034] The circuit 102 further comprises a cryptographic circuit 116 (CRYPTO). The cryptographic circuit 116 is for example configured to generate message authentication codes (MAC). The generation of the message authentication codes comprises for example the application of one or more cryptographic operations such as for example hashing operations and / or cryptographic operations such as CMAC (from "Cipher Message Authentication Code") and / or GMAC (from the English "Galois Message Authentication Message") type functions.In another example, the cryptographic circuit 116 is configured, in addition to or as an alternative to the generation of the message authentication codes, to encrypt received data, for example by applying a symmetric encryption algorithm thereto such as, for example, an AES-GCM (Advanced Encryption Standard - Galois Counter Mode) or an AES-CCM (Advanced Encryption Standard - Counter with Cipher block chaining Message authentication code) type algorithm. For example, the generation of the message authentication code and / or the application of cryptographic operations is based on the use of a secret key. For example, the secret key is specific to the device 100. In other words, the value of the secret key varies from one device 100 to another. For example, the secret key is . derived from a PUF (Physically Unclonable Function) value.

[0035] The circuit 102 further comprises another cryptographic circuit 118 (PKA). For example, the circuit 118 is a public key accelerator configured to perform cryptographic operations according to an asymmetric cryptography algorithm based on a public key.

[0036] The cryptographic circuit 118 comprises, or is connected to, a volatile memory 120 (PKA RAM). For example, the memory 120 is a random access memory. The volatile memory 120 is for example connected to a coprocessor 122 (CO CPU) of the circuit 102. In some examples, the coprocessor 122 is the same circuit as the processor 104. Thus, in one example, the volatile memory 120 is connected to the processor 104.

[0037] For example, the coupling and chaining circuit 112 is further connected to other peripheral circuits 124 (PERIH.). The other peripheral circuits 124 comprise, for example, one or more other cryptographic circuits, a cyclic redundancy control circuit, etc.

[0038] According to one embodiment, the coupling and chaining circuit 112 is configured to perform coupling and chaining operations between the cryptographic circuits 116 and 118, and more particularly, between the cryptographic circuit 116 and the volatile memory 120.

[0039] According to one embodiment, following the coupling and chaining operations carried out between the cryptographic circuit 116 and the volatile memory 120, the volatile memory 120 is configured to emulate a read-only memory, i.e. a memory accessible for reading only, the content of which is guaranteed to be intact.

[0040] [Fig.2] is a block diagram illustrating an example of a coupling operation implemented by the coupling and chaining circuit 112.

[0041] According to one embodiment, the processor 104 is configured to transmit, to the coupling and chaining circuit 112, an access request for writing in the volatile memory 120 a sequence of one or more data. The data are, for example, each associated with a storage address in the volatile memory 120.

[0042] According to one embodiment, the coupling and chaining circuit 112 is configured to perform a coupling operation by intercepting the access requests for writing each data item of the sequence in the volatile memory 120, coming from the processor 104 and transmitted via the bus 114. The coupling operation further comprises the generation, following each request to write a received data item, of two new access requests for writing. The two new access requests are transmitted, by the coupling and chaining circuit 112 and via a bus 200, to the cryptographic circuit 116. For example, the two access requests for writing comprise an access request for writing the data and another access request for writing the storage address in the volatile memory 120. The coupling operation further comprises writing the data sequence in the circuit 118, or more particularly in the memory 120. For example, the data sequence is transmitted to the volatile memory 120 via a bus 202.

[0043] The circuit 116 is for example configured to, following each data item and address received, perform one or more cryptographic operations on the basis of a secret key 204 (SECRET KEY). For example, the value of the secret key depends on the device 100 and varies from one device to another. For example, the secret key 204 is a key derived from a hardware key HUK (Hardware Unique Key). In another example, the secret key is a hardware key, for example derived from a PUF value. The secret key is for example regenerated by a PUF generation circuit (not shown) each time an operation using this key is to be performed by the circuit 116. In another example, the secret key is a value predefined upstream, for example during the manufacture of the device 100.The value of the secret key is for example further encrypted, for example using a hardware key, such as a derived hardware unique key, or DHUK (from the English “Derived Hardware Unique Key”). For example, the value of the DHUK key depends on the context of use of the circuit 102. For each data item and storage address received, the result of the cryptographic operation(s) is, for example, stored in an internal register of the cryptographic circuit 116. For example, the result is updated, on the fly, following each new data item and address received, and this result constitutes for example a verification value.

[0044] By way of example, the verification value is further included in a binary object of the BLOB (Binary Large Object) type. The verification value is for example a concatenation of each of the results of the cryptographic operations performed on the data and the addresses. Thus, the verification value contains an indication of the order in which the data of the sequence were received. In another example, the value of the secret key is chosen, for example by a user of the device 100, at the time of creation of the binary object. By way of example, the binary object is made up of the sequence of data to be written in the memory 120, a private key encrypted using a secret key and the verification value. The verification value is for example calculated from the sequence of data and the secret key.The verification value is therefore unique for each data sequence, secret key and memory configuration 120. The verification value therefore depends on the value of the secret key. The verification value will therefore not be the same for two different secret keys.

[0045] [Fig.3] is a block diagram illustrating a verification operation implemented implemented by the coupling and chaining circuit 112.

[0046] According to one embodiment, the processor 104 is configured to transmit, upstream of the access request for writing in the volatile memory 120, a reference value (REF VALUE) to the coupling and chaining circuit 112. The reference value is for example calculated at the time of generation of the binary object. The reference value is for example calculated in a similar manner to the verification value. For example, following its generation, the reference value is stored in a register of the circuit 116. Thus, the verification value and the reference value are equal when the data sequence is neither corrupted nor modified, and when the writing of each data item is carried out at the correct address. For example, the reference value is then stored in an internal register 300 of the coupling and chaining circuit 112. The use of the secret key in the calculation of the reference value makes it specific to the device 100.Therefore, each reference value calculated by a device similar to device 100 cannot be used by another device.

[0047] The value of the secret being unknown by the processor 104, the reference value is calculated under controlled and secure conditions. These conditions are for example fulfilled when the data values ​​written in the memory 120 by the processor 104 are known to be authentic.

[0048] According to one embodiment, the coupling and chaining circuit 112 is configured to carry out a verification operation between the circuits 116 and 118, and more particularly between the cryptographic circuit 118 and the volatile memory 120. The verification operation is, for example, carried out following the reception of an access request for reading, from the processor 104, of the verification value stored in the cryptographic circuit 116.

[0049] For example, in response to the access request for reading the verification value, the coupling and chaining circuit 112 is configured to transmit a default value, for example a zero value, such as a series of zeros, to the processor 104.

[0050] When carrying out the verification operation, the coupling and chaining circuit 112 is for example configured to access the verification value stored in the cryptographic circuit 116 and to compare it with the reference value stored in the register 300.

[0051] According to one embodiment, when the reference value is different from the verification value, the coupling and chaining circuit 112 is configured to control the deletion of the content of the volatile memory 120.

[0052] According to one embodiment, when the verification value corresponds to the reference value, the coupling and chaining circuit 112 is configured to authorize read-only access to the volatile memory 120. Consequently, the coupling and chaining circuit 112 is further configured to prohibit any write access request, for example from the processor 104, in the volatile memory 120. For example, the coupling and chaining circuit 112 is configured to transmit an activation signal EN AB LE to the coprocessor 122 allowing it read access to the volatile memory 120. For example, the processor 104 and the coprocessor 122 do not have access to the memory 120 until the verification and reference values ​​have been compared, or do not match. The chaining and coupling circuit 112 is for example configured to authorize read-only access to the coprocessor 122 and to the memory 120 only when the comparison between the verification and reference values ​​has been carried out and the two values ​​match.In another example, the coupling and chaining circuit 112 is configured to allow read access to the coprocessor 122 and the processor 104 to the memory 120 only when the comparison between the check and reference values ​​has been performed and the two values ​​match. In another example, the circuit 122 is configured to prevent read access to the memory 120 by the processor 104 and / or the coprocessor 122 when write operations in the memory 120 are not completed.

[0053] By way of example, the cryptographic circuit 118 has access, when it has been determined that the reference value corresponds to the verification value, to the data stored in the memory 120. The cryptographic circuit 118 has for example the possibility of carrying out one or more cryptographic operations, for example asymmetric cryptography operations, on one or more data of the volatile memory 120. In another example, the circuit 122 is configured to prevent, by the processor 104 and / or the coprocessor 122, read access to the memory 120 when the write operations in the memory 120 are not completed.

[0054] [Fig.4] is a flowchart illustrating steps of a method according to an embodiment of the present description.

[0055] In a step 400 (COUPLING MODE), the processor 104 is for example configured to access a control register (not shown) of the coupling and chaining circuit 112 in order to program the circuit 112 by storing in this register a configuration corresponding to a read-only memory emulation mode. For example, this configuration defines the actions to be performed by the circuit 112 in response to a write and read operation by the processor. In other embodiments, the circuit 112 is configured to always perform the same operations, and does not need to be programmed. In this example, the coupling and chaining circuit remains activated, however. For example, the coupling and chaining circuit is activated, respectively deactivated when a specific value, for example the value CCB_ON, respectively CCB_OFF, is stored in the control register. In another example, in the configuration not corresponding to the ROM emulation mode, the coupling and chaining circuit 112 behaves as a router and is configured to transfer the operations requested by the processor 104 to the requested peripherals, without changing the nature of the requested operations. In particular, in the configuration not corresponding to the ROM emulation mode, the coupling and chaining circuit 112 is configured to create new transactions, for example by means of chaining and coupling operations, on the basis of an access request, coming from the processor 104 and towards one of the peripheral circuits.

[0056] In a step 401 (CPU PROVIDES REF VALUE), the processor 104 transmits, for example via the buses 110 and 114, a reference value, for example calculated upstream by the cryptographic circuit 116. The reference value is for example calculated on the basis of a sequence of data, for example stored in the volatile memory 108. The calculation of the reference value is for example further carried out on the basis of one or more storage addresses in the volatile memory 120.

[0057] In a step 402 (WRITING ACCESS REQUESTS AND COUPLING OPERATIONS), the processor 104 transmits a write access request for a sequence of one or more data, each data being associated with a storage address in the volatile memory 120. In response to the write access request, the coupling and chaining circuit 112 is configured to perform a coupling operation, as described in relation to [Fig. 2] between the cryptographic circuit 116 and the volatile memory 120. When performing step 402, the processor 104 performs, for example, several writes in the volatile memory 120

[0058] Following each writing of a data item, in association with its storage address in the memory 120, in the cryptographic circuit 116, a verification value is for example generated, or updated. The generation, or the updating, of the verification value is for example calculated by the cryptographic circuit 116, by applying one or more cryptographic operations on the data item and the storage address. For example, the cryptographic operation(s) is the calculation of a message authentication code of the data item and the storage address. For example, following each data item and each storage address, the generated message authentication code is concatenated to the verification value, the verification value being for example initially an empty string.

[0059] The processor 104 is further configured to, when the writing of the data sequence in the volatile memory 120 is complete, transmit, in a step 406 (MATCHES?), an access request for reading the verification value to the coupling and chaining circuit 112.

[0060] In response to the read request made, the coupling and chaining circuit 112 is configured to perform a verification operation comprising reading the verification value in the circuit 116 and comparing it with the reference value stored in the register 300, as described in relation to [Fig. 3]. In particular, the coupling and chaining circuit 112 determines whether the verification value is equal to the reference value, for example stored in the register 300.

[0061] In the case where the two values ​​do not correspond, (branch N at the output of block 406), this means that the data sequence has not been correctly written in the volatile memory 120. For example, the value of one or more written data is incorrect and / or has been written to incorrect addresses and / or has been written several times and / or the data sequence has not been written in the correct order. In this case, the method ends in a step 407 (DELETION) in which the coupling and chaining circuit 112 commands the deletion of the contents of the volatile memory 120. In other words, when the data sequence transmitted for writing during step 401 is not exactly identical to the data sequence used for calculating the reference value, the contents of the memory 120 are deleted.

[0062] In the case where, during step 406, it is determined that the verification value corresponds to the reference value (Y branch at the output of block 406), this means that the data sequence has been correctly written in the volatile memory 120. Indeed, the verification value corresponds to the reference value when the data written in the circuit 116 corresponds to the data of the sequence transmitted by the processor 104, that each data item is accompanied by the correct storage address in the memory 120 and that the data are written, in the circuit 116, in the order in which the processor commands the writing of the sequence in the volatile memory 120.

[0063] In this case, the method ends in a step 408 (ROM EMULATION), in which the volatile memory 120 becomes accessible, for example by the coprocessor 122, only for reading. The coupling and chaining circuit 112, or the circuit 122 following the reception of an access request from the coupling and chaining circuit 112, is for example configured to prohibit access for writing in the volatile memory 120.

[0064] An advantage of the embodiments described is that they allow the emulation of a memory accessible only for reading while improving the performance of the circuit in terms of energy consumption. Indeed, a single write and / or read operation by the processor 104 on the bus 110 makes it possible to carry out all of the operations associated with this emulation. Similarly, the embodiments The described implementations allow the emulation of a ROM while improving the costs in implementation and certification of the circuit.

[0065] Another advantage of the described embodiments is that they guarantee the integrity of the contents of a ROM type memory.

[0066] Another advantage of the described embodiments is that they protect the device against hardware attacks, for example targeting the processor 104.

[0067] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0068] Finally, the practical implementation of the described embodiments and variants is within the reach of those skilled in the art from the functional indications given above. In particular, with regard to the method of calculating the verification and reference values, other cryptographic algorithms may be used. Likewise, the type of cryptographic algorithm implemented by the cryptographic circuit 116 may vary.

Claims

Claims

1. Coupling and chaining circuit (112) configured to: - perform a coupling operation between a volatile memory (120) and a cryptographic circuit (116), connected to the coupling and chaining circuit, in response to a request for write access of one or more data to the volatile memory, the write access request coming from a processor (104) connected to the coupling and chaining circuit, the access request further comprising a storage address in the volatile memory, the coupling operation comprising: writing the data or data in the volatile memory; and for each of the one or more data, generating a first access request for writing, in the cryptographic circuit, the data and generating a second access request for writing, in the cryptographic circuit, the storage address;- performing a verification operation between the cryptographic circuit and the volatile memory, in response to an access request for reading, from the processor, of a verification value stored in the cryptographic circuit, the verification operation comprising: comparing the verification value with a reference value, stored in the coupling and chaining circuit; and - based on the comparison, authorizing access to the volatile memory for reading only.;

2. The coupling and chaining circuit (112) of claim 1, further configured to, in response to the access request for reading the verification value, from the processor (104), return a default value to the processor.

3. The coupling and chaining circuit (112) of claim 1 or 2, further configured to, if upon comparison it is determined that the verification value does not match the reference value, delete the contents of the volatile memory (120).

4. Coupling and chaining circuit according to any one of claims 1 to 3, comprising a register programmable by the processor allowing the configuration of the coupling and chaining circuit (112).

5. A coupling and chaining circuit (112) according to any one of claims 1 to 4, further comprising a second register (300) configured to receive, from the processor (104), the reference value.

6. Electronic device (100) comprising: - the coupling and chaining circuit (112) according to any one of claims 1 to 5; - the cryptographic circuit (116) connected to the coupling and chaining circuit via a first bus (200); - the volatile memory (120) connected to the coupling and chaining circuit via a second bus (202); and - the processor (104) connected to the coupling and chaining circuit via a system bus (110) and a third bus (114).

7. The electronic device (100) of claim 6, wherein the cryptographic circuit (116) is configured to generate the verification value by performing one or more cryptographic operations on each of the data and storage address values and based on a secret key, the secret key being only readable by the cryptographic circuit.

8. An electronic device (100) according to claim 6 or 7, further comprising a second cryptographic circuit (118) connected to the coupling and chaining circuit (112) and comprising the volatile memory (120).

9. A method comprising: - performing a coupling operation, by a coupling and chaining circuit (112) of an electronic device (100), based on a reception, by the coupling and chaining circuit, of an access request for writing, from a processor (104) of the device, of one or more data in a volatile memory (120) of the device, each data being associated with a storage address in the volatile memory, the coupling operation comprising: intercepting, by the coupling and chaining circuit, the access request for writing; for each of the one or more data, generating a first access request for writing the data and a second access request for writing the associated storage address in a first cryptographic circuit (116); and for each of the one or more data, writing it in the volatile memory;- the execution of a verification operation, by the coupling and chaining circuit, on the basis of a reception, by the coupling and chaining circuit, of an access request, coming from the processor, for; reading a verification value stored in the first cryptographic circuit, the verification operation comprising: reading, by the coupling and chaining circuit, the verification value and comparing it with a reference value stored in the coupling and chaining circuit; and - authorizing access, only for reading, to the contents of the volatile memory, on the basis of the comparison.

10. The electronic method (100) of claim 9, wherein the coupling and chaining circuit (112) is configured to return a default value, for example a sequence of zeros, to the processor (104) in response to the access request for reading the verification value.

11. The method of claim 9 or 10, wherein the first cryptographic circuit (116) is configured to generate the verification value by applying, to each data item and to each storage address received, one or more cryptographic operations, the cryptographic operation(s) further being performed on the basis of a secret key.

12. Method according to claim 11, wherein the cryptographic operation(s) are hash operations and / or operations of a cryptographic algorithm of the AES - GCM (Advanced Encryption Standard - Galois Counter Mode) type or of the AES - CCM (Advanced Encryption Standard - Counter with Encrypted Blockchain Message Authentication Code) type comprising the generation of said verification value.

13. The method of any one of claims 9 to 12, wherein the processor (104) is configured to transmit the reference value to the coupling and chaining circuit (112) before transmitting the write access request.

14. A method according to any one of claims 9 to 13, further comprising deleting the contents of the volatile memory (120), controlled by the coupling and chaining circuit (112), when, upon comparison, it is determined that the verification value does not correspond to the reference value.

15. Method according to any one of claims 9 to 14, further comprising, before the coupling operation, writing, by the processor (104) and in a register (300) of the coupling and chaining circuit (112), the reference value.

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