Tantalum oxide transistor gate

Abstract

The invention relates to a field effect transistor comprising a drain, a source and a gate deposited on an upper layer made of a first semiconductor material of a stack of layers deposited on a substrate and forming a base structure; the gate comprising: an electrical contact structure made of a first electrically conductive material; a barrier layer made of an alloy of tantalum and tantalum oxide; the barrier layer separating said upper layer from the contact structure to block the diffusion of the first electrically conductive material into the base structure; the barrier layer having a tantalum oxide concentration gradient, the tantalum oxide being in the majority compared to the tantalum in a first part of the barrier layer located at a first interface between the barrier layer and the upper layer. Figure for the abstract: Fig. 2a

Description

Title of the invention: Tantalum oxide-based transistor gate

[0001] The invention relates to the field of transistor manufacturing, more particularly the manufacturing of transistor gates subjected to high thermal stresses.

[0002] The manufacture of transistors includes a crucial step: the manufacture of the control gate. Indeed, the gate is subjected to high thermal stresses, both during manufacture and during use. The transistor gates produced tend not to sufficiently prevent the diffusion of the conductive metal of said gate into the body of the transistor, which is generally made of a semiconductor material. The term "transistor body" refers to the structure of at least one semiconductor layer in which the conduction channel between the source and the drain is formed when the transistor is in an on state. This diffusion leads to a reduction in the performance of the transistor, with an increase in leakage currents.In addition, the diffusion of the metal constituting the gate contact into the transistor body induces a degradation of the rectifier contact between the gate and the upper semiconductor layer of the transistor body. In other words, the technical robustness and reliability of transistors depend on the electrical, thermal and mechanical properties of the control gate.

[0003] The identified technical problem is encountered in the various transistor structures covering, by way of non-limiting illustrative example, CMOS (acronym for the expression in English Complementary metal-oxide-semiconductor), SOI (acronym for the expression in English Silicon-on-Insulator), HEMT (acronym for the expression in English High Electron Mobility Transistor) and FinFET (acronym for the expression in English fin field-effect transistor) technologies.

[0004] More specifically, high electron mobility transistors (HEMTs) are intended for microwave power applications. Thus, during their use, HEMT transistors are subjected to significant thermal stresses. The high temperatures to which the transistors are exposed cause failures due to the diffusion of the conductive material from the gate to the surface of the semiconductor constituting the body of the transistor. Diffusion leads to an increase in leakage currents which degrade the performance of the transistor and reduce its lifetime.

[0005] In addition, the diffusion phenomenon may present limitations with respect to the execution of other steps in the transistor manufacturing process requiring the application of a high thermal budget. For example, the production of a diamond encapsulation layer at high temperature causes the diffusion phenomenon. previously described. This limits the choice of encapsulation layer materials and prevents the deposition of encapsulation layers with improved protection such as diamond.

[0006] In this sense, it is therefore important to develop a gate architecture and a method of manufacturing said gate making it possible to eliminate the phenomenon of metallic diffusion of the control gate in the body of the transistor subjected to high thermal and / or electrical stresses.

[0007] We will begin by introducing the solutions known to those skilled in the art presenting materials used to produce a control grid for a transistor subjected to high thermal or electrical stresses.

[0008] Different metal stacks constituting a control gate of a transistor, such as Ni / Au, Mo / Au, Pt / Au and Ni / Pt / Au, have been studied, but this has not led to a significant improvement in the robustness of the gates.

[0009] US patent US7411226B2 relates to an InP high electron mobility transistor structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum Mo or platinum Pt. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer.

[0010] To overcome the limitations of existing solutions, the invention proposes a control gate structure of a transistor comprising a barrier layer made of an alloy of tantalum and tantalum oxide. The barrier layer CB separates the electrical contact structure of the gate from the body of the transistor to block the diffusion of the metal into the body of the transistor. Mainly, the gate structure according to the invention makes it possible to eliminate the phenomenon of metallic diffusion and thus improve the reliability and robustness of the transistor.

[0011] Furthermore, the invention allows the improvement of the electrical characteristics of the transistor. Indeed, the stack of layers constituting the gate according to the invention makes it possible to obtain a rectifier contact with a high barrier height with or without thermal annealing.

[0012] Furthermore, the structure of the control grid according to the invention is compatible with operation of the applications in aggressive environments. Indeed, the grid has improved resistance to corrosion and chemical attack.

[0013] The invention further proposes an “in-situ” method for manufacturing the control grid according to the invention. Indeed, the stacking of layers forming the grid according to the invention can be carried out in the same environment without the need to unload the sample from the deposition equipment. This makes it possible to simplify the grid manufacturing process and thus save production time and yield.

[0014] We will describe the invention in the context of a high electron mobility transistor for illustrative purposes, without limitation and without loss of generality. The gate according to the invention and its manufacturing method remain compatible with any type of field effect transistor, regardless of the nature of the stack of layers constituting the body of the transistor.

[0015] The subject of the invention is a field effect transistor comprising a drain, a source and a gate deposited on an upper layer of a first semiconductor material of a stack of layers deposited on a substrate and forming a base structure; the gate comprising: - an electrical contact structure made of a first electrically conductive material; - a barrier layer made of an alloy of tantalum and tantalum oxide; the barrier layer separating said upper layer from the contact structure to block the diffusion of the first electrically conductive material into the base structure; the barrier layer having a tantalum oxide concentration gradient, the tantalum oxide being in the majority compared to the tantalum in a first part of the barrier layer located at a first interface between the barrier layer and the upper layer.

[0016] According to a particular aspect of the invention, the barrier layer comprises a second part made of tantalum located at a second interface opposite the first interface.

[0017] According to a particular aspect of the invention, the first electrically conductive material is gold or aluminum or copper.

[0018] According to a particular aspect of the invention, the grid further comprises an intermediate layer confined between the contact structure and the barrier layer; said intermediate layer being made of a platinoid or of nickel or of molybdenum.

[0019] According to a particular aspect of the invention, the first semiconductor material has an output work function lower than that of tantalum for producing a rectifier contact.

[0020] According to a particular aspect of the invention, the barrier layer has a thickness of between 5nm and 30nm.

[0021] According to a particular aspect of the invention, the first part of the barrier layer has a thickness of between 5 nm and 10 nm.

[0022] According to a particular aspect of the invention, the field effect transistor further comprises an encapsulation layer of diamond or boron nitride; the gate being covered by said encapsulation layer.

[0023] According to a particular aspect of the invention, the contact structure comprises a pillar and an upper contact layer resting on said pillar and having a width greater than that of the pillar.

[0024] The invention also relates to a method of manufacturing a gate of a field effect transistor comprising the following steps: - providing a stack of layers forming a basic structure comprising an upper layer made of a first semiconductor material; - depositing a resin with a chemical composition comprising free oxygen functions on the upper layer and fabricating a pattern corresponding to a predetermined shape of the grid in the resin by lithography; - depositing a barrier layer made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern in the enclosure of deposition equipment having a temperature greater than 1900°C; the deposition being carried out from a tantalum source placed at a separation distance from the basic structure chosen so as to obtain a barrier layer having a tantalum oxide concentration gradient; - depositing a layer of a first electrically conductive material to fill the pattern in order to obtain a contact structure; the deposition being carried out in the enclosure of said deposition equipment without discharging the base structure; the deposition being carried out from a source of the first electrically conductive material; - destroy the resin.

[0025] Other characteristics and advantages of the present invention will appear more clearly on reading the description which follows in relation to the following appended drawings.

[0026] [Fig-1] [Fig.l] represents a sectional view of a transistor having a gate according to a first embodiment of the invention.

[0027] [Fig.2a] [Fig.2a] represents a sectional view of a transistor having a gate according to a second embodiment of the invention.

[0028] [Fig.2b] [Fig.2b] represents a sectional view of the grid according to the second embodiment of the invention.

[0029] [Fig.3] the figure represents a sectional view of a transistor having a gate according to a third embodiment of the invention.

[0030] [Fig.4] the figure represents a sectional view of a transistor having a gate according to a fourth embodiment of the invention.

[0031] [Fig.5] [Fig.5] illustrates a flowchart of the method of manufacturing the grid according to any one of the embodiments of the invention.

[0032] [Fig.6a] [Fig.6a] illustrates the first step of the method of manufacturing the grid according to the invention.

[0033] [Fig.6b] [Fig.6b] illustrates the second step of the grid manufacturing process according to the invention.

[0034] [Fig.6c] [Fig.6c] illustrates the third step of the method of manufacturing the grid according to the invention.

[0035] [Fig.6d] [Fig.6d] illustrates the third optional step of the method of manufacturing the grid according to the invention.

[0036] [Fig.6e] [Fig.6e] illustrates the fourth step of the method of manufacturing the grid according to the invention.

[0037] [Fig.6f] [Fig.6f] illustrates the fifth step of the method of manufacturing the grid according to the invention.

[0038] [Fig.6g] [Fig.6g] illustrates the seventh step of the method of manufacturing the grid according to the invention.

[0039] [Fig.7] [Fig.7] illustrates an example of execution of the third step of the method of manufacturing the grid according to the invention.

[0040] [Fig.l] represents a sectional view of a transistor Tl having a gate G1 according to a first embodiment of the invention. By way of illustration and without loss of generality, the transistor Tl is a high electron mobility transistor. The transistor Tl comprises a drain Dl, a source SI, a gate G1 and a base structure B1 corresponding to the body of the transistor TL. The base structure B1 is formed by a stack of thin layers deposited on a substrate SUB forming a hetero-structure. Alternatively, the base structure B1 may be a massive layer made of a semiconductor material. Generally, the base structure comprises an upper semiconductor layer Cl starting from the substrate SUB. The drain Dl, the source SI and the gate G1 are arranged on said upper semiconductor layer CL. The base structure B1 is intended to contain the conduction channel between the source SI and the drain DL.

[0041] In the illustrated example of a high electron mobility transistor T1 (HEMT), the basic structure B1 comprises the following stack of layers starting from the substrate SUB: - a C3 buffer layer to adjust the crystal structure during epitaxial growth. For example, the C3 buffer layer is made of gallium nitride alloy with GaN / AlGaN aluminum. - The C2 channel layer corresponding to the transistor channel. It is made of a high electron mobility semiconductor material, such as gallium nitride GaN. - The confinement layer Cl to generate the charge carriers in the channel layer. The confinement layer Cl is made of a semiconductor material having an energy gap greater than that of the semiconductor material of the channel layer C2. For example, the confinement layer Cl is made of quaternary III-V semiconductor alloy.

[0042] Advantageously, the basic structure B1 comprises isolation trenches TR produced by etching or ion implantation to laterally delimit the transistor T1 and thus reduce leakage currents.

[0043] In the illustrated example, the upper layer of the basic structure B1 is the confinement layer Cl. Said upper layer Cl has a contact interface with the gate Gl, the drain DI and the source SI.

[0044] The drain DI and the source SI are each made by a layer of an electrically conductive material making an ohmic contact with the upper layer CL. For example, the drain DI and the source SI are made by copper or aluminum or gold preferably, because gold has better resistance to chemical attack. Alternatively, it is possible to make the drain DI and the source SI by epitaxial growth of GaN.

[0045] The grid Gl according to the first embodiment of the invention comprises an electrical contact structure SC formed by a layer of a first electrically conductive material, an intermediate layer CI and a barrier layer CB. A grid is thus obtained in the form of a pillar formed by the stacking of the planar layers CB, CI, SC. ​​The pillar is produced in this order starting from the upper layer Cl of the base structure B1: the barrier layer CB then the intermediate layer CI then the electrical contact structure SC. The barrier layer CB separates the upper semiconducting layer Cl from the electrical contact structure SC.

[0046] The electrical contact structure SC is intended to receive a control signal applied to the control gate Gl of the transistor Tl to configure it according to an on state or a off state. For example, the first electrically conductive material is gold or aluminum or copper. Preferably, the first electrically conductive material is gold which has electrical characteristics compatible with microwave operation and good resistance to chemical corrosion.

[0047] The barrier layer is made of an alloy of tantalum and tantalum oxide. The barrier layer CB has a tantalum oxide concentration gradient. The barrier layer based on tantalum and tantalum oxide makes it possible to prevent the diffusion of atoms of the first electrically conductive material in all of the semiconductor layers C1, C2, C3 forming the basic structure B1, and corresponding to the body of the transistor TL. The elimination of the diffusion phenomenon makes it possible to improve the reliability and technological robustness of the transistor.

[0048] The barrier layer CB has a thickness of between 5nm and 30nm, preferably between 10nm and 20nm. A thickness of the barrier layer CB of less than 20nm makes it possible to minimize the leakage currents of the transistor TL.

[0049] Tantalum oxide is predominant compared to tantalum in a first PI part of the barrier layer CB. The first PI part is located at the interface between the barrier layer CB and the upper layer Cl of the basic structure Bl. The concentration of tantalum oxide is thus maximum at a first interface between the barrier layer CB and the upper layer Cl and decreases progressively as it moves away from said interface. The first PI part of the barrier layer CB is comparable to a tantalum oxide layer having a thickness of between 5 nm and 10 nm. The first PI part plays the electrical role of an oxide layer in the gate of a field effect transistor at said interface.

[0050] Conversely, tantalum is in the majority compared to tantalum oxide in a second part P2 of the barrier layer CB. The second part P2 is located at the interface opposite the first interface between the barrier layer CB and the upper layer Cl of the base structure BL. The tantalum concentration is thus maximum at the interface between the barrier layer CB and the intermediate layer CI and gradually decreases moving away from said interface. The second part P2 in tantalum makes it possible to improve the mechanical robustness of the gate by supporting at least the electrical contact structure SC.

[0051] According to a particular aspect of the invention, the total thickness of the barrier layer CB is less than 5 nm. In this case, the entire barrier layer CB is mainly made of tantalum oxide.

[0052] In the context of the invention, the intermediate layer CI is optional. The intermediate layer CI is made of a platinoid or of nickel or molybdenum. A platinoid is a material chosen from platinum, rhodium, palladium, ruthenium, iridium and osmium. The intermediate layer CI is confined between the barrier layer CB and the electrical contact structure SC. This makes it possible to improve the adhesion of the electrical contact structure SC, more particularly in the case of gold, and thus improve the mechanical robustness of the gate GL. In addition, the introduction of the intermediate layer CI makes it possible to add an additional barrier to the diffusion of the atoms of the first electrically conductive material in all of the semiconductor layers C1, C2, C3 forming the basic structure BL.

[0053] The structure of the gate Gl comprising a barrier layer made of a tantalum alloy and tantalum oxide as described above makes it possible to produce a rectifier contact. This makes it possible to obtain a considerable reduction in the leakage currents of the transistor Tl over time. A rectifier electronic contact is designed to allow the flow of electric current in only one direction from the gate Gl to the upper layer Cl, while blocking the flow of current in the opposite direction. Consequently, a rectifier electronic contact offers a high resistance in the opposite direction of current flow, and low resistance in the forward direction.

[0054] In addition, tantalum and tantalum oxide are refractory materials that can withstand high temperatures (generally above 1000°C) without deforming, melting or degrading. Thus, the barrier layer CB makes it possible to provide the gate G1 with high thermal robustness, and thus protect the body of the transistor T1.

[0055] [Fig.2a] represents a sectional view of a transistor T1 having a gate G1 according to a second embodiment of the invention. [Fig.2b] represents an enlarged sectional view of the gate G1 according to the second embodiment of the invention.

[0056] The technical characteristics and advantages described for the first embodiment remain valid for the second embodiment. The second embodiment of the invention differs from the first embodiment by the shape of the grid G1. The grid G1 comprises an electrical contact structure SC consisting of a pillar PG and an upper contact layer CH. The upper contact layer CH rests on the pillar PG. The pillar PG has a first width L1 in a parallel direction X orthogonal to the direction of the stack Z. The upper contact layer CH has a second width L2 in a parallel direction X orthogonal to the direction of the stack Z. The second width L2 of the upper contact layer CH is greater than the first width L1 of the pillar PG.Reducing the first width L1 allows to reduce the parasitic capacitance of the gate Gl and increasing the maximum operating frequency of the transistor TL. Widening the second width L2 allows to reduce the resistance of the gate GL.

[0057] The thickness el of the PG pillar is between 20nm and 500nm. A thickness el less than 20nm can cause an increase in the parasitic capacitances of the GL gate. A thickness el greater than 500nm can mechanically weaken the GL gate.

[0058] The stack formed by the barrier layer CB and the intermediate layer CI is arranged between, on the one hand, the pillar PG of the electrical contact structure SC and, on the other hand, the upper layer CL. Advantageously, the barrier layer CB is deposited on the external walls of the pillar PG, with direct or indirect contact through the intermediate layer CL. Advantageously, the barrier layer CB is deposited, in addition, on the lower external wall of the upper contact layer CH, with direct or indirect contact through the intermediate layer CL.

[0059] Advantageously, the second width L2 is greater than or equal to six times the first width LL. This makes it possible to optimize the resistance of the grid Gl and the reduction of parasitic capacitances on the one hand, and the mechanical robustness of the structure of the grid Gl on the other hand.

[0060] [Fig.3] represents a sectional view of a transistor Tl having a gate Gl according to a third embodiment of the invention. The technical characteristics and advantages described for the first and second embodiments remain valid for the third embodiment. The third embodiment of the invention differs from the second embodiment by a progressive variation in the width of the electrical contact structure SC so as to obtain a “tulip” type structure. The electrical contact structure SC gradually widens as it moves away from the basic structure Bl. This makes it possible to reduce the resistance of the gate G1 while reducing the parasitic capacitance of the gate Gl.A progressive increase in the width of the electrical contact structure SC makes it possible to obtain a more mechanically robust gate without degrading the electrical performance of the transistor TL. The barrier layer CB is deposited on the external walls of the electrical contact structure SC, with direct or indirect contact through the intermediate layer CI so as to confine the first electrically conductive material.

[0061] [Fig.4] represents a sectional view of a transistor T1 having a gate Gl according to a fourth embodiment of the invention. The characteristics and technical advantages described for the first and second embodiments remain valid for the fourth embodiment. This is a variant of the shape of the gate Gl in the form of Gamma.

[0062] According to a particular aspect of the invention, the transistor T1 comprises a diamond or boron nitride encapsulation layer which encapsulates at least the gate GL. This variant is compatible with all the embodiments previously described. The deposition of a diamond or boron nitride layer requires the application of a high thermal stress on the transistor TL. The structure of the gate GL according to the invention makes it possible to carry out this step of deposition of a diamond or boron nitride encapsulation layer without degradation of the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide.

[0063] [Fig. 5] illustrates a flowchart of the method PI for manufacturing the grid Gl according to any one of the embodiments of the invention. Figures 6a to 6g illustrate the steps of the method PI according to the invention.

[0064] The first step i) consists of providing a stack of layers forming a basic structure B1 comprising the upper layer C1 made of a first semiconductor material. The basic structure B1 is produced on a substrate SUB. The basic structure B1 is intended to form the body of the transistor T1 during manufacture. [Fig.6a] illustrates by way of non-limiting example and without loss of generality the basic structure B1 described previously for the production of a high electron speed transistor HEMT. The first step i) can be carried out by the growth of thin layers by epitaxy.

[0065] The second step ii) consists of depositing an electro-sensitive resin RES over the entire upper surface of the base structure B1 and to manufacture a pattern 11 corresponding to a predetermined shape of the grid G1 in said resin. As a non-limiting illustrative example, the manufacture of the pattern 11 is carried out by electron beam lithography: The RES resin is exposed to an electron beam. The beam defines the pattern 11 according to a predetermined program. In the example illustrated in [Fig.6b], the pattern 11 corresponds to an empty volume manufactured in a portion of the resin. The parts of the RES resin exposed to the electron beam are weakened and then removed by a suitable solvent. The RES resin must have a chemical composition comprising free oxygen functions. As an example, the RES resin is made of Poly-methyl-methacrylate (PMMA). The PI process is illustrated with a grid shape G1 according to the second embodiment for illustrative and non-limiting purposes.The PI method is compatible with the other embodiments of the grid G1 according to the invention by adapting the shape of the pattern 11.

[0066] The third step iii) consists of depositing a barrier layer CB made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern 11 as illustrated in [Fig.6c]. The deposition can be carried out by evaporation or by sputtering. [Fig.7] illustrates the performance of this step in evaporation deposition equipment as an example. Indeed, the sample is loaded into the enclosure E0 (also called frame or chamber) of a deposition equipment. The enclosure E0 comprises a source of tantalum SoMl heated to a temperature To greater than 1900°C. The pressure Po in the enclosure is less than 5.105 Pa. The tantalum source SoMl is bombarded by an electron beam, which causes tantalum atoms to be torn off from the tantalum source SoMl and to move towards the upper surface of the sample (target formed by the basic structure B1 on which the pattern 11 was fabricated).The tantalum source SoMl placed at a separation distance dl from the basic structure B1 chosen so as to obtain an oxidation reaction between the deposited tantalum atoms and the free oxygen atoms provided by the resin RES. As a non-limiting example, the separation distance dl is between 30 cm and 70 cm and preferably between 45 cm and 55 cm. The intensity of the oxidation reactions decreases progressively with the growth of the deposited layer. We thus obtain the barrier layer CB made of an alloy of tantalum and tantalum oxide with a tantalum oxide concentration gradient decreasing with the increase in the thickness of the barrier layer CB, and conversely a tantalum concentration gradient increasing with the increase in the thickness of the barrier layer CB.The barrier layer CB is deposited on internal walls of the pattern 11 formed by the resin RES and on the visible upper surface of the upper layer Cl of the basic structure Bl.

[0067] Optionally, the following step iii') consists of depositing an intermediate layer CI on the barrier layer CB previously deposited inside the pattern 11 as illustrated in [Fig.6d]. The intermediate layer CI is made from a source of a platinoid or nickel or molybdenum in the same deposition equipment without unloading the sample from the EO enclosure and keeping the same pressure Po. In this case, we speak of an “in-situ” deposition because it does not require the unloading of the basic structure B1 of the frame. This makes it possible to reduce the number of steps in the manufacturing process of the grid G1 compared to a manufacturing process according to the state of the art.

[0068] Step iv) consists of depositing a layer of a first electrically conductive material to fill the pattern 11 in order to obtain a contact structure SC as illustrated in [Fig.6e]. The deposition is carried out in the enclosure EO of the same deposition equipment without discharging the base structure B1 and while maintaining the same pressure Po. In this case, we speak of an “in-situ” deposition because it does not require the discharge of the base structure B1 from the frame. The deposition is carried out from a source of gold metal, for example bombarded by an electron beam.

[0069] Step v) consists of destroying the remaining RES resin structure to keep only the grid G1 from the pattern 11. The destruction of the RES resin can be carried out chemically using specific solvents.

[0070] Optionally, the method PI further comprises a step vi) of thermal annealing of the transistor T1 at a temperature between 400°C and 600°C for a duration between 1 and 2 minutes in a nitrogen atmosphere or under vacuum. The annealing step makes it possible to obtain a strong reduction in the leakage current density to values ​​lower than 200nA / mm. This reduction in leakage currents is also accompanied by an increase in the output current density, for example from 0.77 A / mm (before annealing) to 1.4 A / mm (after annealing). The structure of the gate G1 according to the invention makes it possible to carry out this thermal annealing step without degradation of the robustness of the transistor by diffusion thanks to the barrier layer made of tantalum alloy and tantalum oxide.

[0071] Optionally, the PI method further comprises a step vii) of depositing an encapsulation layer of diamond or boron nitride by the chemical vapor deposition (CVD) technique at a temperature above 600°C as illustrated in [Fig.6g]. The structure of the gate G1 according to the invention makes it possible to carry out this encapsulation layer deposition step without degrading the robustness of the transistor by diffusion thanks to the barrier layer of tantalum alloy and tantalum oxide. In addition, the barrier layer CB gives the gate G1 excellent temperature resistance, preventing the latter from deforming under the effect of heat.

Claims

Claims

1. Field effect transistor (Tl) comprising a drain (Dl), a source (SI) and a gate (Gl) deposited on an upper layer (Cl) made of a first semiconductor material of a stack of layers deposited on a substrate (SUB) and forming a base structure (Bl); the gate (Gl) comprising: - an electrical contact structure (SC) made of a first electrically conductive material; - a barrier layer (CB) made of an alloy of tantalum and tantalum oxide; the barrier layer (CB) separating said upper layer (Cl) from the contact structure to block the diffusion of the first electrically conductive material into the base structure (Bl);the barrier layer (CB) having a tantalum oxide concentration gradient, the tantalum oxide being in the majority compared to the tantalum in a first part (PI) of the barrier layer (CB) located at a first interface between the barrier layer (CB) and the upper layer (Cl).;

2. Field effect transistor (Tl) according to claim 1 wherein the barrier layer (CB) comprises a second portion (P2) made of tantalum located at a second interface opposite the first interface.

3. A field effect transistor (Tl) according to any one of claims 1 or 2 wherein the first electrically conductive material is gold or aluminum or copper.

4. Field effect transistor (Tl) according to any one of claims 1 to 3 wherein the gate (Gl) further comprises an intermediate layer (CI) confined between the contact structure (SC) and the barrier layer (CB); said intermediate layer (CI) being made of a platinoid or nickel or molybdenum.

5. Field effect transistor (Tl) according to any one of claims 1 to 4 in which the first semiconductor material has a lower output work than tantalum to provide a rectifier contact.

6. Field effect transistor (Tl) according to any one of claims 1 to 5 in which the barrier layer (CB) has a thickness between 5nm and 30nm.

7. Field effect transistor (Tl) according to any one of claims 1 to 6 in which the first part (PI) of the barrier layer (CB) has a thickness of between 5nm and 10nm.

8. Field effect transistor (Tl) according to any one of claims 1 to 7 further comprising an encapsulation layer (CE) of diamond or boron nitride; the gate (Gl) being covered by said encapsulation layer (CE).

9. Field effect transistor (Tl) according to any one of claims 1 to 8 wherein the contact structure (SC) comprises a pillar (PG) and an upper contact layer (CH) resting on said pillar and having a width (L2) greater than that of the pillar (Ll).

10. Method (PI) for manufacturing a gate (Gl) of a field effect transistor (Tl) comprising the following steps: i. providing a stack of layers forming a base structure (Bl) comprising an upper layer (Cl) made of a first semiconductor material; ii. depositing a resin with a chemical composition comprising free oxygen functions on the upper layer (Cl) and manufacturing a pattern (11) corresponding to a predetermined shape of the gate (Gl) in the resin by lithography; iii.depositing a barrier layer (CB) made of an alloy of tantalum and tantalum oxide on the internal walls of said pattern (11) in the enclosure of deposition equipment having a temperature greater than 1900°C; the deposition being carried out from a tantalum source placed at a separation distance (dl) from the base structure (Bl) chosen so as to obtain a barrier layer (CB) having a tantalum oxide concentration gradient; iv. depositing a layer of a first electrically conductive material to fill the pattern (11) in order to obtain a contact structure (SC); the deposition being carried out in the enclosure of said deposition equipment without discharging the base structure (Bl); the deposition being carried out from a source of the first electrically conductive material; v. destroying the resin (RES). 14

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