Improved High Mobility Field-Effect Transistor

Abstract

The invention relates to a high-mobility field-effect transistor comprising: a z-axis stack (10) deposited on a substrate (11) and comprising: a buffer layer (12), a barrier layer (13), a heterojunction (15) between said buffer layer (12) and said barrier layer (13), and a two-dimensional electron gas (9), a drain (D), a source (S), and a gate (G), a first passivation layer (PLhi) having a first dielectric constant (εhi) greater than or equal to 15, a second passivation layer (PLlow) having a second dielectric constant (εlow) less than or equal to 10 and extending over at least the second zone (Z2). Figure to be published: Figure 3

Description

Title of the invention: Improved high-mobility field-effect transistor. FIELD OF THE INVENTION

[0001] The present invention is in the field of high electron mobility field-effect transistors called HEMTs (acronym for the Anglo-Saxon expression "High Electron Mobility Transistor") in GaN technology and for microwave applications, typically at frequencies up to 40 GHz, or even 80 GHz in the near future.

[0002] More particularly, the invention relates to the passivation of transistors in the vicinity of the gate. STATE OF THE ART

[0003] Fig. 1 schematically represents a cross-section of the structure of a conventional elementary HEMT transistor system, in an Oxz plane, made on a substrate 11. Classically, an insulating or semiconducting substrate 11 is used, for example comprising silicon (Si), silicon carbide (SiC) or sapphire (Al2O3), on which is stacked along the z-axis at least two layers of semiconductor extending in the Oxy plane.

[0004] A first layer 12, called a buffer layer, or “buffer” (term used in the Anglo-Saxon literature), has a wide band gap (semiconductor material called a large gap) for example comprising a binary nitrogen compound material, such as GaN or a material based on a ternary compound of element III nitride, called IIIN, such as AlGaN, or more precisely AlxGaN.

[0005] A second layer, called barrier layer 13, has a larger band gap than buffer layer 12. This layer comprises a quaternary, ternary or binary nitride material of elements III, called IIIN, based on Al, Ga, In or B.

[0006] For example, with a GaN buffer layer, the barrier layer comprises AlxGai_xN or InnixAlxN, or an In,xAlxN / AIN or AlxGai xN / AIN sequence. The thickness of the barrier layer 13 is typically between 5 nm and 40 nm, and the thickness of the buffer layer 12 is typically between 0.2 pm and 3 pm. The buffer layer 12 and the barrier layer 13 are conventionally produced by epitaxy using MOCVD or MBE. As an example, a GaN-based buffer layer with an AlGaN or InAlN-based barrier layer, and more specifically an AlxGai xN or InzAli_zN-based barrier layer, can be cited, with x typically between 15% and 35% and z typically between 15% and 25%.

[0007] Additional layers may be present either on the surface or between the buffer layer and the barrier layer.

[0008] The junction between the buffer layer and the barrier layer constitutes a heterojunction 15 which also extends in the Oxy plane. The origin O of the Oxyz frame is chosen in this plane.

[0009] A HEMT transistor conventionally comprises a source S, a drain D, and a gate G deposited on the upper surface 14 of the barrier layer 13. The gate G is deposited between the source S and the drain D and controls the transistor. Typically, the gate-source distance dGS is between 0.4 and 1 pm, and the gate-drain distance dGD is between 0.6 and 2 pm. Preferably, the gate G has a T-shape and consists of a stem 16 surmounted by at least one cap 17 (there may be several, one on top of the other). The two branches of the cap are not necessarily symmetrical, and the branch on the drain side may even be absent (so-called T-gate). The base of the trunk 16 in contact with the barrier layer 13 is commonly referred to as the grid foot, with reference 18s corresponding to the grid foot on the source side and reference 18d corresponding to the grid foot on the drain side in [Fig.l].

[0010] The conductance between the source S and the drain D is modulated by the electrostatic action of the gate G, classically of Schottky type or of MIS type for (metal / insulator / semiconductor), and the voltage VGS applied between the gate and the source controls the transistor.

[0011] A two-dimensional electron gas 9 (denoted 2DEG for "two-dimensional electron gas") is located in the vicinity of the heterojunction 15. These electrons are mobile in the Oxy plane and have high electron mobility pe, typically greater than 1000 cm² / Vs. In normal transistor operation, these electrons cannot circulate in the z direction because they are confined in the potential well formed in the Oxy plane near the heterojunction 15. The electron gas 9, confined in what is called the transistor channel, is therefore capable of carrying a current IDS flowing between the drain and the source. Conventionally, a potential difference VDS is applied between the source S and the drain D, typically with the source S connected to ground, and the value of the current IDS is a function of the applied voltage VGS between the gate G and the source S.

[0012] The transistor effect is based on the modulation of the conductance gm between contacts S and D by the electrostatic action of the control electrode G. The variation of this conductance is proportional to the number of free carriers in the channel, and therefore to the current between the source and drain. It is the transistor amplification effect that allows a weak signal applied to the gate to be transformed into a stronger signal received at the drain.

[0013] In order for GaN technology components to operate at millimeter wave frequencies (> 20 GHz) with sufficient performance, it is necessary to modify a number of parameters defining the transistor. Among these modifications, those of primary importance are:

[0014] Reducing the thickness of the barrier 13, by bringing the gate closer to the electron channel, improves the gain of the transistor.

[0015] Increasing the number of carriers in the structures to reduce access resistance.

[0016] Reducing the gate length of the transistors reduces the transit time of electrons under the gate. This latter option may require optimization of the buffer layer 12 to maintain good electron confinement within the channel.

[0017] However, some of its modifications, notably the increase in carrier density in the ns channel and the reduction in the thickness of barrier 13, contribute to increasing the electric field strength in the structure when the transistor is operating. This increase in the electric field is particularly pronounced for InAl(Ga)N / GaN or AIN transistor technologies for which the electron density in the ns channel is in the range of 1.2 x 10⁻¹¹ / cm² to 2 x 10⁻¹³ / cm². This results in reduced robustness of this technology.

[0018] The particularly intense electric field in these materials can locally reach an intensity greater than 10 MV / cm. The maximum electric field is located at the base of the grid, typically in the grid-drain space.

[0019] Due to the lack of large GaN substrates (greater than 3”), it is necessary to grow semiconductor materials on host substrates such as Al2O3, SiC, or silicon. However, these substrates have a lattice parameter different from that of GaN, which results in a high density of defects oriented perpendicular to the current flowing in the channel.

[0020] These defects extend throughout the entire structure, and the typical density of emerging surface defects is on the order of a few 10⁸ to a few 10⁹ / cm². Figure 2 illustrates one of these dislocations 20 located at the base of the gate in a cross-sectional plane xz. These defects constitute points of weakness in the transistor which, under the action of a high electric field and the stresses induced by the inverse piezoelectric effect, will lead to a degradation of performance (in particular, an increase in gate current) or even to component failure. This area of ​​intense electric field has been identified in the literature as impacting the reliability of devices (see, for example, the publication "Correlation between Physical Defects"). and Performance in AlGaN / GaN High Electron Mobility Transistor Devices”, DOI: 10.4313 / TEEM.2010.11.2.049).

[0021] Since the electric field in the structure is proportional to the voltages applied to the transistor, one solution would be to reduce these voltages, particularly the drain voltage Vds. However, this would be at the expense of the power added efficiency (PAE) and the available output power of the transistor.

[0022] Furthermore, according to the prior art, face 14 is coated with a dielectric layer, called a passivation layer, because the upper face 14 of the barrier layer 13 must be protected from contact with the outside to protect the surface from external aggressions (humidity, impurities) and to stabilize / neutralize the surface states present on the surface of the semiconductor. The dielectric materials typically used are: Al₂O₃, Si₃N₄, SiO₂, SiOxNy, or A₂N. They have dielectric constants ranging from 3.7 (SiO₂) to 10 (Al₂O₃).

[0023] Document US9099433 describes a HEMT transistor with a T-gate comprising two passivation layers. A first passivation layer is deposited on the surface 14 between the gate and the source and between the gate and the drain, and has a conventional passivation function. A second passivation layer coats the gate and covers the first layer.

[0024] US patent 9099433 proposes a solution to optimize RF performance by reducing Cgd and Cgs capacitances without degrading leakage currents and pulsed mode electrical performance (drain lag and gate lag) which are related to the electric field.

[0025] To reduce the capacitances Cgd and Cgs, the gate T-branches are moved further away from the component surface. This increases the electric field within the transistor, leading to increased leakage currents and degraded electrical performance in pulsed mode.

[0026] To maintain the effect of the Cgd and Cgs capacitors on the electric field while minimizing (or not degrading) RF performance, a dielectric material is deposited locally, as close as possible to the gate root where the electric field is strongest. This adds MIS capacitors that are sufficiently small compared to Cgd and Cgs. This approach preserves the field-reducing effect while limiting the impact on the Cgd and Cgs capacitors and therefore on RF performance. This second layer is made of a standard dielectric material such as those listed above.

[0027] This second layer helps to partially solve the problem of high electric field but is of limited effectiveness by the choice of dielectric materials with dielectric constants which must not be too high (<= to 10), because they are present over the whole of the transistor, so as not to degrade RF performance.

[0028] The invention aims to overcome at least one of the aforementioned drawbacks by proposing a HEMT transistor having two passivation layers configured to reduce the value of the electric field at the gate foot. DESCRIPTION OF THE INVENTION

[0029] The present invention relates to a high-mobility field-effect transistor comprising: • a stacking along a z-axis deposited on a substrate and comprising: • a buffer layer comprising a first semiconductor material comprising a binary, ternary, or quaternary nitride compound and having a first band gap, • a barrier layer comprising a second semiconductor material comprising a binary, ternary, or quaternary nitride compound and having a second band gap, the second band gap being greater than the first band gap, • a heterojunction between said buffer layer and said barrier layer and, • a two-dimensional electron gas localized in an xy plane perpendicular to the z-axis and in the vicinity of the heterojunction, • a drain, a source, and a grid arranged on an upper face of said barrier layer between the source and the drain, • the grid having a shape comprising a trunk surmounted by at least one cap, the base of the trunk in contact with said barrier layer being called the grid base, • the upper surface of the barrier layer between the source and the drain having a first zone located from the base of the grid and extending over a distance of at most 100 nm on either side of the grid, and a second zone located on the remaining part of the upper surface, • a first passivation layer having a first dielectric constant greater than or equal to 15 and extending over at least the first zone, the first passivation layer being in direct contact with the barrier layer only in the first zone, • a second passivation layer having a second dielectric constant less than or equal to 10 and extending over at least the second zone, the second passivation layer being in direct contact with the barrier layer only over the second zone.

[0030] According to one embodiment, the second passivation layer is configured to at least partially cover the first passivation layer.

[0031] According to one embodiment, the first passivation layer is configured to at least partially cover the second passivation layer.

[0032] According to one embodiment, the first passivation layer is further configured to cover the trunk of the grid.

[0033] According to one embodiment, the first passivation layer is further configured to coat the grid.

[0034] According to one embodiment the first passivation layer is delimited by the projection along Z of said cap.

[0035] According to one embodiment, the first passivation layer extends at most over half the distance between the grid and the source and over half the distance between the grid and the drain.

[0036] According to one embodiment the first passivation layer comprises a material selected from: Y2O3, ZrO2, HfO2, La2O5, TiO2, Pr2O3, La2O3, SrTiO3, BaTiO3.

[0037] Another aspect of the invention relates to a method for making a high-mobility field-effect transistor comprising: • a step of creating a stack along a z-axis deposited on a substrate, the stack comprising: • a buffer layer comprising a first semiconductor material comprising a binary, ternary, or quaternary nitride compound and having a first band gap, • a barrier layer comprising a second semiconductor material comprising a binary, ternary, or quaternary nitride compound and having a second band gap, the second band gap being greater than the first band gap, • a heterojunction between said buffer layer and said barrier layer and, • a two-dimensional electron gas localized in an xy plane perpendicular to the z-axis and in the vicinity of the heterojunction, then • a step of constructing a drain, a source, and a grid arranged on an upper face of said barrier layer between the source and the drain, and such that the grid has a shape comprising a trunk surmounted by at least one cap, a base of the trunk in contact with said barrier layer being called the grid base, • the upper surface of the barrier layer between the source and the drain having a first zone located from the base of the grid and on either side of the grid over a distance of no more than 100 nm, and a second zone located on the remaining part of the upper surface, • a step of depositing a first passivation layer having a dielectric constant greater than or equal to 15, said deposit being carried out so that the first passivation layer extends over at least the first zone, the first passivation layer being in direct contact with the barrier layer only in the first zone, • a step of depositing a second passivation layer having a dielectric constant less than or equal to 10, said deposit being carried out so that the second passivation layer extends over at least the second zone, the second passivation layer being in direct contact with the barrier layer only over the second zone.

[0038] According to one embodiment, the step of depositing the first passivation layer takes place before the step of depositing the second passivation layer, said second passivation layer then at least partially covering the first passivation layer.

[0039] According to one embodiment, the step of depositing the second passivation layer takes place before the step of depositing the first passivation layer, said first passivation layer then partially covering the second passivation layer.

[0040] According to one embodiment, the step of depositing the first passivation layer includes a sub-step of etching through said grid cap, the first passivation layer then being delimited by the projection along Z of said cap.

[0041] The following description presents several embodiments of the device of the invention. These examples are not limiting to the scope of the invention. These embodiments illustrate both the essential features of the invention and additional features related to the embodiments considered.

[0042] The invention will be better understood and other features, objectives and advantages thereof will become apparent from the following detailed description and with reference to the accompanying drawings given by way of non-limiting examples and in which:

[0043] The [Fig. 1] already cited illustrates a high mobility field-effect transistor according to the prior art.

[0044] The [Fig.2] already cited illustrates a dislocation localized at the foot of the grid.

[0045] Figure 3 illustrates the first variant of a HEMT transistor according to the invention in in which the first passivation layer is deposited first.

[0046] Figure 4 illustrates the second variant of a HEMT transistor according to the invention in which the second passivation layer is deposited first.

[0047] Figure 5 illustrates an embodiment of a HEMT transistor according to the invention in which the first passivation layer covers the entire gate.

[0048] Figure 6 illustrates an embodiment of the first variant of a HEMT transistor according to the invention in which the first passivation layer is delimited by the projection along Z of the gate cap.

[0049] Figure 7 illustrates an embodiment of the second variant of a HEMT transistor according to the invention in which the first passivation layer is delimited by the projection along Z of the gate cap.

[0050] Fig. 8a illustrates the first variant of a transistor according to the invention with the option of a first passivation layer which coats the entire gate and which is deposited using the gate cap as a mask.

[0051] Fig. 8b illustrates the second variant of a transistor according to the invention with the option of a first passivation layer which coats the entire gate and which is deposited using the gate cap as a mask.

[0052] Fig. 9 illustrates the value of the electric field Fz(B) as a function of x for three different values ​​7, 15 and 30 of the dielectric constant of the first passivation layer.

[0053] Fig. 10 illustrates the value of the electric field Fx(ch) as a function of x for three different values ​​7, 15 and 30 of the dielectric constant of the first passivation layer.

[0054] Fig. 11 illustrates the value of the electric field magnitude IF(D)I as a function of x for three different values ​​7, 15 and 30 of the dielectric constant of the first passivation layer.

[0055] Figure 12 illustrates the gain of a transistor according to the invention as a function of the operating frequency for a deposit of the first passivation layer localized over the entire surface, at 100 nm on either side of the gate or at 25 nm on either side of the gate. DETAILED DESCRIPTION OF THE INVENTION

[0056] The invention relates to a HEMT 10 transistor having a stack, a gate, a source and a drain as described [Fig.1].

[0057] An example of grid sizing for a high frequency application (operating frequency greater than 10 GHz, typically between 10 and 80 GHz) is a trunk 16 with a width between 40 and 250 nm, a drain-side branch with dimension Bd between 0 and 150 nm, and a source-side branch with dimension Bs between 0 and 300 nm.

[0058] The distance between the grid and the source is denoted dGS and the distance between the grid and the drain is denoted dGD. For a high-frequency application, dGS is typically between 0.5 and 2 pm and dGD is typically between 1 and 4 pm.

[0059] The specificity of the HEMT 10 according to the invention is that it has a particular arrangement of two passivation layers PLhi and PLlow as illustrated in figures 3 and 4, the PLhi passivation layer having a specific characteristic as explained later.

[0060] For high-frequency applications (typically > 20 GHz), the barrier layer 13 comprises a material selected from: InAIN, AlGaN, InAlGaN, AIN. These different materials are commonly used today for the fabrication of high-frequency GaN components.

[0061] The upper surface 14 of the barrier layer 13 between the source S and the drain D is decomposed into a first zone ZI located from the base of the grid 18s, 18d, and on either side of the grid G ​​over a distance of at most 100 nm on each side of the base of the grid, and a second zone Z2 located on the remaining part of the upper face 14 between the grid and the source and between the grid and the drain.

[0062] The transistor 10 according to the invention comprises a first passivation layer PLhi which has a dielectric constant ehi greater than or equal to 15. This high value of the dielectric constant is counterintuitive, as explained below. The portion of PLhi in direct contact with the top face extends only over the ZI zone. The ZI zone on the source side is not necessarily the same size as the ZI zone on the drain side.

[0063] The transistor 10 also includes a second passivation layer PLlow having a dielectric constant Eiow less than or equal to 10. The portion of PLlow in direct contact with the barrier layer extends only over the second zone Z2. This second passivation layer has a standard thickness (typically 10-50 nm), and a dielectric constant less than 10 corresponds to the case of a common passivation layer in this type of transistor.

[0064] The barrier layer 13 is thus in direct contact with a PLhi passivation layer with a high dielectric constant at the foot of the grid (over a maximum of 100 nm) and in direct contact with a PLlow passivation layer with a low dielectric constant over the rest of its surface.

[0065] The manufacturing technology allows two arrangements constituting two variants of the transistor 10.

[0066] Figure 3 illustrates the first variant in which the PLhi layer is deposited first. The portion of the PLhi layer in contact with face 14 (Z1 zone) then constitutes the entire PLhi layer extending along the xy plane. The PLlow layer deposited after the PLhi layer has a portion in contact with face 14 extending over the Z2 region and a portion that at least partially covers the first PLhi passivation layer. Whether the PLlow layer extends to the base of the grid (PLhi overlay) or not depends on the manufacturing technology. Typically, the grid cap creates shading during deposition, and the PLlow layer decreases in thickness from the projection along the z-axis of the cap, as illustrated in Figures 3 and 4. The distance between the grid and the source is denoted dGS, and the distance between the grid and the drain is denoted dGD.

[0067] Figure 4 illustrates the second variant in which the PLlow layer is deposited First, the PLlow layer is deposited in such a way as to leave an unlayered zone ZI. The portion of the PLlow layer in contact with face 14 (zone Z2) then constitutes the entirety of the PLlow layer extending along the xy plane. The PLhi layer, deposited after PLlow, has a portion in contact with face 14 extending along ZI and another portion that at least partially covers the PLlow layer.

[0068] Depending on the PLhi layer deposition technology, the first passivation layer can, according to a first option, cover the trunk 16 of the grid G, or, according to a second option, coat the entire grid, as illustrated [Fig. 5]. These options are of course compatible with all the aforementioned variants and embodiments.

[0069] According to an embodiment which presents technological implementation facilities, the extent of the first PLhi passivation layer is delimited by the projection along Z of the grid cap 17, as illustrated [Fig.6] for the first variant and [Fig.7] for the second variant.

[0070] Using numerous simulations and experiments, the inventors have demonstrated that using a PLhi passivation layer with a high dielectric constant, compared to using a layer with a lower dielectric constant, for example 7 for a Si3N4 layer, significantly reduces the electric field near the gate root (see below). The reduction effect is particularly noticeable when ehi is greater than or equal to 15. Typically, ehi is in the range of 15-200. The reduction of the electric field at the gate root allows the mechanical stresses induced by the inverse piezoelectric effect to be relaxed to values ​​acceptable for the target operating voltages. An example of these voltages is: Vds_max = 40 V and Vgs_max = -9 V

[0071] In order to avoid degrading the power gain of the transistor, the PLhi layer is located near the gate root when it is in direct contact with the barrier layer 13 (ZI region extending over a maximum of 100 nm). The second passivation layer PLlow covers the rest of face 14 (Z2 region) in order to passivate the entire face 14.

[0072] Thus, locating the first passivation makes it possible to use materials with higher relative permittivity (so-called High-K materials) and to considerably improve voltage withstand without degrading RF performance (at optimum, up to 30-40% reduction of the electric field is obtained, compared to at best 10% for US patent 9099433).

[0073] Typically the first passivation layer is made of a material chosen from: Y2O3, ZrO2, HfO2, Ta2O5, TiO2, La2O3, Pr2O3, SrTiO3, BaTiO3.

[0074] These materials with high dielectric constants are not conventionally used for the passivation of high-frequency HEMT transistors: the presence of a dielectric layer with a high dielectric constant at the gate root is counterintuitive. Indeed, for high-frequency applications, the aim is to reduce the capacitances Cgs and Cgd as much as possible, and therefore to use passivations with the lowest possible dielectric constants.

[0075] The choice of the dielectric material for PLhi depends on the maximum voltages seen by the transistor and the electron density ns in the channel. Thus, the higher the operating voltages and the electron density in the channel, the higher the dielectric constant of the material must be to reduce the intensity of the electric field in the barrier and relax the stresses induced by the inverse piezoelectric effect, which are responsible for some of the degradation of power components.

[0076] The thickness of the PLhi layer is limited, at its lower end by its effect on the electric fields, and at its upper end by the degradation that appears in the RF performance of the transistor. For a localized PLhi layer, the critical upper value for RF performance is higher when the extent of the ZI region is small.

[0077] Figure 8a illustrates transistor 10 according to the invention in the first variant (layer PLhi deposited first) with the option of a PLhi layer that wraps around the entire grid and is deposited using the grid cap as a mask.

[0078] Figure 8b illustrates transistor 10 according to the invention in the second variant (layer PLlow is deposited first, with the option of a PLhi layer that covers the entire grid and is deposited using the grid cap as a mask. The PLlow layer is deposited only on a Z2 area, leaving a ZI area free so that the PLhi layer deposited afterward is in direct contact with the barrier layer 13.

[0079] Figure 8b also illustrates the different electric fields of interest in the vicinity of the gate foot: the field Fz(B) is the projection along z of the electric field in the barrier layer near the surface 14; the term |F(D)| is the magnitude of the electric field in the part of the PLhi layer in contact with the barrier layer; the field Fx(ch) is the projection along x of the electric field in the channel 9 located in the buffer layer 12 near the interface 15.

[0080] Preferably as illustrated in figures 8b the space between the Source and the Drain is filled with a BCB type material to avoid any contact with air.

[0081] Figures 9, 10, and 11 illustrate the respective values ​​of the electric fields Fz(B), Fx(ch), and IF(D)I (magnitude of the electric field) as a function of x (drain side), the value of x corresponding to the grid root (18s source side, 18d drain side) being indicated in the figures. The electric field at the grid root is greatest on the drain side; the field on the source side is lower than the field on the drain side. In figures 9 and 10 the origin of x is the source S, and in [Fig.1 1] the origin of x is the grid foot 18d and the electric field is traced between 4 angstroms and 10nm from this origin.

[0082] The solid line curves 91, 101, 111 correspond to a value of the dielectric constant of the first passivation layer PLhi equal to 7 (classical case of Si3 N4), the long dashed line curves 92, 102, 112 to a value of ehi of 15 and the dashed line curves 93, 103 and 113 to a value of 30 (for example TiO2 or Ta2O5).

[0083] Simulations of a GaN HEMT according to the invention for an InAlGaN / AlN / GaN type structure shown in Figures 9 to 11 were carried out using Silvaco software, with:

[0084] - a configuration of type [Fig.8a] PLhi extends along ZI and around the grid

[0085] - dGs = 0.8 pm ; dGD = 1-6 pm ;

[0086] -Grid: trunk width 16: 150 nm; branch dimensions: 150 nm on each side,

[0087] -an electron density in the channel ns = 1.6.10n / cm2, a voltage Vds = 40V; a voltage Vgs = -9V (most stressful conditions for the transistor);

[0088] - ZI extension of 100 nm on each side of the grid base; a thickness of the PLhi layer ehi = 30 nm;

[0089] -Eiow = 7 eiow = 30 nm;

[0090] These three figures show a very significant decrease in the values ​​of the three electric fields in the vicinity of the gate root 18d as the value of the dielectric constant of PLhi increases. The field Fz(B) decreases from a value of almost 21 MV / cm for ehi=7 to a value of 15 MV / cm for ehi=15. Similarly, Fx(ch) decreases from a value of 5 MV / cm for ehi=7 to a value of 3.8 MV / cm for ehi=15. The magnitude of F(D) decreases from almost 21 MV / cm for ehi=7 to a value of 12 MV / cm for ehi=15. These lower electric field values, by 30 to 40%, make the transistor much less sensitive to local dislocations and relax the stresses induced by the inverse piezoelectric effect.

[0091] Figure 12 illustrates the Gain or MAG (“Max Available Gain”) of the transistor according to the invention as a function of the operating frequency, for the following configuration:

[0092] - a configuration of type [Fig.8a] PLhi extends along ZI and around the grid

[0093] - dGS = 0.8 pm ; dGD = 1.6 pm ;

[0094] -Grid: trunk width 16: 100 nm; branch dimension: 150 nm on each side.

[0095] -ns = 1.6 1013 / cm2 ; Vds=20V ; Ids = 150 mA / mm (corresponds to a class AB operating situation).

[0096] ehi = 30 and ehi = 30 nm

[0097] eiow = 7 and eiow = 30 nm

[0098] Curve 6 illustrates the case where PLhi extends over the entire surface (does not correspond to the invention), curve 7 illustrates the case of a PLhi deposit with ZI extending 100 nm on either side of the grid, and layer 8 illustrates the case of a PLhi deposit localized over 25 nm on either side of the grid.

[0099] We can see from curve 6 (extension of PLhi over the whole surface) that the gain of the transistor is degraded: the extension of the ZI zone is limited by maintaining an acceptable transistor gain, and an excessively extended ZI zone is not desirable.

[0100] For a 25 nm extension (curve 8), performance is better than for 100 nm (curve 7), and 100 nm is therefore considered an upper limit for the ZI extension. Beyond this, the gains are deemed too significant. Thus, the maximum value of the ZI extension is given by the acceptable decrease in transistor gain performance.

[0101] The minimum value of the extension of ZI at the foot of the grid is that which allows obtaining a significant effect on the reduction of the electric field evaluated by simulation at 1 nm.

[0102] According to another aspect, the invention relates to a method for making a high-mobility field-effect transistor comprising a step of making a stack 10 along a z-axis deposited on a substrate, the stack comprising a buffer layer 12, a barrier layer 13, a heterojunction 15 between said buffer layer 12 and said barrier layer 13 and, a two-dimensional electron gas 9 as described above.

[0103] The method also includes a step of constructing a drain D, a source S, and a grid G ​​disposed on the upper face 14 of the barrier layer 13 between the source and the drain, such that the grid G ​​has a shape comprising a trunk 16 surmounted by at least one cap 17, the base of the trunk in contact with the barrier layer being called the grid foot, with 18s corresponding to the grid foot on the source side and 18d corresponding to the grid foot on the drain side. The upper face 14 of the barrier layer between the source and the drain has a first zone Z1 located from the grid foot and on either side of the grid over a distance of at most 100 nm, and a second zone Z2 located on the remaining part of the upper face.

[0104] The process also includes a step of depositing a first passivation layer PLhi having a first dielectric constant greater than or equal to 15, the deposition being carried out such that the first passivation layer extends over at least the first zone Zl, the first PLhi passivation layer being in direct contact with the barrier layer 13 only over the first zone Zl

[0105] The process also includes a step of depositing a second passivation layer PLlow having a dielectric constant eiow less than or equal to 10, the deposition being carried out so that the second passivation layer extends over at least the second zone Z2, the second passivation layer being in direct contact with the barrier layer 13 only on the second zone Z2.

[0106] According to a first variant, the deposition step of the first passivation layer takes place before the deposition step of the second passivation layer, the second passivation layer then at least partially covering the first passivation layer.

[0107] According to a second variant the step of depositing the second passivation layer takes place before the step of depositing the first passivation layer, the first passivation layer then partially covering the second passivation layer.

[0108] According to an embodiment compatible with both variants, the step of depositing the first passivation layer includes a substep of etching through said grid cap, the first passivation layer (PLhi) then being delimited by the projection along Z of said cap.

[0109] According to one embodiment, the step of deposition of the first PLhi passivation layer is carried out by plasma atomic deposition called PE-ALD for "Plasma Enhanced-Atomic Layer Deposition" in English.

[0110] ALD deposition is a technique that allows the controlled deposition of ultrathin films a few nanometers thick. This technique offers excellent control over the thickness and uniformity of the deposited layer and also allows for conformal deposition on 3D structures with high aspect ratios. Plasma allows these depositions to be carried out at lower temperatures.

[0111] This first layer can also be produced by PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Plasma Vapor Deposition), ALD (Atomic Layer Deposition), HWCVD (Hot Wire Chemical Vapor Deposition), CAT-CVD (catalytic Chemical Vapor Deposition), ECR-CVD (Electron-Cyclotron Resonance Chemical Vapor Deposition), ICP-CVD (Inductively Coupled Plasma Chemical Vapor Deposition), by evaporation, spraying or any other known deposition technique.

[0112] According to one embodiment, the step of deposition of the second PLlow passivation layer is carried out by ICP CVD (for "Inductively Coupled Plasma Chemical Vapor Deposition" in English).

[0113] This deposition technique makes it possible to produce dielectric films (typically SiO2, Si3N4, SiON) of very good quality, at low temperature (from 5°C) without damaging the surface on which these films are deposited.

[0114] This second layer can also be produced by LPCVD (Low-Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PVD (Plasma Vapor Deposition), ALD (Atomic Layer Deposition in English), PEALD (Plasma Enhanced Atomic Layer Deposition in English), ICP-CVD (Inductively Coupled Plasma Chemical Vapor Deposition in English), by evaporation, spraying or any other known deposition technique.

Claims

1. Demands A method for making a high-mobility field-effect transistor comprising: - a step of creating a stack (10) along a z-axis deposited on a substrate (11), the stack comprising: • a buffer layer (12) comprising a first semiconductor material comprising a binary, ternary or quaternary nitride compound and having a first band gap, • a barrier layer (13) comprising a second semiconductor material comprising a binary, ternary or quaternary nitride compound and having a second band gap, the second band gap being greater than the first band gap, • a heterojunction (15) between said buffer layer (12) and said barrier layer (13) and, • a two-dimensional electron gas (9) localized in an xy plane perpendicular to the z-axis and in the vicinity of the heterojunction (15), then - a step of constructing a drain (D), a source (S), and a grid (G) disposed on an upper face (14) of said barrier layer (13) between the source and the drain, and such that the grid (G) has a shape comprising a trunk (16) surmounted by at least one cap (17), a base of the trunk in contact with said barrier layer being called the grid foot (18s, 18d), the upper face (14) of the barrier layer between the source and the drain having a first zone (Z1) located from the base of the grid and on either side of the grid over a distance of at most 100 nm, and a second zone (Z2) located on the remaining part of the upper face, - a step of depositing a first passivation layer (PLhi) having a dielectric constant (ehi) greater than or equal to 15, said deposit being carried out so that the first passivation layer extends over at least the

2.

3. first zone (Zl), the first passivation layer (PLhi) being in direct contact with the barrier layer (13) only on the first zone (Zl), - a step of depositing a second passivation layer (PLlow) having a dielectric constant (e1ow) less than or equal to 10, said deposit being carried out so that the second passivation layer extends over at least the second zone (Z2), the second passivation layer being in direct contact with the barrier layer (13) only over the second zone (Z2), - said step of depositing the first passivation layer comprising a sub-step of etching through said grid cap, the first passivation layer (PLhi) then being delimited by the projection along Z of said cap. A method according to the preceding claim in which the step of depositing the first passivation layer takes place before the step of depositing the second passivation layer, said second passivation layer then at least partially covering the first passivation layer. A method according to claim 1 wherein the step of depositing the second passivation layer takes place before the step of depositing the first passivation layer, said first passivation layer then partially covering the second passivation layer.

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