ESD protection device for integrated circuit

Abstract

ESD Protection Device for Integrated Circuit This description relates to an ESD protection device (100) comprising at least one semiconductor electronic switch (102) electrically coupled in parallel with a diode (104), wherein the semiconductor electronic switch (102) and the diode (104) each have at least one finger (112.1 – 112.7; 113.1 – 113.7) extending substantially parallel to a first direction, the fingers of the semiconductor electronic switch (102) and the diode (104) being aligned with each other along this first direction. Figure for the abstract: Fig. 2

Description

Title of the invention: ESD protection device for integrated circuit Technical field

[0001] The present description relates generally to the field of ESD protection (ElectroStatic Discharges in English), or protection against electrostatic discharges. Prior art

[0002] The inputs / outputs of integrated circuits include ESD protection circuits. For example, at the package level of an integrated circuit, the ESD protection circuit at each of the pins of the package may be such that it withstands an electrostatic discharge of a voltage of 2 kV HBM (i.e. according to the HBM model or “Human Body Model” in English). On the other hand, at the substrate, or wafer, level of the integrated circuit, the required level of ESD protection of the inputs / outputs is generally lower, for example such that the inputs / outputs withstand an electrostatic discharge of a voltage of 200 V HBM.

[0003] When pins of the integrated circuit package are electrically coupled to each other (as may be the case, for example, with pins intended to receive the supply voltage of the integrated circuit), the ESD protection thresholds of the circuits of each of the inputs / outputs coupled to these pins are cumulative. In order to ensure that this cumulative value reaches the required ESD protection level for the package pins, the ESD protection circuits of the integrated circuit inputs / outputs may be sized such that each of them can withstand the required electrostatic discharge voltage level for the package pins.Although this solution guarantees a sufficient level of ESD protection for the package pins (even for the IC inputs / outputs each coupled to a single package pin), this oversizing of the ESD protection circuits of the IC inputs / outputs results in a significant semiconductor occupation surface for the realization of these protection circuits, unnecessarily increasing the total semiconductor surface required for the IC.

[0004] Alternatively to the above solution, the ESD protection circuits of the inputs / outputs of the integrated circuit can be individually sized according to the intended wiring with the pins of the package. This alternative solution is however very time-consuming due to the specific design required for each of the ESD protection circuits of the inputs / outputs of the integrated circuit. Summary of the invention

[0005] There is a need to propose a solution to address the problems encountered with existing solutions.

[0006] A particular embodiment addresses at least some of these problems and provides an ESD protection device comprising at least one semiconductor electronic switch electrically coupled in parallel to a diode, wherein the semiconductor electronic switch and the diode each comprise at least one finger extending substantially parallel to a first direction, the fingers of the semiconductor electronic switch and the diode being aligned with each other in this first direction.

[0007] According to a particular embodiment, the semiconductor electronic switch and the diode each comprise several fingers, each finger of the semiconductor electronic switch being aligned with one of the fingers of the diode in the first direction, together forming a pair of fingers, the pairs of fingers being aligned with each other in a second direction substantially perpendicular to the first direction.

[0008] According to a particular embodiment, the ESD protection device comprises at least one resistor having a larger dimension substantially parallel to the first direction.

[0009] According to a particular embodiment, the semiconductor electronic switch comprises a GGNMOS or GCPMOS or BiCMOS type transistor, or comprises a thyristor.

[0010] According to a particular embodiment, the ESD protection device further comprises two connection terminals to which electrodes of the semiconductor electronic switch and the diode are coupled.

[0011] According to a particular embodiment, the semiconductor electronic switch and the diode, or each pair of fingers of the semiconductor electronic switch and the diode when the semiconductor electronic switch and the diode each comprise several fingers, are configured to withstand an electrostatic discharge voltage of value equal to a target ESD protection value at the substrate level.

[0012] Another particular embodiment proposes an integrated circuit comprising several inputs / outputs each electrically coupled to at least one ESD protection device as described above.

[0013] According to a particular embodiment, the ESD protection devices are part of an input / output circuit arranged on the periphery of a core region of the integrated circuit.

[0014] According to a particular embodiment, the integrated circuit further comprises a package provided with several pins each electrically coupled to at least one of the inputs / outputs, at least one group of pins being electrically coupled between them, the ESD protection devices coupled to the group of pins or to each of the groups of pins being configured to together withstand an electrostatic discharge voltage of value equal to an ESD protection target value at the package level.

[0015] According to a particular embodiment, at least one of the pins of the package is not electrically coupled to any of the other pins, the ESD protection device coupled to said at least one of the pins being configured to alone withstand an electrostatic discharge voltage of value equal to the ESD protection target value at the package level. Brief description of the drawings

[0016] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0017] - [Fig.l] schematically represents an example of embodiment of a device of ESD protection;

[0018] - [Fig.2] represents an example of a topology of an ESD protection device

[0019] - [Fig.3] represents, in the form of a functional diagram, an example of ESD protection device;

[0020] - [Fig.4] schematically represents an example of the realization of a circuit integrated including ESD protection devices. Description of the embodiments

[0021] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0022] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, different elements (transistor, thyristor, diode, etc.) of the ESD protection device, as well as the different parts of the integrated circuit (core, input / output circuit, package) are not detailed. Those skilled in the art will be able to produce these elements in detail from the functional description given here.

[0023] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0024] In the following description, when referring to position qualifiers absolute, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures in a normal position of use. Similarly, the terms "parallel" and "perpendicular" are interpreted by considering differences in angle corresponding to the manufacturing tolerances normally allowed in the field.

[0025] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0026] An exemplary embodiment of an ESD protection device 100 is described below in connection with [Fig.l].

[0027] The device 100 comprises at least one semiconductor electronic switch 102 corresponding to a transistor or a thyristor. In the example of [Fig.l], the switch 102 is formed by, or comprises, a transistor which may be of the GGNMOS, or GCPMOS (Gate Coupled PMOS), or BiCMOS type (an NMOS type transistor is shown in [Fig.l]). Alternatively, it is possible for the switch 102 to be formed by, or comprises, a triac or a bipolar transistor, or more generally any component configured to discharge an electrostatic discharge.

[0028] According to another variant, it is possible for the semiconductor electronic switch 102 to be formed by, or to comprise, a diode, or several diodes coupled in series when voltages higher than the trigger threshold of a single diode (for example 0.6 V) must be maintained.

[0029] Throughout the document, the expression "electronic semiconductor switch" designates one or more electronic semiconductor components allowing or not allowing the passage of a current, for example, depending on the value of a control signal applied to this or these components and / or depending on a direction of circulation of the current.

[0030] The switch 102 is coupled in parallel to a diode 104. In the example of [Fig.l], the anode of the diode 104 is electrically coupled to the source of the transistor forming the switch 102, and the cathode of the diode 104 is electrically coupled to the drain of this transistor. According to an exemplary embodiment, the diode 104 may be of the “Gated Diode” type, i.e. comprising a gate to separate the anode and the cathode of the diode 104, or STI (“Silicon Trench Isolation”), i.e. comprising an isolation trench to separate the anode and the cathode of the diode 104.

[0031] The device 100 shown in [Fig.l] further comprises a first connection terminal 106 to which the cathode of the diode 104 and a first current input / output electrode of the switch 102 (this first electrode corresponding to the drain of the transistor in the example of [Fig.l]) are electrically coupled. A supply voltage of an integrated circuit comprising the device 100 is for example intended to be applied to this first connection terminal 106.

[0032] The device 100 shown in [Fig.l] further comprises a second connection terminal 108 to which the anode of the diode 104 and a second current input / output electrode of the switch 102 (this second electrode corresponding to the source of the transistor in the example of [Fig.l]) are electrically coupled. This second connection terminal 108 is for example intended to be coupled to a reference electrical potential, i.e. the ground, of the integrated circuit comprising the device 100.

[0033] When the semiconductor electronic switch 102 is formed by, or comprises, a diode, or several diodes coupled in series, the anode of this diode (or of each of these diodes in the case of several diodes coupled in series) can be coupled to the first connection terminal 106, and the cathode of this diode (or of each of these diodes in the case of several diodes coupled in series) can be coupled to the second connection terminal 108.

[0034] In the example of [Fig.l], the device 100 further comprises a resistor 110. In the particular configuration described, a first electrode of the resistor 110 is electrically coupled to the gate and to the substrate electrode, or “bulk” electrode, of the transistor forming the switch 102, and a second electrode of the resistor 110 is electrically coupled to the second current input / output electrode of the switch 102, i.e. the source of the transistor in the example of [Fig.l], and therefore also to the anode of the diode 104 and to the second connection terminal 108. According to an exemplary embodiment, the value of the resistor 110 may be between 500 Ohms and 10 kOhms. The resistor 110 may make it possible to adjust the trigger voltage of the parasitic bipolar transistor of the MOS transistor forming the switch 102.In fact, it is this parasitic bipolar transistor that will cause the entire discharge to pass for a positive ESD discharge between terminals 106 and 108. For a negative ESD discharge between terminals 106 and 108, the current will be evacuated through diode 104.

[0035] Although not shown, the device 100 may include other components coupled to the switch 102 and the diode 104, such as for example a flip-flop or other resistors.

[0036] The switch 102 and the diode 104 each comprise at least one finger extending substantially parallel to a first direction and which are aligned with each other in this first direction. These characteristics are visible in [Fig. 2] which represents an example of topology, or “layout” in English, of the device 100.

[0037] In the example of [Fig.2], the switch 102 and the diode 104 each have several fingers. The fingers of the switch 102 are referenced 112.1 - 112.7, and those of the diode 104 are referenced 113.1 - 113.7. Each finger 112.1 - 112.7 of the switch 102 is aligned with one of the fingers 113.1 - 113.7 of the diode 104 in the first direction, together forming a pair of fingers. The pairs of fingers 112.1 - 112.7, 113.1 - 113.7 are aligned with each other in a second direction substantially perpendicular to the first direction. In [Fig.2], the first direction is parallel to the Y axis, and the second direction is parallel to the X axis.

[0038] For the switch 102, each finger 112.1 - 112.7 may correspond to an active portion of the switch 102. More particularly, when the switch 102 is formed by, or comprises, a transistor, each finger 112.1 - 112.7 may comprise a semiconductor region in which portions of the source, channel and drain regions of the transistor are formed, with a portion of the gate of the transistor extending above this portion of the channel region. The width of this portion of the gate, which corresponds to the dimension of the gate that is substantially perpendicular to the direction of alignment of the source, drain and channel regions of the transistor (i.e. the direction of current flow in the active portion of the transistor), may be substantially parallel to the first direction, and the length of this portion of the gate may be substantially perpendicular to the first direction.

[0039] For the diode 104, each finger 113.1 - 113.7 may correspond to an active portion of the diode 104 including portions of the anode and cathode regions of the diode 104 extending substantially parallel to each other and substantially parallel to the first direction.

[0040] In the example of [Fig.2], the resistor 110 is arranged such that its largest dimension is substantially parallel to the first direction.

[0041] This configuration in pairs of fingers 112.1 - 112.7; 113.1 - 113.7 of the switch 102 and the diode 104 can allow a modular design of the device 100. According to this modular design, the device 100 can comprise a first fixed part (the term "fixed" can be understood here in the sense of "always present") including a pair of fingers of the switch 102 and the diode 104. In [Fig. 2], this first fixed part is delimited by a rectangle designated by the reference 114 and comprises the pair of fingers 112.1, 113.1. The device 100 can also comprise a second fixed part including in particular the component(s) of the device 100 other than the fingers of the switch 102 and the diode 104, i.e. the resistor 110 in the example described. In [Fig.2], this second fixed part is delimited by a rectangle designated by the reference 116.

[0042] Between the two fixed parts 114, 116, one or more pairs of fingers of the switch 102 and the diode 104 may be present (the pairs 112.2 - 112.7, 113.2 - 113.7 in [Fig.2]). The number of pairs of fingers of the switch 102 and the diode 104 present between the fixed parts 114, 116 is chosen, during the design of the device 100, as a function of the value of the electrostatic discharge of a voltage intended to be supported by the device 100 both for the electrostatic discharges of voltage at the substrate level (before packaging) and those at the packaging level.

[0043] [Fig. 3] represents, in the form of a functional diagram, the modular structure of the device 100. In this figure, the device 100 comprises the two fixed parts 114, 116 (the fixed part 114 including the first pair of fingers 112.1, 113.1 of the switch 102 and of the diode 104) and the possible n-1 pairs of additional fingers 112.2 - 112.n of the switch 102 and 113.2 - 113.n of the diode 104, interposed between the fixed parts 114, 116, n being an integer greater than or equal to 1.

[0044] For example, each pair of fingers 112.1 - 112.n, 113.1-113.n of the switch 102 and the diode 104 may be sized to withstand, on its own, an electrostatic discharge of voltage value at least equal to a target ESD protection value at the substrate level, for example equal to approximately 100 V or 200 V HBM. Thus, even without a pair of fingers of the switch 102 and the diode 104 present between the fixed parts 114, 116, the pair of fingers of the switch 102 and the diode 104 (referenced 112.1, 113.1 in [Fig. 2]) present in the fixed part 114 ensures that the device 100 can withstand an electrostatic discharge of voltage value equal to the target ESD protection value at the substrate level. In the example of [Fig.2], considering that each of the pairs of fingers 112.1 - 112.7, 113.1 - 113.7 allows to withstand an electrostatic discharge of voltage equal to approximately 100 V HBM, the device 100 shown is configured to withstand an electrostatic discharge voltage equal to approximately 700 V HBM. In a particular configuration, the device 100 can comprise a number of pairs of fingers of the switch 102 and the diode 104 allowing it to withstand an electrostatic discharge of voltage value between approximately 100 V HBM and 2000 V HBM.

[0045] [Fig.4] schematically represents an integrated circuit 1000 comprising several ESD protection devices 100.

[0046] The integrated circuit 1000 comprises a core region 1002 comprising, for example, calculation circuits, memory circuits, controllers, etc. The integrated circuit 1000 also comprises an input / output circuit 1004, also called “FO ring” in English, arranged on the periphery of the core region 1002 and comprising the ESD protection devices 100 (not visible in [Fig.4]).

[0047] Each of the ESD protection devices 100 is electrically coupled to one of the inputs / outputs of the integrated circuit 1000. By making the devices 100 such that each comprises at least one pair of fingers of the switch 102 and the diode 104 di designed to withstand an electrostatic discharge of voltage value at least equal to the target ESD protection value at the substrate level, for example equal to approximately 100 V or 200 V HBM, each of the inputs / outputs of the integrated circuit 1000 is well protected from electrostatic discharges at the substrate level by one of the devices 100.

[0048] The integrated circuit 1000 further comprises a package 1006 provided with several pins (not visible in [Fig. 4]) each electrically coupled to at least one of the inputs / outputs of the integrated circuit 1000. Some of these pins, for example those to which the supply voltage of the integrated circuit 1000 is intended to be applied, may be electrically coupled to each other by forming a group of pins. The devices 100 which are electrically coupled to the electrically connected pins of this group may be configured, or dimensioned, to together withstand an electrostatic discharge of voltage value equal to a target ESD protection value at the package level, for example equal to approximately 2000 V HBM. Thus, the integrated circuit 1000 is well protected at each of the pins of the package 1006 of the integrated circuit 1000.

[0049] Thus, by using the devices 100 within the integrated circuit 1000, it is possible to reduce the occupied surface area dedicated to the ESD protection of the inputs / outputs of the integrated circuit 1000 at the substrate level while maintaining the required ESD protection level at the package level because it is possible to configure, or dimension, individually and easily each of the devices 100, by choosing the number of pairs of fingers of the switch 102 and the diode 104 present in each of the devices 100 (modular nature of the devices 100). The modular nature of the devices 100 makes it possible to avoid a significant development time for these devices 100.

[0050] Several exemplary embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0051] Finally, the practical implementation of the exemplary embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An ESD protection device (100) comprising at least one semiconductor electronic switch (102) electrically coupled in parallel to a diode (104), wherein the semiconductor electronic switch (102) and the diode (104) each comprise at least one finger (112.1 -112.7; 113.1 - 113.7) extending substantially parallel to a first direction, the fingers (112.1 - 112.7; 113.1 - 113.7) of the semiconductor electronic switch (102) and the diode (104) being aligned with each other along this first direction.

2. The ESD protection device (100) of claim 1, wherein the semiconductor electronic switch (102) and the diode (104) each comprise a plurality of fingers (112.1 - 112.7; 113.1 - 113.7), each finger (112.1 - 112.7) of the semiconductor electronic switch (102) being aligned with one of the fingers (113.1 - 113.7) of the diode (104) in the first direction, together forming a pair of fingers (112.1 - 112.7; 113.1 - 113.7), the pairs of fingers (112.1 - 112.7; 113.1 - 113.7) being aligned with each other in a second direction substantially perpendicular to the first direction.

3. An ESD protection device (100) according to claim 2, comprising at least one resistor (110) having a largest dimension substantially parallel to the first direction.

4. ESD protection device (100) according to one of the preceding claims, wherein the semiconductor electronic switch (102) comprises a GGNMOS or GCPMOS or BiCMOS type transistor, or comprises a thyristor.

5. An ESD protection device (100) according to one of the preceding claims, further comprising two connection terminals (106, 108) to which electrodes of the semiconductor electronic switch (102) and the diode (104) are coupled.

6. An ESD protection device (100) according to one of the preceding claims, wherein the semiconductor electronic switch (102) and the diode (104), or each pair of fingers (112.1 - 112.7; 113.1-113.7) of the semiconductor electronic switch (102) and the diode (104) when the semiconductor electronic switch (102) and the diode (104) each comprise several fingers (112.1 - 112.7; 113.1-113.7), are configured to withstand a discharge voltage electrostatic of value equal to a target ESD protection value at the substrate level.

7. Integrated circuit (1000) comprising several inputs / outputs each electrically coupled to at least one ESD protection device (100) according to one of the preceding claims.

8. The integrated circuit (1000) of claim 7, wherein the ESD protection devices (100) are part of an input / output circuit (1004) disposed at the periphery of a core region (1002) of the integrated circuit (1000).

9. An integrated circuit (1000) according to one of claims 7 or 8, further comprising a package (1006) having a plurality of pins each electrically coupled to at least one of the inputs / outputs, at least one group of pins being electrically coupled to each other, the ESD protection devices (100) coupled to the group of pins or to each of the groups of pins being configured to together withstand an electrostatic discharge voltage of a value equal to an ESD protection target value at the package level.

10. The integrated circuit (1000) of claim 9, wherein at least one of the pins of the package is not electrically coupled to any of the other pins, the ESD protection device (100) coupled to said at least one of the pins being configured to withstand alone an electrostatic discharge voltage of value equal to the target ESD protection value at the package level.

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