Image sensor

Abstract

Image Sensor This description concerns an image sensor comprising a pixel array (Pix3) arranged in first rows and first columns. The pixels are organized into groups of N*N pixels, where N is an integer greater than or equal to 2. Within each group, the pixels are divided into one or more subgroups of several pixels. Each pixel comprises: a photosensitive element (PD), a first node (SN) coupled to the photosensitive element, a second node (300) common to all pixels in the same subgroup and coupled to a first potential (Vrst), a first transistor (TB) coupling the first and second nodes, a second transistor (TSF) with a source follower having its gate connected to the first node (SN), and a third transistor (TS) coupling the source of the third transistor (TSF) to a readout line (Vxi). Figure for the abstract: Fig. 3

Description

Title of the invention: Image sensor technical field

[0001] This description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, to image sensors. Previous technique

[0002] Image sensors comprising a pixel matrix arranged in rows and columns are known. Among these known sensors, some are configured to operate alternately according to a first operating mode, corresponding to a reduced resolution mode, and a second operating mode, corresponding to a full resolution mode.

[0003] In the second mode of operation, the pixels of the same line are read simultaneously and individually, each pixel read providing an output signal to a different corresponding reading circuit.

[0004] In the first operating mode, the pixels are organized into groups of N*N pixels, where N is an integer greater than or equal to 2, and, when reading the pixels of a given group, the output signals of the pixels in the group are combined and supplied to a single readout circuit. Thus, in this first operating mode, unused readout circuits can be switched off so as to reduce the sensor's power consumption.

[0005] However, known image sensors configured to implement the two operating modes described above have several drawbacks. For example, their power consumption remains too high, even in the first operating mode. For example, the time required to capture a low-resolution image in the first operating mode is too long. Summary of the invention

[0006] There is a need to overcome all or part of the disadvantages of known image sensors configured to operate alternately according to a first operating mode at reduced resolution and according to a second operating mode at full resolution.

[0007] An embodiment overcomes all or part of the disadvantages of known image sensors configured to operate alternately according to a first operating mode at reduced resolution and according to a second operating mode at full resolution.

[0008] One embodiment provides an image sensor comprising a pixel matrix arranged in first rows and first columns, in which: - pixels are organized into groups of N*N pixels, with N an integer greater than or equal to 2; - within each group, the pixels of the group are divided into one or more subgroups of several pixels; - Each pixel includes: a photosensitive element, a first node coupled to the photosensitive element, a second node common to all pixels of the same subgroup and coupled to a first potential, a first transistor coupling the first and second nodes, a second source follower transistor having its gate connected to the first node, and a third transistor coupling the source of the third transistor to a read line.

[0009] According to one embodiment, the sensor further comprises a control circuit configured, in a first mode of operation, for each group, to implement a read of said group by controlling: the conducting state of the first transistor of each pixel of the group, for each subgroup, the conducting state of the third transistor of one or more given pixels among the pixels of the subgroup, and the blocking state of the third transistor of all the other pixels of the subgroup; and in which, in each group, the given pixel or pixels of said group have their third transistors connected to the same read line.

[0010] According to one embodiment, in each group, the pixels are distributed into a single subgroup which is indistinguishable from said group.

[0011] According to one embodiment, each subgroup comprises a single given pixel.

[0012] According to one embodiment: - the sensor includes, for each first column, exactly P reading lines associated with said first column, where P is a positive integer; and - for each reading line, the sensor includes a reading circuit connected to the reading line.

[0013] According to one embodiment: - the groups are organized into second rows and second columns; - the control circuit is configured, in the first operating mode, to implement a reading of groups of K second lines simultaneously, with K an integer belonging to a range from 2 to N*P; and - in each second column, the third transistors of said given pixels of the groups of said K second rows are connected to different read lines if they belong to different groups.

[0014] According to one embodiment, in each first line, all the pixels of the line have their third transistors connected to a different read line.

[0015] According to one embodiment, the first rows are organized into sets of P first rows, and, in each set of P first rows, the third transistors of the pixels of the same first column are connected to different read lines among the P read lines associated with said first column.

[0016] According to one embodiment, the control circuit is configured, in a second operating mode, in each set of the first P rows, to implement a simultaneous reading of the pixels of the first P rows of the set by controlling: the blocked state of the first transistor of each pixel of each of the first P rows of the set, and the on state of the third transistor of each pixel of each of the first P rows of the set.

[0017] According to one embodiment, in the second operating mode, for each pixel, the control circuit is configured, for each integration phase by said pixel, to control the blocked state of the first transistor of said pixel.

[0018] According to one embodiment: Each pixel further includes a fourth transistor coupling the second node of said pixel to the first potential, the first potential being an initialization potential; and The control circuit is configured, for each pixel, to implement pixel initialization by simultaneously controlling the on state of the first and fourth transistors of the pixel.

[0019] According to one embodiment, each pixel includes a transfer gate coupling the first node to the photosensitive element, and in which the control circuit is configured, for each pixel, to implement pixel initialization by putting the pixel transfer gate into the conducting state while the first and fourth pixel transistors are in the conducting state, and, preferably, to switch the transfer gate to the blocked state at the end of pixel initialization.

[0020] According to one embodiment, in the first mode of operation, in each group, the control circuit is configured to implement an initialization of a first part of the pixels of the group and an initialization of a second part of the pixels of the group ending after the initialization of the first part of the pixels of the group. Brief description of the drawings

[0021] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0022] [Fig.1] partially represents an example of a pixel of an image sensor;

[0023] [Fig. 2] represents an example of an image sensor implemented with the pixel of the [Fig.l] and configured to operate alternately according to a first operating mode at reduced resolution and according to a second operating mode at full resolution;

[0024] [Fig.3] represents an embodiment of a pixel of an image sensor;

[0025] [Fig. 4] represents an embodiment of an implemented image sensor with the pixel of [Fig. 3] and configured to operate alternately in a first operating mode at reduced resolution and in a second operating mode at full resolution; and

[0026] [Fig.5] represents another embodiment of a pixel of an image sensor. Description of the implementation methods

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, common applications in which an image sensor is configured to operate alternately in a first operating mode at reduced resolution and a second operating mode at full resolution have not been detailed, as the described embodiments and variants are compatible with these common applications.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0032] Fig. 1 represents, schematically and partially, an example of a Pixl pixel of an image sensor.

[0033] The Pixl pixel includes a photosensitive element (not shown in [Fig.1]) coupled, for example connected, to a detection node SN of the Pixl pixel.

[0034] The Pixl pixel further includes a MOS (Metal Oxide Semiconductor) transistor TR. The TR transistor is an initializer for pixel 1, and, more specifically, for initializing the SN node of the Pixl pixel to an initialization potential Vrst. The TR transistor is connected between the SN node and a node 100 configured to receive the Vrst potential. When the TR transistor is turned on by an RST signal received on its gate, the SN node is set to the Vrst potential (neglecting the voltage drop across the TR transistor).

[0035] The Pixl pixel further comprises a TSF MOSF transistor. The TSF transistor is a source-follower transistor, or, in other words, is configured as a source follower. The gate of the TSF transistor is connected to the SN node. The drain of the TSF transistor is connected to a VDD bias potential application node 102. The source of the TSF transistor is coupled to a Vxi readout line by a TS MOSFET of the Pixl pixel. More specifically, the TS transistor is connected between the source of the TSF transistor and the Vxi line. In this way, when the TSF transistor is switched on by a SEL signal received at its gate, the TSF transistor charges the Vxi line to a potential determined by the potential of the SN node, and, conversely, when the SEL transistor is switched off by the SEL signal, the TS transistor electrically isolates the Vxi line from the TSF transistor.

[0036] Figure 2 shows an example of an image sensor 2 implemented with the Pixl pixel of Figure 1 and configured to operate alternately in a first operating mode at reduced resolution and in a second operating mode at full resolution. To avoid cluttering the figure, only one Pixl pixel is referenced in Figure 2.

[0037] The sensor 2 comprises a matrix of pixels Pixl arranged in Nr rows Rq and Ne columns Cj, with Nr and Ne being positive integers greater than 2, q an integer index from 1 to Nr and j an integer index from 1 to Ne. In the example in [Fig.2], Nr is equal to 8 and Ne is equal to 8.

[0038] For each column Cj, the sensor 2 comprises exactly P reading lines (or conductive lines) Vxi associated with that column Cj, with P a positive integer and i an integer index from 1 to P. In the example in [Fig. 2], P is equal to 2, and each Column Cj is associated with two corresponding rows Vxl and Vx2. In the example in [Fig.2], the rows Vxl and Vx2 are represented by dashed lines.

[0039] The Rq lines are organized into sets of exactly P Rq lines, preferably P successive Rq lines. Each Rq line belongs to only one set of P Rq lines. In the example in [Fig. 2], P is equal to 2, and each set of P Rq lines comprises an Rq line of odd index q and the next Rq+1 line of index q+1. In other words, in this example, a first set comprises the two lines R1 and R2, a second set comprises the two lines R3 and R4, a third set comprises the two lines R5 and R6, and a fourth set comprises the two lines R7 and R8.

[0040] In each set of P rows Rq, the pixels Pixl in the same column Cj have their transistors TS connected to different Vxi rows among the Vxi rows associated with that column Cj. For example, in the set comprising the two rows RI and R2, the pixel in row RI and column Cia has its transistor TS connected to the Vxl row associated with column Cl, and the pixel in row R2 and column Cia has its transistor TS connected to the Vx2 row associated with column Cl. In [Fig.2], in each pixel Pixl, a point is located on the Vxi row to which the TS transistor of the pixel Pixl is connected.

[0041] In each Rq line of pixels, all the pixels in the line have their TS transistors connected to different Vxi lines.

[0042] In sensor 2, the Pixl pixels are arranged in groups of 202 of N*N Pixl pixels, where N is an integer greater than or equal to 2. Each group of 202 therefore comprises the Pixl pixels belonging to N successive rows Rq and N successive columns Cj. To avoid cluttering the figure, only one group of 202 of N*N pixels is referenced in [Fig. 2]. Furthermore, to facilitate reading [Fig. 2], the groups of 202 of N*N Pixl pixels are separated from each other by spaces, although, in practice, these spaces may be absent.

[0043] In the example in [Fig.2], N is equal to 2 and each group 202 therefore comprises 4 pixels. For example, the group 202 referenced in [Fig.2] comprises the pixels Pixl belonging to the N=2 rows R3 and R4 and the N=2 columns C7 and C8.

[0044] The 202 groups of N*N pixels Pixl are arranged in NGr rows (RGm) and NGc columns (CGn), where NGr and NGc are positive integers greater than 2, m is an integer index from 1 to NGr, and n is an integer index from 1 to NGc. More specifically, NGr is equal to Nr / N and NGc is equal to Nc / N. In other words, sensor 2 comprises a matrix of 202 groups of N*N pixels Pixl arranged in NGr rows (RGm) and NGc columns (CGn) to form a matrix of Nr = N*NGr rows (RGm) and Ne = N*NGc columns (CGn) of pixels Pixl. In the example in [Fig. 2], NGr is equal to 4 and NGc is equal to 4, and sensor 2 comprises NGr*NGc = 16 groups 202 of 4*4 pixels Pixl, the 16 groups 202 being organized into NGr=4 rows RG1, RG2, RG3 and RG4 of groups 202 and NGc=4 columns CGI, CG2, CG3, CG4 of groups 202.

[0045] The sensor 2 includes, for each Vxi reading line, a reading circuit 200 associated with that reading line.

[0046] Sensor 2 also includes NGc circuits 204 for routing Vxi lines to circuits 200.

[0047] More specifically, for each CGn column of groups 202, the sensor 2 includes a circuit 204 associated with that CGn column. Each circuit 204 is connected, for example, has connected inputs, to the Vxi lines associated with the Cj columns that have Pixl pixels belonging to the groups 202 of that CGn column. For example, the circuit 204 associated with the CGI column is connected to the Vxi and Vx2 lines associated with the Cl and C2 columns, the Cl and C2 columns having their Pixl pixels belonging to the groups 202 of the CGI column.

[0048] In addition, each circuit 204 is connected, for example has connected outputs, to the reading circuits 200 which are associated with the Vxi lines to which this circuit 204 is connected.

[0049] The sensor 2 includes a control circuit 206 configured to control the circuits 204 and the Pixl pixels.

[0050] In full-resolution operation, circuit 206 controls circuits 204 so that each read line Vxi is electrically coupled to its associated circuit 200. In this operating mode, each time a line Rq of pixels Pixl is read, all the pixels Pixl in the line are read simultaneously. Furthermore, in this operating mode, sets of P lines Rq are read sequentially, and when each set of P lines Rq of pixels Pixl is read, the P lines Rq in the set are read simultaneously. In other words, the sets of P lines Rq are read one after the other, and the reading of each set of P lines Rq includes the simultaneous reading of all the pixels Pixl that are part of the P lines Rq in that set. To read a pixel Pixl, circuit 206 turns on the pixel's transistor TS with the SEL signal corresponding to that transistor.

[0051] For example, in [Fig.2] where P is equal to 2, in full-resolution operation, the P=2 lines RI and R2 are read simultaneously, all the pixels Pixl of these P=2 lines RI and R2 being read simultaneously, then the P=2 two lines R3 and R4 are read simultaneously, all the pixels Pixl of these P=2 lines R3 and R4 being read simultaneously, then the P=2 two lines R5 and R6 are read simultaneously, all the pixels Pixl of these P=2 lines R5 and R6 being read simultaneously, and, finally, the P=2 lines R7 and R8 are read simultaneously, all the pixels Pixl of these P=2 lines R7 and R8 being read simultaneously.

[0052] In a reduced-resolution operating mode, the circuit 206 controls the circuits 204 so that, for each circuit 204, the Vxi lines connected to that circuit 204 are all electrically coupled to a single circuit 200 connected to the circuit 204. In this operating mode, reading a group 202 includes supplying the output signals of the pixels Pixl in that group to a corresponding circuit 204 where these signals are combined before being supplied to a single readout circuit. In particular, reading a group 202 of pixels Pixl includes turning on the transistors TS of all the pixels Pixl in that group. In this operating mode, the RGm lines of groups 202 of pixels Pixl are read one after the other, with reading an RGm line corresponding to the simultaneous reading of all the groups 202 in that line.

[0053] For example, in [Fig.2] where P is equal to 2, in a reduced resolution operating mode, the RG1 line of groups 202 of Pixl pixels is read by turning on the TS transistors of all the Pixl pixels of the groups 202 belonging to this RG1 line, then the RG2 line of groups 202 of Pixl pixels is read by turning on the TS transistors of all the Pixl pixels of the groups 202 belonging to this RG2 line, then the RG3 line of groups 202 of Pixl pixels is read by turning on the TS transistors of all the Pixl pixels of the groups 202 belonging to this RG3 line, and, finally, the RG4 line of groups 202 of Pixl pixels is read by turning on the TS transistors of all the Pixl pixels of the groups 202 belonging to this RG4 line.

[0054] In reduced-resolution mode, since each circuit 204 only supplies a signal to one of the circuits 200 to which it is connected, the other circuits 200 to which circuit 204 is connected and to which circuit 204 does not supply a signal can be switched off, thus reducing power consumption. However, since the reading of the groups 202 is performed one line RGm after the other, the reading time for all the groups 202 of N*N pixels Pixl of the sensor 2 is long. The longer this reading time for the groups 202, the greater the power consumption of the sensor 2. Furthermore, when this reading time is long, the sensor 2 is no longer able to acquire and provide images at a frame rate (fps) sufficient for certain applications.

[0055] For example, a sensor 2 comprising Nr = 320 rows of pixels Pixl and Ne = 320 columns of pixels Pixl consumes approximately 20 mW with an acquisition rate of 30 frames per second at full resolution. In a reduced-resolution mode with 202 groups of 10*10 pixels Pixl (N equals 10), this sensor 2 is, however, not capable of acquiring images at a frame rate equal to or greater than 5 while consuming less than 10 pW, which is required by certain applications.

[0056] It is proposed here, in a reduced-resolution operating mode, to take advantage of the unused and switched-off circuits 200 of sensor 2. Indeed, a sensor similar to sensor 2 is proposed, in which, in low-resolution operating mode, during each reading of all groups 202 of N*N pixels, the reading circuits 200 are all left on and are then used to read several RGm lines of groups 202 of N*N pixels simultaneously.

[0057] Leaving all circuits 200 on during the reading of all groups 202 in low-resolution operating mode appears to be contrary to the low-power objective.

[0058] However, this allows, in low-resolution operating mode, a reduction in the time required to read all groups of N*N pixels. Thus, in low-resolution operating mode, for a target frame rate, the time between each two successive reads of all groups of N*N pixels is increased. Between each two successive reads of all groups of N*N pixels, the read circuits 200 and, preferably, all peripheral circuits necessary for the operation of these read circuits (voltage regulators, image processing circuits receiving the outputs of the circuits 200, circuits generating a clock signal for the circuits 200) can then be switched off or put into standby mode to reduce power consumption.

[0059] For example, to acquire five images per second in low-resolution mode with a 320*320 pixel sensor arranged in groups of 10*10 pixels, a sensor has 200 ms to acquire an image and, when this sensor is as proposed, it needs, for example, 20 ps or less to read all the groups 202. This means that, for each low-resolution image acquired, the circuits 200 and, preferably, their peripheral circuits can be turned off or put into standby for 199.98 ms, which makes it possible to reduce the sensor's consumption to below 10 pW for each low-resolution image acquired.

[0060] To implement the operation described above, a pixel and a sensor implemented with this pixel are proposed.

[0061] Fig. 3 represents an example of an embodiment of such a Pix3 pixel.

[0062] The Pix3 pixel includes many elements in common with the Pixl pixel, and only the differences between these pixels are detailed here.

[0063] In particular, the Pix3 pixel differs from the Pixl pixel in that it comprises a MOS transistor TB connected between the SN node and a 300 node, and that the TR transistor of the Pix3 pixel is connected between the 300 node and the 100 node receiving the Vrst potential. The TB transistor is controlled by a BIN signal that it receives on its gate.

[0064] Although this is not visible in [Fig. 3], when the Pix3 pixels are arranged in groups of 202 of N*N Pix3 pixels for low-resolution operation, the node 300 is common and unique for all Pix3 pixels in the same group 202. In particular, each group 202 of Pix3 pixels includes its own node 300 which is preferably different from the nodes 300 of other groups 202 of pixels.

[0065] Thus, by switching transistor TB on while transistor TR is off, all the pixels Pix3 in the same group 202 of N*N pixels Pix3 share a common node 300 on which, at the time of reading the group of pixels Pix3, there is a voltage representing the amount of light received by the pixels Pix3 in that group. It is therefore no longer necessary to provide a circuit 204 to combine the output signals of the pixels.

[0066] In the example in [Fig. 3], the PD photodetector, for example a pinched or unpinched photodiode, of pixel Pix3 is shown. As indicated in relation to [Fig. 2], this PD photodetector is coupled to the SN node of pixel Pix3.

[0067] More specifically, as shown in Figure 3, the Pix3 pixel includes, for example, a transfer grid TG coupling the SN node to the PD photodetector, the TG grid being, for example, connected between the SN node and the PD photodetector. The TG grid is controlled by an STG signal.

[0068] In another example not shown, the pixel Pix3 is devoid of grid TG and the node SN is connected to the photodetector PD.

[0069] Fig. 4 represents an example of an embodiment of an image sensor 4 implemented with the Pix3 pixel described above and configured to operate alternately according to a first operating mode at reduced resolution and according to a second operating mode at full resolution.

[0070] Sensor 4 shares many features with sensor 1, and only the differences between these two sensors are detailed here. Thus, unless otherwise indicated, everything described for sensor 2 in relation to [Fig. 2] applies to sensor 4 described in relation to [Fig. 4].

[0071] In particular, compared to sensor 2, the Pixl pixels have been replaced by Pix3 pixels, with only one Pix3 pixel being referenced in [Fig.4] so as not to overload it.

[0072] Furthermore, sensor 4 does not have a circuit 204. Thus, each Vxi line is connected to its associated circuit 200. Eliminating the circuits 204 reduces the size of sensor 4 compared to sensor 2. Moreover, since circuits 204 are typically implemented as switches that change state when the sensor changes operating mode, thereby incurring switching losses, eliminating the circuits 204 also reduces power consumption and increases the linearity of sensor 4 compared to sensor 2.

[0073] The control circuit 206 of sensor 2 is replaced by a control circuit 400 in sensor 4. This circuit 400 is configured to provide the SEL, BIN, and RST signals to the Pix3 pixels, and the STG signals when these pixels include Each pixel has a transfer gate TG. Naturally, the SEL signals supplied to the pixels by the 400 circuit can differ between two pixels. For example, one pixel might receive an SEL signal that turns its transistor TS on, while another pixel simultaneously receives an SEL signal that turns its transistor TS off.

[0074] In particular, in a low-resolution operating mode, for each group 202 of N*N pixels Pix3, the circuit 400 is configured to perform a group read by switching the TB transistor of each pixel Pix3 in the group on, so that they share node 300 ([Fig. 3]), and simultaneously switching the TS transistor of a single given pixel Pix3 in the group 202 on and the TS transistors of the other pixels Pix3 in the group off. Thus, it is this given pixel Pix3 that will provide the output signal of the group 202 of pixels Pix3 on the Vx line to which the TS transistor of this given pixel Pix3 is connected. In each group 202, this given pixel Pix3 whose TS transistor is switched on during the group read is, for example, called the group 202 read pixel, and is hatched in [Fig. 4].Put another way, in low-resolution operating mode, for each group, the 400 circuit is configured to implement a read of said group by providing a SEL signal to the read pixel of the group which is different from the SEL signal provided to all other pixels of the group, this different SEL signal being able to be seen as a SEL' signal.

[0075] By way of example, when the Pix3 pixels include a transfer grid TG as described in relation to [Fig.3], before a readout of a group 202 of Pix3 pixels, the TG grid of each Pix3 pixel in the group is switched to the conducting state so that the potential of node 300 is determined by the amount of light received by the PD photodetectors of these Pix3 pixels, and then is returned to the blocked state before the group 202 is readout.

[0076] In other examples where the Pix3 pixels are devoid of TG grid, this switching of the TG grids before reading is of course omitted.

[0077] In sensor 4, as in sensor 2, for each column Cj, the sensor comprises P readout conductive lines Vxi associated with that column Cj. Furthermore, the lines Rq are organized into sets of exactly P lines Rq, preferably P successive lines Rq, each line Rq belonging to only one set of P lines Rq. In each set of P lines Rq, the pixels Pix3 of the same column Cj have their transistors TS connected to different lines Vxi among the lines Vxi associated with that column Cj.

[0078] In [Fig. 4], for each pixel Pix3, the connection of the transistor TS of pixel Pix3 to a corresponding Vxi line is represented by a point located within the pixel and on that Vxi line. For example, the pixel Pix3 located in the upper left corner in [Fig. 4] has its TS transistor connected to the Vxl line associated with the Cl column containing this Pix3 pixel.

[0079] In the sensor 4, the circuit 400 is configured, in low-resolution operating mode, to implement a simultaneous reading of the groups 202 of K RGm lines of groups 202, with K an integer belonging to a range from 2 to N*P. To read these K RGm lines simultaneously, in each column CGn of groups 202 of N*N pixels Pix3, the reading pixels Pix3 (hatched in [Fig.4]) of the groups 202 belonging to these K RGm lines are connected to different Vxi lines.

[0080] By way of example, in [Fig. 4], the 400 circuit is configured to read K = 2*2 = 4 RGn lines simultaneously, that is, to read the four RG1, RG2, RG3, and RG4 lines simultaneously. Thus, in each CGn column, the group read pixels Pix3 (hatched in [Fig. 4]) that belong to that CGn column and also to one or another of the RG1, RG2, RG3, and RG4 lines have their TS transistors connected to different Vxi lines. For example, as shown in [Fig.4] : - the Pix3 reading pixel of group 202 of column CGI and row RG1 belongs to column Cl and is connected to row Vxl associated with this column Cl; - the Pix3 reading pixel of group 202 of column CGI and row RG2 belongs to column Cl and is connected to row Vx2 associated with this column Cl; - the Pix3 reading pixel of group 202 of column CGI and row RG3 belongs to column C2 and is connected to row Vxl associated with this column C2; and . - the Pix3 pixel reading group 202 of column CGI and row RG4 belongs to column C2 and is connected to row Vx2 associated with this column C2.

[0081] Of course, a person skilled in the art is able, from the description given here of the sensor 4, to foresee other examples of arrangement of the reading pixels Pix3 of the groups 202 and / or of connection of the reading pixels Pix3 of the groups 202 to the Vxi lines of the sensor.

[0082] Although in the above example all RGm lines are read simultaneously, in another example (not shown) where sensor 4 only includes one Vxi line per column Cj, the circuit 400 is then configured to read K = 2*1 = 2 RGm lines simultaneously in a first step, and the other 2 RGm lines simultaneously in a second step, the reading of all groups 202 then taking place in two successive steps.

[0083] However, preferably, the number P of rows Vxi per column Cj and the number N are determined, for a sensor 4 comprising a given number of pixels Pix3, such that N*P is equal to NGr and, for example, that the numbers Nr / N and Nc / N are integers. The circuit 400 can then preferably be configured to simultaneously read NGr group 202 lines in low-resolution operating mode.

[0084] The circuit 400 is further configured, in full-resolution operating mode, to read sets of P lines Rq one after the other, the reading of each set of P lines Rq corresponding to the simultaneous reading of all the pixels Pix3 of the P lines Rq in that set. In other words, in full-resolution operating mode, in each set of P lines Rq of pixels Pix3, the circuit 400 is configured to implement a simultaneous reading of the pixels Pix3 of the P lines Rq in that set.

[0085] In particular, in full-resolution operating mode, for each set of P lines Rq of pixels Pix3, the circuit 400 implements a simultaneous reading of the pixels of the P lines Rq of the set by controlling: - the blocked state of the TB transistor of each of these Pix3 pixels, so that the SN node of the pixel is isolated from the 300 node common to all the Pix3 pixels of the 202 group to which this Pix3 pixel belongs, from which it follows that, when reading the Pix3 pixel, the potential of the SN node of the Pix pixel is determined only by the amount of light received by the PD photodetector of this Pix3 pixel; and - the conducting state of the TS transistor of each of these Pix3 pixels, so that each Pix3 pixel charges the Vxi line to which its TS transistor is connected to a potential determined by the potential of the SN node of that Pix3 pixel.

[0086] By way of example, taking up the distinction between the SEL' signals received by the read pixels of the groups 202 and the SEL signals received by all the other pixels, in the full resolution operating mode, when a line Rq is read, each read pixel that is part of this line Rq receives an SEL' signal identical to the SEL signal received by each of the other pixels of this line Rq, namely SEL and SEL' signals controlling the switching on of the TS transistors that receive these signals.

[0087] As is customary in image sensors, the circuit 400 is configured to implement an initialization of each pixel Pix3 of the sensor 3, that is to say an initialization of the SN node of each pixel Pix3 to the potential Vrst.

[0088] By way of example, for each pixel Pix3 in sensor 4, circuit 400 initializes the potential of node SN to potential Vrst not only by switching the TR transistor of pixel Pix3 on, but also by switching the TB transistor of that pixel on simultaneously with the TR transistor on. This initialization phase also initializes the potential of node 300 to potential Vrst. Preferably, in full-resolution operating mode, the TR transistor can be left permanently on, so that node 300 is not floating.

[0089] By way of example, when the Pix3 pixels each include a transfer grid TG, the latter can be switched to the conducting state and then to the blocked state during an initialization of the Pix3 pixel, so as to also initialize the photodetector PD, for example by emptying the photogenerated charges which are in it and which are evacuated to the node 102. The switching to the blocked state of the TG of the Pix3 pixel then marks the beginning of an integration phase by this Pix3 pixel.

[0090] According to one embodiment, using the above example of Pix3 pixels equipped with TG grids, in each group 202, in the low-resolution operating mode, all the Pix3 pixels in the group integrate the light they receive during a time period common to all these pixels. In other words, in the low-resolution operating mode, in each group 202, the integration of light by the Pix3 pixels in group 202 begins simultaneously in all the Pix3 pixels of the group and ends simultaneously in all the Pix3 pixels of the group.

[0091] According to one embodiment, using the above example of Pix3 pixels equipped with TG grids, in each group 202, in the low-resolution operating mode, a portion of the Pix3 pixels in the group is initialized, then the other portion of the Pix3 pixels in the group is initialized. For example, all the pixels in the group are initialized simultaneously, then the initialization completes for a first portion of the Pix3 pixels in the group while it continues for the second portion of the Pix3 pixels in that group, and the initialization of the second portion of the Pix3 pixels in the group completes at a time later than the initialization of the first portion of the Pix3 pixels in the group.

[0092] Predicting the completion of initialization at different times for two parts of the Pix3 pixels in a group 202 allows the integration time of the Pix3 pixels whose initialization finished earlier to be longer than the integration time of the Pix3 pixels whose initialization finished later. This makes it possible to achieve an operation, for example, called "high dynamic range" or HDR.

[0093] An advantage of implementing HDR mode in low-resolution operating mode is that it is not necessary to provide a processing circuit to combine the output signals of Pix3 pixels with a shorter integration time and the output signals of Pix3 pixels with a longer integration time, this combination being done directly on node 300 during the reading phase.

[0094] Of course, although the HDR mode in the second operating mode has been described for an example where, in each group 202, the pixels of the group are organized into two parts, each having a different integration time, a person skilled in the art can, from the above description, adapt this example to cases where, in each group 202, the pixels of the group are organized into more than two parts, each having a different integration time.

[0095] As an alternative example, when the Pix3 pixels each lack a TG gate, in each Pix3 pixel, the initialization of the SN node of the Pix3 pixel by the simultaneous switching on of both transistors TR and TB also allows the initialization of the PD photodetector of that Pix3 pixel. In this case, in each Pix3 pixel, switching the TB transistor of the Pix3 pixel to the off state marks the end of the pixel initialization and the beginning of an integration phase by that pixel in full-resolution operating mode. Furthermore, in each group 202, the simultaneous switching of the TR transistors of the Pix3 pixels in the group marks the end of the initialization of the Pix3 pixels in group 202 and the beginning of an integration phase by group 202.

[0096] Taking the example above where the Pix3 pixels each lack a TG gate, in full-resolution operating mode, for each Pix3 pixel, when the Pix3 pixel is in an integration phase, for example, an integration phase beginning with the end of pixel initialization and ending with the reading of that Pix3 pixel, the circuit 400 is configured to control the blocked state of the pixel's TB transistor. Thus, only the light received by that Pix3 pixel during this integration phase determines the potential of the SN node at the time the pixel is read; or, in other words, the light received by other Pix3 pixels sharing the same node 300 does not affect the potential of that pixel's SN node.

[0097] By way of example, when the Pix3 pixels each include a TG gate, during the integration phase of each Pix3 pixel, in full-resolution operating mode, the pixel's TB transistor is preferably left in the blocked state, although it can also be left conducting until the TG gate is successively switched to the conducting state and then to the blocked state to terminate the integration.

[0098] By way of example, when the pixels Pix3 each include a TG gate, during the integration phase of each pixel Pix3, in the low-resolution operating mode, the pixel's TB transistor is preferably left in the conducting state although it can also be left blocked until the reading of this pixel Pix3, that is to say until the reading of the group of pixels including this pixel Pix3.

[0099] For example, when the Pix3 pixels are each devoid of a TG gate, during the integration phase of each Pix3 pixel, in full-resolution operating mode, the pixel's TB transistor is left in the blocked state.

[0100] By way of example, when the pixels Pix3 are each without a TG gate, during the integration phase of each pixel Pix3, in the low-resolution operating mode, the pixel's TB transistor is preferably left in the conducting state although it can also be left blocked until the reading of this pixel Pix3, that is to say until the reading of the group of pixels including this pixel Pix3.

[0101] In the example of sensor 4 described in relation to [Fig.4], Nr is equal to 8, Ne is equal to 8, P is equal to 2 and N is equal to 2.

[0102] Table 1 below lists further examples of sensor 4. In particular, in this Table 1, the first column indicates the number of the example, the second column indicates the total number Nr*Nc of pixels Pix3 of the sensor which also corresponds to the resolution of the sensor when it is operating in full resolution mode, the third column indicates the number N, the fourth column indicates the total number NGr*NGc of groups 202 of N*N pixels Pix3 which also corresponds to the resolution of the sensor when it is operating in reduced resolution mode, the fifth column indicates the number P of lines Vxi per column Cj, the sixth column indicates the total number of circuits 200 of the sensor, and the seventh column indicates the maximum value Kmax (N*P) of the number K of lines RGm of groups 202 which can be read simultaneously.

[0103] [Tables] Nr*Nc N NGr*NGc P Kmax 1 300*300 10 30*30 3 900 30 2 320*320 10 32*32 3 960 30 3 320*320 10 32*32 2 640 20 4 324*324 9 36*36 2 648 18 5 363*363 11 33*33 3 1089 33

[0104] In Example 1 of Table 1 above, the sensor comprises NGr = 30 RGm lines of 202 groups of 30*30 pixels Pix3, and the maximum value Kmax of RGm lines that can be read simultaneously is equal to 30. Thus, the 400 circuit is able to implement a simultaneous reading of all the RGm lines of the sensor.

[0105] In Example 2 of Table 1 above, the sensor comprises NGr = 32 RGm lines of 202 groups of 32*32 pixels Pix3, and the maximum value Kmax of RGm lines that can be read simultaneously is 30. Thus, the 400 circuit is able to implement a simultaneous reading of 30 RGm lines from the sensor in a first step and will then implement the simultaneous reading of the remaining 2 RGm lines in a second step. During this second step, only 32*2 = 64 200 circuits are used, and the unused 200 circuits can be switched off to reduce power consumption.

[0106] In Example 3 of Table 1 above, the sensor comprises NGr = 32 RGm lines of 202 groups of 32*32 pixels Pix3, and the maximum value Kmax of RGm lines that can be read simultaneously is equal to 20. Thus, the 400 circuit is able to implement a simultaneous reading of 20 RGm lines from the sensor at a first This step will then involve simultaneously reading the remaining 12 RGm lines in a second step. During this second step, only 32*12 = 384 200 circuits are used, and unused 200 circuits can be switched off to reduce power consumption.

[0107] In Example 4 of Table 1 above, the sensor comprises NGr = 36 RGm lines of 202 groups of 9*9 pixels Pix3, and the maximum value Kmax of RGm lines that can be read simultaneously is equal to 18. Thus, the 400 circuit is able to implement a simultaneous reading of 18 RGm lines of the sensor in a first step and will then have to implement the simultaneous reading of the remaining 18 RGm lines in a second step.

[0108] In Example 5 of Table 1 above, the sensor comprises NGr = 33 RGm lines of 202 groups of 11*11 pixels Pix3, and the maximum value Kmax of RGm lines that can be read simultaneously is equal to 33. Thus, the 400 circuit is able to implement a simultaneous reading of the 33 RGm lines of the sensor in a single step.

[0109] As an example, to capture five low-resolution images per second, the sensor has 200 ms to capture each image, and in particular to read all the groups 202 of the sensor. Considering that, for each group 202, reading the group requires 20 ps, ​​then, for each acquisition of a low-resolution image: - the circuits 200 of the sensor 4 of example 1 of table 1 can be turned off for 199.98 ms whereas those of a sensor 2 comprising the same number of pixels, the same number of groups 202, and the same number of rows Vxi per column Cj as this sensor 4 can only be turned off for 199.4 ms; - the circuits 200 of sensor 4 of example 2 of table 1 can be turned off for 199.96 ms (or even for 199.98 ms for 960-64 = 896 of them) whereas those of a sensor 2 comprising the same number of pixels, the same number of group 202, and the same number of row Vxi per column Cj as this sensor 4 can only be turned off for 199.36 ms; - the circuits 200 of sensor 4 of example 3 of table 1 can be turned off for 199.96 ms (or even for 199.98 ms for 640-384 = 256 of them) whereas those of a sensor 2 comprising the same number of pixels, the same number of group 202, and the same number of row Vxi per column Cj as this sensor 4 can only be turned off for 199.36 ms; - the circuits 200 of sensor 4 in example 4 of table 1 can be switched off for 199.96 ms, whereas those of a sensor 2 comprising the same number of pixels, the same number of groups 202, and the same number of rows Vxi per column Cj as this sensor 4 can only be switched off for 199.28 ms; and - the circuits 200 of sensor 4 of example 5 of table 1 can be turned off for 199.98 ms whereas those of a sensor 2 comprising the same number of pixels, the same number of group 202, and the same number of row Vxi per column Cj as this sensor 4 can only be turned off for 199.34 ms.

[0110] Although not explicitly stated in the above description, in each group 202 of Pix3 pixels, the node 300 common to the Pix3 pixels in group 202 is distinct from the nodes 300 of the Pix3 pixels in the other groups 202.

[0111] Fig. 5 represents another embodiment of a Pix3 pixel of image sensor 4.

[0112] Only the differences between the Pix3 pixel of [Fig.3] and that of [Fig.5] are highlighted here.

[0113] In particular, in this other embodiment, the node 300 of the pixel Pix3 is not coupled to the node 100 by the transistor TR, but by a capacitive element C, and, furthermore, the node 100 does not receive the potential Vrst but a biasing potential Vpoll.

[0114] Furthermore, in this embodiment, the SN node of the Pix3 pixel is coupled to the PD photodetector of the pixel by the TG transfer gate and by a TSF2 transistor configured as a source follower. More specifically, the TG gate is connected between the PD photodetector and a CN node, and the TSF2 transistor has its source connected to the SN node and its gate connected to the CN node. The drain of the TSF2 transistor is connected to a 400 node configured to receive a Vrd potential.

[0115] Pixel Pix3 of embodiment [Fig. 5] includes, like pixel Pix3 of embodiment [Fig. 3], a transistor TR controlled by a signal RST. However, in [Fig. 5], this transistor TR is connected between node CN and a node 402 configured to receive the potential Vrst.

[0116] Pixel Pix3 of [Fig. 5] includes a switch T1 controlled by a signal S1 and a capacitive element C1 in series with switch T1 between node SN and a node 404 configured to receive a potential, for example, a reference potential GND, for example, ground. Switch T1 is connected between node SN and element C1. Pixel Pix3 of [Fig. 5] also includes a switch T2 controlled by a signal S2 and a capacitive element C2 in series with switch T2 between node SN and a node 406 configured to receive a potential, for example, the reference potential GND. Switch T2 is connected between node SN and element C2.

[0117] The operation of sensor 3 in the case where the Pix3 pixels are implemented in the manner described in relation to [Fig. 5] is within the grasp of a person skilled in the art, based on this description and their general knowledge. In particular, what has been indicated concerning the control of transistors TB and TS of the Pix3 pixels of [Fig.3] during a low-resolution reading phase and during a full-resolution reading phase applies to pixel Pix3 of [Fig.5].

[0118] More generally, a person skilled in the art will be able to adapt this description to other examples of Pix3 pixels provided that these Pix3 pixels include: a TSF transistor with a source follower having its gate connected to an SN node coupled to a PD photodetector of the pixel

[0119] In the embodiments and variants described above, each group 202 comprises only one Pix3 reading pixel having its TS transistor which is put into the conducting state during a reading of this group 202.

[0120] In alternative embodiments, each group 202 comprises several group read Pix3 pixels, all connected to the same read Vxi line. This can be the case, for example, when the number N is equal to D*P with D an integer greater than or equal to 2, since each group then comprises D Pix3 pixels connected to each of the Vxi lines associated with the columns Cj containing Pix3 pixels of that group. In this case, in low-resolution operating mode, for each group 202, the reading of group 202 includes the switching on by the control circuit 400 of the TS transistors of the read pixels Pix3 of the group and the switching off by the control circuit 400 of all the other pixels Pix3 of group 202. In this case, during the reading of the group, there are D conducting TS transistors connected in parallel to the same Vxi line, which reduces read noise and increases the dynamic range of the signal on the Vxi line.

[0121] In the embodiments and variants described above, in each group, all the Pix3 pixels of the group share the same node 300.

[0122] In embodiments where each group 202 comprises several group read pixels Pix3, all connected to the same read line Vxi, the pixels in each group 202 are divided into several subgroups of several pixels. In each subgroup, the pixels Pix3 of the subgroup share a common node 300, which is common to all the pixels Pix3 of the subgroup but distinct from the node 300 of each of the other subgroups. Each subgroup further comprises at least one of the read pixels Pix3 of the group 202 to which that subgroup belongs. In this case, in the low-resolution operating mode, for each group 202, the reading of group 202 includes the switching on of the TS transistors of the group's read pixels Pix3 by the control circuit 400, and the switching off of all the other pixels Pix3 in group 202 by the control circuit 400.Thus, when reading the group, in each subgroup, the reading pixel(s) Pix3 of the group tend to impose the potential on the Vxi line to which the . The TS transistors passing through these group readout pixels are connected according to the potential present at node 300 of that subgroup. Since, within each subgroup of the same group 202, the group readout pixel(s) belonging to that subgroup can only pull the potential of the Vxi line upwards, the subgroup(s) of the group that have defects, for example, white pixels, and therefore have their nodes 300 pulled to ground (GND), cannot pull the potential of the Vxi line downwards. Consequently, for each group 202, during group 202 readout, the potential of the Vxi line on which the group output signal is read is determined solely by the subgroups of group 202 that do not have defects, thus eliminating (or filtering out) the subgroups of group 202 that have defects.

[0123] It will be noted that the case where, in each group 202, all the pixels Pix3 of the group share the same node 300 is a special case of the embodiment variant described above, this special case corresponding to the case where each group 202 includes only one subgroup confused with this group 202.

[0124] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0125] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, although not detailed, a person skilled in the art can, based on this description, implement a circuit configured to switch off, in low-resolution operating mode, the sensor 4 circuits 200, and preferably their peripheral circuits, when these circuits 200 are not in use.

Claims

Demands

1. Image sensor (4) comprising a pixel matrix (Pix3) arranged in first rows (RI, R8) and first columns (Cl, C8), wherein: - the pixels are arranged in groups (202) of N*N pixels, with N an integer greater than or equal to 2; - in each group, the pixels of the group are divided into one or more subgroups of several pixels; - each pixel comprises: a photosensitive element (PD), a first node (SN) coupled to the photosensitive element, a second node (300) common to all the pixels of the same subgroup and coupled to a first potential, a first transistor (TB) coupling the first and second nodes (SN; 300), a second transistor (TSF) with a source follower having a gate connected to the first node (SN), and a third transistor (TS) coupling the source of the second transistor (TSF) to a readout line (Vxi, Vxl, Vx2);- the sensor (4) further includes a control circuit (400) configured, in a first operating mode, for each group (202), to implement a reading of said group by controlling: the conducting state of the first transistor (TB) of each pixel (Pix3) of the group (202), for each subgroup, the conducting state of the third transistor (TS) of one or more given pixels (Pix3) among the pixels of the subgroup (202), and the blocking state of the third transistor (TS) of all the other pixels (Pix3) of the subgroup (202); - in each group, the given pixel(s) of said group have their third transistors connected to the same reading line; - the sensor (4) includes, for each first column (Cl, C8), exactly P reading lines (Vxi, Vxl, Vx2) associated with said first column, with P a positive integer; - for each reading line (Vxi, Vxl, Vx2), the sensor (4) includes a reading circuit (200) connected to the reading line; - the groups (202) are organized into second rows (RG1, RG8) and second columns (CGI, CG8); - the control circuit (400) is configured, in the first operating mode, to implement a reading of the groups (202) of K second rows (RG1, RG8) simultaneously, with K an integer belonging to a range from 2 to N*P; and - in each second column (CGI, CG8), the third transistors (TS) of said pixels (Pix3) given of the groups (202) of said K second rows (RG1, RG8) are connected to different reading lines (Vxi, Vxl, Vx2) if they belong to different groups.

2. Image sensor according to claim 1, wherein, in each group, the pixels are distributed into a single subgroup indistinguishable with said group.

3. Image sensor according to claim 1 or 2, wherein each subgroup comprises a single given pixel.

4. Image sensor according to any one of claims 1 to 3, wherein, in each first row (RI, R8), all pixels (Pix3) of the row have their third transistors (TS) connected to a different readout row (Vxi, Vxl, Vx2).

5. Image sensor according to any one of claims 1 to 4, wherein the first rows (RI, R8) are arranged in sets of P first rows (RI, R8), and, in each set of P first rows (RI, R8), the third transistors (TS) of the pixels (Pix3) of the same first column (Cl, C8) are connected to different read lines (Vxi, Vxl, Vx2) among the P read lines associated with said first column (Cl, C8).

6. Image sensor according to claim 5, wherein the control circuit (400) is configured, in a second operating mode, in each set of first P rows (RI, R8), to implement a simultaneous reading of the pixels (Pix3) of the first P rows of the set by controlling: the blocked state of the first transistor (TB) of each pixel (Pix3) of each of said first P rows (RI, R8) of the set, and the on state of the third transistor (TS) of each pixel (Pix3) of each of said first P rows (RI, R8) of the set.

7. Image sensor according to claim 6, wherein, in the second mode of operation, for each pixel (Pix3), the control circuit (400) is configured, for each integration phase by said pixel (Pix3), to control the blocked state of the first transistor (TB) of said pixel.

8. Image sensor according to any one of claims 1 to 7, wherein: each pixel further comprises a fourth transistor coupling the second node of said pixel to the first potential, the first potential being an initialization potential; and the control circuit (400) is configured, for each pixel (Pix3), to implement an initialization of the pixel (Pix3) by simultaneously controlling the on-state of the first and fourth transistors (TB, TR) of the pixel.

9. Image sensor according to claim 8, wherein each pixel (Pix3) comprises a transfer gate (TG) coupling the first node (SN) to the photosensitive element (PD), and wherein the control circuit (400) is configured, for each pixel (Pix3), to implement the initialization of the pixel (Pix3) by putting the transfer gate (TG) of the pixel into the conducting state while the first and fourth transistors (TB, TR) of the pixel are in the conducting state, and, preferably, to switch the transfer gate to the blocking state at the end of the pixel initialization.

10. Image sensor according to claim 8 or 9, wherein, in the first mode of operation, in each group (202), the control circuit (400) is configured to implement an initialization of a first part of the pixels (Pix3) of the group and an initialization of a second part of the pixels (Pix3) of the group (202) ending after the initialization of the first part of the pixels (Pix3) of the group (202).

Images