Method for manufacturing MOSFET transistors incorporating air cavities for reducing capacitive coupling in radio frequency operation

Abstract

Title: Method for manufacturing MOSFET transistors incorporating air cavities for reducing capacitive coupling in radio frequency operation. The invention relates to a method for manufacturing a microelectronic device (100) with a cavity (20) comprising at least one transistor (11a), said method comprising at least the following step: Removing materials from a stack of dielectric layers (1) of the microelectronic device (100), selectively with respect to the materials of a set of interconnect lines (2) and a cover (3) of an active area by high-frequency vapor etching, thereby forming the cavity (20) extending laterally in a direction x at least until the walls of the set of interconnect lines (2) are exposed opposite the first transistor (11a), and in a direction z perpendicular to the direction x until an upper face of the cover (3) of the active area is exposed. Figure for the abstract: Fig. 4

Description

Title of the invention: Method for producing MOSFET transistors integrating air cavities for reducing capacitive coupling in radiofrequency mode Technical field

[0001] The present invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of RF (“Radiofrequency”) switches with MOS (“Metal-Oxide-Semiconductor”) transistors and cavities. STATE OF THE ART

[0002] To meet the continuous evolution of communication standards, the multiplicity of RF switches is a necessity. The existence of several communication standards requires the reduction of insertion losses in the RF switch. To do this, the transistors that compose it must have as low a resistance as possible in linear operating mode. A technological lever for reducing the resistance of a transistor R0N consists of reducing the length of its channel and therefore of its gate. In return, this gate reduction leads to a substantial increase in the blocked state capacitance COff, the magnitude of which can lead to a degradation of the time constant R0nC0ff- The variations of R0N and COff generally follow antagonistic trends, because any process variation tending to improve one of the two parameters results in a simultaneous degradation of the other.

[0003] A solution that allows to partially decouple the interdependence between R0N and COff, consists in replacing the dielectric layers between the metallic lines of the interconnection network of the device, by another material of lower dielectric permittivity such as air, thus allowing the reduction of the capacitance COff independently of Ron- This can be achieved by partially removing the dielectric layers between the metallic connection lines in post-process mode after completion of the manufacturing process of the RF switches, thus giving rise to cavities above the transistors.

[0004] Document US 10707120 B1 discloses a method for producing air cavities above transistor gates in the dielectric layers between the metal connection lines. These air cavities are produced by several successive dry etchings, a first anisotropic etching allowing the formation of holes in a first dielectric layer, and a second isotropic dry etching allowing the formation of a reduced air cavity in a second dielectric layer above the transistors. However, this etching is not selective, and the level of isotropy and The geometry of the etch in the second dielectric layer strongly depends on the size of the openings in the first layer and the etch parameters, which limits the lateral extension of the air cavity, and consequently the removal of the dielectric layers.

[0005] Document EP 3859777 A1 discloses a device with air cavities produced by several successive etchings, a first anisotropic and non-selective dry etching allows the formation of a trench crossing several dielectric layers between the metal connection lines and stopping in a dielectric layer above the transistor without exposing an etching stop layer covering the transistor, and a second isotropic wet etching by HF acid ("Hydrofluoric" in English or Hydrogen Fluoride) allows the formation of a cavity which also extends in a reduced manner in a dielectric layer between metal interconnections.

[0006] Document US 10211146 B2 discloses another method for producing air cavities above transistors by two successive etchings. A first anisotropic and non-selective dry etching allows the formation of a first straight air cavity crossing the different dielectric layers between the metal connection lines. A second isotropic wet etching by HF acid allows the lateral extension of the cavity.

[0007] The present invention proposes to overcome at least in part the drawbacks of the known methods. In particular, an objective of the present invention is to propose a method for producing cavities, in particular in an RF switch, which makes it possible to effectively reduce the time constant R0nC0ff of the transistor(s). SUMMARY

[0008] To achieve this objective, according to one embodiment, a method is provided for manufacturing a cavity microelectronic device comprising at least a first transistor, said first transistor comprising a first channel surmounted by a first gate extending laterally in a direction y, a first source and a first drain, said method comprising the following steps: • Provide on a substrate: - An active area having an active layer comprising the first channel, the first source and the first drain of the first transistor, and the first gate above the active layer surmounting the first channel, - A cover of the active area comprising at least one mechanical stress layer covering the active layer and the first grid, - A stack of dielectric layers above the coverage of the active area comprising at least a first dielectric layer electric and a second dielectric layer superimposed in a z direction perpendicular to the y direction, - A set of at least two interconnection lines passing along the z direction through the stack of dielectric layers and the cover of the active area up to, respectively, the first source and the first drain so as to form an electrical contact, respectively, with the first source and the first drain, each line of said set of interconnection lines comprising at least a first contact extending along the z direction through the first dielectric layer and the cover of the active area, and a first metal interconnection extending laterally in the second dielectric layer along the y direction, said first contact being in contact with a lower face of the first metal interconnection and with an upper face, respectively, of the first source and the first drain, - A passivation layer covering the stack of dielectric layers and the set of interconnection lines, • Form openings in the passivation layer by dry etching exposing the stack of dielectric layers, • Removing, through the openings, the materials of the stack of dielectric layers selectively with respect to the materials of the set of interconnection lines and of the cover of the active zone by an HF vapor phase etching, thus forming a cavity extending laterally in a direction x perpendicular to the directions y and z at least until the exposure of the walls of the set of interconnection lines opposite the first transistor, and in the direction z until the exposure of an upper face of the cover of the active zone.

[0009] A principle of the method according to the invention consists in etching the dielectric material by vapor phase HF. The dielectric material forming the stack of dielectric layers and the metallic material forming the set of interconnection lines are chosen so that one is etched selectively with respect to the other by vapor phase HF. This selectivity as well as the isotropic nature of vapor phase HF etching allow complete removal of the dielectric material and consequently, the substantial reduction of the capacitance C0FF independently of the resistance Ron of the transistor, in particular the reduction of the contribution of the parasitic capacitance induced by the volume of the area comprising the interconnections, to the total capacitance C0FF of the microelectronic device. While the state of the art reflects a constant prejudice according to which the creation of a cavity in the dielectric parts obeys lateral extension limits to avoid degradation of the metal connection elements, the process here proposes the use of a specific engraving offering great selectivity between the materials involved.

[0010] Another aspect of the invention relates to a microelectronic device, comprising: - A substrate and an active layer above the substrate, - At least a first transistor, comprising a first channel surmounted by a first gate, a first source and a first drain, the first channel, the first source and the first drain being in the active layer, the first gate extending laterally in the y direction above the active layer, the first transistor and the active layer forming an active zone, - A cover of the active area comprising at least one mechanical stress layer covering the active layer and the first grid, - A set of at least two interconnection lines crossing in the z direction the coverage of the active zone up to, respectively, the first source and the first drain so as to form an electrical contact, respectively, with the first source and the first drain, each line of said set of interconnection lines comprising at least a first contact extending in the z direction, and a first metal interconnection extending laterally in the y direction, said first contact being in contact with a lower face of the first metal interconnection and with an upper face, respectively, of the first source and the first drain, - A passivation layer covering the set of interconnection lines, - A cavity above the active zone, the device being characterized in that the cavity extends laterally in the x direction so as to expose walls of all the interconnection lines opposite the first transistor, and in the z direction so as to expose an upper face of the cover of the active zone.

[0011] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0012] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0013] [Fig.l] [Fig.l] schematically illustrates a top view in an xy plane of a RF switch made according to the present invention.

[0014] [Fig.2]

[0015] [Fig.3]

[0016] [Fig.4]

[0017] [Fig.5]

[0018] [Fig.6] Figures 2 to 6 schematically illustrate, along a transverse section in an xz plane, the different stages of manufacturing a cavity RF switch according to the present invention. A preferably orthonormal reference frame, comprising the x, y, z axes, is shown in these figures.

[0019] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not strictly representative of reality. DETAILED DESCRIPTION

[0020] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0021] According to one example, the cavity microelectronic device comprises at least a first transistor. Said first transistor comprises a first channel surmounted by a first gate extending laterally in a direction y, a first source and a first drain. Said method comprises the following steps: • Providing on a substrate: - An active area having an active layer comprising the first channel, the first source and the first drain of the first transistor, and the first gate above the active layer surmounting the first channel, - A cover of the active area comprising at least one mechanical stress layer covering the active layer and the first grid, - A stack of dielectric layers above the coverage of the active area comprising at least a first dielectric layer and a second dielectric layer superimposed in a z direction perpendicular to the y direction, - A set of at least two interconnection lines passing along the z direction through the stack of dielectric layers and the cover of the active area up to, respectively, the first source and the first drain so as to form an electrical contact, respectively, with the first source and the first drain, each line of said set of interconnection lines comprising at least a first contact extending in the z direction through the first dielectric layer and the cover of the active area, and a first metal interconnection extending laterally in the second dielectric layer in the y direction, said first contact being in contact with a lower face of the first metal interconnection and with an upper face, respectively, of the first source and the first drain, - A passivation layer covering the stack of dielectric layers and the set of interconnection lines, • Form openings in the passivation layer by dry etching exposing the stack of dielectric layers, • Removing through the openings the materials of the stack of dielectric layers selectively with respect to the materials of the set of interconnection lines and of the cover of the active zone by an HF vapor phase etching, thus forming a cavity extending laterally in an x ​​direction perpendicular to the y and z directions at least until the exposure of the walls of the set of interconnection lines opposite the first transistor, and in the z direction until the exposure of an upper face of the cover of the active zone.

[0022] According to one example, the method further comprises the following steps: • Before HF vapor phase etching, deposit a first barrier layer on the passivation layer, • Form openings in the first barrier layer in line with the openings in the passivation layer.

[0023] According to one example, the width of the first metal interconnections extends laterally in the x direction beyond the width of the first contacts, such that the HF vapor etched cavity further exposes at least the portion of the lower face of the first metal interconnections extending beyond the width of the first contacts.

[0024] According to one example, the materials of the stack of dielectric layers have a dielectric permittivity less than or equal to 2, and are preferably based on SiOx oxides.

[0025] According to one example, the materials of all the interconnection lines are based on metals such as aluminum, copper or tungsten coated with a layer of titanium nitride.

[0026] According to one example, the first metal interconnections are based on aluminum or copper.

[0027] According to one example, the first contacts are based on Tungsten (W) coated with a layer of Titanium Nitride (TiN).

[0028] According to one example, the materials of the stack of dielectric layers have a selectivity ratio SD:M greater than 100 compared to the materials of all the interconnection lines.

[0029] According to one example, the covering of the active area further comprises a second barrier layer covering the constraint layer.

[0030] According to one example, a passivation barrier layer is deposited across the openings in the cavity so as to cover at least an upper face of the mechanical stress layer and the exposed walls of the set of interconnect lines.

[0031] According to one example, the stack of dielectric layers further comprises a third dielectric layer and a fourth dielectric layer above the third dielectric layer, superimposed on the first dielectric layer and the second dielectric layer along the z direction.

[0032] According to one example, each line of the set of metal interconnection lines further comprises a via extending through the third dielectric layer in the z direction, and a second metal interconnection extending laterally in the fourth dielectric layer in the y direction, said via being in contact with an upper face of the first metal interconnection and a lower face of the second metal interconnection.

[0033] According to one example, the second metal interconnections are based on aluminum or copper.

[0034] According to one example, the vias are copper-based when the second metal interconnections are copper-based.

[0035] According to one example, the vias are based on Tungsten (W) coated with a layer of Titanium Nitride (TiN) when the second metal interconnections are based on aluminum.

[0036] According to one example, the first contacts of the set of interconnection lines are in the form of pillars.

[0037] According to one example, the microelectronic device further comprises at least one second transistor adjacent to the first transistor in the x direction, comprising a second channel surmounted by a second gate extending laterally in the y direction, a second source and a second drain.

[0038] According to one example, the cavity is filled with air or a gas having a dielectric permittivity of less than 2.

[0039] It is specified that, in the context of the present invention, the terms “on”, “overcomes”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposit or application of a first layer on a second layer, does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0040] A layer may also be composed of several sub-layers of the same material or of different materials.

[0041] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride SixNy may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0042] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator.

[0043] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0044] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0045] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0046] The term “selective etching with respect to” or “etching having selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0047] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0048] The relative terms “on”, “overcomes”, “under”, “underlying” refer to positions taken along the z direction. A “lateral” dimension corresponds to a dimension along a direction of the xy plane. A “lateral” or “laterally” extension means an extension along one or more directions of the xy plane.

[0049] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0050] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0051] The following description presents an example of implementation of the method according to the invention in a context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0052] [Fig.l] schematically illustrates a top view in an xy plane of an RF switch. Said RF switch represents an application of the manufacturing method detailed below. It comprises several MOS transistors ("Metal-Oxide-Semiconductor") Tl, T2, T3, arranged in parallel along an x ​​direction, and two levels of metal interconnects Ml, M2. The metal interconnects Ml, M2 are used to connect the sources and drains of transistors Tl, T2, T3 and to control the switching of transistors Tl, T2, T3. An RF switch having a comb configuration like the one illustrated in [Fig.l], further comprises two other metal levels M3, M4 not illustrated.

[0053] Figures 2 to 6 schematically illustrate the different steps of the manufacturing method of a cavity RF switch according to the present invention.

[0054] For the sake of simplification, Figures 2 to 6 represent a transverse section in an xz plane of a microelectronic device 100 at each step of the manufacturing process. The microelectronic device 100 does not correspond exactly to the device illustrated in [Fig.l] for reasons of simplification. Those skilled in the art will easily adapt Figures 2 to 6 to visualize the different steps of the manufacturing process of a device as illustrated in [Fig.l].

[0055] Each step of the method of manufacturing a cavity RF switch according to the present invention will be detailed below.

[0056] As illustrated in [Fig.2], a first step consists in providing a microelectronic device 100 manufactured by a method well known to those skilled in the art. The microelectronic device 100 comprises at least one, but preferably a plurality of MOS transistors 11a, 11b. Each transistor 11a, 11b respectively comprises a channel 12a, 12b, a source 13a, 13b, a drain 14a, 14b and a gate 15a, 15b. Each gate 15a, 15b is separated from the channel 12a, 12b respectively, by a thin dielectric layer not shown. This thin layer, referred to as a gate dielectric, is preferably based on a material preferably chosen from the materials: SiOx, SixOyNz or a hafnium oxide. An active layer 10 fabricated above a substrate S, comprises the channels 12a, 12b, the sources 13a, 13b and the drains 14a, 14b of the transistors 11a, 11b. Each gate 15a, 15b surmounts the channel 12a, 12b of the corresponding transistor 11a, 11b, and extends laterally above the active layer 10 in a direction y perpendicular to the direction x. Spacers 16 line the sides of the grids 15a, 15b, forming a continuous ring in an xy plane around each grid 15a, 15b, with a closed contour.The active layer 10 and the gates 15a, 15b of the transistors 11a, 11b are included in an active zone of the microelectronic device 100 called FEOL (“Front-End-Of-Line” in English, or start of line).

[0057] The substrate S may be an SOI (Silicon-on-Insulator) type substrate. These known substrates comprise, according to the terminology commonly used by those skilled in the art, a carrier silicon substrate "Si bulk" (or solid silicon) and a layer of silicon oxide called "BOX" (Buried Oxide, or buried oxide). MOS transistors on SOI substrates are particularly well suited to the RF switching function because they benefit from insulation by the buried oxide. This insulation makes it possible to attenuate the effects of parasitic propagation of the RF signal (crosstalk) by the substrate S.

[0058] The microelectronic device 100 further comprises a cover 3 of the active zone comprising at least one mechanical stress layer 70, covering the active layer 10, the spacers 16 and the gates 15a, 15b. The cover 3 of the active zone may further comprise a siliciding layer, not illustrated, below the mechanical stress layer 70. The siliciding layer covers the active layer 10, the spacers 16 and the gates 15a, 15b. It is preferably based on cobalt silicide (CoSi2), nickel silicide (eg, NiSi) or an equivalent alloy.The mechanical stress layer 70 known by the English term CESL (Contact Etch-Stop Layer), commonly used as a barrier during an etching process, further serves to increase the mobility of the carriers (electrons or holes) in the channels 12a, 12b of the transistors 11a, 11b by applying a mechanical stress which modifies the mesh size of the crystal lattice of the channel 12a, 12b. The mechanical stress layer 70 is preferably based on SiyNz nitrides. The cover 3 of the active zone may comprise a plurality of layers.

[0059] The microelectronic device 100 further comprises a zone called BEOL (Back-End-Of-Line), comprising a stack of dielectric layers 1 superimposed with the cover 3 of the active zone in a direction z perpendicular to the xy plane, and a set of interconnection lines 2 crossing in the z direction the stack of dielectric layers 1 and the cover 3 of the active zone up to the sources 13a, 13b and drains 14a, 14b.

[0060] The interconnection lines 2 form electrical contacts with the sources 13a, 13b and the drains 14a, 14b respectively, and each comprise at least two levels of metal interconnections M1, M2 alternating with a first contact 31 and a via 32. The metal interconnections M1, M2 are based on metal materials M, preferably based on aluminum (Al) or copper (Cu).

[0061] The stack of dielectric layers 1 comprises an alternation of dielectric layers 41, 42 alternating with dielectric layers 51, 52 in the z direction. The metal interconnections M1, M2 extend laterally in the y direction through the dielectric layers 51, 52, respectively. The dielectric layers 41, 42 and the dielectric layers 51, 52 are based on dielectric materials D, preferably based on SiOx oxides. These materials are characterized by relative dielectric permittivities e>- typically of the order of 4. The dielectric materials of the stack of dielectric layers 1 are intended to be replaced by another material with a dielectric permittivity er < 2, such as air for example 1).This replacement can be achieved by selectively removing the materials of the dielectric layer stack 1 with respect to the metallic materials of the set of interconnect lines 2 by a vapor phase HF etching step. Generally, the materials of the dielectric layer stack 1 and the metallic materials of the set of interconnect lines 2 are chosen so that one can be selectively etched with respect to the other by vapor phase HF. In the case of SiOx and aluminum for example, the selectivity ratio SSiOx:Ai is greater than 100.

[0062] The first contacts 31 are in the form of pillars which extend in the z direction through the first dielectric layer 41 and the cover 3 of the active zone. The first contacts 31 are in contact with lower faces of the first metal interconnections M1 and in contact with upper faces of the sources 13a, 13b and the drains 14a, 14b respectively. The first contacts 31 are based on a metallic material M, preferably based on Tungsten (W) coated with a layer of Titanium nitride (TiN).

[0063] The vias 32 are cylindrical in shape, filled with a metallic material M, preferably copper-based when the second metallic interconnections M2 are copper-based, or tungsten (W)-based coated with a layer of titanium nitride (TiN) when the second metallic interconnections M2 are aluminum-based.

[0064] The vias 32 extend through the third dielectric layer 42 in the z direction. The vias 32 are in contact with upper faces of the first inter metal connections Ml and lower faces of the second metal interconnections M2.

[0065] The first metal interconnections M1 and the second metal interconnections M2 may have the same width along the x direction, or different widths. The first contacts 31 and the vias 32 may also have the same width or different widths along the x direction. Furthermore, the width of the first metal interconnections M1 and the second metal interconnections M2 extends laterally along the x direction beyond the width of the first contacts 31 and the vias 32.

[0066] The microelectronic device 100 further comprises a passivation layer 60, covering the stack of dielectric layers 1 and the set of interconnection lines 2. The passivation layer 60 is preferably based on oxide (SiO x) and SiyNz nitrides. A first thin and conformal barrier layer 80 is advantageously deposited on the passivation layer 60, and serves to protect the surface of the microelectronic device 100 during the vapor phase HF etching step. The first barrier layer 80 has a thickness preferably between 10 nm and 150 nm, and is based on a material preferably chosen from dielectric materials: A12O3, AIN or Si-rich SiNx. A layer of A12O3 for example, having a thickness between 40 nm and 150 nm constitutes an effective barrier to the diffusion of HF in the vapor phase.The first barrier layer 80 is preferably produced by atomic layer deposition (ALD)•.

[0067] As illustrated in [Fig. 3], openings 101 are then made through the passivation layer 60 and the first barrier layer 80 by dry etching. The openings 101 are preferably made in two stages. First openings 101 in the passivation layer 60 are defined by a first dry etching in a first stage before the deposition of the first barrier layer 80. Second openings are then defined by a second dry etching in the first barrier layer 80 in line with the openings 101 of the passivation layer 60 in a second stage, following the deposition of the first barrier layer 80. The openings 101 passing through the passivation layer 60 and the first barrier layer 80 can furthermore be made in a single stage by dry etching.

[0068] As illustrated in [Fig. 4], the dielectric material D of the stack of dielectric layers 1 is then selectively removed through the openings 101 by HF vapor phase etching, with respect to the materials M of the set of interconnection lines 2, and with respect to the materials of the cover 3 of the active zone, of the passivation layer 60 and of the first barrier layer 80, thus creating cavities 20 above the transistors 11a, 11b. The HF vapor phase etching being isotropic and selective to the dielectric material D of the stack of dielectric layers 1, allows the cavities 20 to extend laterally in the x direction at least until the exposure of the walls of all the interconnection lines 2 opposite the first transistor 11a as well as the part of the width of the metal interconnections M1, M2 extending beyond the width of the first contacts 31 and the vias 32. The cavities 20 also extend in the z direction until the exposure of an upper face of the cover 3 of the active zone. The removal of the dielectric material D from the stack of dielectric layers 1 until the exposure of the walls of all the interconnection lines 2, allows the reduction of the capacitance Coff independently of the resistance R0N of the transistors 11a, 11b, in particular the reduction of the contribution of the capacitance of the BEOL zone to the total capacitance COff of the microelectronic device 100.

[0069] Following the vapor phase HF etching, the upper face of the cover 3 of the active area is exposed to the air present within the cavities 20, which can alter the properties of the FEOL active area of ​​the microelectronic device 100 in the event of the presence of humidity in the air filling the cavities 20. To overcome this problem, two embodiments of the present invention are possible. The two embodiments are illustrated schematically in [Fig.5] and [Fig.6] respectively.

[0070] As illustrated in [Fig.5], according to the first embodiment of the present invention, the cover 3 of the active zone further comprises a second barrier layer 90 covering the mechanical stress layer 70. This second barrier layer 90 is deposited on the mechanical stress layer 70 during the manufacture of the microelectronic device 100, before the production of the stack of dielectric layers 1 and prior to the formation of the cavities 20. The second barrier layer 90 is based on a material preferably chosen from the dielectric materials: Al2O3, AlN or Si-rich SiNx. The second barrier layer 90 serves to protect the active zone FEOL of the microelectronic device 100 in order to prevent any penetration of moisture or other elements that could alter or degrade the properties of the transistors 11a, 11b.In addition, the choice of a material with high thermal conductivity such as AlN for example, allows the second barrier layer 90 to direct the heat flows in the active FEOL zone towards the set of interconnection lines 2. According to another variant of the present invention, the second barrier layer 90 can be deposited between two dielectric layers in the BEOL zone of the microelectronic device 100.

[0071] As illustrated in [Fig.6], according to the second embodiment of the present invention, following the formation of the cavities 20, a passivation barrier layer 95 is deposited through the openings 101 in the cavities 20. The passivation barrier layer 95 serves to cover in particular the upper face of the cover 3 of the zone active as well as the exposed parts of the set of interconnection lines 2 and the sides of the openings 101. The passivation barrier layer 95 is based on a material preferably chosen from dielectric materials: Al2O3, AlN or Si-rich SiNx. The passivation barrier layer 95 may further be based on the same material as that of the first barrier layer 80 so as to form a continuous layer with the first barrier layer 80. The passivation barrier layer 95 serves to protect the active FEOL zone of the microelectronic device 100 in order to prevent any penetration of humidity or other elements which could alter or degrade the properties of the transistors 11a, 11b. The passivation barrier layer 95 also serves to protect the set of interconnection lines 2.

[0072] An advantageous variant can be implemented by simultaneously combining the two embodiments of the present invention detailed above.

[0073] In view of the foregoing description, it is clear that the proposed method offers a particularly effective solution for removing dielectric materials from the BEOL zone of an RF switch. This solution is furthermore advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

Claims

Claims

1. Method for manufacturing a microelectronic device (100) with a cavity (20) comprising at least a first transistor (11a), said first transistor (11a) comprising a first channel (12a) surmounted by a first gate (15a) extending laterally in a direction y, a first source (13a) and a first drain (14a), said method comprising the following steps: • Provide on a substrate (S): An active area having an active layer (10) comprising the first channel (12a), the first source (13a) and the first drain (14a) of the first transistor (11a), and the first gate (15a) above the active layer (10) surmounting the first channel (11a), A cover (3) of the active area comprising at least one mechanical stress layer (70) covering the active layer (10) and the first grid (15a), A stack of dielectric layers (1) above the cover (3) of the active zone comprising at least a first dielectric layer (41) and a second dielectric layer (51) superimposed in a z direction perpendicular to the y direction, A set of at least two interconnection lines (2) passing along the z direction through the stack of dielectric layers (1) and the cover (3) of the active area up to, respectively, the first source (13a) and the first drain (13b) so as to form an electrical contact, respectively, with the first source (13a) and the first drain (14a), each line of said set of interconnection lines (2) comprising at least a first contact (31) extending along the z direction through the first dielectric layer (41) and the cover (3) of the active area, and a first metal interconnection (Ml) extending laterally in the second dielectric layer (51) along the y direction, said first contact (31) being in contact with a lower face of the first metal interconnection (Ml) and with a upper face, respectively, of the first source (13a) and of the first drain (14a), - A passivation layer (60) covering the stack of dielectric layers (1) and the set of interconnection lines (2), • Forming in the passivation layer (60) openings (101) by dry etching exposing the stack of dielectric layers (1), • Removing through the openings (101) the materials of the stack of dielectric layers (1) selectively with respect to the materials of the set of interconnection lines (2) and of the cover (3) of the active zone by an HF vapor phase etching, thus forming a cavity (20) extending laterally in a direction x perpendicular to the directions y and z at least until the exposure of the walls of the set of interconnection lines (2) opposite the first transistor (11a), and in the direction z until the exposure of an upper face of the coverage (3) of the active area.

2. Method for manufacturing a microelectronic device (100) according to the preceding claim, further comprising the following steps: • Before the vapor phase HF etching, depositing a first barrier layer (80) on the passivation layer (60), • Forming in the first barrier layer (80) openings in line with the openings (101) of the passivation layer (60).

3. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the width of the first metal interconnections (Ml) extends laterally in the x direction beyond the width of the first contacts (31), such that the cavity (20) etched by HF in the vapor phase further exposes at least the portion of the lower face of the first metal interconnections (Ml) extending beyond the width of the first contacts (31).

4. Method of manufacturing a microelectronic device (100) according to any one of the preceding claims, in which the materials of the stack of dielectric layers (1) have a dielectric permittivity less than or equal to 2, and are preferably based on SiOx oxides.

5. Method of manufacturing a microelectronic device (100) according to any one of the preceding claims, in which the materials of the set of interconnection lines (2) are based on metals such as aluminum, copper or tungsten coated with a layer of titanium nitride.

6. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the materials of the stack of dielectric layers (1) have a selectivity ratio SD:m greater than 100 relative to the materials of all the interconnection lines (2).

7. A method of manufacturing a microelectronic device (100) according to any preceding claim, wherein the cover (3) of the active area further comprises a second barrier layer (90) covering the mechanical stress layer (70).

8. A method of manufacturing a microelectronic device (100) according to any one of claims 1 to 6, wherein a passivation barrier layer (95) is deposited through the openings (101) in the cavity (20) so as to cover at least an upper face of the mechanical stress layer (70) and the exposed walls of the set of interconnect lines (2).

9. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the stack of dielectric layers (1) further comprises a third dielectric layer (42) and a fourth dielectric layer (52) above the third dielectric layer (42), superimposed with the first dielectric layer (41) and the second dielectric layer (51) along the z direction.

10. A method of manufacturing a microelectronic device (100) according to the preceding claim, wherein each line of the set of metal interconnection lines (2) further comprises a via (32) extending through the third dielectric layer (42) in the z direction, and a second metal interconnection (M2) extending laterally in the fourth dielectric layer (52) along the y direction, said via (32) being in contact with an upper face of the first metal interconnection (M1) and a lower face of the second metal interconnection (M2).

11. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the first contacts (31) of the set of interconnection lines (2) are pillar-shaped.

12. A method of manufacturing a microelectronic device (100) according to any one of the preceding claims, wherein the microelectronic device (100) further comprises at least one second transistor (11b) adjacent to the first transistor (11a) in the x direction, comprising a second channel (12b) surmounted by a second gate (15b) extending laterally in the y direction, a second source (13b) and a second drain (14b).

13. Microelectronic device (100), comprising: - A substrate (S) and an active layer (10) above the substrate (S), - At least one first transistor (11a), comprising a first channel (12a) surmounted by a first gate (15a), a first source (13a) and a first drain (14a), the first channel (12a), the first source (13a) and the first drain (14a) being in the active layer (10), the first gate (15a) extending laterally in the y direction above the active layer (10), the first transistor (11a) and the active layer (10) forming an active area, - A cover (3) of the active area comprising at least one mechanical stress layer (70) covering the active layer (10) and the first gate (15a), - A set of at least two interconnection lines (2) crossing in the z direction, the cover (3) of the active area up to, respectively,the first source (13a) and the first drain (13b) so as to form an electrical contact, respectively, with the first source (13a) and the first drain (14a), each line of said set of interconnection lines (2) comprising at least a first contact (31) extending in the z direction, and a first inter-, metallic connection (Ml) extending laterally in the y direction, said first contact (31) being in contact with a lower face of the first metallic interconnection (Ml) and with an upper face, respectively, of the first source (13a) and of the first drain (14a), - A passivation layer (60) covering the set of interconnection lines (2), - A cavity (20) above the active zone, the device (100) being characterized in that the cavity (20) extends laterally in the x direction so as to expose walls of the set of interconnection lines (2) opposite the first transistor (11a), and in the z direction so as to expose an upper face of the cover (3) of the active zone.

14. A microelectronic device (100) according to the preceding claim, wherein the width of the first metal interconnections (Ml) extends laterally in the x direction beyond the width of the first contacts (31), and the cavity (20) further exposes at least the portion of the lower face of the first metal interconnections (Ml) extending beyond the width of the first contacts (31).

15. A microelectronic device (100) according to any one of claims 13 and 14, wherein the cavity (20) is filled with air or a gas having a dielectric permittivity of less than 2.

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