IMPROVED SRAM MEMORY INITIALIZATION MANAGEMENT DEVICE

Abstract

A control unit (100, 200) of an SRAM memory to trigger an initialization, selected from various possible distinct initialization types, of at least one given group of SRAM memory cells of said SRAM memory, said control unit being configured to adopt a "locked" operating mode, in which it triggers an initialization of the given group of cells according to a "default" initialization type corresponding to a first initialization type among said different distinct initialization types or an erasure, and maintains at output (OM1) said "hard masking" control signal (Z', R') in the same given state until a particular signal sequence called "unlocking" is received on said hard masking inputs (HM1, HM2), the control unit being further configured to,Following the reception of said particular signal sequence known as the "unlock" signal, the given group can be initialized according to different types of initialization, which may be distinct from the default initialization. See Figure 1 for an abbreviation.

Description

Title of the invention: IMPROVED SRAM MEMORY INITIALIZATION MANAGEMENT DEVICE technical field

[0001] The present invention relates to the field of memories, and in particular of the SRAM type (SRAM for "Static Random Access Memory"), and more precisely concerns that of the initialization of SRAM memories.

[0002] The present invention implements an improved device for managing the selection of an initialization type from among several possible initialization types of a group of memory cells when this group of cells is powered up and of particular operating modes such as a secure operating mode or of particular events such as detection of fraudulent access to the memory. STATE OF THE PRIOR ART

[0003] There are a limited number of techniques for initializing an SRAM memory.

[0004] A known type of initialization is the so-called "free" initialization, which consists of an unconstrained switching on of a plane of memory cells. With a free initialization, the state in which each cell is initialized is established freely. In particular, during an unconstrained switching on of a Uth chip among a very large number Np ~ 10,000 of chips produced, the cell of the i-th column and the j-th row has a probability pijk of initializing to a logic level '1' and a probability l-pijk of initializing to a logic level '0'. Over a large number ~ 100 unconstrained initializations, the average of the initialization values ​​of the cell of the i-th column and the j-th row in a memory plane of the k-th chip will tend towards this probability value piJk.It turns out that this probability value changes from one cell to another and between one chip and another, in such a way that on a set of cells of different chips we will have a p statistic which depends in particular on the local variability of its manufacturing process and more globally on PT conditions (“Process”, “Temperature”, i.e. manufacturing process, temperature) in other words on local and global variations of the manufacturing process, of the scanning speed VSR. ("slew-rate" in Anglo-Saxon terminology expressed in Volt / seconds) of the supply voltage level used, and the operating temperature.

[0005] With such an initialization technique, the initialization state of the memory or of certain memory cells is thus likely to constitute a digital fingerprint or signature. For a fixed k, these are in particular the cells with a high probability of switching and initializing to a given logic level (piJk equal to or very high). close to 1 for cells with a strong tendency to initialize to '1'; etpijk equal to or very close to 0 for cells with a strong tendency to initialize to '0') which can be used to form this digital fingerprint of the k-th chip.

[0006] One disadvantage of free initialization may be that, in the event of malicious intrusion after such initialization, a third-party device may possibly recover this digital fingerprint or signature.

[0007] Another initialization technique, known as "deterministic," consists of writing, address by address, predetermined content that may have been previously defined by the user or the memory designer. Among deterministic initialization techniques are the "set to 0" type, in which the state of each memory cell is forced to a logical value of '0', and the "set to 1" type, in which the state of each memory cell is forced to a logical value of '1'. Implementing this type of initialization comes at the cost of time spent rewriting a number of memory locations at different addresses, increased power consumption, and the risk of information leakage related to this rewriting process or maliciously performed during this lengthy operation.

[0008] There is therefore a need to be able to manage different types of initialization and to be able to initialize a set of memory cells according to an initialization type selected from several distinct initialization types.

[0009] Furthermore, PMOS type transistors used in SRAM cells undergo a physical phenomenon called NBTI (in English "Negative-Bias Temperature In-stability", i.e. "Negative bias temperature instability") which has the effect of increasing their threshold voltage, this all the more so when their dimensions (length and gate width) are reduced. This phenomenon is also accelerated when the temperature and / or the negative voltage VGS applied between the gate and the source of the transistor increase. An SRAM memory cell is commonly equipped with two inverters connected in a head-to-tail crossed manner, each being formed in particular of a first P-type transistor and a second N-type transistor.

[0010] The value stored in an SRAM memory cell will influence the PMOS transistors of the same memory cell differently and the VTP1 / VTP2 ratio of the respective threshold voltages of the two PMOS transistors will change over time in one direction or the other depending on the stored value.

[0011] Thus, the NBTI phenomenon influences the probability of an SRAM cell to spontaneously initialize upon power-up to logic level '1' or its opposite level '0', since the initialization logic level is linked to the VTP1 / VTP2 ratio.

[0012] However, memory data from the initialization of SRAM cells can be used to generate encryption keys or a hardware identifier or a unique digital fingerprint. They can be used to create a Physical Unclonable Function (PUF).

[0013] Certain cells having a high VTP1 / VTP2 ratio can in particular be identified as cells that are sufficiently stable to be used to constitute a PUF function during a so-called enrollment phase. However, due to the effects of the aforementioned NBTI phenomenon, the VTP1 / VTP2 ratio may be modified over time, which makes the cells less suitable for their use to constitute a PUF, one of the prerequisites of which is long-term temporal stability.

[0014] A problem related to the effects of NBTI and which influences data security is the so-called "data imprint effect". Such an effect is described in the document: “Challenging On-Chip SRAM Security with Boot-State Statistics", by J. McMahan et al., HOST 2017. When data stored in memory remains there for a long time (with a memory in operation, under power supply), the threshold voltage VTP of the PMOS transistor on changes, due to the same physical effect which causes NBTI. A harmful remanence effect or "data imprint" then makes it possible to retrieve data which has been previously stored even when the memory is reset.

[0015] Techniques such as "power analysis" (known as "CPA" or "DPA" according to the English acronyms "correlated Power analysis" or "differential power analysis") can be used to reveal data intended to remain secret, based among other things on this phenomenon of drift of the threshold voltage of the transistors by using means to accelerate this drift. Such a technique is described for example in the document: "Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications", by R. Giterman et al., ESSCIRC 2019.

[0016] There is also a need to find a control device designed to manage different types of initialization of a memory and which makes it possible to improve the operation of the memory with respect to the effects of NBTI. Statement of the invention

[0017] According to one aspect, the present application relates to a control unit for an SRAM memory capable of triggering an initialization, selected from different possible distinct initialization types, of at least one given group of SRAM memory cells of said SRAM memory, said control unit comprising:

[0018] - a first so-called "hard masking" input, capable of receiving a so-called "hard masking" signal, detection”,

[0019] - a second input called "hard masking", capable of receiving a signal called "activation",

[0020] - one or more so-called "soft masking" inputs capable of receiving signals initialization indicators according to different distinct initialization types,

[0021] said control unit being configured to adopt a so-called “locked” operating mode, in which following a power-up of the memory and whatever the value of signals emitted on the first input and the second hard masking input and on the soft masking inputs, or following the reception of a so-called “locking” sequence on said first hard masking input,

[0022] said control unit produces at output a control signal capable of triggering an initialization of said given group of cells according to a so-called “default” initialization type corresponding to a first type of initialization among said different distinct initialization types or an erasure, and maintains at output said control signal in the same given state as long as a particular signal sequence called “unlocking” is not received on said hard masking inputs,

[0023] said control unit being further configured to, following the reception of said particular signal sequence called "unlock" on said hard masking inputs, adopt at least one other operating mode in which, in the absence of new signals or change of signal state on said hard masking inputs, when said control unit receives an initialization indicator signal of the first type of initialization, produce as output an initialization control signal of the first type to trigger an initialization of the memory cells of said given group of cells according to said first type of initialization and when the control unit receives an initialization indicator signal of the second type of initialization,outputting an initialization control signal of a second type to trigger an initialization of the memory cells of said given group of cells according to said second initialization type.

[0024] Advantageously, the detection signal may come from a module for detecting fraudulent access to said SRAM memory, said locking sequence on said first hard masking input corresponding to a change of state of said detection signal.

[0025] According to one possible implementation, the unlocking sequence may consist, in this order, of a given logic state or a change of logic state of said detection signal on said first hard masking input to said given logic state then, a change of the activation signal on said second hard masking input.

[0026] In said at least one other operating mode, the control unit can be further configured to, following the receipt of said activation signal on the second "hard masking" input and in the absence of a change of state of the detection signal on the first "hard masking" input, emit an initialization control signal of the first type to trigger an initialization of the memory cells of said given group according to said first type of initialization.

[0027] According to one possible implementation, the control unit may be provided with: an asynchronous flip-flop logic module having a so-called "control" input coupled to the first hard masking input and another so-called "control" input coupled to the second hard masking input, said logic module being configured to, following a power-up or the reception of said locking sequence, maintain at output a first logic state as long as said logic module does not receive said unlocking sequence and to, following the reception of said unlocking sequence, produce at output a second logic state complementary to said first logic state.

[0028] The control unit may further comprise a logic gate stage coupled to an output of said logic module and to said soft masking inputs, said logic gate stage being provided with:

[0029] - of at least one first logic gate implementing a given logic function, in particular performing an OR function between a first soft masking input and the complement of an output of said logic module, an output of the first logic gate being coupled to a first output of the control unit provided for delivering the initialization control signal of the first type,

[0030] - of at least a second logic gate performing a distinct logic function of the given logic function, in particular an AND function between a second input of said plurality of "soft masking" inputs and the output of said logic module being coupled to a second output of the control unit provided for delivering the initialization control signal of the second type.

[0031] According to one possible implementation of the control unit, the asynchronous flip-flop logic module may be provided with an asymmetrical asynchronous flip-flop such as an asymmetrical RS flip-flop.

[0032] Advantageously, said asynchronous flip-flop may be formed of a first set of transistors performing a given logic function, in particular a NOR function or a NAND function, and a second set of transistors performing said same given logic function, said asynchronous flip-flop being asymmetrical so that said first set of transistors is provided with at least a first group of transistors having an arrangement similar to that of a second group of transistors of said second set of transistors, the transistors of the first group being provided with a threshold voltage different from that of the transistors of said second group.

[0033] According to one possible embodiment of the control unit, among said soft masking inputs there may be:

[0034] - a first soft masking input is adapted to receive an indicator signal initialization of a first type of initialization,

[0035] - a second soft masking input, capable of receiving an indicator signal initializing a second type of initialization among said different types of initialization, the second type of initialization being distinct from said first type of initialization and said second type of initialization,

[0036] - a third soft masking input, capable of receiving an indicator signal initializing a third type of initialization among said different types of initialization, the third type of initialization being distinct from said first type of initialization and said second type of initialization,

[0037] wherein in said at least one other mode of operation when the third soft masking input receives an initialization indicator signal of the third initialization type, the control unit produces as output an initialization control signal of a third type to trigger an initialization of the memory cells of said given group of cells according to said third initialization type.

[0038] According to one possible implementation, the first initialization type and the second initialization type are distinct initialization types among:

[0039] - an initialization of the “set to 1” or “set to 0” type consisting of setting all the cells of said group to the same logical state,

[0040] - a “random” type initialization consisting of imposing on each column of cells of said group the same given logical state randomly selected between a first logical state and a second logical state,

[0041] - a “free” type initialization consisting of putting the internal nodes of each cell of said group at the same potential and then let these internal nodes respectively charge or discharge in order to let the cell freely establish itself at a given logical state.

[0042] In the locked operating mode, maintaining the output of said control signal in the same given state is capable of maintaining said given group of cells in an indeterminate state called “metastable” for which their respective first storage node and their respective second storage node are set to equal or substantially equal potentials.

[0043] According to another aspect, the present application relates to a static random access memory device comprising:

[0044] - a set of SRAM cells comprising said given group of SRAM cells,

[0045] - at least one first control unit as defined previously, for initialize said given group of said set of SRAM cells.

[0046] Advantageously, the static random access memory device may further include: a second control unit, for controlling the initialization, according to different possible distinct initialization types, of the memory cells of a second group of cells of said set of SRAM memory cells distinct from said given group.

[0047] Advantageously, the given group of cells may contain a non-clonable physical function (PUF), while the second group of cells corresponds to sensitive data storage cells or to freely accessible cells.

[0048] According to one possible implementation of the static random access memory device, the second control unit may be configured to, following each power-up of the memory or following the reception of a locking signal, produce as output an initialization control signal to trigger an initialization of said second group of cells according to a default initialization type among said different distinct initialization types, the default initialization type of the second control unit being different from the default initialization type of the first control unit and selected from:

[0049] - an initialization of the “set to 1” or “set to 0” type consisting of setting all the cells of said group to the same logical state,

[0050] - a “random deterministic” type initialization consisting of imposing on each column of cells of said group the same given logical state selected by random drawing between a first logical state and a second logical state,

[0051] - a “free” type initialization consisting of putting the internal nodes of each cell of said group at the same potential and then let these internal nodes respectively charge or discharge in order to let the cell freely establish itself at a given logical state.

[0052] Advantageously, the default initialization type of the first control unit can be a "set to 1" or "set to 0" type initialization consisting of putting all the cells of said group into the same logical state, the default initialization type of the second control unit being a "random deterministic" type initialization consisting of imposing on each column of cells of said group the same given logical state selected randomly between a first logical state and a second logical state. Brief description of the drawings

[0053] The present invention will be better understood upon reading the description of exemplary embodiments given, purely for informational purposes and in no way limiting, by making reference to the attached drawings in which:

[0054] [Fig.l] gives an example of embodiment of a control unit in an SRAM memory capable of triggering an initialization of at least a first group of cells of an SRAM memory, according to a type of initialization selected from several possible types of initialization.

[0055] [Fig.2] gives an example of a truth table to illustrate the operation of the control unit according to [Fig.l].

[0056] [Fig.3] serves to illustrate different operating modes of an example of a so-called “locking” logic module integrated into a control unit as implemented according to the invention.

[0057] [Fig.4] serves to illustrate an example of the structure of the logic module called "to be verified" rusting” and equipped in particular with an asynchronous and asymmetric rocker switch.

[0058] [Fig.5] gives an example of an asynchronous and asymmetric flip-flop that can be provided in a "latching" logic module.

[0059] [Fig.6] serves to illustrate a second control unit intended to trigger an initialization of a second group of cells of an SRAM memory distinct from the group of cells with which the control unit of [Fig.l] is associated.

[0060] [Fig.7] is used to illustrate different areas of an SRAM memory plane and associated each has a control unit.

[0061] [Fig.8] gives an example of a conventional SRAM memory cell structure.

[0062] [Fig.9] gives an example of initialization management using a timing diagram for different areas of a cell matrix and according to different operating modes, normal or safe.

[0063] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0064] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0065] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0066] An exemplary embodiment of a control unit 100 configured to trigger an initialization of at least one given group of SRAM cells of an SRAM memory is shown schematically in [Fig.l].

[0067] This control unit 100 is capable of triggering different distinct initialization types and makes it possible to trigger an initialization of said at least one given group of cells according to an initialization type selected from different distinct initialization types.

[0068] This initialization control unit 100 makes it possible, after powering up the memory or in a particular operating mode linked for example to a detection of an attempted intrusion, to implement an initialization according to a type so-called "default" initialization among the different types of initialization or an erasure of the given group of cells.

[0069] This initialization control unit 100 also makes it possible to trigger sequences of several successive initializations, each according to a type of initialization which may be different from the previous one, in particular to avoid data imprint phenomena.

[0070] The initialization control unit 100 here comprises a first input HM1 called “hard masking” for receiving a first logic signal TAMPER_FLAG called “detection”. This detection signal TAMPER_FLAG may be for example a signal indicating an attempt at fraudulent access to the memory and may in particular come from an intrusion detection module 11. Such a fraudulent access detection module 11 may be provided with functions similar to those of a TAMP module present in an STM32GO microcontroller marketed by the company STMicroelectronics and described in the notice “STM32GO - TAMP, tamper and back-up registers, revision 1.0”.

[0071] The TAMPER_FLAG detection signal is transmitted asynchronously and may be such that, for example, a high state (or a logic '1') indicates an attempt to access the memory fraudulently.

[0072] The initialization control unit 100 also includes a second HM2 input, referred to as a "hard masking" input, for receiving a second logic signal, referred to as an "activation" signal. This activation signal, PDM_ENABLE, can originate from a memory circuit block 21 forming a Finite State Machine (FSM), typically implemented using a programmable logic device. Such a device may be equipped with at least one register for storing state variables as well as combinational logic blocks. Changes in the PDM_ENABLE activation signal can depend on different operating modes, for example, a normal mode and a secure mode, also called "crypto," in which a group of memory cells may be placed.

[0073] The control unit 100 includes a first SMI input called "soft masking", intended for receiving a logic signal Z indicating a first type of initialization, in this example of the "reset to 0" type of memory cells.

[0074] A second SM2 soft masking input is provided for receiving a logic signal F indicating a second type of initialization, here corresponding to a so-called "free" initialization of memory cells.

[0075] A third SM3 soft masking input can also be provided for receiving a logic signal R indicating a third type of initialization, here corresponding to a so-called "random" initialization (and which can also be called "deterministic random" or "random by column") of memory cells.

[0076] In this exemplary embodiment, a fourth soft masking input SM4 is also provided for receiving a logic signal O indicating a fourth type of initialization in this example of the “setting to 1” type of the memory cells.

[0077] The indicator signals O, F, R, Z emitted respectively on the inputs SMI, SM2, SM3, SM4 can all come from the state machine 21 producing the activation signal PDM_ENABLE.

[0078] The control unit 100 here consists of an asynchronous flip-flop logic module 110 having a LOCK input connected to the first hard-masking input HM1 and another HANDLE input connected to the second hard-masking input HM2. This logic module 110 outputs a logic OUT signal, the state of which is transmitted to a logic stage 150. In this example, the inputs of module 110 are directly connected to the hard-masking inputs HM1 and HM2, respectively.

[0079] Stage 150 is itself coupled to the soft masking inputs SMI, SM2, SM3, SM4 and produces, as a function of the value of the output signal OUT of the module 110 and the values ​​of the signals F, R, O, Z, each indicating a type of initialization, one or more initialization control signals F', R', O', Z' making it possible to trigger different types of initialization intended for at least one initialization circuit.

[0080] This initialization circuit (not shown in this figure) is itself configured to initialize said at least one given group of memory cells, according to different distinct initialization types depending on the initialization control signals F', R', O', Z' received.

[0081] In the particular embodiment illustrated, the logic stage 150 is formed of a set of logic gates 152, 154, 156, 158.

[0082] A logic gate 158 of said set of logic gates here performs an OR function between the first soft masking input SMI and the complement of the output OUT of the module 110 to produce at a first output OMI of the control unit 100 a control signal Z' called "hard masking" or first initialization control signal making it possible to trigger an initialization of cells according to the initialization type called "setting to 0".

[0083] An initialization circuit of the type described in application No. 2111286, in particular in connection with its [Fig. 4], can be triggered by the signal Z' in order to allow all the memory cells to be written to "0" and thus implement an initialization of the "set to 0" type.

[0084] A second initialization control signal F', of another initialization type than the control signal Z', is capable of being produced on a second output OM2 of the control unit 100 and in particular by means of a logic gate 152 of the stage 150. This gate 152 performs in this example a logic function different from that of the gate 158, here an AND function, between the second input SM2 of soft masking and the output OUT of the module 110. The initialization control signal F' is here provided to trigger an initialization of said group of cells according to a “free” type initialization.

[0085] Reference may be made to a French patent application No. 2111286 filed by the applicant on October 25, 2021 before the National Institute which describes an SRAM memory initialization circuit, configured to implement a free-type initialization. This type of “free” initialization consists of letting each memory cell initialize to a specific value during the progressive power-up of the elements constituting the memory cell, in particular two looped inverters as illustrated in [Fig. 8], without seeking to impose a value “0” or “1” on the internal nodes NT and NF of the cell. In the free initialization mode, the access transistors TAt and TAF are non-conducting, the cell being as if “isolated” from the other cells and the bit lines BLT and BLF.

[0086] A third initialization control signal R', in this example of a "random" type of cells, is likely to be produced on a third output OM3 of the control unit 100 by a logic gate 154 of the stage 150 performing here an AND function, between the soft masking input SM3 and the output OUT of the module 110. The third initialization control signal is here intended to trigger an initialization of said group of cells according to an initialization of the "random" type.

[0087] In another French patent application No. 2213917 filed by the applicant on December 20, 2022, with the French National Institute of Industrial Property (INPI), an initialization circuit for implementing random initialization is described. It allows a value to be assigned to all or part of the cells in the same column; this value having been previously defined by a random selection process. The term "random" initialization is used for this type of initialization, which proceeds in two stages: random selection followed by forced initialization. For this type of initialization, it is possible, for example, to have all the cells in one column set to a state corresponding to a logical "0" and all the cells in a second column set to a state corresponding to a logical "1", the respective states of these columns being the result of random selections.

[0088] A fourth initialization control signal O', in this example of the "set to '1'" type for the cells, is likely to be produced on a fourth output OM4 of the control unit 100 by a logic gate 156 of the stage 150 performing here an AND function, between the soft masking input SM4 and the output OUT of the module 110. The fourth initialization control signal is intended here to trigger an initialization of said group of cells according to an initialization of the "set to '1'" type.

[0089] An initialization circuit described in application No. 2111286, in particular in connection with its [Fig. 4], makes it possible to write all the memory cells to “1” and thus implement a “set to 1” type initialization. To do this, the memory device plans to control, for each column, one of the BLT or BLF bit lines by connecting it to a supply voltage by turning on a bit line selection transistor. The selected and powered bit line thus tends to impose a value “1” or “0” on one of the nodes of each memory cell connected to this bit line.

[0090] An example of a truth table T2 illustrating the operation of the control unit 100 of [Fig.1] is given in [Fig.2].

[0091] The initialization control unit 100 is configured to adopt a so-called "locked" operating mode (first line of the truth table) in which the initialization control unit 10 is configured so that following a power-up, regardless of the value of signals emitted on the first hard mask input HM1, on the second hard masking input HM2 and on the soft masking inputs SMI, SM2, SM3, SM4, the control unit produces at output a control signal making it possible to trigger an initialization of said given group of cells according to a so-called "default" initialization type or an erasure of said given group of cells prior to placing this given group of cells in a metastable state.

[0092] In the so-called “default” operating mode, the logic module 110 is put into a so-called “locked” state and produces at output OUT the same given logic state, for example OUT='0', as long as it does not receive a so-called unlocking sequence to make it exit this given state.

[0093] The given state of the signal Z' emitted on the first OMI output is capable of causing an erasure of the data and the placing of said at least one group of cells in a so-called "metastable" state for which their first node and second node are placed at equal or substantially equal potentials, in particular when the given group of cells associated with the control unit 100 are intended to perform a non-clonable physical function (PUF). French patent application No. 2214117 filed by the applicant on December 21, 2022 before the National Institute of Intellectual Property provides a circuit configured to trigger such an erasure and a placing in a metastable state. The first OMI output can thus be coupled to such a type of circuit. During a memory erasure operation, the internal nodes of the memory cells can be positioned at identical or substantially identical values ​​(i.e.which differ by less than 10 mV), either by short circuit or by discharging the nodes following a power cut. A possible initialization phase therefore consists of changing a memory cell from an “indeterminate” state (and indeterminable by reading) to a state with a “determined” stored value (and therefore determinable by reading). This application follows other patent applications by the applicant relating to the subject of SRAM memory devices. On . may also refer to patent application FR, No. 1761692, filed on December 6, 2017 in which an erasure mechanism is described. Reference may also be made to French patent application No. 2111286 filed by the applicant on October 25, 2021 before the National Institute of Intellectual Property in which an erasure is also described.

[0094] Alternatively, when the given group of cells associated with the control unit 100 is intended to store sensitive CSP (Critical Security Parameter) data, the signal Z' emitted on the first OMI output can trigger an initialization of this given group according to the so-called "default" initialization type. In the particular embodiment illustrated, the default initialization type corresponds to the first type of initialization, in other words, a "reset" of the cells. The control signal Z' can thus trigger a "reset" initialization of the cells. This signal Z' on the OMI output (here corresponding to a logic state 1) allows, following a power-up of the memory, the cells of a group of cells associated with the control unit 100 to be reset to zero.By "setting cells to 0" we mean here a setting to a potential of their first node or their second node corresponding to a logical '0' according to which of these complementary nodes is supposed by convention to establish the logical state of the cell.

[0095] A particular sequence of hard masking signals on the HM1 and HM2 inputs makes it possible to exit the “default” operating mode. The unlocking sequence can advantageously correspond to a succession of signals on the first hard masking input HM1 then on the second hard masking input HM2.

[0096] In the particular embodiment illustrated in [Fig.2], an unlocking sequence S201 consists of applying a given logic state, for example a logic '0' to the first hard masking input, then applying a falling edge (i.e. a transition from a logic '1' to a logic '0') to the second hard masking input.

[0097] After receiving such a sequence, the logic module 110 is no longer in its locked state and its output is no longer necessarily in the logic state '0' and is thus likely to be modified.

[0098] A “soft masking” operating mode can then be established as long as new signals or a change in signal state on the hard masking inputs HM1, HM2 is not detected, which in this example results in a state being maintained, in particular a low state or a logic level '0', on the inputs HM1, HM2, it being the soft masking signals which control the initialization.

[0099] Thus, in this soft masking mode, when the control unit 100 receives a initialization indicator signal Z "of type set to 0" on its SMI input (third line of the truth table), the control unit 100 produces at output an initialization control signal Z' of type "set to 0" to trigger an initialization of the memory cells by carrying out a setting to a logic state '0' of these cells.

[0100] In soft masking mode, when the control unit receives a free-type initialization indicator signal F on its SM2 input (sixth row of the truth table), the control unit 100 outputs a free-type initialization control signal F' to trigger a "free" type initialization of the memory cells.

[0101] When the control unit 100 receives a random initialization indicator signal R' on its input SM3 (fifth line of the truth table), it produces at output an initialization control signal R' of the “random” type to trigger a random initialization of the memory cells.

[0102] When the initialization management unit receives an initialization indicator signal O of the “set to 1” type on its input SM4 (fourth line of the truth table), the control unit 100 produces at output an initialization control signal O' of the “set to 1” type to trigger a random initialization of the memory cells by setting these cells to a logic state “1”.

[0103] Thus when a given soft masking input SMI, SM2, SM3, SM4, receives an initialization indicator signal of a given type of initialization the control unit produces at output an initialization control signal to trigger an initialization of the memory cells of the given sector according to said given type of initialization.

[0104] When module 110 is unlocked, the reception of an activation signal on the second hard mask input HM2, which in this example results in setting the PDM_ENABLE signal to 1, leads, as long as an intrusion detection signal is not detected (translated in this example by TAMPER_FLAG='O'), to an operating mode in which, regardless of the signals emitted on the soft masking inputs SMI, SM2, SM3, SM4, a control signal is emitted on the output OM4 to trigger a default initialization, here of the type setting to '0' on the group of cells associated with the control unit 100.

[0105] The initialization control unit 100 is configured to re-adopt the so-called "default" operating mode following the receipt of a lock signal or indicator on said first hard masking input HM1.

[0106] Thus, such a signal or indicator causes a locking S202 of the output OUT of the module 110.

[0107] This locking is implemented by detecting a new S202 sequence, for example when a rising edge (transition from a logical '0' to a logical '1') on the intrusion detection TAMPER_FLAG signal is detected. Following such detection, the control unit 100 operates again in its default mode in which regardless of the value of the hard masking and soft masking inputs, a “default” initialization control logic signal is produced, in this example in the form of a “set to 0” type initialization control signal produced at output OM4 of the control unit 100.

[0108] In [Fig.3], different operating modes of the logic module 110 are illustrated by means of a first truth table T3i and a second truth table T32*

[0109] Following a power-up (step E400 corresponding here to a setting to VDD of a power supply rail of the module 110), the output OUT of the module is always initialized to the same logic state, here for example a logic state OUT='0', and this, whatever the value of its control inputs LOCK and HANDLE, themselves corresponding to the hard masking inputs.

[0110] The module 100 is then (truth table T3[) in the “locked” operating mode of the control unit 100 and in which its output OUT always remains in the same logical state, here at '0'.

[0111] The particular unlocking sequence (steps E401 then E402) for taking the module 110 out of its “locked” state consists, for example, of applying a 0 to the LOCK input before applying a falling edge to the HANDLE input. Thus, following receipt of the unlocking sequence, the signal at the output OUT of the module 110 changes from the “locked” state when the power supply starts, in this example '0', to another state, in this example '1'. This makes it possible to exit the default operating mode of the control unit described previously.

[0112] Then, in an “unlocked” operating mode (truth table T32) the OUT output is likely to change state.

[0113] In the “unlocked” operating mode of the module 110, the output OUT can return to a logic state '0' allowing a “default” type initialization to be triggered (i.e. in the embodiment described previously corresponding to a “set to 0” type initialization) without putting the module 110 back into a locked state. This is achieved by setting the signal on the HANDLE input to '1'.

[0114] To put the module 110 back into a “locked” state (step E404), the signal on the LOCK input is set to 1.

[0115] Before a power outage, the lock signal can be applied and the LOCK input set to '1' to ensure that, after power is restored, the logic module 110 restarts correctly in the default state without being affected by a persistence effect of the last stored data.

[0116] This setting to a logic state '1' of the LOCK input can correspond to an activation or a setting to a logic state '1' of the "Tamper_Flag" signal following a detection of supply voltage drop. Such detection is implemented, for example, by an external fraudulent access detection module or circuit.

[0117] [Fig.4] serves to illustrate a detailed embodiment of the logic module 110 mentioned above and receiving the hard masking signals from the hard masking inputs HM1, HM2, respectively on a first control input LOCK and a second control input HANDLE. The logic module 110 here integrates an asynchronous flip-flop 115, in particular an RS flip-flop, the R input of which is coupled to the first control input LOCK. The output of a logic gate 113 performing a logic function between the first control input LOCK and the second control input HANDLE is applied to the S input of the flip-flop. For example, the logic gate 113 performs a NOR function between the first control input LOCK and the complement of the second control input HANDLE. The Q output of flip-flop 115 is coupled to a logic gate 117 performing for example a NOR function and delivering the OUT output signal of module 110.

[0118] The asynchronous flip-flop 115 has the particularity of being asymmetrical, so that when it is powered up (shown schematically in [Fig.4] by a passage from ground to a potential VDD of its power supply) it always initializes to the same logic state, here for example a logic state '1' on the output Q.

[0119] The RS type asynchronous flip-flop 115 can be made asymmetrical by asymmetrically dimensioning the two NOR or NAND gates which make up this flip-flop 115. Thus, by design, the initialization value of the module 110 is determined when it is powered.

[0120] A particular example of an embodiment of an asymmetric RS flip-flop 115 is given in [Fig.5].

[0121] The flip-flop 115 is formed of a first set of transistors M1, M2, M5, M6 performing here a NOR logic function and of a second set of transistors M3, M4, M7, M8 performing the same logic function as the first set of transistors M1, M2, M5, M6.

[0122] The first set of transistors comprises a first group of transistors M1, M2, in this example N-type transistors, having an arrangement similar to that of a second group of transistors M3, M4, of N-type but provided with a lower threshold voltage than that of the transistors M3, M4 of the second group.

[0123] To accentuate the asymmetry, the first set of transistors can be provided with a group of transistors M5, M6, in this example P-type transistors, having an arrangement similar to that of another group of transistors M7, M8, also P-type but provided with a higher threshold voltage than that of transistors M7, M8. Alternatively, or in combination, the asymmetry can also be obtained with different geometries of the transistors relative to each other and in particular of their ratio (W / L) of width W to length L of the channel.

[0124] Advantageously, it is possible to provide the same SRAM memory with several initialization control units of the type described previously in connection with [Fig.l] each associated with a particular group of cells from among a set of SRAM cells of a memory matrix.

[0125] Thus, in [Fig.6], another initialization control unit 200 for controlling the initialization of at least one other given group of SRAM cells of the same SRAM memory as that provided with the group of cells controlled by the initialization control unit 100 is illustrated.

[0126] This other initialization control unit 200 has a structure similar to that of the control unit 100 but differs in particular from that described in connection with [Fig.l], in that its default initialization type this time corresponds to an initialization of the “random” type. The random initialization control signal R' therefore corresponds, in this example, to the default initialization control signal. This signal R' is emitted on the OMI output.

[0127] The initialization indicator signals O, F, R, Z are this time emitted respectively on the inputs SM3, SM2, SMI, SM4, while the initialization control signals O', F', R', Z' come this time respectively from the outputs OM3, OM2, OMI, OM4.

[0128] According to one possible implementation, the control unit 100 and the other control unit 200 can be dedicated to managing the initialization of groups of cells belonging to different zones of a matrix or a memory plane.

[0129] This can thus make it possible to manage the sequence of initializations differently from one area of ​​the memory to another and, in addition, to provide default initialization types from one area of ​​the memory to another.

[0130] An example of a memory plane is shown schematically in [Fig.7] and comprises a matrix M of memory cells. The matrix is ​​typically formed of a plurality of rows and columns of SRAM cells (not shown in this figure). Here, two zones Z1, Z2 are distinguished in the matrix M, each formed of a group of cells. The memory comprises in particular a first group G1 of cells located in a first zone Z1 of the matrix. According to a particular embodiment, the first zone Z1 contains cells intended to carry out a non-clonable physical function (PUF) and whose logical state, in particular the initialization logical state, is capable of being used to form a digital signature or a digital fingerprint of the memory.

[0131] The memory also comprises a second group G2 located in a second zone Z2 of the matrix typically larger in terms of size than the first zone ZL. The second group G2 can be formed from several subgroups G21, G22. and advantageously include a G22 subgroup of cells capable of storing sensitive CSP data (for “Critical Security Parameters”).

[0132] The memory can then have an initialization control unit 100 as described for example in connection with [Fig.l] dedicated to the first zone ZI corresponding to the non-clonable physical function (PUF). Another control unit 200 as described for example in connection with [Fig.6] can be dedicated to the second zone Z2 and provided to control the initialization of the subgroup G22 of CSP cells capable of storing sensitive data. It is thus possible to manage the default initialization and the sequencing of the initialization of the zone ZI dedicated to the PUF differently from those of other zones and in particular of the zone of CSP cells.

[0133] The initialization control units 100, 200 may be implemented in a region peripheral to the memory cells, for example a region in which a row or column controller of the matrix is ​​located.

[0134] [Fig. 9] gives an example of a timing diagram of the operation of a memory device which may be provided with one or more initialization control units as described previously. The time scale on this timing diagram is not represented in a linear manner, the ratio of the durations respectively between the instants t1 and t2 and between the instants t2 and 3 being typically much greater than on this schematic representation.

[0135] Powering up the memory matrix here results in a transition from 0 to VDD of a gate or conductive line between an instant t0 and an instant t1. The cells of the first group G1 are then erased and then maintained in a metastable state while the cells of the subgroup G22 are initialized. The cells of the subgroup G22 will be initialized according to the default initialization type provided for powering up. Thus, it can for example be provided that the cells of the set G22 will have a random initialization. To put the cells of the first group G1 in a metastable state, their high power supply line VDD ([Fig.8]) is disconnected from a gate or conductive power supply line and / or their internal nodes NT and NF are connected to each other, for example by activating their access transistors TAt and TAF and by connecting the bit lines BLTi, ..., BLFi together.

[0136] A falling edge on the activation signal PDM_ENABLE makes it possible to put the control unit associated with the subgroup G22 of the CSP zone in an unlocked state, while the control unit associated with the first group G1 remains in a locked state.

[0137] During a phase between an instant t1 and an instant t2, the device is in a so-called “normal” operating mode, which corresponds to a majority of the overall operating time of the matrix when it is powered, for example at least 99% and in this example 99.9% of the time the power supply conductive grid is powered and thus brought to the supply voltage VDD.

[0138] When the Tamper_flag detection signal is modified, for example following the detection of an attempted intrusion or fraudulent access (“tampering event”), the output(s) of the control unit associated with the first group G1 is not modified.

[0139] In the CSP area, it is possible to ensure that the Tamper_flag detection signal is not modified in NORMAL mode. Indeed, in this NORMAL mode, the data stored by this area is not considered sensitive and does not particularly need to be erased.

[0140] Then, from time t2, another mode called "crypto" is triggered. This operating mode may in particular be an operating mode in which one wishes to access the cells of the first group G1 in order to carry out an enrollment procedure to determine the cells that one wishes to use to create a digital signature and / or an encryption key (PUF), or in order to read a digital signature and / or an encryption key contained in certain cells of the first group G1. At a time t2, the state of the activation signal PDM_ENABLE is such that it does not modify that of the output(s) of the control unit associated with the first group G1 of cells. Then, a falling edge on the activation signal PDM_ENABLE makes it possible to unlock the control unit associated with the first group G1 of cells.During an "N-time READ" phase, initializations according to initialization types that may be distinct from the default initialization type can be launched. For example, "free" type initializations can be carried out during this phase on the cells of the first GL group. During this time, the CSP area is in a restricted access mode.

[0141] This is possible in particular when each of the PUF and CSP zones uses its own control unit, the control unit of the PUF zone being able to be distinct from the control unit of the CSP zone.

[0142] During the crypto mode, an attempt at fraudulent access (“tampering event”) to the memory may possibly be detected and results in a change of state of the detection signal Tamper_flag which, for example by means of a transition to a given state, here a high state corresponding to a logic '1', makes it possible to launch a default initialization of the cells of the first group Gl and the cells of the subgroup G22. The control unit(s) associated with the first group Gl and the subgroup G22 of cells are then put into a locked state. The cells of the first group Gl and the cells of the subgroup G22 are then put into a metastable state.

[0143] An unlocking sequence (change of state of the detection signal then of the activation signal) then makes it possible to reset the control unit associated with the first group G1 in an unlocked state, which again allows one or more initializations to be performed on the cells of the first group G1 according to respective types which may be distinct from that of the default initialization.

[0144] A new change of state of the activation signal can, from a time t3, allow a return to a "normal" operating mode. This change of state can occur in particular at the end of an enrollment operation or at the end of an "interrogation" or "challenge" operation of the PUF zone in which the cells of the first group G1 may be located.

Claims

Claims

1. Control unit (100, 200) of an SRAM memory for triggering an initialization, selected from different possible distinct initialization types, of at least a given group of SRAM memory cells of said SRAM memory, said control unit comprising: - a first input (HM1) called “hard masking”, capable of receiving a signal called “detection” (TAMPER_FLAG), - a second input (HM2) called “hard masking”, capable of receiving a signal called “activation” (PDM_ENABLE), - one or more inputs (SMI, SM2, SM3, SM4) called "soft masking" capable of receiving initialization indicator signals according to different distinct initialization types, said control unit being configured to adopt a so-called "locked" operating mode, in which following a power-up of the memory and whatever the value of signals emitted on the first hard masking input (HM1) and the second hard masking input (HM2) and on the soft masking inputs (SMI, SM2, SM3, SM4), or following the reception of a so-called "locking" sequence on said first hard masking input (HM1), said control unit produces at output (OMI) a so-called "hard masking" control signal (Z', R') capable of triggering an initialization of said given group of cells according to a so-called "default" initialization type corresponding to a first type of initialization among said different distinct initialization types or an erasure,and maintains at output (OMI) said “hard masking” control signal (Z', R') in the same given state as long as a particular signal sequence called “unlocking” is not received on said hard masking inputs (HM1, HM2), said control unit being further configured to, following the reception of said particular signal sequence called “unlocking” on said hard masking inputs (HM1, HM2), adopt at least one other operating mode in which, in the absence of new signals or change of signal state on said hard masking inputs (HM1, HM2), when said control unit receives an indicator signal (F, R, O, Z) of initialization of the first type of initialization, produce at output a control signal, (Z', R') of initialization of the first type to trigger an initialization of the memory cells of said given group of cells according to said first type of initialization and when the control unit receives an initialization indicator signal of the second type of initialization (F, 0), outputting an initialization control signal (F', O') of a second type to trigger an initialization of the memory cells of said given group of cells according to said second type of initialization.

2. Control unit according to claim 1, wherein said detection signal (TAMPER_FLAG) comes from a module (11) for detecting fraudulent access to said SRAM memory, said locking sequence on said first hard masking input (HM1) corresponding to a change of state of said detection signal (TAMPER_FLAG).

3. Control unit according to one of claims 1 or 2, in which said unlocking sequence consists, in this order, of a given logic state or a change of logic state of said detection signal (TAMPER_FLAG) on said first hard masking input (HM2) to said given logic state then, a change of the activation signal (PDM_ENABLE) on said second hard masking input (HM2).

4. Control unit according to one of claims 1 to 3, further configured to, in said at least one other operating mode, following the reception of said activation signal (PDM_ENABLE) on the second “hard masking” input (HM2) and in the absence of a change in state of the detection signal on the first “hard masking” input (HM1), emit a hard masking control signal to trigger an initialization of the memory cells of said given group according to said default initialization type.

5. Control unit according to one of claims 1 to 4, in which the control unit (100, 200) is provided with: an asynchronous flip-flop logic module (110) having a so-called "control" input (LOCK) coupled to the first hard masking input (HM1) and another so-called "control" input (HANDLE) coupled to the second hard masking input (HM2), said logic module (110) being configured to, following a power-up or the reception of said locking sequence, maintain at output a first logic state as long as said logic module (110) does not receive said unlocking sequence and to, following the reception of said unlocking sequence, produce at output a second complementary logic state of said first logical state.

6. Control unit according to claim 5, further comprising a logic gate stage (150) coupled to an output (OUT) of said logic module (110) and to said soft masking inputs, said logic gate stage (150) being provided with: - at least a first logic gate (158) performing a given logic function, in particular performing an OR function between a first soft masking input (SM4) and the complement of an output (OUT) of said logic module (110), an output of the first logic gate (158) being coupled to a first output (OM4) of the control unit (100, 200) provided to deliver the initialization control signal of the first type, - at least a second logic gate (152, 154, 156) performing a logic function distinct from the given logic function, in particular an AND function between a second input (SMI, SM2,SM3) of said plurality of “soft masking” inputs and the output (OUT) of said logic module (110) being coupled to a second output (OMI, OM2, OM3) of the control unit (100, 200) provided to deliver the initialization control signal of the second type.,

7. Control unit according to one of claims 6 or 5, in which the logic module (110) with asynchronous flip-flop (115) is provided with an asymmetrical asynchronous flip-flop such as an asymmetrical RS flip-flop.

8. A control unit according to claim 7, wherein said asynchronous flip-flop (115) is formed of a first set of transistors (M1, M2, M5, M6) performing a given logic function, in particular a NOR function or a NAND function, and a second set of transistors (M3, M4, M7, M8) performing said same given logic function, said asynchronous flip-flop (115) being asymmetrical such that said first set of transistors (M1, M2, M5, M6) is provided with at least a first group of transistors (M1, M2) having an arrangement similar to that of a second group of transistors (M3, M4) of said second set of transistors, the transistors (M1, M2) of the first group being provided with a threshold voltage or a size different from that of the transistors (M3, M4) of said second group.

9. Control unit according to one of claims 1 to 8, wherein among said soft masking inputs: - a first “soft masking” input (SMI) is capable of receiving

10.

11. a signal (Z) indicating initialization of a first type of initialization, - a second soft masking input (SM2), capable of receiving an indicator signal (F) for initialization of a second type of initialization among said different types of initialization, the second type of initialization being distinct from said first type of initialization and said second type of initialization, - a third soft masking input (SM3), capable of receiving an initialization indicator signal (F, R, Z) of a third type of initialization among said different types of initialization, the third type of initialization being distinct from said first type of initialization and said second type of initialization, wherein in said at least one other operating mode when the third soft masking input receives an initialization indicator signal of the third type of initialization, the control unit produces as output an initialization control signal of a third type to trigger an initialization of the memory cells of said given group of cells according to said third type of initialization. Control unit according to one of claims 1 to 9, the first type of initialization and the second type of initialization are distinct types of initialization among: - an initialization of the “set to 1” or “set to 0” type consisting of putting all the cells of said group in the same logical state, - an initialization of the “random” type consisting of imposing on each column of cells of said group the same given logical state selected randomly between a first logical state and a second logical state, - a “free” type initialization consisting of putting the internal nodes of each cell of said group at the same potential then letting these internal nodes respectively charge or discharge in order to let the cell establish itself freely at a given logical state. Control unit according to one of claims 1 to 10, in which, in the locked operating mode, said output (OMI) maintains said hard masking control signal (Z') in the same given state is capable of maintaining said given group of cells in an indeterminate state called "metastable" for which their first storage node (NT) and their respective second storage node (NF) are set to equal or substantially equal potentials.

12. Static random access memory device comprising: - a set of SRAM cells comprising said given group of SRAM cells, - at least one first control unit (100) according to one of claims 1 to 11, for initializing said given group of said set of SRAM cells.

13. Static random access memory device according to claim 12, further comprising: - a second control unit (200) according to claim 1, for controlling the initialization, according to different possible distinct initialization types, of the memory cells of a second group of cells of said set of SRAM memory cells distinct from said given group.

14. A static random access memory device according to one of claims 12 or 13, wherein said given group of cells contains a physical unclonable function (PUF), said second group of cells corresponding to sensitive data storage cells or to open access cells.

15. Static random access memory device according to one of claims 12 to 14, wherein the second control unit (200) is configured to, following each power-up of the memory or following the reception of a locking signal (TAMPER_FLAG), produce as output an initialization control signal to trigger an initialization of said second group of cells according to a default initialization type among said different distinct initialization types, the default initialization type of the second control unit being different from the default initialization type of the first control unit and selected from: - an initialization of the "set to 1" or "set to 0" type consisting of setting all the cells of said group to the same logic state,- a “random deterministic” type initialization consisting of imposing on each column of cells of said group the same given logical state selected by random drawing between a first logical state and a second logical state, - a “free” type initialization consisting of putting the internal nodes of each cell of said group at the same potential then letting these internal nodes respectively charge or discharge in order to, let the cell settle freely into a given logical state.

16. Static random access memory device according to claim 15, the default initialization type of the first control unit being a "set to 1" or "set to 0" type initialization consisting of setting all the cells of said group to the same logical state, the default initialization type of the second control unit being a "random deterministic" type initialization consisting of imposing on each column of cells of said group the same given logical state selected randomly between a first logical state and a second logical state.

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