Contactless communication device using active charge modulation

Abstract

Active Charge Modulation Contactless Communication Device This description relates to an active charge modulation contactless communication device (100), comprising at least: - a receiving circuit (110) configured to receive as input a receive signal from an electromagnetic field intended to be received by an antenna (102) and to output a first clock signal; - a transmitting circuit (116) comprising an output coupled to the antenna (102) and intended to output a modulation signal in phase with the received signal; - a compensation circuit (118) for a first delay of the first clock signal due to the receiving circuit (110) and the amplitude of the received signal, configured to determine a phase shift value to be applied to an input signal of the transmitting circuit (116) to compensate for the first delay. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Contactless communication device by active charge modulation Technical field

[0001] The present description relates generally to the field of wireless communications between a reader and a contactless communication device by active charge modulation, in particular between a reader and such a device emulated in card mode (or CE for “Card Emulation” in English). The present description may relate in particular to the field of contactless communications implemented in NFC technology (“Near Field Communication” in English, or near field communication). Prior art

[0002] Near field communication, or NFC, is a wireless connectivity technology enabling communication over a short distance, for example of the order of ten centimeters, between electronic devices, such as a contactless smart card and a reader, or a CE device (for example a mobile phone or a connected object) and a reader.

[0003] A contactless communication device is a device capable of exchanging information via an antenna with another contactless device, for example a reader, according to a contactless communication protocol.

[0004] An NFC device, which is a contactless device, is a device compatible with NFC technology. NFC technology is an open technology platform standardized in ISO / IEC 18092 and ISO / IEC 21481 but incorporates many already existing standards such as for example the type A and type B protocols defined in ISO-14443 which can be communication protocols usable in NFC technology.

[0005] A CE device may be used to exchange information with another contactless device, for example a contactless reader, using a contactless communication protocol usable in NFC technology.

[0006] When transmitting information between a reader and a CE device or an NFC card, the reader generates an electromagnetic field via its antenna which is generally, according to the standards conventionally used, a sinusoidal wave with a frequency equal to 13.56 MHz. Each of the NFC devices (reader and CE device) transmits data using a modulation scheme, for example amplitude shift keying or ASK.

[0007] Two operating modes are possible: a passive mode, which corresponds to the mode used by an NFC card, or an active mode, which generally corresponds to the mode used by a CE device.

[0008] In passive mode, also called PLM or Passive Load Modulation, only the reader generates the electromagnetic field and the card is then passive. The card antenna modulates the electromagnetic field generated by the reader via a modification of a load connected to the terminals of the card antenna, which modifies the output impedance of the reader antenna due to the magnetic coupling between the two antennas. This results in a change in the amplitudes and / or phases of the voltages and currents present at the reader and card antennas. Information is thus transmitted from the card to the reader by load modulation to the reader antenna currents.

[0009] In the active mode, also called ALM or Active Load Modulation, both the reader and the CE device generate an electromagnetic field. This operating mode is used when the CE device is provided with its own power source, for example a battery.

[0010] Generally, a CE device has a smaller antenna than that of an NFC card, and this is the reason why active load modulation is generally used in such a device.

[0011] During active load modulation, the electromagnetic fields emitted by the reader and the CE device are in phase with each other so that the detection sensitivity of the device is not reduced. The CE device may in particular comprise a reception circuit including for example a variable gain amplifier, or VGA (Variable Gain Amplifier) ​​and a sinusoidal signal to square signal converter making it possible to extract from the field generated by the reader a clock signal used to synchronize in phase a phase-locked loop, or PLL (Phase Locked Loop) used in particular to compensate for the propagation delay in the reception circuit.

[0012] The VGA and the converter are however subject to PVT (Process, Voltage, Temperature) variations which can cause a delay or an advance of the received signal, resulting in a phase shift between the electromagnetic field emitted by the reader and that emitted by the CE device. Variations in the amplitude of the electromagnetic field emitted by the reader and / or the coupling between the antennas of the reader and the CE device can also contribute to this phase shift given that the transmission delay of the signal through the reception circuit also varies depending on the amplitude of the received electromagnetic field and therefore the coupling between the antennas of the reader and the CE device. Summary of the invention

[0013] There is a need to propose a solution to address the problems encountered with existing solutions.

[0014] One embodiment overcomes all or part of the drawbacks mentioned above and proposes a contactless communication device by active load modulation, comprising at least: a reception circuit configured to receive as input a reception signal from an electromagnetic field intended to be received by an antenna and to deliver as output a first clock signal; a transmission circuit comprising an output coupled to the antenna and intended to deliver at its output a modulation signal in phase with the reception signal; a circuit for compensating for a first delay of the first clock signal due to the receiving circuit and the amplitude of the receiving signal, configured to determine a phase shift value to be applied to an input signal of the transmitting circuit to compensate for the first delay.

[0015] According to one embodiment, the reception circuit comprises at least: a variable gain amplifier configured to receive the reception signal as input; a sinusoidal signal to square signal converter, comprising an input coupled to an output of the variable gain amplifier, and an output on which the first clock signal is intended to be delivered.

[0016] According to one embodiment, the device further comprises a phase-locked loop configured to receive as input the first clock signal and the phase shift value, and to deliver on a first output the input signal of the transmission circuit.

[0017] According to one embodiment, the compensation circuit comprises at least one look-up table configured to store several phase shift values, each associated with an amplitude value of the reception signal, and to deliver as output one of the phase shift values ​​as a function of a value of a control signal applied to the input of the look-up table and the value of which depends on the amplitude of the reception signal.

[0018] According to one embodiment, the compensation circuit further comprises: an analog-to-digital converter comprising an input coupled to the output of the variable gain amplifier; a first calculation circuit comprising an input coupled to an output of the analog-digital converter, and configured to determine the amplitude value of the reception signal and to output the control signal whose value is a function of the amplitude value of the determined reception signal.

[0019] According to one embodiment, the output of the first calculation circuit is coupled to a variable gain amplifier gain control input.

[0020] According to one embodiment, the compensation circuit comprises at least one circuit for measuring a phase difference between the first clock signal and a second clock signal synchronous with the reception signal.

[0021] According to one embodiment, the measuring circuit comprises at least: a counting trigger circuit comprising two inputs to which the first and second clock signals are intended to be applied, and configured to output a counting trigger signal having a first value for a duration equal to the first delay and a second value, different from the first value, outside this duration; a counter comprising a clock input coupled to an output of the counting trigger circuit, and a data input coupled to a second output of the phase-locked loop on which a periodic signal of frequency equal to a multiple of that of the input signal of the transmission circuit is intended to be delivered; a second calculation circuit configured to determine the phase shift value as a function of a value of a counting signal intended to be delivered by the counter.

[0022] According to one embodiment, the compensation circuit further comprises a buffer memory circuit configured to receive the second clock signal as input and comprising an output coupled to one of the two inputs of the counting trigger circuit.

[0023] Another embodiment provides a method for calibrating a device as defined above, comprising at least the implementation of the following steps: applying a reception signal to the input of the reception circuit of the device; calculation and storage, by the compensation circuit of the device, of a phase shift value which is a function of the amplitude of the reception signal; and wherein steps a) and b) are repeated several times by modifying, at each repetition, an amplitude value of the reception signal.

[0024] According to one embodiment, steps a) and b) are repeated by scanning a range of amplitude values ​​of the reception signal going from a minimum value to a maximum value expected from this amplitude.

[0025] According to one embodiment, for each amplitude value of the reception signal, steps a) and b) are repeated several times by modifying, at each repetition, a value of a supply voltage of the device and / or a value of a temperature of the device.

[0026] Another embodiment provides a method of contactless communication between a reader and a device as defined above, comprising at least the implementation of the following steps: detection of an electromagnetic field by the device; when an electromagnetic field is detected by the device, emission of a first clock signal by the reception circuit of the device receiving as input a reception signal from the electromagnetic field; application, by the compensation circuit of the device, of a phase shift value to a signal applied at the input of the transmission circuit of the device, the phase shift value applied being intended to compensate for a first delay of the first clock signal due to the reception circuit and to the amplitude of the reception signal and being dependent on the amplitude of the reception signal; application to the antenna, by the transmission circuit of the device, of a modulation signal in phase with the reception signal.

[0027] According to one embodiment, the reception circuit of the device comprises at least one variable gain amplifier configured to receive the reception signal as input, and further comprising, before the application of the phase shift value to the signal applied as input to the transmission circuit of the device, a control of the gain of the variable gain amplifier by the compensation circuit, the chosen gain value being a function of the amplitude of the reception signal. Brief description of the drawings

[0028] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular exemplary embodiments given without limitation in relation to the attached figures among which:

[0029] - [Fig.l] schematically represents an example of a communication device contactless by active charge modulation communicating with a contactless reader, according to a particular embodiment;

[0030] - [Fig.2] schematically represents details of the production of an example of contactless communication device by active charge modulation, according to a particular embodiment;

[0031] - [Fig.3] schematically represents steps of an example of a method calibration of a contactless communication device by active load modulation, according to a particular embodiment;

[0032] - [Fig.4] schematically represents steps of an example of a com method communication of a contactless communication device by active charge modulation with a reader, according to a particular embodiment;

[0033] - [Fig.5] schematically represents details of the production of an example of contactless communication device by active charge modulation, according to a particular embodiment;

[0034] - [Fig.6] schematically represents an example of the embodiment of a counter of a phase-locked loop of a contactless communication device by active load modulation, according to a particular embodiment;

[0035] - [Fig.7] schematically represents an example of the realization of a circuit of de triggering of counting and of a counter forming part of a contactless communication device by active load modulation, according to a particular embodiment;

[0036] - [Fig.8] represents a timing diagram of examples of signals used in the circuits of [Fig.7]. Description of the embodiments

[0037] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the described embodiments and examples have been shown and are detailed. In particular, the production of the various elements and circuits (variable gain amplifier, sinusoidal signal to square signal converter, phase-locked loop, look-up table, analog-digital converter, calculation circuit, delay circuit, flip-flops, counters, etc.) of the device is not detailed. Those skilled in the art will be able to produce the various functions of the device in detail from the functional description given here.

[0039] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0040] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0041] An example of a contactless communication device 100 by active load modulation according to a particular embodiment is described below in connection with [Fig.l],

[0042] The device 100 is of the NFC type, that is to say is configured to use a communication protocol compatible with NFC technology. In the example described, the device 100 corresponds to a device emulated in card mode (CE). In [Fig.l], the device 100 is shown during communication with a contactless reader 200 of the NFC type.

[0043] In the exemplary embodiment described, the device 100 comprises an antenna 102 intended to exchange data with an antenna 202 of the reader 200 via the emission of electromagnetic fields by these antennas 102, 202 and the magnetic coupling of these antennas 102, 202.

[0044] In the particular configuration shown in [Fig.l], the device 100 further comprises an adaptation circuit 104 coupled between the antenna 102 and the other elements of the device 100. The circuit 104 can be used in particular to adapt the impedance of the antenna 102 to interface the input and output signals of the antenna 102.

[0045] The device 100 further comprises a reception circuit 110 configured to receive as input a reception signal from an electromagnetic field intended to be received by the antenna 102 and to deliver as output a first clock signal. In [Fig.l], the reception signal is called “RFI” and corresponds to a sinusoidal signal. The frequency of the RFI signal is for example equal to 13.56 MHz.

[0046] In a particular configuration corresponding to that shown in [Fig.l], the reception circuit 110 comprises at least:

[0047] - a variable gain amplifier, or VGA, 112 configured to receive as input the RFI signal;

[0048] - a converter 114 from sinusoidal signal to square signal, comprising an input coupled to an output of the VGA 112, and an output on which the first clock signal is intended to be delivered.

[0049] In this particular configuration, the signal emitted at the converter output 114 corresponds to a square signal with an amplitude greater than that of the RFI signal, i.e. corresponds to the transformation of the RFI signal into an amplified square signal with a gain greater than 1.

[0050] Alternatively, the reception circuit 110 may comprise additional and / or different elements from those of the exemplary embodiment of [Fig.l].

[0051] The device 100 further comprises a transmission circuit 116 comprising an output coupled to the circuit 104 and which is intended to deliver on this output a modulation signal called “RFO” to the antenna 102. This RFO signal includes information intended to be transmitted by the device 100 to the reader 200. The RFO signal is intended to be in phase with the RFI signal.

[0052] The device 100 further comprises a compensation circuit 118 for a first delay θ of the first clock signal due to the reception circuit 110, including the delay due to at least part of the PVT variations of the components of the reception circuit 110, and to the amplitude of the RFI signal. When the device 100 is in communication with the reader 200, the amplitude of the RFI reception signal may be directly proportional to that of the electromagnetic field received by the antenna 102 and therefore of the coupling between the antennas 102, 202. The compensation circuit 118 is configured to determine a phase shift value to be applied to an input signal of the circuit transmission 116 to compensate for the first odex delay.

[0053] In the particular configuration shown in [Fig.l], the device 100 further comprises a phase-locked loop, or PLL, 120 intended to synchronize the RFO signal with the received RFI signal, and thus compensate for the delays linked to the processing of the signals in the different circuits and elements of the device 100. This PLL 120 is configured to receive as input the first clock signal delivered by the reception circuit 110 as well as the phase shift value determined by the compensation circuit 118, and to deliver on a first output the input signal of the transmission circuit 116. Thus, the PLL 120 is here configured to take into account the phase shift value determined by the compensation circuit 118 so that the signal delivered at the output of the PLL 120 to the transmission circuit 116 no longer comprises a phase shift, or delay, linked to the reception circuit 110 and to the amplitude of the reception signal. RFI.

[0054] In the diagram of [Fig.l], only some of the elements of the device 100 are shown. The device 100 comprises, in addition to those visible in [Fig.l], other circuits and elements not described here, such as for example the modulation and demodulation circuits of the data received and transmitted by the device 100.

[0055] In the configuration shown in [Fig.l], the device 100 further comprises a battery 122 intended to electrically supply the various circuits and components of the device 100.

[0056] A more detailed embodiment of the device 100 is described below in connection with [Fig. 2]. In [Fig. 2], only a portion of the components and circuits of the device 100 are shown and described below. For example, compared to [Fig. 1], the antenna 102 and the circuit 104 of the device 100 are not shown in [Fig. 2].

[0057] In this exemplary embodiment, the device 100 comprises an input 124 on which a square signal, of the same frequency as the RFI signal and in phase with the RFI signal, is intended to be applied during a calibration method of the device 100 which will be described later. This square signal applied to the input 124 during the calibration method is for example delivered by a calibrated oscillator whose output is coupled to the input 124 during the calibration method of the device 100.

[0058] In the example of [Fig.2], the compensation circuit 118 comprises a buffer memory circuit 126, or buffer, allowing good propagation of the signal received on the input 124 during the calibration of the device 100. This circuit 126 applies a second delay called ôstatic and whose value is much lower than that of the first delay ôciex. The value of the second delay ôstatic does not depend on the amplitude of the reception signal and can be considered as static, or constant, during the calibration of the device 100. The signal delivered at the output of the circuit 126 forms a second clock signal with which the first clock signal delivered at the output of the circuit reception 110 will be compared to determine the phase shift to compensate for the first delay.

[0059] Alternatively, the second clock signal could be obtained in a manner different from that described herein.

[0060] In the exemplary embodiment described, the compensation circuit 118 further comprises a circuit for measuring a phase difference between the first and second clock signals.

[0061] In a particular configuration corresponding to that shown in [Fig.2], this measuring circuit comprises:

[0062] - a counting trigger circuit 128 comprising two inputs on to which the first and second clock signals are intended to be applied, and configured to output a counting trigger signal having a first value for a duration equal to the first delay and a second value, different from the first value, outside this duration;

[0063] - a counter 130 comprising a clock input coupled to an output of the circuit 128, and a data input coupled to a second output of the PLL 120 on which a periodic signal of frequency equal to a multiple of that of the input signal of the transmission circuit 116 is intended to be delivered;

[0064] - a calculation circuit 132 configured to determine the phase shift value at apply as a function of a value of a counting signal intended to be delivered by the counter 130, the output of the counter 130 being coupled to an input of the calculation circuit 132.

[0065] The value of the frequency of the periodic signal delivered on the second output of the PLL 120 may depend on the components of the PLL 120, and for example on the operating frequency of an oscillator present in the PLL 120. For example, the frequency of the reception signal and the frequency of the input signal of the transmission circuit 116 may be equal to 13.56 MHz, and the frequency of the periodic signal delivered on the second output of the PLL 120 may be equal to approximately 868 MHz (64*13.56 MHz).

[0066] This example of a measurement circuit therefore proposes to measure the phase difference between the first and second clock signals, which is representative of the first odex delay, via a count whose result will be representative of this phase difference and therefore of this first odex delay.

[0067] Alternatively, the function performed by the measuring circuit could be obtained by using circuits and components different from those described above.

[0068] In the embodiment described, the compensation circuit 118 further comprises a look-up table 134, or LUT or “Look-Up Table” in English, configured to store several phase shift values ​​each associated with an amplitude value of the reception signal. These phase shift values ​​can be sent from the output of the calculation circuit 132 which is coupled to one of the inputs of the look-up table 134. The LUT 134 further comprises an output on which one of the stored phase shift values ​​is intended to be delivered to the PLL 120, this value being chosen from those stored as a function of the value of a control signal intended to be applied to the input of the LUT 134. As described later, the value of this control signal, and therefore the phase shift value delivered to the output of the LUT 134, will be a function of the amplitude value of the reception signal received by the reception circuit 110.

[0069] In the embodiment described in connection with [Fig.2], the compensation circuit 118 further comprises:

[0070] - an analog-digital converter 136, also CAN or ADC for "Analog-Digital Converter" in English, comprising an input coupled to the output of the VGA 112;

[0071] - another calculation circuit 138 comprising an input coupled to a TADC output 136, and configured to determine the amplitude value of the reception signal and to output the control signal whose value is a function of the determined amplitude value of the reception signal.

[0072] An output of the calculation circuit 138 is coupled to a second input of the LUT 134. Thus, depending on the value supplied on this second input, i.e. the amplitude value of the determined reception signal, the LUT 134 can deliver as output one of the stored phase shift values ​​which corresponds to that stored for this amplitude value. In [Fig.2], this phase shift value delivered by the look-up table 134 is called " <pOffset » et permet de compenser le premier retard ôdex (compensation symbolisée par l’indication « - ôdex » en sortie de la LUT 134).

[0073] Alternatively, circuits other than circuits 136 and 138 described below may be used to perform similar functions.

[0074] In the exemplary embodiment described, the output of the calculation circuit 138 is also coupled to a control input of the gain of the VGA 112. Thus, depending on the value of the amplitude of the reception signal, the gain of the VGA 112 can be adjusted.

[0075] During a calibration process of the device 100 the following steps can be implemented:

[0076] a) application of a reception signal at the input of the reception circuit 110 of the device 100;

[0077] b) calculation and storage, by the compensation circuit 118, of a phase shift value which is a function of the amplitude of the reception signal.

[0078] These steps a) and b) are repeated several times by modifying, at each repetition, an amplitude value of the reception signal. These steps can in particular be repeated by scanning a range of amplitude values ​​of the reception signal going from a minimum value to a maximum value expected from this amplitude.

[0079] Thus, this calibration method makes it possible to associate and store, in the LUT 134, several phase shift values ​​as a function of several amplitude values ​​of the reception signal.

[0080] [Fig.3] schematically represents the steps of an example of a method for calibrating the device 100.

[0081] During an initial step 300, a reception signal of minimum amplitude is applied to the input of the reception circuit 110, either preferably via wiring coupled directly to the card on which the device 100 is produced, for example during an industrial test during the manufacture of the device 100, or via the application of a minimal electromagnetic field detected by the antenna 102, for example during a test carried out with the final device 100. This minimum amplitude is for example between 1 mV and 100 mV.

[0082] This reception signal is amplified by the VGA 112, digitally converted by the ADC 136 and processed by the calculation circuit 138. The gain of the VGA 112 is automatically adjusted according to the amplitude of the reception signal (step 302).

[0083] The first clock signal is obtained at the output of the converter 114, then its phase is compared, by the circuit 128, to that of the second clock signal applied to the input 124 and buffered in the circuit 126.

[0084] A value of a phase shift to be applied to the reception signal to compensate for the first odex delay is then calculated using elements 130 and 132 (step 304).

[0085] The calculated phase shift value is then stored in the LUT 134, in which this phase shift value is associated with the amplitude value of the reception signal (step 306).

[0086] During a step 308, the amplitude value of the reception signal is compared with a maximum amplitude value of the reception signal. If the amplitude value of the reception signal is less than this maximum value, the amplitude of the reception signal is increased (step 310) and steps 302 to 308 are repeated. The amplitude of the reception signal is for example increased by a value corresponding to a gain step of the VGA 112. If the amplitude value of the reception signal is equal to the maximum value, the calibration method ends (step 312). The maximum amplitude value of the reception signal is for example between 10 V and 30 V. Furthermore, steps 302 to 308 can be repeated X times, with X integer between 10 and 20.

[0087] The implementation of this calibration method thus makes it possible to store in the LUT 134 phase shift values ​​to be applied to the reception signal to compensate for the delay due to process variations of the reception circuit 110 and to the amplitude of the reception signal.

[0088] Alternatively, the method for calibrating the device 100 may comprise other steps and / or steps different from those described above. For example, to compensate, in addition to the delay due to process variations of the receiving circuit 110, the delay due to voltage and / or temperature variations of the receiving circuit 110 (which is however much less than that due to process variations), the method for calibrating the device 100 may comprise a repetition of the steps previously described for different values ​​of the supply voltage of the device 100 and / or the temperature of the device 100.

[0089] [Fig.4] schematically represents the steps of an example of a method of communication of the device 100 with the reader 200.

[0090] The device 100 may be in an inactive state (step 400).

[0091] During a step 402, the device 100 checks whether an electromagnetic field corresponding to a communication is detected.

[0092] In the absence of such an electromagnetic field, the device 100 is maintained in the inactive state (return to step 400).

[0093] In the presence of such an electromagnetic field, the first clock signal is delivered by the reception circuit 110 which receives as input the reception signal from the electromagnetic field received by the antenna 102 (step 404).

[0094] The gain of the VGA 112 can be adjusted by the compensation circuit 118, this gain value being a function of the amplitude of the reception signal (step 406).

[0095] A phase shift value is then applied by the compensation circuit 118, for example at the input of the PLL 120, this phase shift value being able to correspond to one of those stored in the LUT 134 for the amplitude value of the reception signal (step 408). The PLL 120 can then take this phase shift value into account and compensate for the first delay in the signal applied at the input of the transmission circuit 116.

[0096] A modulation signal, in phase with the reception signal, is then obtained at the output of the transmission circuit 116 and applied to the antenna 102, allowing communication between the device 100 and the reader 200 (step 410).

[0097] The exemplary embodiment of the device 100 is described below in connection with [Fig. 5]. In [Fig. 5], only a portion of the components and circuits of the device 100 are shown and described below. For example, compared to [Fig. 1], the antenna 102 and the circuit 104 of the device 100 are not shown in [Fig. 5]. In addition, the circuits 134, 136, 138 previously described in connection with [Fig. 2] are not shown in [Fig. 5].

[0098] Compared to the device 100 previously described in connection with [Fig.2], an example of embodiment of the PLL 120 is detailed in [Fig.5].

[0099] In the example of [Fig.5], the PLL 120 comprises a counter 140, an oscillator 142, a filter 144 and a subtractor 146 and an adder 148.

[0100] In this example, the counter 140 comprises a clock input coupled to the output of the receiving circuit 110, a data input coupled to an output of the oscillator 142 which corresponds to the second output of the PLL 120 previously described in connection with [Fig. 2], and an output coupled to a negative input of the subtractor 146 and on which a counting value is delivered. The counter 140 also delivers, on another output, the input signal of the transmitting circuit 116.

[0101] A target phase value, called “ <ptarget », est appliquée sur une entrée positive du soustracteur 146. Cette valeur <ptarget peut correspondre à une valeur prédéterminée, par exemple mémorisée dans un registre du dispositif 100, et qui correspond par exemple au déphasage attendu en considérant le retard dû aux différents éléments et circuits du dispositif 100 sans prendre en compte le retard dû aux variations PVT du circuit de réception 110 et à l’amplitude du signal de réception.

[0102] The output of the subtracter 146 is coupled to a first input of the adder 148 and the phase shift value <pOffset est appliquée sur une deuxième entrée de l’additionneur 148.

[0103] The output of adder 148 is coupled to the input of filter 144, and the output of filter 144 is coupled to the input of oscillator 142.

[0104] According to one example, the oscillator 142 may be of the DCO type, or “Digital Controlled Oscillator” in English (oscillator controlled by digital input).

[0105] According to one example, the frequency of the periodic signal delivered by the oscillator 142 may be equal to approximately 868 MHz (64*13.56 MHz), and those of the input signal of the transmission circuit 116 delivered by the counter 140 and of the reception signal and of the first clock signal equal to 13.56 MHz.

[0106] Alternatively, the PLL 120 may comprise circuits and / or components different from those described above and shown in [Fig.5].

[0107] An example embodiment of the counter 140 is shown in [Fig.6].

[0108] In this example, the counter 140 has an input 149 to which the output signal of the oscillator 142 is applied. The counter 140, in the example of [Fig. 6], also has several frequency dividers 150 coupled in series with each other such that the output of each of these dividers is coupled to the clock input of the following divider. In this example, the output signal of the oscillator 142 is applied to the clock input of the first divider 150. Furthermore, the output signal of one of the dividers 150 corresponds to the input signal of the transmission circuit 116. In this example, the frequency dividers 150 are configured to divide by a factor of 2 the frequency of the signal received at their input. Thus, in the example described, given that the ratio between the frequency of the periodic signal delivered by the oscillator 142 and that of the input signal of the transmission circuit 116 is equal to 64, the input signal of the transmission circuit 116 is obtained at the output of the 6th divider 150 (26 = 64). Furthermore, in a particular configuration, each of the dividers 150 configured to divide by a factor of 2 the frequency of the signal received on their input can be formed by a D flip-flop whose output is looped back to its input via an inverter.

[0109] In this example, the counter 140 further comprises several flip-flops 152 (3 D flip-flops in [Fig.6]) coupled in series with each other such that the output of each of the flip-flops 152 is coupled to the data input of the next flip-flop 152. The output signal of the oscillator 142 is here applied to the clock input of each of the flip-flops 152. The first clock signal delivered by the reception circuit 110 is applied to the data input of the first flip-flop 152. These flip-flops 152 make it possible to avoid the appearance of metastability in the counter 140.

[0110] In the embodiment described, the counter 140 also comprises other D flip-flops 154 coupled in series with each other such that the clock inputs of these flip-flops 154 are coupled with each other. The first of these flip-flops 154 receives on its clock input the output signal of the last of the flip-flops 152, and on its data input the output signal of the oscillator 142. The other flip-flops 154 receive on their data input the output signals of the dividers 150. The output signals of the flip-flops 154 together form the counting signal (called “cnt_out” in [Fig. 6]) which is coded in binary form in this example (the output signal of each of the flip-flops 154 corresponding to a bit of this counting signal).

[0111] Alternatively, the counter 140 may be produced with elements and / or components different from those described above and shown in [Fig.6].

[0112] An exemplary embodiment of the counting trigger circuit 128 and the counter 130 is shown in [Fig.7]. A timing diagram of the signals used in these circuits 128, 130 is also shown in [Fig.8].

[0113] In Figures 7 and 8, the following legends are used:

[0114] - CLK_FIRST: clock signal previously called second clock signal;

[0115] - CLK_SECD: clock signal previously called first clock signal;

[0116] - Window: counting trigger signal;

[0117] - WIND0W_EN: activation signal of the counting trigger circuit 128;

[0118] - DCO: output signal of oscillator 142;

[0119] - Gated DCO: Output signal from the AND gate of counter 130 shown in the [Fig.7] ;

[0120] - DFLL_counter: output signal of counter 130;

[0121] - Delay_meas_done: signal delivered at the output of circuit 128 and indicating that the counting is completed and can be read at the output of circuit 130;

[0122] - RN: signal resetting the D flip-flops when its value is at state 0, and leaving operate the D flip-flops at each clock edge when its value is at state 1;

[0123] - Rni: end of measurement indication signal.

[0124] In [Fig.7], the “Dff” blocks correspond to D flip-flops, and the “ / 2” blocks correspond to frequency dividers applying a division factor equal to 2.

[0125] The details of operation of the circuits 128 and 130 shown in [Fig.7] are not described here; the person skilled in the art will understand the operation of these circuits from the components and wiring visible in [Fig.7] as well as from the timing diagram in [Fig.8]. Furthermore, the signals in the timing diagram in [Fig.8] are shown schematically and not to scale relative to each other, both for the amplitudes and for the durations of the different parts of these signals.

[0126] In the various embodiments, the proposed device 100 can allow the implementation of a calibration method serving, during a subsequent use of the device to communicate with a reader, to compensate for the delay due to at least part of the PVT variations of the reception circuit 110 of the device 100 and to the amplitude of the reception signal received at the input of the reception circuit 110. The various elements of the device 100 can allow in particular:

[0127] - a synchronization of a clock signal (first clock signal in the description above), corresponding for example to a square signal, without variation in delay with a reception signal, corresponding for example to a sinusoidal signal, the amplitude of which can vary;

[0128] - a measurement of delay between the reception signal and the first clock signal from of the reception signal;

[0129] - use of a PLL as a precise time base to achieve automa tically a measurement of the delay occurring in the device, and to calibrate the device to compensate for this delay;

[0130] - a storage, for example in a lookup table, of values ​​of phase shift to compensate for different delay values, depending on the amplitude of the reception signal, which may depend on the gain of the variable gain amplifier.

[0131] In all exemplary embodiments, the device can perform precise compensation of the extracted first clock signal as a function of the input amplitude of the receive signal.

[0132] In all exemplary embodiments, the proposed device may facilitate contactless communications between the device and a reader, allowing the device to have a small antenna and / or low power and / or a large distance between the device and the reader.

[0133] In all the exemplary embodiments, the compensation of the delay by the device can be carried out without using an external device to measure the delays, and / or without having to output one or more measurement signals, this compensation being able to be carried out within the device.

[0134] In all the exemplary embodiments, the device may comprise counters for automatically carrying out delay measurements.

[0135] In all the embodiments, thanks to the delay compensation carried out, the phase of the signal emitted by the device remains stable even when the amplitude of the electromagnetic field received by the device varies, which results in a resulting electromagnetic field in which the amplitude levels are very distinct and different from each other.

[0136] In the above description, the device 100 corresponds to a contactless communication device by active charge modulation which is, during communication with a reader, emulated in card mode. The device 100 may be provided with functionalities other than those described above. The device 100 may correspond, for example, to a mobile telephone or a connected object such as a watch.

[0137] Various exemplary embodiments and variations have been described. Those skilled in the art will understand that certain features of these various exemplary embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0138] Finally, the practical implementation of the exemplary embodiments and variants described is within the reach of those skilled in the art based on the functional indications given above.

Claims

Claims

1. Device (100) for contactless communication by active load modulation, comprising at least: - a reception circuit (110) configured to receive as input a reception signal from an electromagnetic field intended to be received by an antenna (102) and deliver as output a first clock signal; - a transmission circuit (116) comprising an output coupled to the antenna (102) and intended to deliver on its output a modulation signal in phase with the reception signal; - a compensation circuit (118) for a first delay of the first clock signal due to the reception circuit (110) and to the amplitude of the reception signal, configured to determine a phase shift value to be applied to an input signal of the transmission circuit (116) to compensate for the first delay.

2. Device (100) according to claim 1, wherein the reception circuit (110) comprises at least: - a variable gain amplifier (112) configured to receive the reception signal as input; - a converter (114) from sinusoidal signal to square signal, comprising an input coupled to an output of the variable gain amplifier (112), and an output on which the first clock signal is intended to be delivered.

3. Device (100) according to one of the preceding claims, further comprising a phase-locked loop (120) configured to receive as input the first clock signal and the phase shift value, and to deliver on a first output the input signal of the transmission circuit (116).

4. Device (100) according to one of the preceding claims, in which the compensation circuit (118) comprises at least one look-up table (134) configured to store several phase shift values ​​each associated with an amplitude value of the reception signal, and to output one of the phase shift values ​​in function of a value of a control signal applied at the input of the look-up table (134) and the value of which depends on the amplitude of the reception signal.

5. Device (100) according to claims 2 and 4, wherein the compensation circuit (118) further comprises: - an analog-to-digital converter (136) comprising an input coupled to the output of the variable gain amplifier (112); - a first calculation circuit (138) comprising an input coupled to an output of the analog-to-digital converter (136), and configured to determine the amplitude value of the reception signal and to output the control signal whose value is a function of the determined amplitude value of the reception signal.

6. The device (100) of claim 5, wherein the output of the first computing circuit (138) is coupled to a gain control input of the variable gain amplifier (112).

7. Device (100) according to one of the preceding claims, in which the compensation circuit (118) comprises at least one circuit for measuring a phase difference between the first clock signal and a second clock signal synchronous with the reception signal.

8. Device (100) according to claims 3 and 7, wherein the measuring circuit comprises at least: - a counting trigger circuit (128) comprising two inputs to which the first and second clock signals are intended to be applied, and configured to output a counting trigger signal having a first value for a duration equal to the first delay and a second value, different from the first value, outside this duration; - a counter (130) comprising a clock input coupled to an output of the counting trigger circuit (128), and a data input coupled to a second output of the phase-locked loop (120) on which a signal pe- periodic frequency equal to a multiple of that of the input signal of the transmission circuit (116) is intended to be delivered; - a second calculation circuit (132) configured to determine the phase shift value as a function of a value of a counting signal intended to be delivered by the counter (130).

9. The device (100) of claim 8, wherein the compensation circuit (118) further comprises a buffer circuit (126) configured to receive as input the second clock signal and comprising an output coupled to one of the two inputs of the counting trigger circuit (128).

10. Method for calibrating a device (100) according to one of the preceding claims, comprising at least the implementation of the following steps: a. application of a reception signal at the input of the reception circuit (110) of the device (100); b. calculation and storage, by the compensation circuit (118) of the device (100), of a phase shift value which is a function of the amplitude of the reception signal; and in which steps a) and b) are repeated several times by modifying, at each repetition, an amplitude value of the reception signal.

11. A method according to claim 10, wherein steps a) and b) are repeated by scanning a range of amplitude values ​​of the received signal from a minimum value to a maximum value expected from this amplitude.

12. Method according to one of claims 10 or 11, in which, for each amplitude value of the reception signal, steps a) and b) are repeated several times by modifying, at each repetition, a value of a supply voltage of the device (100) and / or a value of a temperature of the device (100).

13. Method of contactless communication between a reader (200) and a device (100) according to one of claims 1 to 9, comprising at least the implementation of the following steps: - detection (402) of an electromagnetic field by the device (100); - when an electromagnetic field is detected by the device (100), transmission (404) of a first clock signal by the reception circuit (110) of the device (100) receiving as input a reception signal from the electromagnetic field; - application (408), by the compensation circuit (118) of the device (100), of a phase shift value on a signal applied at the input of the transmission circuit (116) of the device (100), the applied phase shift value being intended to compensate for a first delay of the first clock signal due to the reception circuit (110) and to the amplitude of the reception signal and being dependent on the amplitude of the reception signal; - application (410) on the antenna (102), by the transmission circuit (116) of the device (100), of a modulation signal in phase with the reception signal.

14. Method according to claim 13, in which the reception circuit (110) of the device (100) comprises at least one variable gain amplifier (112) configured to receive the reception signal as input, and further comprising, before the application of the phase shift value to the signal applied as input to the transmission circuit (116) of the device (100), a control of the gain of the variable gain amplifier (112) by the compensation circuit (118), the chosen gain value being a function of the amplitude of the reception signal.

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