Method for manufacturing a bipolar transistor

Abstract

Method for manufacturing a bipolar transistor This description relates to a method for manufacturing a bipolar transistor (201) comprising: - the formation of a first part (213A, 213B) of a collector (213) doped with a first type of conductivity in a semiconductor layer (210); - the formation of a first insulating region (231, 232), comprising a first insulating material, on the first part of the collector; - the formation of a conduction layer on the first insulating region, said conduction layer being intended to form a first part (214C) of a base (214) doped with the second type of conductivity; - the formation of an opening in the conduction layer, said opening leading to the first insulating region and having a first width; - the formation of an insulating layer on the conduction layer and in the opening;- the formation of a cavity in the insulating layer and in the first insulating region, said cavity opening onto a portion of the first part of the collector by passing through the opening, the cavity having at the level of the opening a second width less than the first width; - the formation of a second part (213C) of the collector in the cavity on the portion of the first part of the collector. Figure for the abbreviation: Fig. 2L;

Description

Title of the invention: Method for manufacturing a bipolar transistor. Technical field

[0001] This description relates generally to electronic devices and more particularly to bipolar transistors and their manufacturing processes. Prior art

[0002] A bipolar transistor is a semiconductor-based electronic device belonging to the transistor family. Its operating principle is based on two PN junctions, one generally forward-biased and the other generally reverse-biased. For example, a vertical bipolar transistor is a bipolar transistor in which the emitter, base, and collector regions are arranged one above the other.

[0003] A bipolar transistor can be integrated into a CMOS (Complementary Metal Oxide Semiconductor) process, with one or more other transistors, for example an insulated gate field-effect transistor, or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) type transistor. Summary of the invention

[0004] There is a need to improve certain operating parameters of bipolar transistors, in particular vertical bipolar transistors, and to improve the manufacturing process of bipolar transistors.

[0005] An embodiment overcomes all or part of the disadvantages of known bipolar transistors and / or known bipolar transistor manufacturing processes.

[0006] One embodiment provides a method for manufacturing a bipolar transistor, said method comprising: - the formation of a first part of a collector in a semiconductor layer, the collector being doped with a first type of conductivity; - the formation of a first insulating region, comprising a first insulating material, on the first part of the collector; - the formation of a conduction layer on the first insulating region, said conduction layer being intended to form a first part of a base doped with the second type of conductivity opposite to the first type of conductivity; - the formation of an opening in the conduction layer, said opening leading to the first insulating region and having a first width; - the formation of at least one insulating layer on the conduction layer and in the opening; - the formation of a cavity in at least one insulating layer and in the first insulating region, said cavity opening onto a portion of the first part of the collector by passing through the opening, the cavity having, at the level of the opening, a second width less than the first width; - the formation of a second part of the collector in the cavity on the portion of the first part of the collector.

[0007] According to one embodiment, the method further comprises: - the formation of a second part of the base on the second part of the collector, at least partially within the cavity; and - the formation of a region of an emitter opposite the second part of the base, the emitter being doped with the first type of conductivity.

[0008] According to one embodiment, the method further comprises the formation of insulating spacers between the second part of the base and the emitter region.

[0009] According to one embodiment, the method further comprises: - the removal of at least one insulating layer; - the growth, for example epitaxial growth, of the conduction layer and the second part of the base so as to increase the thickness of said conduction layer, and fill the opening, forming an extended conduction layer in contact with the second part of the base; and - the removal, for example by etching, of a peripheral lateral portion of the extended conduction layer so as to form the first part of the base in contact with the second part of the base.

[0010] According to one embodiment: - the cavity is approximately centered with respect to the opening; and / or - a distance between the cavity and the opening is greater than or equal to -20 nm, for example greater than or equal to 30 nm; and / or - the first width is greater than or equal to 200 nm, for example greater than or equal to 300 nm.

[0011] According to one embodiment, the second part of the collector: - is made of a semiconductor material similar to the material of the semiconductor layer; and / or - exhibits a doping level lower than that of at least one initial region of the first part of the collector; and / or - is formed by epitaxial growth; and / or - extends to the boundary between the first insulating region and the conduction layer, or even below said boundary.

[0012] According to one embodiment, the at least one insulating layer comprises a third insulating layer made of a second insulating material different from the first insulating material, for example silicon nitride, on the conductive layer and in the opening.

[0013] According to one embodiment, the at least one insulating layer is a stack which comprises an alternation of insulating layers of two different insulating materials, for example the stack comprises a third insulating layer in a second insulating material different from the first insulating material, for example a silicon nitride, on the conduction layer and in the opening, and a fourth insulating layer in the first insulating material, for example a silicon oxide, on the third insulating layer.

[0014] According to one embodiment, the first width is between 200 nm and 1 pm, and the second width is between 150 and 950 nm.

[0015] One embodiment provides a bipolar transistor comprising: - a semiconductor layer; - a collector, a base and an emitter formed in and on the semiconductor layer, the collector and the emitter being doped with a first type of conductivity, and the base being doped with the second type of conductivity opposite to the first type of conductivity; the collector comprising a first part in the semiconductor layer; - a first insulating region comprising a first insulating material, said insulating region being between the first part of the collector and the base; - a cavity extending into the insulating region up to a portion of the first part of the collector; - a second part of the collector in the cavity in contact with the portion of the first part of the collector; - a first part of the base on the insulating region on either side of the cavity; - a second part of the base on the second part of the collector, the second part of the base being located at least partially within the cavity; and - a region of a transmitter in relation to the second part of the base; the base having notches in a semiconductor material of the second part of the base in the insulating region, between the second part of the base and the first part of the base.

[0016] According to one embodiment: - the first part of the collector comprises a first collector region having a first thickness and extending to a first face of the semiconductor layer, and a second collector region having a second thickness less than the first thickness and not extending to the first face of the semiconductor layer, the first collector region being in contact with at least one end of the second collector region, the second collector region including the portion of the first part of the collector; and - the first insulating region comprises a first insulating layer on the second collector region and in the semiconductor layer, said first insulating layer extending to the first face of the semiconductor layer, and a second insulating layer on the first insulating layer, and for example on the first collector region, the first and second insulating layers being the same first insulating material, for example in a silicon oxide.

[0017] According to one embodiment, the first collector region and the second collector region are formed on a buried region of the semiconductor layer.

[0018] According to one embodiment, the first collector region surrounds the second collector region.

[0019] According to one embodiment, the bipolar transistor further comprising an insulating trench in the semiconductor layer around the first part of the collector.

[0020] According to one embodiment: - the semiconductor layer is made of silicon; and / or - the first part of the base is made of polycrystalline silicon doped with the second type of conductivity; and / or - the second part of the base comprises at least a first base region made of a semiconductor material, such as silicon or a silicon-germanium alloy, doped with the second type of conductivity, and for example a second base region made of a semiconductor material, such as silicon, not intentionally doped over the first base region; and / or - the emitter region is made of polycrystalline silicon doped with the first type of conductivity.

[0021] One embodiment provides an electronic device comprising at least one of the bipolar transistors described above. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] [Fig.1] is a cross-sectional view representing an example of an electronic device comprising a bipolar transistor;

[0024] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2J, Fig. 2K, and Fig. 2L are cross-sectional views representing steps in a process for manufacturing a bipolar transistor according to an embodiment; and

[0025] Figure 3 represents an electronic device comprising a bipolar transistor according to an embodiment obtained by the manufacturing process of figures 2A to 2L. Description of the implementation methods

[0026] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0027] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, not all manufacturing steps and details of a bipolar transistor are described, as they can be carried out using standard methods known to those skilled in the art.

[0028] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0029] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to a bipolar transistor in a normal operating position.

[0030] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0031] Unless otherwise specified, when reference is made to a transistor, reference is made to a bipolar transistor, for example a vertical bipolar transistor.

[0032] Unless otherwise specified, when referring to an insulating element, one is referring to an electrically conductive element. Similarly, when referring to a conductive element, one is referring, unless otherwise specified, to an electrically conductive element.

[0033] The examples and embodiments shown in the figures, and described in the following description, relate to an NPN type bipolar transistor, N doping corresponding to the first type of conductivity, and P doping to the second type of conductivity.

[0034] However, a person skilled in the art will easily understand that the principles described in this description can also be applied to a PNP type bipolar transistor, with P-type doping corresponding to the first type of conductivity, and N-type doping to the second type of conductivity.

[0035] Fig. 1 is a cross-sectional view representing an example of an electronic device 100 comprising a bipolar transistor 101.

[0036] In [Fig.1], elements of the electronic device 100 or of the bipolar transistor 101 are shown only on one side of a vertical axis Z, it being understood that the same elements are located symmetrically on the other side of this vertical axis.

[0037] The bipolar transistor 101 is formed in and on a semiconductor layer 110. The semiconductor layer 110 is positioned on a substrate, or corresponds to all or part of a substrate. The semiconductor layer is, for example, a silicon layer, for example, monocrystalline silicon. The silicon layer may be a layer of a SOI stack, with an insulating layer formed in a substrate (not shown in [Fig. 1]) beneath the silicon layer.

[0038] The transistor 101 includes a region 111 of the semiconductor layer 110. The region 111 is a buried region of the semiconductor layer 110. In other words, the buried region 111 does not extend to the top face 110A of the semiconductor layer 110. Preferably, the buried region 111 is not doped.

[0039] The electronic device 100 further includes insulating trenches 120 formed in the semiconductor layer 110, for example, to separate the transistor 101 from adjacent electronic components that can be implemented in, and on, the semiconductor layer 110, such as other bipolar transistors, MOSFET transistors, and / or other electronic components. An insulating trench 120 is an opening formed in the semiconductor layer 110 and then filled with an electrically insulating material, for example, silicon oxide. Each insulating trench 120 extends into the semiconductor layer 110, for example, from its upper face 110A, and may extend to the lower face of the buried layer 111, or before the lower face of the buried layer 111.

[0040] The insulating trenches 120 also allow the buried region 111 to be separated, at least partially, from the polarization regions 112 of the semiconductor layer 110. The polarization regions 112 are made of the same material as, preferably with the same doping as, the buried region 111, for example they are not doped.

[0041] Instead of several insulating trenches, it may be an insulating trench 120 which laterally surrounds the buried region 111, and instead of several polarization regions, it may be a polarization region 112 which laterally surrounds the insulating trench 120.

[0042] The polarization regions 112 can be electrically connected to the buried region 111 under the insulating trenches 120 such that the polarization of at least one of the polarization regions 112 causes the polarization of the buried region 111. To allow this polarization, either the insulating trenches 120 do not extend up to the buried region, i.e. a portion of the unshown semiconductor layer extends under the insulating trenches.

[0043] A first contact region 102 in an electrically conductive material, for example in a metal, covers the upper face of each polarization region 112.

[0044] The transistor 101 includes a collector 113. The collector includes first regions 113A above the buried region 111, for example in contact with the buried region 111, on the periphery of this buried region, up to the upper face 110A of the semiconductor layer 110. A central region of the buried region 111 is not covered by the first collector regions 113A. The first collector regions 113A are located on the opposite side of the insulating trenches 120 from the biasing regions 112. The first collector regions 113A are made of the semiconductor material of the semiconductor layer 110, and are doped with a first type of conductivity, for example, N-type doped.

[0045] Second contact regions 103 made of an electrically conductive material, for example a metal, cover the upper face of each first collector region 113A, forming collector contacts 113.

[0046] Between the first collector regions 113A, the collector 113 includes a second collector region 113B, for example, joining the first collector regions 113A. The second collector region 113B is above the buried region 111, for example, in contact with the buried region 111, but does not extend to the upper face 110A of the semiconductor layer 110. The second collector region 113B preferably has a thickness less than that of the first collector regions 113A. The second collector region 113B is in contact with the first collector regions 113A. The second collector region 113B is made of the semiconductor material of the semiconductor layer and is doped with the first type of conductivity, for example, N-type doped, like the first collector regions 113A.The second collector region 113B may have a doping level, i.e. a concentration of first-type dopants, less than or equal to the doping level, i.e. the concentration of dopants, of the first collector regions 113A.

[0047] Instead of several first collector regions 113A, it may be a first collector region which laterally surrounds the second collector region 113B.

[0048] The first and second collector regions 113A, 113B form an extrinsic collector region, or extrinsic collector.

[0049] The transistor 101 includes a first insulating region 121 made of an electrically insulating material, for example silicon oxide. The first insulating region 121 extends over the second collector region 113B up to a level higher than the at the level of the upper faces of the first collector regions 113A, and of the second contact regions 103. The first insulating region 121 is thus preferably in contact with the internal side walls of the second contact regions 103 and the first collector regions 113A, and with the upper face of the second collector region 113B. This first insulating region 121 may include a lower portion which corresponds to an insulating trench in the semiconductor layer 110 opposite, and extending to, the second collector region 113B, this insulating trench being able to be designated by the term shallow trench insulation (STI).

[0050] The first insulating region 121 includes a first cavity 122 which extends through the thickness of this first insulating region to the second collector region 113B. The first cavity 122 is preferably substantially centered horizontally with respect to the external lateral edges of the first insulating region 121. A portion, for example a central portion, of the upper face of the second collector region 113B thus forms the bottom of the first cavity 122.

[0051] So-called "internal" spacers 123 made of an insulating material, for example silicon oxide, are located against the internal side walls of the first cavity 122, starting from the upper face of the second collector region 113B. A central portion of the bottom of the cavity 122 is not covered by the internal spacers 123. The internal spacers 123 have a decreasing profile from the upper face of the second collector region 113B.

[0052] A third collector region 113C fills the first cavity 122 between the internal spacers 123. The third collector region 113C covers, and is in contact with, the central portion of the bottom of the first cavity 122, that is, the portion of the second collector region 113B forming the bottom of this first cavity. The third collector region 113C covers, and preferably is in contact with, the internal spacers 123. Due to the decreasing profile of the internal spacers 123 from the upper face of the second collector region 113B, the third collector region 113C has an increasing profile from this upper face.

[0053] The third collector region 113C is made of the same material as the first and second collector regions 113A and 113B, and is doped with the first type of conductivity, for example, N-type doped. The doping, i.e., the concentration of dopants, of the third collector region 113C may form a gradient, preferably decreasing, from the second collector region 113B. The third collector region 113C may have a lower average doping level than the doping level of the first and second collector regions. The third collector region 113C forms an intrinsic collector region, or intrinsic collector.

[0054] The first 113A, second 113B and third 113C collector regions form the collector 113 of transistor 101.

[0055] The first insulating region 121 may include a second cavity 124, wider than the first cavity 122, extending from the upper level of the first cavity 122, i.e., from the upper face of the third collector region 113C, to the upper face of the first insulating region 121. The first insulating region 121 thus includes a step at its upper face with an upper ring 121A surrounding the second cavity 124, i.e., it has an enlarged U-shape. The second cavity 124 is preferably substantially centered laterally with respect to the outer lateral edges of the first insulating region 121 and / or with respect to the first cavity 122.

[0056] The transistor 101 further comprises a first base region 114A, located in a central portion of the second cavity 124, preferably substantially opposite the first cavity 122 filled with the third collector region 113C. The first base region 114A preferably covers the upper surface of the third collector region 113C. The first base region 114A is preferably located in the center of the second cavity 124. The first base region 114A is, for example, silicon-based, for example silicon or silicon-germanium. The first base region 114A is doped with the second type of conductivity, that is, the type of conductivity opposite to the first type of conductivity, for example, P-type doped.

[0057] The first base region 114A preferably has a third cavity 126 extending from the upper level of this first base region to a depth less than the thickness of this first base region. The first base region 114A thus includes a step on its upper face, i.e., it has an enlarged U-shape.

[0058] Another semiconductor layer 114B is positioned on the first base region 114A at the bottom of the third cavity 126, preferably covering the bottom of this third cavity, and has a thickness that is preferably less than the depth of the third cavity 126. The material of the other semiconductor layer 114B is, for example, the same as that of the semiconductor layer 110, for example silicon, and is preferably undoped. This other semiconductor layer 114B forms a second base region.

[0059] The first and second base regions 114A, 114B form the intrinsic region of base 114 of transistor 101, or intrinsic base.

[0060] Second insulating regions 127 are positioned in the third cavity 126 on the periphery of the second base region 114B and preferably extend to the upper face of the first base region 114A, leaving access to a central portion of the second base region 114B. The second insulating regions 127 are for example in contact with the first basic region 114A over the entire contour of the third cavity 126.

[0061] Alternatively, the first base region 114A may not include a third cavity, and the second base region 114B and the second insulating regions 127 may then extend laterally up to the level of the external lateral edges of the first base region 114A.

[0062] The transistor 101 includes a third base region 114C, which forms an extrinsic base region, or extrinsic base, positioned in the second cavity 124, and which covers the bottom of this second cavity that is not covered by the intrinsic base region 114A, 114B. Thus, the extrinsic base region 114C laterally surrounds the intrinsic base region 114A, 114B. Preferably, the extrinsic base region 114C does not cover the upper face of the third collector region 113C. More generally, the extrinsic base region 114C is preferably isolated from the intrinsic collector region 113C.

[0063] The bottom of the second cavity 124 is thus preferably entirely covered by the extrinsic and intrinsic base regions.

[0064] The extrinsic base region 114C is, for example, made of polycrystalline silicon (polysilicon), and is doped with the same type of conductivity as the first base region 114A, i.e., the second type of conductivity, for example, type P. Preferably, the extrinsic base region 114C has a doping level, i.e., a concentration of dopants of the second type, higher than the doping level, i.e., the concentration of dopants, of the first base region 114A. The extrinsic base region is therefore electrically conductive.

[0065] The extrinsic base region 114C and the intrinsic base region 114A, 114B form the base 114 of the transistor 101.

[0066] The transistor 101 includes a third contact region 104 made of an electrically conductive material, for example a metal, covering the upper surface of the extrinsic base region 114C. For example, the third contact region 104 fills the second cavity 124, for example, is substantially flush with the upper surface of the first base region 114A. According to another example, the third contact region 104 is above the level of the upper surface of the first base region 114A. The third contact region 104 corresponds to the contact of the base 114 of the transistor 101.

[0067] Alternatively, the first insulating region 121 may not include a second cavity and the basic extrinsic region 114C as well as the third contact region 104 may then extend laterally up to the level of the external lateral edges of the first insulating region 121.

[0068] The transistor 101 further comprises an emitter region 115 above the The third cavity 126, or of the intrinsic base region 114A, 114B. The emitter region 115 covers the second insulating regions 127 and the central portion of the second base region 114B, that is, the portion of the second base region not covered by the second insulating regions 127. The emitter region 115 is thus in contact with the second base region 114B. The emitter region 115 is preferably electrically isolated from the first base region 114A. The emitter region 115 is preferably made of polycrystalline silicon (polysilicon), and is doped with the same type of conductivity as the collector, for example, N-type doped.

[0069] The transistor 101 includes a fourth contact region 105 made of an electrically conductive material, for example a metal, covering the upper face of the emitter region 115. The fourth contact region 105 corresponds to the emitter contact of the transistor 101.

[0070] The transistor 101 further comprises insulating spacers 125, referred to as "D-shaped" spacers, made of an insulating material, for example, silicon nitride. The insulating spacers 125 extend over the lateral walls of the emitter region 115, preferably over the entire lateral walls of the emitter region 115, and come into contact with the intrinsic base region, for example, with the first base region 114A, preferably up to the interface with the third contact regions 104. The emitter region 115 is preferably electrically isolated from the extrinsic base region 114C, in particular by the insulating spacers 125.

[0071] The internal spacers 123 allow, during the formation, generally by epitaxial growth, of the intrinsic collector region 113C in the first cavity 122, to avoid contact between the silicon of the collector 113 and the polysilicon of the extrinsic base region 114C, allowing to decrease the base collector capacitance compared to a similar bipolar transistor but without the internal spacers.

[0072] However, it has been found that these internal spacers can generate epitaxial growth defects in the intrinsic collector region, these defects being able to generate leakage currents.

[0073] Other solutions exist to avoid this contact, for example etching portions of the polysilicon layer intended to form the extrinsic base region through the first cavity, on either side of this first cavity, for example to form air pockets, but this solution can be difficult to control and presents a risk of generating leakage currents.

[0074] There is therefore a need for a bipolar transistor, and for a method of manufacturing a bipolar transistor which can overcome all or part of the disadvantages of known bipolar transistors, in particular reducing the base-collector capacitance without generating defects in the transistor, in particular defects in the collector, for example without this inducing leakage currents in the transistor.

[0075] Embodiments of bipolar transistors and methods for manufacturing bipolar transistors will be described below. The embodiments described are not limiting, and various variations will become apparent to those skilled in the art from the indications in this description.

[0076] Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 2F, Fig. 2G, Fig. 2H, Fig. 2I, Fig. 2J, Fig. 2K, and Fig. 2L are cross-sectional views representing steps in a process for manufacturing a bipolar transistor according to an embodiment.

[0077] In Figures 2A to 2L, as well as in [Fig.3], elements of the different structures of the electronic device 200 and of the bipolar transistor 201 are shown only on one side of a vertical axis Z, it being understood that the same elements are located symmetrically on the other side of this vertical axis.

[0078] Figure 2A represents a starting structure comprising a first semiconductor layer 210 (semiconductor layer). The first semiconductor layer 210 may be positioned on a substrate or be part of a substrate (not shown in Figures 2A to 2L). The first semiconductor layer is, for example, a silicon layer, for example, monocrystalline silicon. The silicon layer may be the top silicon layer of a SOL stack

[0079] A buried region 211 is formed in the first semiconductor layer 210. The buried region 211 does not extend to the top face 210A (first face) of the first semiconductor layer 210. Preferably, the buried region 211 is not doped.

[0080] Insulating trenches 220, for example two insulating trenches, are formed in the first semiconductor layer 210 from its upper face 210A, for example to separate the future transistor from adjacent electronic components that can be implemented in the first semiconductor layer 210. The formation of the insulating trenches 220 comprises forming trenches in the first semiconductor layer 210 and then filling these trenches with an electrically insulating material, for example silicon oxide. Preferably, the insulating trenches 220 do not extend to the lower face 21IB of the buried layer 211, or an unshown portion of the first semiconductor layer extends below the insulating trenches.

[0081] The insulating trenches 220 thus delimit an area of ​​the first semiconductor layer 210 in and on which the collector 213, the base 214 and the emitter 215 of the future transistor 201 will be formed (visible in [Fig.2L]).

[0082] Polarization regions 212 of the first semiconductor layer 210, or of the substrate beneath this first semiconductor layer, can be formed on the other side of the insulating trenches 220 with respect to the buried region 211. The regions of The polarization regions 212 are made of the same material as, and preferably with the same doping as, the buried region 211; for example, they are undoped. The polarization regions 212 can be electrically connected to the buried region 211 under the insulating trenches 220 such that the polarization of at least one of the polarization regions 212 causes the polarization of the buried region 211.

[0083] Instead of several insulating trenches, it may be a single insulating trench, for example which laterally surrounds the buried region 211, and instead of several polarization regions, it may be a single polarization region 212, for example which laterally surrounds the insulating trench 220.

[0084] The first collector regions 213A of the collector 213 of the future bipolar transistor 201 are formed above the buried region 211, for example in contact with the buried region 211, on the periphery of this buried region, up to the upper face 210A of the first semiconductor layer 210. A central region of the buried region 211 is not covered by the first collector regions 213A. The first collector regions 213A are located on the opposite side of the insulating trenches 220 from the biasing regions 212, that is, inside the portion of the first semiconductor layer delimited by the insulating trenches 220. The first collector regions 213A preferably extend along the inner lateral faces of the insulating trenches 220.

[0085] The first collector regions 213A are made of the semiconductor material of the first semiconductor layer 210, for example silicon. The first collector regions 213A are doped with a first type of conductivity, for example N-type doped.

[0086] A second collector region 213B is formed between the first collector regions 213A, for example joining these first collector regions, above the buried region 211, for example in contact with the buried region 211, but does not extend to the upper face 210A of the first semiconductor layer 210.

[0087] The second collector region 213B has a second thickness E2 which is preferably less than the first thickness El of the first collector regions 213A. For example, the first thickness El is between 100 and 300 nm, and the second thickness E2 is between 50 and 250 nm.

[0088] The second collector region 213B is preferably in contact with the first collector regions 213A, and preferably extends along the inner lateral faces of the first collector regions 213A. The second collector region 213B is made of the semiconductor material of the first semiconductor layer 210, for example silicon.

[0089] The second collector region 213B is doped with the first type of conductivity, for example doped with type N, and has a doping level, i.e. a concentration of first-type dopants, less than or equal to the doping level, i.e. the concentration of dopants, of the first 213A collector regions.

[0090] Instead of several first collector regions 213A, there may be a single first collector region. The first collector region 213A may then laterally surround the second collector region 213B. Alternatively, the first collector region may be between one of the insulating trenches and the second collector region, which may then extend to the other insulating trench, or between a portion of the insulating trench and the second collector region, which may then extend to another portion of the insulating trench.

[0091] The first 213A and second 213B collector regions are, for example, formed by doping, for example by ion implantation, corresponding regions of the first semiconductor layer 210. The doping of the first 213A and second 213B collector regions is, for example, carried out with carbon and phosphorus. Alternatively, the doping of the first 213A and second 213B collector regions can be carried out with arsenic.

[0092] The first 213A and second 213B collector regions form the extrinsic region (first part) of the collector, or extrinsic collector.

[0093] A first insulating layer 231 of an insulating material, for example silicon oxide, is deposited on the second collector region 213B between the first collector regions 213A, for example up to the upper face 210A of the first semiconductor layer 210. The first insulating layer 231 completely covers, for example, the second collector region 213B. The first insulating layer 231 may be an insulating trench in the first semiconductor layer 210, this insulating trench being referred to as a shallow trench insulation (STI). For example, the first insulating layer 231 has a thickness of between 40 and 80 nm, for example, approximately 60 nanometers (nm).

[0094] Figure [Fig. 2B] represents a structure obtained at the end of the formation: - a second insulating layer 232 covering the structure of the [Fig.2A], at least the first insulating layer 231 and the first collector regions 213A; and - a conduction layer 233, for example a second semiconductor layer, which is doped, which in this example is a doped polysilicon layer, on the second insulating layer 232.

[0095] Instead of a layer of doped polysilicon, it may be a layer of doped monocrystalline silicon or of doped amorphous silicon.

[0096] The first and second insulating layers 231, 232 form a first insulating region, which is thus in and on the semiconductor layer 210.

[0097] The polysilicon 233 layer is intended to form an extrinsic region 214C (first part) of the base 214 of the future transistor 201 (visible in [Fig.2L]), ​​or extrinsic base.

[0098] The second insulating layer 232 is made of an insulating material, preferably the same insulating material as the first insulating layer 231, for example, silicon dioxide. The second insulating layer 232 may at least partially cover the insulating trenches 220, or even the polarization regions 212. For example, the second insulating layer 232 has a thickness of between 10 and 50 nm, for example, approximately 24 nm.

[0099] The polysilicon 233 layer is preferably doped with the second type of conductivity, that is to say the type of conductivity opposite to the first type of conductivity, for example doped with type P. The polysilicon 233 layer preferably completely covers the second insulating layer 232. For example, the polysilicon 233 layer has a thickness of between 5 and 20 nm, for example equal to about 10 nm.

[0100] Fig. 2C represents a structure obtained after the formation of an opening 233A in the entire thickness of the polysilicon layer 233, up to the second insulating layer 232. The opening 233A can be formed by implementing photolithography and etching steps.

[0101] The aperture 233A has a first width L1. The first width L1 is, for example, greater than or equal to 200 nm, or even greater than or equal to 250 nm, or even greater than or equal to 300 nm, and can reach a few micrometers. For example, the first width L1 is between 200 nm and 1 pm. The aperture 233A is, for example, substantially centered laterally with respect to the first insulating layer 231 and with respect to the second collector region 213B. The aperture 233A is, for example, also positioned at the center of the polysilicon layer 233. The first width L1 can correspond to a first diameter.

[0102] Figure 2D represents a structure obtained by stacking several insulating layers 240. The stack 240, for example, completely covers the structure of Figure 2C, i.e., the polysilicon layer 233 and the opening 233A, and in particular fills the opening 233A. The stack 240 conforms to the shape of the polysilicon layer 233 and the opening 233A, i.e., it follows their shape, and in particular the shape conferred by the opening 233A.

[0103] For example, the 240 stack comprises an alternation of insulating layers of two different insulating materials.

[0104] In the example shown, the 240 stack comprises: - a third insulating layer 241 conformingly covering the polysilicon layer 233 and the opening 233A, in particular filling the opening 233A, the a third insulating layer 241 being made of an insulating material, preferably different from the material of the second insulating layer 232, for example silicon nitride; - a fourth insulating layer 242 conformingly covering the third insulating layer 241, the fourth insulating layer being made of an insulating material, preferably in an insulating material different from the material of the third insulating layer 241, for example silicon oxide; - a fifth insulating layer 243 conformingly covering the fourth insulating layer 242, the fifth insulating layer 243 being made of an insulating material, preferably different from the material of the fourth insulating layer 242, for example silicon nitride; - a sixth insulating layer 244 conformingly covering the fifth insulating layer 243, the sixth insulating layer 244 being made of an insulating material, preferably of an insulating material different from the material of the fifth insulating layer 243, for example silicon oxide.

[0105] Preferably, the third and fifth insulating layers 241, 243 are made of the same material, and the fourth and sixth insulating layers 242, 244 are made of the same material. Preferably, the material of the third and fifth insulating layers 241, 243 can be selectively etched with respect to the material of the fourth and sixth insulating layers 242, 244.

[0106] For example, the third insulating layer 241 has a thickness between 20 and 50 nm, for example approximately 36 nm. For example, the fourth insulating layer 242 has a thickness between 10 and 30 nm, for example approximately 20 nm. For example, the fifth insulating layer 243 has a thickness between 30 and 60 nm, for example approximately 44 nm. For example, the sixth insulating layer 244 has a thickness between 5 and 25 nm, for example approximately 12 nm.

[0107] Figure 2E represents a structure obtained after the formation of a first cavity 222 (cavity) in the stack 240 and in the first and second insulating layers 231, 232 (first insulating region). The first cavity 222 passes through the opening 233A, for example, a central portion of this opening; that is, the polysilicon layer 233 does not need to be etched to form the first cavity. The first cavity 222 extends from the upper face 240A of the stack 240 to the upper face of the second collector region 213B. The first cavity 222 is, for example, centered laterally with respect to the opening 233A.

[0108] The first cavity 222 is, for example, obtained by a photolithography technique to form an etching mask 234 having an aperture 234A whose location and dimensions correspond to the desired location and dimensions of the first cavity 222, and then etching through the aperture 234A of the mask 234.

[0109] The first cavity 222 illustrated in [Fig. 2E] has a substantially straight cross-section, i.e., substantially vertical lateral walls. This is not limiting, and the first cavity may alternatively have an oblique cross-section, i.e., oblique lateral walls, preferably widening towards the upper face 240A of the stack 240.

[0110] The first cavity 222 has, at the opening 233A in the polysilicon layer 233, a second width L2 that is smaller than the first width L1, i.e., the width of the opening 233A. The distance D between the first cavity 222 and the edge of the opening 233A is, for example, at least 20 nm, or even at least 30 nm. This distance D corresponds to a space filled with the insulating material of the third insulating layer 241, for example, silicon nitride. The second width L2 is approximately equal to the first width L1 minus twice the distance D. For example, the second width L2 is between 150 and 950 nm. The second width L2 can correspond to a second diameter.

[0111] Fig. 2F represents a structure obtained at the end of an epitaxial growth step to form a third collector region 213C from the second collector region 213B. The third collector region 213C preferably extends to level 235 of the upper face of the first insulating layer 232, i.e. the face in contact with the polysilicon layer 233, or even below this level.

[0112] The third collector region 213C is made of the same semiconductor material as the second collector region 213B and is doped with the first type of conductivity, for example, N-type doped. The doping, i.e., the dopant concentration, of the third collector region 213C is preferably lower than the doping, i.e., the dopant concentration, of the first collector region 213A and / or the second collector region 213B. The doping, i.e., the dopant concentration, of the third collector region 213C may form a decreasing gradient from the second collector region 213B.

[0113] The third collector region 213C forms an intrinsic region (second part) of the collector, or intrinsic collector.

[0114] The first, second and third collector regions form the collector 213 of transistor 201.

[0115] During this epitaxial growth, the semiconductor material of the third collector region 213C, for example silicon, is not in contact with the polysilicon of the polysilicon layer 233 intended to form the extrinsic region of the transistor base. Indeed, the polysilicon of the polysilicon layer 233 is isolated from each lateral edge of the first cavity 222, and thus from the semiconductor material. in the first cavity, by a portion, whose width is approximately equal to the distance D, of the third insulating layer 241, which is, for example, made of silicon nitride. This makes it possible to reduce the base-collector capacitance without generating defects in the transistor, particularly defects in the collector, and thus to reduce the risk of leakage currents in the transistor.

[0116] Fig. 2G represents a structure obtained at the end of the formation, in the first cavity 222: - a third layer of semiconductor 214A on the third collector region 213C; - a fourth layer of semiconductor 214B on the third layer of semiconductor 214A; - of so-called "L-shaped" insulating spacers 236 which partially cover the fourth semiconductor layer 214B and the side wall of the first cavity 222.

[0117] The fifth and sixth insulating layers 243, 244 were etched, and thus removed.

[0118] The third semiconductor layer 214A forms a first basic region of the future transistor 201. The third semiconductor layer 214A is, for example, silicon-based, for example silicon or silicon-germanium. The third semiconductor layer 214A is preferably doped with the second type of conductivity, for example P-type doped. The third semiconductor layer 214A extends, for example, to level 235 of the upper face of the second insulating layer 232, or even substantially above. For example, the third semiconductor layer 214A has a thickness of between 10 and 30 nm, for example approximately 20 nm.

[0119] The fourth semiconductor layer 214B is, for example, made of the same semiconductor material as the third semiconductor layer 214A, and / or is made of the same semiconductor material as the first semiconductor layer 210, for example silicon, and is preferably undoped. The fourth semiconductor layer 214B extends, for example, to the level of the top face of the polysilicon layer 233, or even substantially above it. The fourth semiconductor layer 214B forms a second base region of the future transistor 201. For example, the fourth semiconductor layer 214B has a thickness of between 5 and 25 nm, for example, approximately 15 nm.

[0120] The third and fourth semiconductor layers 214A, 214B are for example formed by epitaxial growth.

[0121] The third and fourth semiconductor layers 214A, 214B form an intrinsic region (second part) of the base 214, or intrinsic base, of the future transistor 201 (represented in [Fig.2L]).

[0122] The insulating spacers 236 are positioned on the periphery of the fourth semiconductor layer 214B and on a portion of the side wall of the first cavity 222, leaving access to a central portion of the fourth semiconductor layer 214B. The insulating spacers 236 extend substantially to the level of the upper face of the fourth insulating layer 242. For example, the insulating spacers 236 and the fourth insulating layer 242 form a layer of substantially constant thickness, which conformally covers the third insulating layer 241 up to the top of the fourth semiconductor layer 214B.

[0123] Figure [Fig. 2H] represents a structure obtained at the end of the formation: - a fifth semiconductor layer 237 on the structure of [Fig. 2G], preferably completely covering the fourth insulating layer 242, the insulating spacers 236, and a portion of the fourth semiconductor layer 214B not covered by the insulating spacers 236; and - of a seventh insulating layer 238 on, preferably covering entirely, the fifth semiconductor layer 237.

[0124] The fifth semiconductor layer 237 is intended to form an emitter region 215 of the future transistor 201 (shown in [Fig. 21]). The fifth semiconductor layer 237 is preferably made of doped polysilicon, and is doped with the same type of conductivity as the collector 213, for example, N-type doped.

[0125] The seventh insulating layer 238 is preferably made of the insulating material of the fourth insulating layer 242, for example silicon oxide.

[0126] Fig. 21 represents a structure obtained after etching the fifth semiconductor layer 237 and the seventh insulating layer 238 so as to form an emitter region 215 covered with a portion 238A of the seventh insulating layer 238.

[0127] The emitter region 215 covers the insulating spacers 236 and the portion of the fourth semiconductor layer 214B not covered by the insulating spacers 236.

[0128] The emitter region 215 may stop laterally at the outer side walls of the insulating spacers 236, as shown in [Fig. 2I]. Thus, the width of the emitter region 215 may be substantially equal to the width of the third 214A, or the fourth 214B, semiconductor layer, i.e., to the width of the intrinsic region of the base 214 of the future transistor 201 (shown in [Fig. 2L]). According to one embodiment, the emitter region 215 may extend beyond the outer side walls of the insulating spacers 236 onto the fourth insulating layer 242, and have a width greater than the width of the third, or the fourth, semiconductor layer. According to another variant, the emitter region 215 can stop before the vertical portions of the insulating spacers 236, i.e., be positioned on horizontal portions of the insulating spacers 236, and have a width less than the width of the third, or fourth, semiconductor layer.

[0129] Figure [Fig. 2J] represents a structure obtained as a result of: - the removal, preferably by etching, for example wet etching, of the fourth layer of insulation 242, and possibly of portions of the insulating spacers 236 which are not covered by the emitter region 215; then - the removal, preferably by etching, for example wet etching, of the third insulating layer 241, exposing the polysilicon layer 233 and the opening 233A; and - the formation of an encapsulation layer in an insulating material, for example a silicon oxide, of the emitter region 215, the encapsulation layer including for example the portion 238A of the seventh insulating layer 238, the insulating spacers 236, and insulating lateral layers 239 extending the vertical portions of the insulating spacers 236 to cover the lateral walls of the emitter region 215.

[0130] Fig. 2K represents a structure obtained at the end of the epitaxial growth of the polysilicon layer 233 vertically, increasing the thickness of this layer, and laterally towards the opening 233A, forming an epitaxial polysilicon layer 233'.During this epitaxial growth, the intrinsic core region 214A, 214B will also grow vertically and laterally, and contribute to filling the opening 233A, forming portions 214D in the semiconductor material of the intrinsic core region, for example silicon, against the epitaxially grown polysilicon layer 233', and notches 214E in the semiconductor material of the intrinsic core region, for example silicon, in the second insulating layer 232 between the first core region 214A and the epitaxially grown polysilicon layer 233'. Epitaxial growth is maintained such that the opening 233A is filled and the epitaxially grown polysilicon layer 233' reaches at least the intrinsic core region 214A, 214B which is also epitaxially grown.

[0131] Fig. 2L represents a structure obtained by lateral etching of peripheral portions of the epitaxial polysilicon layer 233' and the second insulating layer 232 so as to retain only portions of the epitaxial polysilicon layer and the second insulating layer located directly around the assembly comprising the third collector region 213C, the intrinsic base region 214A, 214B, and insulating lateral layers 239.

[0132] The laterally etched epitaxial polysilicon layer 233' forms an extrinsic region 214C of the base 214 of the transistor 201, or extrinsic base.

[0133] Preferably, the extrinsic base region 214C does not extend above the first collector region 213A. Preferably, the extrinsic base region 214C is not in contact with the intrinsic collector region 213C.

[0134] In the example shown, the etching is configured so that the extrinsic base region 214C and the second insulating layer 232 extend after etching from the isolated emitter region 215 to a portion of the first insulating layer 231. Alternatively, the etching can be configured so that the extrinsic base region 214C and the second insulating layer 232 extend after etching from the isolated emitter region 215 to the boundary between the first insulating layer 231 and the first collector region 213A.

[0135] In the example shown, the etching of the second insulating layer 232 is aligned with the etching of the epitaxial polysilicon layer 233', but this is not limiting. For example, the epitaxial polysilicon layer 233' can be etched laterally over a greater width than the second insulating layer 232.

[0136] The first insulating layer 231 and the second etched insulating layer 232 form a first insulating region 221 positioned between the base extrinsic region 214C and the collector extrinsic region 213A, 213B.

[0137] The emitter region 215 is preferably electrically isolated from the extrinsic base region 214C, in particular by the insulating spacers 225, and from the first base region 214A, in particular by the insulating spacers 236.

[0138] The manufacturing process may then include additional steps.

[0139] In particular, the manufacturing process may include: - the removal of portion 238A of the seventh insulating layer 238; - the formation of insulating spacers 225 in D (visible in [Fig.3]), for example in silicon nitride, on the side walls of the emitter region 215, for example on the insulating side layers 239; - the formation of contact regions 202, 203, 204, 205 (visible in [Fig.3]) respectively on each polarization region 212, on each first collector region 213A, on the extrinsic base region 214C, and on the emitter region 215.

[0140] Fig. 3 represents an electronic device 200 comprising a bipolar transistor 201 according to an embodiment obtained by the manufacturing process of Figures 2A to 2L.

[0141] The bipolar transistor 201 of [Fig.3] differs from the bipolar transistor 101 of [Fig.1] mainly in that it does not have internal spacers, thus reducing the risks of epitaxial growth defects of the collector.

[0142] Furthermore, transistor 201 of [Fig. 3] differs from transistor 101 of [Fig. 1] in that portions 214D in the semiconductor material of the intrinsic base region 214A, 214B, for example silicon, are formed by diffusion in the polysilicon of the extrinsic base region 214C, and notches 214E in the semiconductor material of the intrinsic base region 214A, 214B, for example silicon, are formed in the insulating region 221 between the intrinsic base region and the extrinsic base region 214C.

[0143] The other characteristics of transistor 201 in [Fig.3] may be similar to the characteristics and variants of transistor 101 in [Fig.1] and will not be repeated here.

[0144] The inventors have determined that a bipolar transistor according to the embodiments can allow better control of the base / collector junction, with in particular less leakage currents, as well as a more uniform, or even higher, breakdown voltage.

[0145] A bipolar transistor according to the embodiments can find various applications, for example in telecommunications, space, radars or data centers.

[0146] A particularly advantageous application of a bipolar transistor according to an embodiment concerns Bi-CMOS (complementary bipolar metal-oxide-semiconductor) devices, which combine bipolar and CMOS transistors on the same substrate, for example the same integrated circuit, thus benefiting from both the high-speed characteristics of bipolar technology and the low-power characteristics of CMOS technology.

[0147] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to those skilled in the art. In particular, bipolar transistors according to the embodiments may be of the homojunction type (BJT, from the English Bipolar Junction Transistor), or of the heterojunction type (HBT, from the English Heterojunction Bipolar Transistor), for example with an intrinsic core region at least partially made of a silicon-germanium (SiGe) alloy.

[0148] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. A method of manufacturing a bipolar transistor (201), said method comprising: - forming a first portion (213A, 213B) of a collector (213) in a semiconductor layer (210), the collector being doped with a first conductivity type; - forming a first insulating region (231, 232), comprising a first insulating material, on the first portion of the collector; - forming a conduction layer (233) on the first insulating region (231, 232), said conduction layer being intended to form a first portion (214C) of a base (214) doped with the second conductivity type opposite to the first conductivity type; - forming an opening (233A) in the conduction layer (233), said opening opening onto the first insulating region and having a first width (L1); - the formation of at least one insulating layer (240) on the conduction layer (233) and in the opening (233A);- the formation of a cavity (222) in the at least one insulating layer (240) and in the first insulating region (231, 232), said cavity opening onto a portion of the first part (213A, 213B) of the collector by crossing the opening (233A), the cavity having, at the opening (233A), a second width (L2) less than the first width (L1); - the formation of a second part (213C) of the collector in the cavity (222) on the portion of the first part of the collector.;

2. The method of claim 1, further comprising: - forming a second portion (214A, 214B) of the base (214) on the second portion (213C) of the collector, at least partially in the cavity (222); and - forming a region of an emitter (215) opposite the second portion (214A, 214B) of the base, the emitter being doped with the first conductivity type.

3. The method of claim 2, further comprising forming insulating spacers (236) between the second portion (214A, 214B) of the base (214) and the emitter region (215).

4. The method of claim 2 or 3, further comprising: - removing the at least one insulating layer (240); - the growth, for example epitaxial growth, of conduction layer (233) and of the second part (214A, 214B) of the base so as to increase the thickness of said conduction layer, and fill the opening (233A), forming an extended conduction layer (233') in contact with the second part of the base; and - the removal, for example etching, of a peripheral lateral portion of the extended conduction layer (233') so as to form the first part (214C) of the base in contact with the second part of the base.

5. Method according to any one of claims 1 to 4, wherein: - the cavity (222) is substantially centered relative to the opening (233A); and / or - a distance (D) between the cavity (222) and the opening (233A) is greater than or equal to minus 20 nm, for example greater than or equal to 30 nm; and / or - the first width (L1) is greater than or equal to 200 nm, for example greater than or equal to 300 nm.

6. Method according to any one of claims 1 to 5, in which the second part (213C) of the collector: - is made of a semiconductor material similar to the material of the semiconductor layer (210); and / or - has a doping lower than the doping of at least a first region (213A) of the first part of the collector; and / or - is formed by epitaxial growth; and / or - extends up to the limit between the first insulating region (231, 232) and the conduction layer (233), or even below said limit.

7. A method according to any one of claims 1 to 6, wherein the at least one insulating layer (240) comprises a third insulating layer (241) of a second insulating material different from the first insulating material, for example a silicon nitride, on the conduction layer (233) and in the opening (233A).

8. A method according to any one of claims 1 to 7, wherein the at least one insulating layer (240) is a stack which comprises alternating insulating layers of two different insulating materials, for example the stack comprises a third insulating layer (241) made of a second insulating material different from the first insulating material, for example a silicon nitride, on the conduction layer (233) and in the opening (233A), and a fourth layer insulating (242) made of the first insulating material, for example a silicon oxide, on the third insulating layer.

9. A method according to any one of claims 1 to 8, wherein the first width (L1) is between 200 nm and 1 pm, and the second width (L2) is between 150 and 950 nm.

10. A bipolar transistor (201) comprising: - a semiconductor layer (210); - a collector (213), a base (214) and an emitter (215) formed in and on the semiconductor layer, the collector and the emitter being doped with a first conductivity type, and the base being doped with the second conductivity type opposite to the first conductivity type; the collector comprising a first portion (213A, 213B) in the semiconductor layer (210); - a first insulating region (221) comprising a first insulating material, said insulating region being between the first portion of the collector and the base (214); - a cavity (222) extending into the insulating region (221) to a portion of the first portion (213A, 213B) of the collector; - a second part (213C) of the collector in the cavity (222) in contact with the portion of the first part of the collector;- a first portion (214C) of the base on the insulating region (221) on either side of the cavity; - a second portion (214A, 214B) of the base on the second portion (213C) of the collector, the second portion of the base being located at least partially in the cavity (222); and - a region of an emitter (215) opposite the second portion (214A, 214B) of the base; the base (214) comprising notches (214E) made of a semiconductor material of the second portion (214A, 214B) of the base in the insulating region (221), between the second portion of the base and the first portion (214C) of the base.;

11. A bipolar transistor according to claim 10, wherein: - the first part of the collector comprises a first collector region (213A) which has a first thickness (El) and which extends to a first face (210A) of the semiconductor layer (210), and a second collector region (213B) which has a second thickness (E2) less than the first thickness and which does not extend to the first face of the semiconductor layer conductor, the first collector region being in contact with at least one end of the second collector region, the second collector region (213B) including the portion of the first part of the collector; and - the first insulating region comprises a first insulating layer (231) on the second collector region (213B) and in the semiconductor layer (210), said first insulating layer extending to the first face (210A) of the semiconductor layer (210), and a second insulating layer (232) on the first insulating layer, and for example on the first collector region (213A), the first and second insulating layers being the same first insulating material, for example made of a silicon oxide.

12. The bipolar transistor of claim 11, wherein the first collector region (213A) and the second collector region (213B) are formed on a buried region (211) of the semiconductor layer (210).

13. A bipolar transistor according to claim 11 or 12, wherein the first collector region (213A) surrounds the second collector region (213B).

14. A bipolar transistor according to any one of claims 10 to 13, the bipolar transistor further comprising an insulating trench (220) in the semiconductor layer (210) around the first portion of the collector (213A, 213B).

15. Bipolar transistor according to any one of claims 10 to 14, wherein: - the semiconductor layer (210) is made of silicon; and / or - the first part (214C) of the base (214) is made of polycrystalline silicon doped with the second conductivity type; and / or - the second part of the base comprises at least a first base region (214A) made of a semiconductor material, such as silicon or a silicon-germanium alloy, doped with the second conductivity type, and for example a second base region (214B) made of a semiconductor material, such as silicon, not intentionally doped on the first base region; and / or - the emitter region (215) is made of polycrystalline silicon doped with the first conductivity type.

16. Electronic device (200) comprising at least one bipolar transistor (201) according to any one of claims 10 to 15.

Images