Device for testing a plurality of integrated circuits on a semiconductor wafer

Abstract

Probe card (3002) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), said probe card (3002) comprising: - a plurality of probes (3002a) adapted to ensure a temporary electrical connection with the connectors (2000) of a plurality of integrated circuits (1001) to be tested on a semiconductor wafer (1000); - at least one buffer circuit (4001a) arranged to share the same power supply resource (SC1) of a tester (3004) with the power supply inputs (VCC) of a group of at least four integrated circuits (1001a-d) from among the plurality of integrated circuits (1001) to be tested;- at least one group (4002) of at least four multiplexer circuits (4002a-d) arranged so that the same high-voltage resource (HVC1) of the tester (3004) is shared with a first input of each of the four multiplexer circuits (4002a-d), a different electronic data input / output resource (DC1-4) of the tester (3004) is in electrical communication with a second input of each of the four multiplexer circuits (4002a-d), and the output of each of the four multiplexer circuits (4002a-d) is in electrical communication with a test input / output (SPT) of an integrated circuit (1001a-d) of said group of at least four integrated circuits (1001a-d) from among the plurality of integrated circuits (1001) to be tested.;

Description

Title of the invention: Device for testing a plurality of integrated circuits on a semiconductor wafer technical field

[0001] The present invention relates to a device and a method for testing a plurality of integrated circuits on a semiconductor wafer. Technical background

[0002] In the microelectronics industry, integrated electronic circuits or chips, also called "chips," "integrated circuits," or "dies," are generally manufactured in series and in large quantities on a single semiconductor wafer, particularly a silicon wafer. Integrated circuits can include various elements such as a memory circuit, a microprocessor, a fuse circuit, communication buses, logic circuits such as flip-flops, latches, or buffers, and other input / output interface circuits ("I / O circuits").

[0003] Before being cut and packaged, each integrated circuit undergoes a performance or failure test to verify whether its electrical characteristics conform to the specifications for which it was designed. For example, a performance test may be conducted in which signals in the form of a data frame are sent to the input of the integrated circuit and the response signals at the circuit's output are monitored and analyzed. When the response signals do not conform, the integrated circuit is declared defective and discarded. Alternatively, a static failure test may be conducted in which high voltages and / or currents are applied to the integrated circuits to eliminate those likely to be affected by premature failure.

[0004] It is common practice to conduct performance and failure tests using an automated test equipment (ATE), which is a programmable electronic system whose main function is to implement a test program such as, for example, sending a set of data frames, or voltage and / or current values ​​to the inputs of integrated circuits, and then collecting and analyzing the response signals from said circuits. To perform this function, the tester has input / output ports, called resources (channels), the number of which generally determines the number of integrated circuits it can test simultaneously.

[0005] The automatic tester generally communicates with the integrated circuits under test conditions via an interface card, itself connected to A probe card. The probe card is configured to establish an electrical connection between the interface card and test pads specific to the integrated circuits. The interface card relays and, optionally, preprocesses the signals between the probe card and the tester. When under test conditions by the automated tester, the integrated circuits are often referred to as DUTs (Devices Under Test). They are generally tested in rows directly on the semiconductor wafer.

[0006] The probe card is generally in the form of an electronic card equipped with a plurality of probes or studs, the number and dimensions of which correspond to the density and size of the test connectors specific to the integrated circuits. Their arrangement allows for the redistribution of the electrical signals exchanged between the tester and the integrated circuits via the interface card. In operation, the probe card generally remains fixed, while the wafer containing the integrated circuits is placed beneath the probe card using a movable plate (the "probe") so as to establish electrical contact between the connectors of the integrated circuits in a row of electrical circuits and the probes of the probe card.

[0007] In the semiconductor industry, and more generally in the microelectronics industry, the cost of testers and the time required to conduct integrated circuit performance testing procedures are major concerns in the face of ever-increasing and faster circuit production demands.

[0008] A general trend is to increase the number of integrated circuits tested simultaneously, particularly when the test procedure cycles are especially long. This is the case, for example, with integrated circuits containing non-volatile memory, which require numerous write and erase operations in their test procedures. Today, several dozen or even hundreds of integrated circuits are tested simultaneously in parallel, depending on the available resources of the testers and probe boards. In addition to increasing the number of integrated circuits tested simultaneously, it is also common to optimize test procedures or modify circuit design to reduce test duration.

[0009] US 4956602 A, [AMBER ENGINEERING INC [US]], 11.09.1990 describes a semiconductor wafer whose surface comprises a plurality of integrated circuits and a plurality of multiplexers composed of multiplexing lines located in the wafer's die-cut areas. The integrated circuits are connected to a limited number of test connectors via the multiplexers. A larger number of integrated circuits can be tested in parallel with the same number of test connectors.

[0010] US 6366112 B1 [MICRON TECHNOLOGY INC [US]] 09.10.2001 describes a probe board comprising a multiplexer circuit configured to selectively distribute and transmit test signals from a tester to the integrated circuits of a semiconductor wafer. The multiplexer circuit allows the tester's resources to be distributed across several integrated circuits tested in parallel. The probe board comprises a silicon-based substrate on which contacts are formed by chemical etching. The contacts are sized to make contact with the connectors of the integrated circuits under test. Each multiplexer circuit consists of a plurality of field-effect transistors that select the contacts using control signals. Each multiplexer circuit redistributes the resources of each test site of the tester to multiply the number of integrated circuits that can originally be tested by each test site.

[0011] US 6400173 B1 [HITACHI LTD [JP] 04.06.2002 describes a system for reducing the test time of integrated circuits on a semiconductor wafer. The system comprises a probe board equipped with a plurality of probes spatially arranged so as to be connected to the connectors of the integrated circuits. The probes are connected to a plurality of test circuits included on the probe board. The test circuits are configured to exchange electrical signals with the integrated circuits and generate test results according to a given test program.

[0012] US 2003 074611 Al [TOWER SEMICONDUCTOR LTD [US]] 17.04.2003 describes a system for increasing the number of non-volatile memory integrated circuits that can be tested simultaneously in parallel. The system comprises a tester, a probe board, and an alignment board. The probe board includes a substrate with an auxiliary circuit, a first set of connectors arranged on one of its surfaces and adapted for electrical connection to the tester, and a second set of connectors arranged on its other surface and adapted for electrical connection to connectors arranged on the wafer containing the integrated circuits to be tested. Both sets of connectors are also connected to the auxiliary circuit via switches configured to optionally bypass it.The auxiliary circuitry includes a plurality of self-diagnostic circuits that can be connected in parallel to the integrated circuits on a wafer. This configuration reduces the time required to perform read or erase operations in the non-volatile memory of the integrated circuits. Self-diagnostic circuits can also be directly integrated into the wafer cutting lines containing the integrated circuits under test. They are configured to utilize only a limited number of connectors on the integrated circuits and share some connectors between several circuits, thus increasing the number of circuits that can be tested in parallel.

[0013] US 6903565 B2 [INFINEON TECHNOLOGIES AG [DE]] 07.06.2005 describes a system for testing a plurality of integrated circuits in parallel on a semiconductor wafer. The system comprises a probe board equipped with probes and an interface board. The system includes an external power supply unit for providing a supply voltage to a plurality of integrated circuits. The interface board includes a voltage regulation unit driven by a reference voltage source, and a current limiting unit for measuring the current consumed by the integrated circuits. The current limiting unit is configured to operate an electrical isolation device when the current consumed exceeds a certain threshold.

[0014] WO 2006 083856 A1 [FORMFACTOR INC [US]] 10.08.2006 and WO 2007 146583 A2 [FORMFACTOR INC [US]] 21.12.2007 describe a probe board comprising a circuit for sharing a tester's power supply among four integrated circuits. Each integrated circuit is associated with a voltage regulation module, which allows the integrated circuit to be isolated in case of a current overload. The probe board may include a multiplexer circuit for redirecting the output signals of the integrated circuits to the tester.

[0015] US 8378698 B2 [SAMSUNG ELECTRONICS CO LTD [KR]] 19.02.2013 describes a probe board equipped with tips adapted to make electrical contact with the connectors of a plurality of integrated circuits on a semiconductor wafer. The probe board comprises a plurality of test circuits, each test circuit itself comprising a plurality of signal transmitters corresponding to an integrated circuit to be tested on the semiconductor wafer. The electrical voltages and control signals of a tester are relayed by the signal transmitters and sent to the integrated circuits. The signal transmitters are further configured to relay the response signals from the integrated circuits to the tester.

[0016] US 2016011232 Al [INFINEON TECHNOLOGIES AG [DE]] 14.01.2016 describes a system for increasing the number of integrated circuits that can be tested simultaneously in parallel without increasing the number of tester resources. The system comprises a tester, an interface card, and a probe card in the form of a circuit with a plurality of connectors adapted to be connected to a plurality of integrated circuits. The probe card circuit is configured to exchange an identical instruction with all the integrated circuits to which it is connected and to exchange an instruction with the tester via the interface card.

[0017] US 2022 341991 A1 [WINBOND ELECTRONICS CORP [TW]] 27.10.2022 describes a system for the number of integrated circuits that can be tested simultaneously in parallel by sharing the available resources of a tester. The system includes a tester and a test device consisting of an interface circuit and a circuit Analysis circuitry. The interface circuit is simultaneously connected to four integrated circuits under test on a silicon wafer and allows signals to be transmitted from the tester to the integrated circuits. The interface circuit includes a buffer circuit coupled to the four integrated circuits under test and the design circuit. The buffer circuit redistributes the tester's power supply among the four circuits, as well as the control and input / output signals. The analysis circuit receives and serializes the output signals from the four integrated circuits using flip-flop circuits before sending them to the tester. Summary of the invention Technical problem

[0018] A significant trend in the microelectronics industry is the development of low-power integrated circuits to reduce their energy consumption. Specifically, this trend translates into a decrease in the operating voltages and currents of integrated circuits. For example, in the field of smart cards, development efforts are currently focused on Class B and C integrated circuits as defined by ISO / IEC 7816-3:2006, i.e., integrated circuits with operating voltages and currents below 3.3 V and 50 mA for Class B, and below 1.98 V and 30 mA for Class C, respectively.

[0019] A direct consequence of this trend is the priority given to developing testers adapted to this type of integrated circuit, and, due to the high costs and technical constraints of installing such testers, their preferential deployment within semiconductor foundries, particularly in shared foundries ("open foundries"). In other words, "high-power" testers for electronic circuits with high operating voltages, such as, for example, Class A integrated circuits in the field of smart cards, are becoming less and less available in foundries. Either they are being progressively replaced by "low-power" testers in existing foundries, or they are no longer being deployed in newer foundries.

[0020] Despite the general trend towards low-power electronics, there remains a need for manufacturing high-power integrated circuits – for example, Class A integrated circuits in the field of smart cards. However, implementing performance and failure tests, particularly static failure tests, on this type of integrated circuit requires the use of "high-power" testers, the availability of which is becoming increasingly limited. Furthermore, for cost reasons, it is essential to test the integrated circuits at the production site, i.e., in the foundry. Therefore, there is a need to be able to conducting performance and failure tests on "high power" circuits such as, in particular, class A integrated circuits in the field of smart cards, using testers that are not suitable for carrying out these tests on this type of integrated circuit. Technical solution

[0021] In a first aspect of the invention, a probe card is provided for testing a plurality of integrated circuits on a semiconductor wafer, said probe card comprising: - a plurality of tips adapted to ensure a temporary electrical connection with the connectors of a plurality of integrated circuits to be tested on a semiconductor wafer; - at least one buffer circuit arranged to share a common power supply resource of a tester with the power supply inputs of a group of at least four integrated circuits from among the plurality of integrated circuits to be tested; - at least one group of at least four multiplexer circuits arranged so that the same high-voltage resource of the tester is shared with a first input of each of the four multiplexer circuits, a different electronic data input / output resource of the tester is in electrical communication with a second input of each of the four multiplexer circuits, and the output of each of the four multiplexer circuits is in electrical communication with a test input / output of an integrated circuit of said group of at least four integrated circuits from among the plurality of integrated circuits to be tested.

[0022] In particular embodiments, the probe card according to the invention may further comprise one or more of the following features, taken individually or according to all possible technical combinations:

[0023] - each multiplexer circuit in a group of multiplexer circuits is configured to simultaneously connect the high-voltage resource of the tester with the test input / output of each integrated circuit in the group of at least four integrated circuits from the plurality of integrated circuits to be tested according to a first control signal value.

[0024] - each multiplexer circuit in a group of multiplexer circuits is configured to sequentially connect the high-voltage resource of the tester with the test input / output of each integrated circuit in the group of at least four integrated circuits from the plurality of integrated circuits to be tested according to a second control signal value.

[0025] - each multiplexer circuit in a group of multiplexer circuits is configured to simultaneously connect an electronic resource of the tester with the input / test output of each integrated circuit in the group of at least four integrated circuits from the plurality of integrated circuits to be tested as a function of a third control signal value.

[0026] - the first value of the control signal corresponds to a static failure test integrated circuits to be tested by applying an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0027] - the second value of the control signal corresponds to a circuit measurement test integrated to be tested with an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0028] - the third value of the control signal corresponds to a current measurement of the integrated circuits to be tested with an electrical voltage below a threshold value, preferably below a fixed threshold value of 4.5V.

[0029] - the buffer circuits and / or the groups of multiplexer circuits are integrated into an interface card in electrical communication with said probe card.

[0030] - the probe card is further adapted to be in electrical communication with a Class B and / or C integrated circuit tester, and a plurality of class A integrated circuits to be tested according to ISO / IEC 7816-3:2006.

[0031] - the probe card is further adapted to be in electrical communication with a tester configured to test solid-state mass storage and / or RAM type architectures.

[0032] In a second aspect of the invention, a system is provided comprising a tester and a probe card according to the first aspect of the invention.

[0033] In a third aspect of the invention, alternative or complementary methods are provided for testing a plurality of integrated circuits on a semiconductor wafer, in particular: - A method for testing a plurality of integrated circuits on a semiconductor wafer, said method comprises the following steps: - share a tester's power supply resource with the power supply inputs of a group of at least four integrated circuits from among the plurality of integrated circuits to be tested; - connect in parallel the same high-voltage resource of said tester with a test input / output of each integrated circuit of a group of at least four integrated circuits from among the plurality of integrated circuits to be tested; - apply an electrical voltage greater than a threshold value on the test input / output of each integrated circuit of said at least four integrated circuits; - verify the operation of each of the integrated circuits by analyzing the response signals via their respective test input / output. - A method for testing a plurality of integrated circuits on a semiconductor wafer, said method comprises the following steps: - sequentially connect a high-voltage resource of said tester with a test input / output of each integrated circuit in a group of at least four integrated circuits from among the plurality of integrated circuits to be tested; - sequentially apply an electrical voltage greater than a threshold value to the test input / output of each integrated circuit of said group of at least four integrated circuits; - sequentially measure the response of each of the integrated circuits by analyzing the response signals via their respective test input / output. - A method for testing a plurality of integrated circuits on a semiconductor wafer, said method comprises the following steps: - connect in parallel an electronic data input / output resource of said tester with a test input / output of each integrated circuit of a group of at least four integrated circuits from among the plurality of integrated circuits to be tested; - send in parallel a data frame on the test input / output of each integrated circuit of said group of at least four integrated circuits; - receive in parallel a response data frame from each of the integrated circuits by analyzing the response signals via their respective test input / output.

[0034] In a fourth aspect of the invention, a computer program is provided comprising instructions which, when the program is executed by a computer, lead the computer to implement one of the methods according to the third aspect of the invention using a system according to the second aspect. Brief description of the drawings

[0035] [Fig-1] a schematic representation of a semiconductor wafer on which are made up of integrated circuits.

[0036] [Fig.2] a schematic representation of a group of four integrated circuits.

[0037] [Fig.3] a schematic representation of a performance testing system and Integrated circuit failure on semiconductor wafer.

[0038] [Fig.4] is a structural diagram of a probe card according to the first aspect of the invention.

[0039] [Fig.5] is a functional diagram of a probe card according to a first mode of realization.

[0040] [Fig.6] is a functional diagram of a probe card according to a second mode of realization.

[0041] [Fig.7] is a functional diagram of a probe card according to a third mode of realization. Detailed description of the implementation methods

[0042] With reference to [Fig. 1], integrated circuits 1001, also called electronic chips, are generally manufactured in series and in large quantities on a single semiconductor wafer 1000. Their arrangement is often in a Hippodamian plane in which the circuits are arranged in columns 1002a-n and rows 1003a-n so as to facilitate their identification and allow several to be tested in parallel during performance and failure tests.

[0043] In the context of the present invention, "integrated circuit" means an indivisible set of electrically interconnected electronic components inseparably linked on a semiconductor substrate. The integrated circuit implements, through its components, logic operations for processing electromagnetic signals, particularly electrical signals. It may be a programmable microcontroller or one or more sub-elements such as a microprocessor, random access memory (RAM), read-only memory (ROM), a fuse circuit, communication buses, logic circuits such as flip-flops, latches, or buffers, and other input / output interface circuits ("FO circuits").

[0044] With reference to [Fig. 2], an integrated circuit 1001 comprises a number of VCC, DQ, and SPT inputs / outputs. Some of these VCC and DQ inputs / outputs can be used during performance and failure testing procedures, and subsequently during the implementation and use of the integrated circuits in electronic devices. Other SPT inputs / outputs are solely dedicated to performance and failure testing procedures. The inputs / outputs have different functions. In the example of [Fig. 2], the VCC input / output is a power supply input, the DQ input / output is a data exchange input / output for subsequent use of the circuit in electronic devices, and the SPT input / output is an input / output exclusively dedicated to the performance and failure testing procedures of the circuit 1001.

[0045] On the 1000 wafer, the input / output pins of the circuits are connected to 2000 connectors (“pads”) to allow their connection with the pins of a card probes are used during performance and failure testing procedures. These connectors may be dedicated solely to testing procedures and not intended for use in the electronic device in which the circuit will be subsequently implemented. They may be placed in the wafer's die-cut areas for removal during circuit packaging, or simply retained in the electronic device during packaging but left unused.

[0046] With reference to [Fig.3], a performance and failure testing system 3000 for integrated circuits 1001 on a semiconductor wafer 1000 comprises a mobile holder or probe 3001 for the semiconductor wafer, a probe card 3002, an interface card 3003 and an automatic tester (ATE) 3004. The probe card 3002 has the form of an electronic card with a plurality of probes or studs 3002a. The 3002 probes are made in contact with the test connectors (not shown) specific to the integrated circuits 1001 and allow the redistribution of the electrical signals exchanged between the tester 3004 and the integrated circuits 1001 via the interface board 3003. Their number and dimensions correspond to the density and size of the test connectors of the integrated circuits 1001.

[0047] During system operation, the probe board 3002 generally remains fixed while the wafer 1000 containing the integrated circuits 1001 is placed beneath the probe board by the support 3001 so as to establish electrical contact between the connectors 2000 of the integrated circuits 1001 in a row of electrical circuits and the probe tips 3002a of the probe board 3002. Each test connector of an integrated circuit 1001 is thus electrically connected to a resource 3004a of the tester 3004. By way of example, with reference to [Fig. 2], the VCC input / output can be electrically connected to a power supply resource of the tester, and the SPT input / output can be electrically connected to a high-voltage resource or an electronic resource of the tester. The number of resources of the tester generally determines the number of integrated circuits it is capable of testing simultaneously.

[0048] In the context of the present invention, the "resources" ("channel") of a tester means the inputs and outputs of the tester that allow the exchange of a set of data frames with electronic circuits, and / or the application of voltage and / or electrical current values ​​to the input of integrated circuits.

[0049] In the context of the present invention, the term "power supply resource" of a tester means a resource capable of delivering sufficient voltage and / or electrical current to power and start an integrated circuit. The term "electronic resource" means a resource enabling the exchange of a frame of data between the tester and a connector on an integrated circuit. A tester's "high-voltage resource" is defined as a resource capable of delivering a higher voltage than one of its electronic resources. Specifically, this type of resource can deliver voltages of several tens of volts, for example, up to 30 volts.

[0050] As illustrated in [Fig.3], the probe card 3002 includes a set of electrical circuits 3002b whose function is to distribute the resources of the tester to the connectors of the integrated circuits via the interface card.

[0051] In a first aspect of the invention, with reference to [Fig. 3] & 4, a probe card 3002 is provided for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000, said probe card 3002 comprising: - a plurality of 3002a tips adapted to ensure a temporary electrical connection with the 2000 connectors of a plurality of 1001 integrated circuits to be tested on a 1000 semiconductor wafer; - at least one buffer circuit 4001a arranged to share a common SCI power supply resource of a tester 3004 with the VCC power supply inputs of a group of at least four lOOla-d integrated circuits from among the plurality of integrated circuits 1001 to be tested; - at least one group 4002 of at least four 4002a-d multiplexer circuits arranged so that the same high-voltage resource HVC1 of the tester 3004 is shared with a first input of each of the four 4002a-d multiplexer circuits, a different electronic data input / output resource DC1-4 of the tester 3004 is in electrical communication with a second input of each of the four 4002a-d multiplexer circuits, and the output of each of the four 4002a-d multiplexer circuits is in electrical communication with an SPT test input / output of a lOOla-d integrated circuit of said group of at least four lOOla-d integrated circuits from among the plurality of integrated circuits 1001 to be tested.

[0052] For illustrative purposes, in [Fig. 4], two buffer circuits 4001a, 4001b and two groups 4002, 4003 of multiplexer circuits are shown. The number of buffer circuits and groups of multiplexer circuits depends on the number of high-voltage resources of the tester 3004. For example, for a tester such as the Magnum V EV marketed by Teradyne Inc.®, comprising 512 electronic resources, 128 high-voltage resources, and 128 power supply resources, the number of buffer circuits and groups of multiplexer circuits can reach 512. The probe board 3002 according to the first aspect of the invention can be implemented with other types of testers, in particular with testers comprising 1024 electronic resources, 256 high-voltage resources, and 256 power supply resources. The number of integrated circuits that can be tested simultaneously at the aid of the probe card according to the first aspect of the invention can then reach 1024.

[0053] The number of integrated circuits per buffer circuit and per group of multiplexer circuits is at least four, with one multiplexer circuit per integrated circuit. Thus, in the configuration of the preceding example, a 3002 probe card according to the first aspect of the invention can test 512 integrated circuits simultaneously thanks to the sharing of the tester's power supply and high-voltage resources. The number of integrated circuits per buffer circuit and per group of multiplexer circuits can be higher. It can be equal to a power N of 2, where N is greater than 2.

[0054] A notable advantage of a probe card according to the first aspect of the invention is the ability to perform static tests on integrated circuits, particularly Class A integrated circuits in the field of smart cards, using testers that are not suitable for performing such tests on this type of integrated circuit. In the preceding example, the electrical voltage delivered by the electronic resources of the Magnum V tester is suitable for Class B and C integrated circuits. The probe card according to the first aspect of the invention makes it possible to use such a tester on a Class A integrated circuit, in particular for static performance or failure testing of non-volatile memory elements, for example Flash, of the integrated circuits.

[0055] The multiplexer circuits 4002a-d, 4003a-d of each group 4002, 4003 are configured to propagate one of their inputs to their output depending on the value of a control signal CS1, CS2. This operation can be performed differently depending on the nature of the test implemented on the integrated circuits.

[0056] According to a first embodiment, with reference to [Fig.5], each multiplexer circuit of a group 4002 of multiplexer circuits 4002a-d is configured to simultaneously connect the high-voltage resource HVC1 of the tester 3004 with the test input / output SPT of each integrated circuit of the group of at least four 1001-d integrated circuits among the plurality of integrated circuits 1001 to be tested according to a first control signal value CSL. According to a first control signal value CS1, the multiplexer circuits 4002a-d of the group 4002 simultaneously, therefore in parallel, propagate the same high-voltage resource HVC1 on their output to the test input / output SPT of each 1001-d integrated circuit.

[0057] This first embodiment is particularly suitable for implementing static failure tests on integrated circuits, especially on the memory elements of class A integrated circuits. Thus, according to a preferred variant, the first value of the control signal CS1 corresponds to a static failure test integrated circuits to be tested by applying an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

[0058] According to a second embodiment, alternative or complementary to the first embodiment, with reference to [Fig. 6], each multiplexer circuit in a group 4002 of multiplexer circuits 4002a-d is configured to sequentially connect the high-voltage resource HVC1 of the tester 3004 with the test input / output SPT of each integrated circuit in the group of at least four 1001-d integrated circuits from among the plurality of integrated circuits 1001 to be tested, according to a second value of the control signal CS1. Depending on a second value of the control signal CS1, the multiplexer circuits 4002a-d in the group 4002 propagate, one after the other, the high-voltage resource HVC1 with the test input / output SPT of the circuits in each 1001-d integrated circuit. The integrated circuits are tested individually, one after the other.

[0059] This second embodiment is particularly suitable for implementing static performance tests on integrated circuits based on the measurement and analysis of a response signal from an integrated circuit. The measurement of the response signal may, in particular, consist of measuring the voltage on the SPT test input / output of each 1001-d integrated circuit. Thus, according to a preferred variant, particularly applicable to class A integrated circuits, the second value of the control signal (SCI) corresponds to a measurement test of the integrated circuits under test with an electrical voltage exceeding a threshold value, preferably exceeding a threshold value set at 4.5V.

[0060] According to a third embodiment, alternative or complementary to the two other previous embodiments, with reference to [Fig.7], each multiplexer circuit of a group 4002 of multiplexer circuits 4002a-d is configured to simultaneously connect an electronic resource EC1-4 of the tester 3004 with the test input / output SPT of each integrated circuit of the group of at least four 1001-d integrated circuits among the plurality of integrated circuits 1001 to be tested according to a third control signal value CSL. According to a third control signal value CS1, the multiplexer circuits 4002a-d simultaneously, and therefore in parallel, propagate an electronic data input / output resource DC1-8 of the tester 3004 to the test input / output SPT of each integrated circuit of the group of at least four 1001-d integrated circuits. A single DC1-8 data input / output electronic resource from the 3004 tester is used for each 1001-d integrated circuit.

[0061] This third embodiment is particularly suitable for implementing routine measurement tests on integrated circuits, such as the exchange of one or more data frames between the tester and the integrated circuits. The data frame(s) may consist of a succession of voltage values, of which The durations and values ​​correspond respectively to time constants and bit values. For example, the tester can communicate, via its electronic resources, instructions to the integrated circuits to perform a series of write and read operations in their memory element. In a preferred variant, the third value of the CS1 control signal corresponds to a current measurement of the integrated circuits under test with an electrical voltage below a threshold value, preferably below a fixed threshold value of 4.5V.

[0062] In all the embodiments and their variants described above, the buffer circuits 4001a, 4001b and the groups 4002, 4003 of multiplexer circuits are part of the probe card 3002. However, in some integrated circuit testing systems 3000 for 1001, such as the one illustrated in [Fig. 3], it may be common to use an interface card 3003 between the tester and the probe card 3002. Also, in some alternative embodiments, the buffer circuits 4001a, 4001b and / or the groups 4002, 4003 of multiplexer circuits are integrated into an interface card 3003 in electrical communication with said probe card 3002.

[0063] A probe card 3002 according to the first aspect of the invention can operate with any type of suitable tester. However, as mentioned previously, an advantage of a probe card 3002 according to the first aspect of the invention is the ability to perform static tests on Class A integrated circuits 1001 in the field of smart cards using testers that are not suitable for performing these tests on this type of integrated circuit. Also, according to preferred embodiments, which can be combined with all the embodiments described above, the probe card 3002 according to the first aspect of the invention is further adapted to be in electrical communication with a tester 3004 for Class B and / or C integrated circuits 1001, and a plurality of Class A integrated circuits to be tested according to ISO / IEC 7816-3:2006.

[0064] A probe card 3002 according to any embodiment of the first aspect of the invention can advantageously be used to test any type of integrated circuit, in particular the non-volatile memory elements of integrated circuits. According to preferred embodiments, it can further be adapted to be in electrical communication with a tester 3004 configured to test semiconductor mass storage architectures, for example flash memory, and / or random access memory architectures.

[0065] In a second aspect of the invention, a system 3000 is provided for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000. The system comprises a probe card 3002 according to the first aspect of the invention and a tester 3004. The tester 3004 can be a class 1001 integrated circuit tester A or a class B and / or C integrated circuit tester as defined in ISO / IEC 7816-3:2006.

[0066] In a third aspect of the invention, several alternative or complementary methods are provided for testing a plurality of integrated circuits on a semiconductor wafer.

[0067] According to a first embodiment, a method is provided for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000, said method comprises the following steps: - share an SCI power supply resource of a 3004 tester with the VCC power supply inputs of a group of at least four lOOla-d integrated circuits from among the plurality of 1001 integrated circuits to be tested; - connect in parallel the same high-voltage HVC1 resource of said tester 3001 with an SPT test input / output of each integrated circuit of a group of at least four lOOla-d integrated circuits from the plurality of integrated circuits 1001 to be tested; - apply an electrical voltage greater than a threshold value on the SPT test input / output of each integrated circuit of said at least four lOOla-d integrated circuits; - verify the operation of each of the lOOla-d integrated circuits by analyzing the response signals via their respective SPT test input / output.

[0068] A method according to this first embodiment simultaneously subjects the integrated circuits to a static failure test by applying a voltage above a threshold value via the sharing of the same high-voltage power supply of the tester. The method is particularly suitable for performing static failure tests on the non-volatile memory elements of Class A integrated circuits. The threshold voltage value can advantageously be set at 4.5V.

[0069] According to a second embodiment, a method is provided for testing a plurality of integrated circuits 1001 on a semiconductor wafer 1000, said method comprises the following steps: - sequentially connect a high-voltage HVC 1 resource of said tester 3004 with an SPT test input / output of each integrated circuit of a group of at least four lOOla-d integrated circuits from the plurality of integrated circuits 1001 to be tested; - sequentially apply an electrical voltage greater than a threshold value on the SPT test input / output of each integrated circuit of said group of at least four lOOla-d integrated circuits; - sequentially measure the response of each of the lOOla-d integrated circuits by analyzing the response signals via their respective SPT test input / output.

[0070] A method according to this second variant successively subjects the integrated circuits to a performance test by applying a voltage above a threshold value via the sequential sharing of the same high-voltage resource of the tester. This method is particularly suitable for implementing static failure tests on non-volatile memory elements of class A integrated circuits. The voltage threshold value can advantageously be set at 4.5V.

[0071] According to a third embodiment, a method is provided for testing a plurality of lOOla-d integrated circuits on a 1000 semiconductor wafer, said method comprises the following steps: - connect in parallel an electronic data input / output resource DC1-4 of said tester 3004 with an SPT test input / output of each integrated circuit of a group of at least four lOOla-d integrated circuits from the plurality of integrated circuits 1001 to be tested; - send in parallel a data frame on the SPT test input / output of each integrated circuit of said group of at least four lOOla-d integrated circuits; - receive in parallel a response data frame from each of the lOOla-d integrated circuits by analyzing the response signals via their respective SPT test input / output.

[0072] A method according to this third variant simultaneously subjects the integrated circuits to a routine measurement test by exchanging a data frame between the tester and the integrated circuits via the tester's electronic resources. For example, the tester can communicate, via its electronic resources, instructions to the integrated circuits, in particular class A integrated circuits, for the execution of a series of write and read operations in their memory element.

[0073] The methods according to the three preceding variants can be implemented alternatively or complementaryly by any means. Preferably, they are implemented using a system according to the second aspect of the invention. They can be implemented by the tester himself or via a data processing device configured to control the tester so that he executes the steps.

[0074] An example of a data processing device is a device that can be responsible for automatically executing sequences of arithmetic or logical operations to perform tasks or actions. This device, also called a computer, may include one or more central processing units (CPUs) and / or one or more graphics processing units (GPUs), as well as at least one control device adapted to perform these operations. It may also include other electronic components such as input / output interfaces, non-volatile or volatile storage devices, and communication buses for transferring data between internal components of the device or with external components. One of the input / output interfaces may be a user interface for human-machine interaction, for example, a graphical user interface for displaying human-understandable information.For the implementation of one or more. methods according to the third aspect of the invention, the device may include an input / output interface in electronic communication with a tester, and optionally a card according to the first aspect of the invention.

[0075] In a fourth aspect of the invention, a computer program is provided comprising instructions which, when the program is executed by a computer, cause the computer, through a system according to the second aspect of the invention, to implement one or more of the methods according to the third aspect of the invention. The program can be stored in the memory of a data processing device as described above and executed by that device. Alternatively, it can be executed by the tester itself after being loaded into memory.

[0076] Any type of programming language, compiled or interpreted, can be used to implement the steps of the method according to the third aspect of the invention in a computer program. The computer program may be part of a software solution, that is to say, a collection of executable instructions, code, scripts or other elements, and / or databases.

[0077] The computer program can be stored on a storage medium readable by the computer or the tester. The storage medium is preferably non-volatile memory, for example, a hard drive or a solid-state drive. It can be removable storage media or non-removable storage media that are part of the computer. It can also be volatile memory within removable media or be part of a computer used as a server from which executable instructions can be downloaded and, when executed by a computer, cause the computer to execute a method according to the third aspect of the invention. References Literature patent

[0078] US 4956602 A, [AMBER ENGINEERING INC [US]], 11.09.1990.

[0079] US 6366112 B1 [MICRON TECHNOLOGY INC [US]] 09.10.2001.

[0080] US 6400173 B1 [HITACHI LTD [JP] 04.06.2002.

[0081] US 2003 074611 Al [TOWER SEMICONDUCTOR LTD [US]] 17.04.2003.

[0082] US 6903565 B2 [INFINEON TECHNOLOGIES AG [DE]] 07.06.2005.

[0083] WO 2006 083856 Al [FORMFACTOR INC [US]] 10.08.2006.

[0084] WO 2007 146583 A2 [FORMFACTOR INC [US]] 21.12.2007.

[0085] US 8378698 B2 [SAMSUNG ELECTRONICS CO LTD [KR]] 19.02.2013.

[0086] US 2016011232 Al [INFINEON TECHNOLOGIES AG [DE]] 14.01.2016.

[0087] US 2022 341991 Al [WINBOND ELECTRONICS CORP [TW]] 27.10.2022. Littérature non-brevet

[0088] ISO / IEC 7816-3 - Identification cards — Integrated circuit cards — Part 3: Cards with contacts — Electrical interface and transmission protocols, 2006.

Claims

Demands

1. Probe card (3002) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), said probe card (3002) comprising: - a plurality of probes (3002a) adapted to provide a temporary electrical connection with the connectors (2000) of a plurality of integrated circuits (1001) to be tested on a semiconductor wafer (1000); - at least one buffer circuit (4001a) arranged to share a common power supply resource (SCI) of a tester (3004) with the power supply inputs (VCC) of a group of at least four integrated circuits (1001-d) from among the plurality of integrated circuits (1001) to be tested;- at least one group (4002) of at least four multiplexer circuits (4002a-d) arranged so that the same high-voltage resource (HVC1) of the tester (3004) is shared with a first input of each of the four multiplexer circuits (4002a-d), a different electronic data input / output resource (DC1-4) of the tester (3004) is in electrical communication with a second input of each of the four multiplexer circuits (4002a-d), and the output of each of the four multiplexer circuits 4002a-d is in electrical communication with a test input / output (SPT) of an integrated circuit (1001a-d) of said group of at least four integrated circuits (1001a-d) from among the plurality of integrated circuits (1001) to be tested.;

2. Probe card (3002) according to claim 1, wherein each multiplexer circuit of a group (4002) of multiplexer circuits (4002a-d) is configured to simultaneously connect the high-voltage resource (HVC1) of the tester (3004) with the test input / output (SPT) of each integrated circuit of the group of at least four integrated circuits (1001a-d) among the plurality of integrated circuits (1001) to be tested as a function of a first control signal value (CS1).

3. Probe card according to any one of claims 1 to 2, wherein each multiplexer circuit of a group (4002) of multiplexer circuits (4002a-d) is configured to sequentially connect the high-voltage resource (HVC1) of the tester (3004) with the test input / output (SPT) of each integrated circuit in the group of at least four integrated circuits (lOOla-d) from the plurality of integrated circuits (1001) to be tested as a function of a second control signal value (CS1).

4. Probe card (3002) according to any one of claims 1 to 3, wherein each multiplexer circuit of a group (4002) of multiplexer circuits (4002a-d) is configured to simultaneously connect an electronic resource (EC1-4) of the tester (3004) with the test input / output (SPT) of each integrated circuit in the group of at least four integrated circuits (1001a-d) from among the plurality of integrated circuits 1001 to be tested as a function of a third control signal value (CS1).

5. Probe card (3002) according to claim 2, wherein the first value of the control signal (CS1) corresponds to a static failure test of the integrated circuits to be tested by applying an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

6. Probe card (3002) according to claim 3, wherein the second value of the control signal (CS1) corresponds to a measurement test of the integrated circuits to be tested with an electrical voltage greater than a threshold value, preferably greater than a threshold value set at 4.5V.

7. Probe card (3002) according to claim 4, wherein the third value of the control signal (CS1) corresponds to a current measurement of the integrated circuits to be tested with an electrical voltage below a threshold value, preferably below a fixed threshold value of 4.5V.

8. Probe card (3002) according to any one of claims 1 to 7, such that the buffer circuits (4001a, 4001b) and / or the groups (4002, 4003) of multiplexer circuits are integrated into an interface card (3003) in electrical communication with said probe card (3002).

9. Probe card (3002) according to any one of claims 1 to 8, further adapted to be in electrical communication with a tester (3004) of class B and / or C integrated circuits (1001), and a plurality of class A integrated circuits to be tested according to ISO / IEC 7816-3:2006.

10. Probe card (3002) according to any one of claims 1 to 9, further adapted to be in electrical communication with a tester (3004) configured to test semiconductor mass storage and / or RAM type architectures.

11. System (3000) for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000) comprising a tester (3004) and a probe card (3002) according to any one of claims 1 to 10.

12. A method for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), using a system according to claim 11, said method comprising the following steps: - sharing a power supply resource (SCI) of a tester (3004) with the power supply inputs (VCC) of a group of at least four 1001-d integrated circuits from among the plurality of integrated circuits (1001) to be tested; - connecting in parallel the same high-voltage resource (HVC1) of said tester (3001) with an SPT test input / output of each integrated circuit of a group of at least four 1001-d integrated circuits from among the plurality of integrated circuits (1001) to be tested; - applying an electrical voltage greater than a threshold value to the test input / output (SPT) of each integrated circuit of said at least four 1001-d integrated circuits;- verify the operation of each of the integrated circuits (1001a-d) by analyzing the response signals via their respective test input / output (SPT).

13. A method for testing a plurality of integrated circuits (1001) on a semiconductor wafer (1000), using a system according to claim 11, said method comprising the following steps: - sequentially connecting a high-voltage resource (HVC 1) of said tester (3004) with a test input / output (SPT) of each integrated circuit of a group of at least four integrated circuits (1001-d) from among the plurality of integrated circuits (1001) to be tested; - sequentially applying an electrical voltage greater than a threshold value on the test input / output (SPT) of each integrated circuit of said group of at least four integrated circuits (1001-d); - sequentially measure the response of each of the integrated circuits (lOOla-d) by analyzing the response signals via their respective test input / output (SPT).

14. Method for testing a plurality of integrated circuits (1001-d) on a semiconductor wafer (1000), using a system according to claim 11, said method comprises the following steps: - connecting in parallel an electronic data input / output resource (DC1-4) of said tester (3004) with a test input / output (SPT) of each integrated circuit of a group of at least four integrated circuits (1001-d) among the plurality of integrated circuits (1001) to be tested; - send in parallel a data frame on the test input / output (SPT) of each integrated circuit of said group of at least four integrated circuits (lOOla-d); - receive in parallel a response data frame from each of the integrated circuits (lOOla-d) by analyzing the response signals via their respective test input / output (SPT).

15. A computer program comprising instructions which, when the program is executed by a computer, cause the computer to implement the method according to any one of claims 12 to 14 using a system according to claim 11.

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