Microelectronic device with reduced leakage currents

Abstract

Title: Low Leakage Current Microelectronic Device The invention relates to a field-effect transistor comprising a gate made of a first material, a source, and a drain. The gate, source, and drain are arranged on a substrate having a lower face extending in a transverse plane. The gate, when projected into the transverse plane, has an internal contour forming a closed loop around one of the source and drain components. The other of the source and drain components lies outside the internal contour when projected into the transverse plane. The first material has a hexagonal crystal system. The internal contour of the gate consists of a plurality of portions. Each portion of the internal contour extends, when projected into the transverse plane, along an orientation direction. The orientation directions of two adjacent portions of the internal contour of the gate form an angle of 60°. Figure for the abstract: Fig. 2

Description

Title of the invention: Microelectronic device with reduced leakage currents Technical field

[0001] The present invention relates to the field of microelectronic devices, in particular lateral transistors. It finds, for example, a particularly advantageous application in the field of power electronics. STATE OF THE ART

[0002] One of the main challenges in optimizing the performance of lateral or planar transistors concerns the reduction of leakage currents that can occur between the drain and the source of the transistor on the one hand and between the drain and the gate on the other hand. Several solutions have been developed to reduce these leakage currents.

[0003] A first solution illustrated in [Fig.lA] consists of the implantation of underlying regions 1400 at the ends of the gate 1000. These regions 1400 preferably extend over the entire lateral dimension of the transistor, a dimension extending in the figure in the Y direction. In the typical case of transistors formed, among other things, by an active layer of GaN and a barrier layer of AlGaN, such an implantation makes it possible to prevent the conduction of the 2D gas at the GaN / AlGaN interface. Furthermore, the implantation induces the creation of defects in the active layer (typically GaN) which themselves generate beneficial traps because they make the insulating layer more resistive. This method has proven effective for transistors having applications at ambient temperatures. However, beyond certain temperatures, the implanted species no longer provide sufficient insulation.Furthermore, the higher the temperature, the less effective the traps created by the implantation are. The arrows shown in [Fig.lA] illustrate the residual leakage currents present between the gate 1100, the source 1200 and the drain 1300 despite the isolation by implantation. Thus, at high temperature values ​​of the operating ranges of standard components, for example above 150°C or even below this threshold, if it is desired that the leakage currents remain very low, isolation by implantation is no longer satisfactory. Consequently, this solution is not used for transistors having high temperature applications. Furthermore, the implantation can generate defects in regions of the active layer where these are not desirable because they are harmful during the operation of the device. Thus, this first solution is not optimal.

[0004] Another solution has been developed to reduce leakage currents within a lateral transistor. This solution is notably presented in the document US 2014 / 0327011 Al, a figure of which has been reproduced in [Fig.lB]. It consists of forming the gate 2100 of the transistor according to a closed contour around the source 2200. This solution has the particular advantage of distancing the insulation zone from the active zones of the transistor. However, it appeared that the etching processes used to form the gate 2100 enveloping the source did not make it possible to obtain a uniform quality of the flank 2101 of the gate 2100 located opposite the source 2200. These differences in the quality of the surface state of the gate 2100 result in different insulation capacities from one zone to another of the gate 2100 as well as parasitic transistor effects. Thus, this second solution is not optimal either.

[0005] An objective of the present invention is therefore to propose a solution for improving the performance of a lateral transistor. This solution will advantageously reduce the leakage currents between the drain and the source of a lateral transistor. Preferably, this reduction in leakage currents will be effective at high temperature values ​​of the operating ranges of standard components. SUMMARY

[0006] To achieve this objective, according to one embodiment, a field effect transistor is provided comprising a gate based on a first material, a source and a drain, the gate, the source and the drain being arranged on a substrate having a lower face extending mainly in a transverse plane, the gate having in projection in the transverse plane an internal contour facing the source, the internal contour forming a closed contour around one of the source and the drain, the other of the source and the drain being located outside the internal contour in projection in the transverse plane, the first material having a hexagonal crystal system.The internal contour of the grid consists of a plurality of portions, each portion of the internal contour of the grid extending mainly, in projection in the transverse plane, in a direction of orientation, the directions of orientation of two adjacent portions of the internal contour of the grid together forming an angle substantially equal to 60°.

[0007] The fact that the grid completely surrounds the source makes it possible to isolate the latter from the drain. Furthermore, the particular shape of the grid makes it possible, over the entire periphery of the grid, for its internal contour to be directed along a crystalline plane of the first material. Thus, the surface condition of its internal flank is good and substantially the same over the entire periphery of the grid. It appears that in the prior art, and in particular in document US 2014 / 0327011 A1, the etching used to form the grid is not done along the crystalline planes of the material making up the grid. The internal contour of the grid formed by this etching therefore does not follow these planes and has differences in crystalline orientation. These differences in crystalline orientation create a strong roughness of the internal flank. This roughness has been found to significantly limit the performance of the transistor. The particular shape of the gate proposed in the invention makes it possible to reduce or even avoid these differences in crystal orientation and therefore this roughness. In this way, the insulation properties of the gate are more homogeneous, or even similar, around the entire perimeter of the gate. Leakage currents between the drain and the source and between the gate and the drain are thus reduced or even eliminated. This also limits parasitic transistor phenomena. The performance of the transistor is thus improved.

[0008] Thanks to the invention, it is also possible to avoid having to implement additional process optimizations so that the gate is compliant in all the crystalline directions of the first material. The cost of obtaining the transistor is thus reduced.

[0009] Furthermore, the insulation guaranteed by the gate according to the invention makes it possible not to have to implement another insulation solution, as envisaged in document US 2014 / 0327011 A1, to overcome the insulation defects at the curved zones of the gate. Indeed, to ensure insulation between the source and the drain in all directions of the transverse plane, it is possible to carry out an implantation as defined in the introductory part under the curved zones of the gate. However, such an implantation is accompanied by the drawbacks explained above, in particular very poor temperature resistance. Furthermore, such an implantation generates interface states available for the passage of carriers by tunnel effect through the gate, which increases the leakage currents between the drain and the gate and between the source and the drain.

[0010] It might seem conceivable, drawing inspiration from techniques sometimes used in the silicon-based transistor technology industry, to produce, by etching and then filling, isolation trenches under the curved areas of the gate to ensure isolation between the source and the drain. However, the integration of lithography, etching and filling steps to form these trenches would not only prove complex but would also generate significant additional costs.

[0011] Thus, the present invention proposes a solution allowing a significant reduction in leakage currents within a lateral transistor. The transistor according to the invention thus has improved performance compared to the transistors of the prior art. Furthermore, unlike transistors in which insulation is ensured by implantation, the transistor according to the invention can be used at high temperature. BRIEF DESCRIPTION OF THE FIGURES

[0012] The aims, objects, as well as the characteristics and advantages of the invention will emerge better than the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0013] [Fig.lA] [Fig.lA] is a schematic top view of a first example of a lateral transistor according to the prior art.

[0014] [Fig.lB] [Fig.lB] illustrates a second example of a lateral transistor according to the prior art.

[0015] [Fig.2] Figures 2 to 5 are schematic top views of the side transistor according to the invention. Figures 2 to 4 illustrate embodiments in which the isolation between the drain and the source is provided by the shape of the grid, without additional insulation underlying the grid. Figures 2, 3A and 3B illustrate examples in which the internal contour of the grid has six portions.

[0016] [Fig.3A] Figures 3A and 3B illustrate embodiments including field effect plates around the grid and the source.

[0017] [Fig.3B]

[0018] [Fig.4] [Fig.4] illustrates an example in which the internal contour of the grid presents ten portions.

[0019] [Fig.5] [Fig.5] illustrates an embodiment in which the insulation between the drain and the source is completed by an insulation underlying the grid.

[0020] [Fig.6] [Fig.6] illustrates two sectional views of the transistor according to the invention.

[0021] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0022] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0023] According to a preferred embodiment, the transistor further comprises an insulating region, the insulating region being located, in projection in the transverse plane, at a distance dmin from the gate with dmin>0 and preferably dmin>100nm. This isolation region makes it possible in particular to electrically isolate the transistor from a neighboring transistor manufactured on the same support substrate.

[0024] According to one example, dmin<1000nm.

[0025] According to an advantageous example, the one among the source and the drain being surrounded by the internal contour of the gate has two main flanks each located opposite at least one portion of the internal contour, each main flank of the source being parallel to the at least one portion of the internal contour of which it is located opposite. look. This improves the performance of the transistor, particularly in the on state.

[0026] According to one example, each main flank is located opposite a single portion of the internal contour of the grid.

[0027] According to one example, the internal contour of the grid has at least six portions.

[0028] According to one example, the internal contour of the grid has only six portions.

[0029] According to one example, the internal contour of the grid has at least ten portions and preferably exactly ten servings.

[0030] According to one embodiment, the transistor further comprises an insulating region, the insulating region being located at least partially, in a third direction perpendicular to the transverse plane, under the gate.

[0031] According to one example, the insulating region is an implanted area based on a semiconductor material comprising implantations of an insulating material.

[0032] According to one example, the insulating region is based on an electrically insulating material. This embodiment finds particular application for low temperature applications.

[0033] According to one example, the first material is one of: GaN, AlN, AlGaN, GaO, hexagonal SiC (H-SiC), hexagonal BN (h-BN).

[0034] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0035] A layer may also be composed of several sub-layers of the same material or of different materials.

[0036] A substrate, a layer, a device, “based” on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus a material based on a III-V material may comprise a III-V material with added dopants. Similarly, a GaN-based layer typically comprises GaN and AlGaN or InGaN alloys.

[0037] The term "III-V material" refers to a semiconductor composed of one or more elements from column III and column V of Mendeleev's periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony and phosphorus.

[0038] A reference frame, preferably orthonormal, comprising the axes X, Y, Z is represented in figures 2A to 6. This reference frame is applicable by extension to the other figures.

[0039] In the present patent application, we will preferably speak of thickness for a layer and of height for a structure or a device. The height is taken perpendicular to the transverse plane XY. The thickness is taken in a direction normal to the main extension plane of the layer. Thus, a layer typically has a thickness along Z, when it extends mainly along the transverse plane XY, and a projecting element, for example an isolation trench, has a height along Z. The relative terms “on”, “under”, “underlying” preferably refer to positions taken along the third direction Z.

[0040] The terms “substantially”, “approximately”, “of the order of” mean “to within 10%, preferably to within 5%”.

[0041] The device according to different embodiments of the invention will now be described with reference to Figures 2 to 6.

[0042] The transistor 1 according to the invention comprises a gate 100, a source 200 and a drain 300. The transistor 1 is typically formed in and / or on a substrate 10 which may in particular comprise, stacked in a direction called the third direction Z: a ​​support substrate (not shown), an active layer 20, a barrier layer 30 and a passivation layer 40.

[0043] The substrate 10 has a lower face 12 extending mainly in a plane called the transverse plane XY, defined by a first direction X and a second direction Y. The transverse plane XY is perpendicular to the third direction Z. The substrate 10 also has an upper face 11 of which at least certain portions extend mainly in the transverse plane XY.

[0044] The transistor 1 is of the lateral or planar transistor type. Thus, the gate 100, the source 200 and the drain 300 are located on or opposite the same face of the active layer 20 of the stack. The charge carriers move within the active layer 20 essentially in a plane parallel to a lower face of the active layer 20. Thus, the charge carriers move essentially parallel to the transverse plane XY. They do not pass through the active layer 20 in its thickness, that is to say in the third direction Z.

[0045] The support substrate may, for example, be based on silicon, sapphire, SiC or even poly-SiC.

[0046] The active layer 20 is typically based on a semiconductor material, for example a III-V material, preferably a IILN material, for example GaN or a material of the Ah_xGaxN type (with x varying from 0 to 1).

[0047] The barrier layer 30 may for example be based on a material of the type Al[ xGaxN (with x varying from 0 to 1).

[0048] The passivation layer 40 may for example be based on SiN, SiO, or more generally SiOxNy.

[0049] Furthermore, a dielectric layer 50, also called gate dielectric 50, may be interposed between the gate 100 and the stack 10. This layer 50 is based on a dielectric that may be taken from SiO2, PAIN, Al2O3, Si3N4 and HfO2. In general, this layer 50 may be based on an alloy of the AlSiON or AlSiHfON type, or be composed of a stack of layers based on such an alloy.

[0050] The grid 100 is based on a first material having a hexagonal crystal system. A hexagonal crystal system is a system whose elementary mesh is a right prism with a rhombus base. This rhombus has two opposite angles of 120° and two opposite angles of 60°. Preferably, the first material has a wurtzite structure, which is part of the hexagonal crystal system. The first material is advantageously GaN. It can also be one of the following materials: AIN, AlGaN, H-SiC, GaO, h-BN (hexagonal boron nitride).

[0051] The grid 100, the source 200 and the drain 300 may be made from the same material.

[0052] The transistor 1 furthermore preferably comprises an insulating region 400. This Insulating region 400 may be a region of the stack 10 having undergone ion implantation so as to make it electrically insulating. Alternatively, the insulating region 400 may be based on an insulating material such as an oxide, for example SiO2, AlN, Al2O3, Si3N4 or alloys or multilayers composed of AlSiON. As will be described further on, this region is preferably located at a distance from the gate 100 in projection in the transverse plane XY (Figures 2, 3A, 3B, 4) but it is also conceivable that it is underlying the gate 100 in the third direction Z ([Fig.5]).

[0053] Geometry of the gate and source of the transistor

[0054] The geometry of the grid 100 will now be described with reference to FIGS. 2 to 6. It should be noted that the barrier layer 30 and the passivation layer 40 have not been shown in FIGS. 2 to 5 in order in particular to be able to better visualize the position of the insulating region 400 depending on the embodiments.

[0055] In projection in the transverse plane XY, the grid 100 surrounds either the source 200 or the drain 300. Only the embodiment in which the grid 100 surrounds the source 200 is illustrated in the figures, but it is understood that both embodiments are perfectly conceivable. The remainder of the description refers mainly to the embodiment in which the grid 100 surrounds the source 200 without surrounding the drain 300, but all the characteristics described apply mutatis mutandis to the embodiment in which the grid 100 surrounds the drain 300 without surrounding the source 200.

[0056] More precisely, the grid 100 has an internal flank 101 located opposite the source 200 or the drain 300, depending on the embodiment. The internal flank 101 of the grid 100 may be inclined relative to the third direction Z or parallel to the third direction Z. In projection in the transverse plane XY, the grid 100 has an internal contour 100a located opposite the source 200 (or the drain 300). If the internal flank 101 of the grid 100 is parallel to the third direction Z, then the projection of the internal flank 101 corresponds to this internal contour 100a. If, on the other hand, as is typically the case (see [Fig.6]), the internal flank 101 is inclined, then the internal contour 100a corresponds to the internal edge of the projection of the internal flank 101 in the transverse plane XY.

[0057] When the gate 100 surrounds the source 200, it is therefore possible to find, aligned in the following order, for example along the second direction Y: the drain 300, a part of the gate 100, the source 200, another part of the gate 100, and possibly a second drain 300'. Indeed, it is possible to find successively on the substrate 10 several transistors according to the invention, two adjacent transistors sharing the same drain 300, 300'.

[0058] When the gate surrounds the drain 300, it is possible to find, aligned in the following order, for example along the second direction Y: the source 200, a part of the gate 100, the drain 300, another part of the gate 100, and possibly a second gate. Indeed, it is possible to find successively on the substrate 10 several transistors according to the invention, two adjacent transistors sharing the same source.

[0059] The internal contour 100a has a plurality of portions or sections 110a, 120a, 130a, 140a, 150a, 160a. These portions are rectilinear. They are juxtaposed with each other to form a continuous contour. Together they form the closed contour defined by the internal contour 100a.

[0060] Each of the portions 110a, 120a, 130a, 140a, 150a, 160a of the internal contour 100a extends mainly in an orientation direction 110b, 120b, 130b, 140b, 150b, 160b. The orientation directions of two adjacent portions of the internal contour 100a together form an angle of 60°. This condition is respected over the entire periphery of the internal contour 100a, that is to say for all the portions of this contour 100a. This angle formed by the orientation directions does not necessarily correspond to the angle formed by the adjacent portions considered facing the source 200 (when the source 200 is surrounded by the grid 100): it may be its supplement. The internal angles of the polygon defined by the internal contour 100a of the grid 100 can thus be approximately 60°, 120°, 240° or 300°. Internal angles of 120° or 240° will be preferred.In all cases, the orientation directions of adjacent portions considered form an angle of 60° (as well as an additional angle of 120°).

[0061] Considering only the internal angles of the polygon defined by the internal contour 100a, the orientation directions of two adjacent portions of this contour 100a together form an angle substantially equal to 60°*N, N being taken from the values ​​1, 2, 4 or 5. Preferably, N is taken from the values ​​2 and 4.

[0062] This particular shape of the grid 100 is modeled on the shape of the elementary mesh of a material belonging to the hexagonal crystal system. By ensuring that the internal contour 100a only forms angles that are multiples of 60°, it is limited or even avoided that, during the structuring etching of the grid 100, elementary meshes are cut. The internal flank 101 of the grid 100 thus has a low roughness, which makes it possible to improve the insulation provided by the grid between the source 200 and the drain 300. This reduces the leakage currents between the source 200 and the drain 300 to an unexpected extent.

[0063] It should be noted that the orientation of the crystal lattice of the material constituting a substrate is always known thanks to one or two flats formed during their manufacture. The precision of this indication on the real angle of the mesh is excellent (<1°). Furthermore, current lithography processes are of very high angular precision. Thus, the person skilled in the art will know, by aligning in a completely usual manner with the substrate the lithography mask(s) used to produce the grid, how to align the shape of the latter with the crystal orientation of the substrate in which the transistor is formed. In particular, the prismatic planes of the hexagonal structure of the material constituting the grid can be very easily aligned, in projection in the XY plane, with the different portions of the internal contour 100a.

[0064] In [Fig.2], the portions adjacent in pairs are identified by the references: 110a and 120a, 120a and 130a, 130a and 140a, 140a and 150a, 150a and 160a, 160a and 110a. In [Fig.4], the portions adjacent in pairs are identified by the references: 110a and 120a, 120a and 130a, 130a and 170a, 170a and 180a, 180a and 140a, 140a and 190a, 190a and 195a, 195a and 150a, 150a and 160a, 160a and 110a.

[0065] The grid 100 typically has a plurality of portions 110, 120, 130, 140, 150, 160 in continuity with each other. Each of these portions 110, 120, 130, 140, 150, 160 extends from a portion of the flank 101 of the grid 100 defining, in projection in the transverse plane XY, a portion 110a, 120a, 130a, 140a, 150a, 160a of the internal contour 100a. These portions are further delimited by an external flank 102 of the grid 100, opposite its internal flank 101. The external flank 102 is typically inclined relative to the third direction Z. The grid 100 thus typically has a flared shape, with a width increasing as it approaches the upper face 11 of the substrate 10.

[0066] The width of the grid 100 can be measured, in any plane perpendicular to the third direction Z, between the internal flank 101 and the external flank 102, perpendicular broadly to a direction tangent to the grid 100. Preferably, for any plane perpendicular to the third direction Z, the width taken in this plane by the grid 100 is the same in all the portions 110, 120, 130, 140, 150, 160.

[0067] The maximum width Lg of the grid 100 is defined in each of these portions 110, 120, 130, 140, 150, 160. This maximum width Lg corresponds to the maximum value taken along the third direction Z by the width of the portion of the grid considered. Typically, the maximum width Lg of the grid 100 is the same in all its portions 110, 120, 130, 140, 150, 160.

[0068] Thus, preferably, the external contour 102 has the same shape as the internal contour 101. In particular, the portions of the external contour define a closed contour and two adjacent portions of the external contour 101 together form an angle substantially equal to 60°*N, N being taken from the values ​​1, 2, 4 or 5.

[0069] Typically this maximum width Lg is greater than or equal to 0.1 pm, and preferably Lg > 0.3 pm. According to one example Lg < 5 pm, and preferably Lg < 3 pm.

[0070] The source 200 has two main flanks 201, 202, advantageously parallel to each other. Preferably, these main flanks 201, 202 correspond to the long edges of a rectangle formed by projection of the source 200 in the transverse plane XY. These main flanks 201, 202 of the source are advantageously each parallel to a portion 110a, 140a of the internal contour 100a. These portions 110a, 140a can be designated main portions 110a, 140a. The fact that the main flanks 201, 202 and the main portions 110a, 140a are parallel makes it possible to maximize the performance of the transistor 1, in particular in the on state.

[0071] Preferably, the main portions 110a, 140a extend beyond the main flanks 201, 202 in the direction in which these elements 110a, 140a, 201, 202 extend (here the first direction X). Thus, in the direction X, the main portions 110a, 140a of the grid 100 are longer than the main flanks 201, 202 of the source 200. Advantageously, this is the case on either side of the main flanks 201, 202.

[0072] According to an embodiment illustrated in [Fig.2], the internal contour 100a has six portions 110a, 120a, 130a, 140a, 150a, 160a. The internal angles defined by the hexagon formed by the internal contour 100a are then all substantially equal to 120°. The portions of the closed contour 100a are preferably parallel in pairs: 110a and 140a, 120a and 150a, 130a and 160a.

[0073] According to an embodiment illustrated in [Fig.4], the internal contour 100a has ten portions 110a, 120a, 130a, 170a, 180a, 140a, 190a, 195a, 150a, 160a. The internal angles defined by the decagon formed by the internal contour 100a are for some substantially equal to 120° and for others substantially equal to 240°. Advantageously, by traversing the internal contour 100a of the grid 100, the internal angles of the decagon formed by the orientation directions of the successive portions take the following values, in the following order: 120° (formed in part by the orientation direction 110b, 140b of one of the main portions 110a or 140a), 120°, 240°, 120°, 120°, 120°, 120°, 240°, 120°, 120°. The decagon thus formed has an optimized footprint. As illustrated in [Fig.4], an angle of 60° is formed by the orientation directions of all the portions two by two neighboring.

[0074] This embodiment is particularly advantageous when the source 200 has large dimensions, for example a characteristic dimension greater than 2 μm, which can go for example up to 10 μm. As illustrated in [Fig. 4], the source 200 can for example have in projection in the transverse plane XY the shape of a square or a rectangle whose short edges are defined by the projection of the main flanks 201, 202 of the source 200. The characteristic dimension of the source 200 corresponds to the dimension of its long edges in the case of a source 200 of rectangular shape, or of its side in the case of a source 200 of square shape. The two returns to the source 200 formed on the one hand by the portions referenced 130 and 170 and on the other hand by the portions referenced 150 and 195 make it possible to minimize the size of the transistor 1.

[0075] Advantageously, the assembly consisting of the source 200 and the internal contour 100a admits in projection in the transverse plane XY at least one axis of symmetry, and preferably two axes of symmetry. This can be applied to all the embodiments previously described. In the examples illustrated in FIGS. 2 to 5, this assembly admits an axis of symmetry parallel to the first direction X and an axis of symmetry parallel to the second direction Y, which is particularly advantageous.

[0076] Preferably, this is also the case for the assembly consisting of the source 200 and the grid 100.

[0077] Field effect plates

[0078] As illustrated in Figures 3A, 3B and 6, it is possible to integrate one or more field plates 100', 200' into the transistor 1. In particular, it is advantageously provided that the transistor 1 comprises a first field plate 100' adjacent to the gate 100 in the transverse plane XY. This first plate 100' then preferably extends from the gate 100, as illustrated in [Fig.6]. Advantageously, it extends on either side of the grid 100, that is to say on the one hand from its internal flank 101 and on the other hand from its external flank 102. It can be formed from the same material as the grid 100. This first field plate 100' has the effect of reducing the electric fields in the barrier layer 30 and in the passivation layer 40. The dielectric layer 50 preferably extends between the stack 10 and the first field plate 100'.

[0079] Transistor 1 also preferably comprises a second field plate 200' surrounding source 200.

[0080] Figures 3A and 3B illustrate two examples of shapes that can be given to the first field plate 100'. The first field plate 100' preferably has an external contour 102' and an internal contour 101' located on either side of the grid 100, the internal contour 101' of the first field plate 100' being located opposite the source 200.

[0081] According to a first example illustrated in [Fig.3A], the external contour 102' of the first field plate 100' may have a similar and enlarged shape compared to the projection in the transverse plane XY of the external flank 102 of the grid 100. Advantageously, the internal contour 101' of the first field plate 100' has a similar and narrowed shape compared to the internal contour 100a of the grid 100.

[0082] In this example, Lfpg denotes the width of the portion of the first field plate 100' extending on the other side of the grid relative to the source 200. This width Lfpg is measured between the external flank 102 of the grid 100 and the external contour 102' of the first field plate 100', perpendicular to this external contour 102'. This width Lfpg is preferably constant over the entire periphery of the first field plate 100'. Preferably, Lg and Lfpg are substantially equal.

[0083] According to a second example illustrated in [Fig.3B], the external contour 102' of the first field plate 100' may have a rectangular shape in projection in the transverse plane XY. The same may be true for its internal contour 101'.

[0084] It is understood that these two examples are given for information purposes and that other dimensions of the first field plate 100' are possible.

[0085] Insulating region

[0086] As indicated previously, the transistor 1 advantageously comprises an insulating region 400.

[0087] As illustrated in Figures 2, 3A, 3B and 4, this insulating region 400 is preferably located at a distance from the gate 100 in projection in the transverse plane XY. Advantageously, the gate 100, the source 200 and the drain 300 extend entirely between two portions 401, 402 of the insulating region 400.

[0088] In this embodiment, dmin denotes the minimum distance in the transverse plane XY between the insulating region 400 and the gate 100. dmin is greater than or equal to 0 nm, preferably strictly greater than 0 nm, preferably greater than or equal to 100 nm. Typically, in order to limit the size induced by the transistor 1, dmin is less than or equal to 3 pm. dmin is illustrated in [Fig.2].

[0089] In this embodiment, the insulating region 400 makes it possible to isolate the transistor 1 from neighboring transistors manufactured on the same substrate. Furthermore, during the singulation of transistor 1 of these neighboring transistors, the cutting is typically done at the level of the insulating region 400.

[0090] The particular shape of the gate 100 gives the transistor 1 very good insulation between the drain 300 and the source 200. This insulation is sufficiently satisfactory so that it is not necessary to implement another method of insulation between these two elements. The embodiments illustrated in FIGS. 2, 3A, 3B and 4 are therefore perfectly functional and very advantageous from the point of view of the insulation between the source 200 and the drain 300. It is however conceivable that the insulating region 400 extends partially under the gate 100, as illustrated in [Fig.5]. This may be of interest for minimizing the effects of spikes when the contour 100a has internal angles of 60° or 300°.

[0091] In view of the various embodiments previously described, the invention proposes an effective solution for reducing the leakage currents between the drain and the source of a lateral transistor. The performance of this transistor is thus improved.

[0092] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Claims

1. Field effect transistor (1) comprising a gate (100) based on a first material, a source (200) and a drain (300), the gate (100), the source (200) and the drain (300) being arranged on a substrate (10) having a lower face (12) extending mainly in a transverse plane (XY), the gate (100) having in projection in the transverse plane (XY) an internal contour (100a) facing the source (200), the internal contour (100a) forming a closed contour around one of the source (200) and the drain (300), the other of the source (200) and the drain (300) being located outside the internal contour (100a) in projection in the transverse plane (XY), the first material having a hexagonal crystal system, characterized in that the internal contour (100a) of the grid (100) is made up of a plurality of portions (110a, 120a, 130a, 140a, 150a, 160a), each portion (110a, 120a, 130a, 140a, 150a,160a) of the internal contour (100a) of the grid (100) extending mainly, in projection in the transverse plane (XY), in a direction of orientation (110b, 120b, 130b, 140b, 150b, 160b), the directions of orientation of two adjacent portions of the internal contour (100a) of the grid (100) together forming an angle substantially equal to,

2. OR . Transistor (1) according to the preceding claim further comprising an insulating region (400), the insulating region (400) being located, in projection in the transverse plane (XY), at a distance dmin from the gate (100) with dmin>0 and preferably dmin>100nm.

3. Transistor (1) according to the preceding claim in which dmin<1000nm.

4. Transistor (1) according to any one of the preceding claims wherein the one of the source (200) and the drain (300) being surrounded by the internal contour (100a) of the gate (100) has two main flanks (201, 202) each located opposite at least one portion (110a, 140a) of the internal contour (100a), each main flank (201, 202) of the source (200) being parallel to at least one portion (110a, 140a) of the internal contour (100a) which it is located opposite.

5. Transistor (1) according to the preceding claim in which each main flank (201, 202) is located opposite a single portion (110a, 140a) of the internal contour (100a) of the gate (100).

6. Transistor (1) according to any one of the preceding claims wherein the internal contour (100a) of the gate (100) has at least six portions (110a, 120a, 130a, 140a, 150a, 160a).

7. Transistor (1) according to the preceding claim in which the internal contour (100a) of the gate (100) has only six portions (110a, 120a, 130a, 140a, 150a, 160a).

8. Transistor (1) according to any one of claims 1 to 6 wherein the internal contour (100a) of the gate (100) has at least ten portions (110a, 120a, 130a, 140a, 150a, 160a, 170a, 180a, 190a, 195a) and preferably exactly ten portions (110a, 120a, 130a, 140a, 150a, 160a, 170a, 180a, 190a, 195a).

9. Transistor according to any one of claims 1 and 4 to 8 further comprising an insulating region (400), the insulating region (400) being at least partially located, in a third direction (Z) perpendicular to the transverse plane (XY), under the gate (100).

10. A transistor according to any one of claims 2 to 9 wherein the insulating region (400) is based on a semiconductor material comprising implantations of an insulating material.

11. A transistor according to any one of claims 2 to 9 wherein the insulating region (400) is based on an electrically insulating material.

12. Transistor (1) according to any one of the preceding claims wherein the first material is one of: GaN, TAIN, AlGaN, H-SiC, GaO, hexagonal BN (h-BN).

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