QUANTUM DEVICE AND ASSOCIATED MANUFACTURING METHOD

Abstract

One aspect of the invention relates to a quantum device (100) comprising: A semiconductor layer (110) adapted to form a two-dimensional array (115) of quantum dots (1151), the semiconductor layer (110) having a front face (110a), a dielectric (120), arranged on the front face (110a) of the semiconductor layer (110), First gates (131) and second gates (132) for controlling the quantum dots (1151), the first gates (131) and the second gates (132) extending directly over the dielectric (120), each second gate (132) intersecting the first gates (131), Charge detectors (140), each charge detector (140) comprising a conductive island (141), a source (143) and a drain (142), the conductive island (141) of each charge detector (140) being formed between two adjacent first grids (131) and directly on the dielectric (120). Figure to be published with the abstract: Figure 1

Description

Title of the invention: QUANTUM DEVICE AND ASSOCIATED MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of quantum electronics and more particularly of quantum electronic devices and the manufacture of the latter. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] The use of measurable two-level quantum states as information vectors, also called "qubits" for "quantum bits" in English, and the laws of quantum mechanics (superposition, entanglement, measurement) offers the possibility of developing quantum algorithms that surpass certain classes of classical algorithms in performance. To implement them, thousands of qubits are required. Finally, three types of operations must be able to be performed on the qubits: initialization in a known state, manipulation (logic gates on one or more qubits), and reading these qubits.

[0003] Semiconductor technologies capable of enabling the manipulation of qubits include islands, also called quantum dots, made in nanometric-sized confinement structures defined for example electrostatically within a semiconductor layer. Quantum dots ensure the confinement of elementary charges, electrons or holes, and the quantum information is, for example, coded on the spin of these particles.

[0004] For a quantum box to be initialized for example with a single electron or hole, it must be coupled to readout electronics capable of determining the number of charges in the quantum box.

[0005] The use of additional devices coupled to reading electronics, such as charge detectors measured in current or in reflectometry, makes it possible to achieve more efficient detection of the charge number than in-situ detection methods.

[0006] Single Electron Transistors (SET) are among the most efficient charge detectors.

[0007] In general, a SET comprises a quantum island, two charge reservoirs, also called drain and source, and a gate contact.

[0008] The quantum island is connected to each of the reservoirs by at least one junction, for example a tunnel junction, or tunnel coupling.

[0009] The load reservoirs (drain and source) are considered as mechanical materials massive metals whose electrons obey Fermi-Dirac statistics, and the island is, for example, a metal grain whose size is a few nanometers. The gate contact is typically separated from the island by a layer of dielectric material. The tunnel junction is, for example, produced by another layer of dielectric material, called a tunnel junction, arranged so as to separate the island from the charge reservoirs.

[0010] One or more electrodes are further connected to the charge reservoirs and to the gate contact to apply a voltage to these elements.

[0011] The operation of SETs is based on capacitive coupling with the quantum box, a change in the number of charges in the latter being able, for example, to affect the impedance of the SET.

[0012] This detection, or reading, of the resulting charge is generally carried out in current (in transport) or by reflectometry with the use of an LC resonator.

[0013] When the SET is read in current, its drain and its source are polarized independently of each other. In other words, two independent charge reservoirs (source and drain) are necessary. When the SET is read by reflectometry, its drain and its source are polarizable at the same potential, and only one charge reservoir (drain or source) is necessary.

[0014] Integrating SETs as close as possible to the qubits would be advantageous for improving detection sensitivity. However, SETs, and particularly current-read SETs, are costly in terms of size due to the large number of elements that constitute them. Their integration in the qubit plane reduces the number of qubits that can be integrated per unit area, and / or requires longer-range interactions between neighboring qubits to enable interconnectivity to at least 4 nearest neighbors.

[0015] In the absence of a mechanism allowing long-range interaction between qubits, SETs are generally integrated on the periphery of a quantum dot matrix. The disadvantage is that the size of this matrix must be reduced to a few quantum dots per side to allow the qubits arranged in the center of the matrix to be read.

[0016] It is also proposed to integrate and connect the charge detectors in planes different from the plane comprising the quantum dots. In this case, we speak of circuits with non-planar architecture, also called "3D" for "3-dimensional".

[0017] Thus, the patent application FR 3 066 297 proposes a quantum electronic circuit with parallel control, comprising a semiconductor layer receiving a qubit matrix, an electrode network arranged on each side of this semiconductor layer, and a stacked layer on the semiconductor layer comprising a charge detector matrix. Thus, each level, or each layer, of the quantum device is dedicated to a specific function.

[0018] This solution has the advantage that each qubit is connected to at least one charge detector located vertically above it, regardless of the qubit considered in the matrix.

[0019] However, the architecture of this circuit is particularly complex, especially due to the high density of vias and interconnections required to connect the different layers of the device. Therefore, some manufacturing steps may be difficult to implement.

[0020] Thus, there is currently no satisfactory solution for integrating SETs into high-density 2D quantum electronic circuits. There remains a need for a solution for integrating charge detectors measured in transport into two-dimensional quantum dot matrices, which allows good capacitive coupling between these charge detectors and these quantum dots while being simple to implement. Summary of the invention

[0021] The present invention provides a solution to the problems mentioned above by making it possible to reduce, on the electronic chip, the size and complexity of charge detectors read in current.

[0022] More particularly, a first aspect of the invention proposes a quantum device comprising: • A semiconductor layer suitable for forming a two-dimensional matrix of quantum dots, the semiconductor layer having a front face, • A dielectric, placed on the front face of the semiconductor layer, • First grids and second grids to control the boxes quantum, the first grids and the second grids extending directly over the dielectric, each second grid crossing the first grids, the first and second grids defining a network of two-dimensional meshes, each two-dimensional mesh being opposite a quantum box, • Charge detectors, each charge detector comprising a conductive island, a source and a drain, the conductive island of each charge detector being formed at the level of a two-dimensional mesh, between two first adjacent grids and directly on the dielectric.

[0023] Thus, advantageously according to the invention, the conductive island of each charge detector is formed at the same level as that of the first and second grids (the expression “same level” here means between the lower face and the upper face of the first grids). This makes it possible to obtain a compact quantum device. (in terms of height). This also makes it possible to obtain a quantum device that uses only a single semiconductor substrate and whose manufacturing does not require bonding steps.

[0024] In addition, thanks to the conductive island which is placed on the dielectric in a two-dimensional mesh, there is a good capacitive coupling between the quantum dot formed directly above the two-dimensional mesh and the neighboring quantum dots. This proximity improves the sensitivity of the detection of the quantum device. It should be added that the fact of forming the conductive islands between first grids offers the advantage of being able to use these first grids as an alignment reference during the manufacturing steps of the conductive islands. In other words, the first grids make it possible to “self-align” the conductive islands. This self-alignment facilitates these manufacturing steps.

[0025] The quantum device according to the invention thus offers an integration solution compatible with industrial manufacturing processes and the integration of quantum dots on a large scale, while allowing the required proximity between the charge detectors read in current and the quantum dots.

[0026] In addition to the characteristics which have just been mentioned in the preceding paragraph, the quantum device according to the first aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • the drain of each charge detector comprises a conductive via coated with an electrically insulating material, the coated conductive via having one end arranged in contact with a barrier layer arranged directly above the conductive island of said charge detector. • the conductive island of each charge detector is formed in a quantum dot control grid distinct from the first grids, said grid crossing the first grids and extending directly onto the dielectric, said grid having insulating recesses covered with an electrically insulating layer, the insulating recesses being arranged at the intersections of said grid with the first grids, each insulating recess housing a first grid, the insulating recesses defining in said grid a plurality of lower conductive regions extending directly onto the dielectric, and a continuous upper conductive region. • said grid is one of the second grids. • Alternatively, said grid is a third grid of a set of third grids intended to control the chemical potential of the quantum dots, each third grid being arranged directly above the quantum dots formed along a column or a diagonal of the matrix of quantum dots Said grid has an internal structure of a first type comprising: • a tunnel layer covering each insulating recess of said grid, • one lower conductive region out of four extending the upper conductive region towards the dielectric, said lower conductive region out of four defining three complementary lower conductive regions, • the two lower conductive regions located at the ends of the three complementary lower regions being covered with an upper barrier layer, the upper barrier layer being arranged on the tunnel layers, • the lower conductive region located at the center of the three complementary lower conductive regions is extended by a conductive via coated with an electrically insulating material, said conductive via crossing the upper region to the upper barrier layer. a second grid out of two, or a third grid out of two, can then present the internal structure of the first type. the conductive islands are then arranged in a staggered pattern relative to each other. Alternatively, every second grid, or every third grid, may have the internal structure of the first type. Alternatively to the structure of the first type, said grid has an internal structure of a second type comprising: • A barrier layer covering all the lower conductive regions of said grid, the barrier layer being continuous and arranged on the insulating recesses of said grid, • Conductive vias coated with an electrically insulating material passing through the upper conductive region to the barrier layer, each conductive via having one end arranged, for one part, directly above a lower conductive region and, for the other part, directly above an insulating recess adjacent to said lower conductive region, a second grid out of two, or a third grid out of two, can then present the internal structure of the second type. Alternatively, every second grid, or every third grid, may have the internal structure of the first type. • The quantum device may include addressing gates for addressing the drains of the charge detectors, each addressing gate being coupled to the conductive vias located on the same column of the quantum dot matrix. • When said grid has the internal structure of the first or second type, the upper region of said grid is coupled to a voltage source for addressing the sources of the charge detectors formed in said grid. • the quantum device may comprise grids for controlling the chemical potentials of the conductive islands, each control grid extending over one of the first grids and being housed under the insulating recesses of the second grids at the crossings of the first and second grids. • the semiconductor layer includes holes to form the quantum dots, • The holes being arranged directly above the intersections between the first and second grids.

[0027] A second aspect of the invention relates to a method of manufacturing a quantum device comprising charge detectors, each charge detector comprising a conductive island, a drain and a source, the method comprising the following steps: • Providing a semiconductor layer suitable for forming a two-dimensional array of quantum dots, said semiconductor layer having a front face, said semiconductor layer comprising a dielectric disposed on the front face and first gates for controlling the quantum dots, the first gates extending directly over the dielectric, • Coating of the sides and the upper face of each first grid to house each first grid under an insulating recess, • Definition of conductive islands from the first coated grids, each conductive island extending between two adjacent first grids and directly on the dielectric, • Formation, from the defined conductive islands, of second grids to control, with the first grids, the quantum dots, each second grid extending directly on the dielectric and crossing the first grids, the first and second grids forming a two-dimensional mesh network on the dielectric.

[0028] Preferably, the step of defining the conductive islands may comprise the following sub-steps: • Filling with a conductive material the spaces of the dielectric delimited by two first adjacent coated grids, the filling stopping at the height of the insulating recesses, • Formation of a barrier layer over the entire surface obtained after filling, • Structuring the barrier layer to form barrier strips oriented at a predetermined angle relative to the first grids.

[0029] Preferably, the predetermined angle is such that the barrier strips are oriented at 45° relative to the direction of the first grids, the barrier strips extending, in the direction perpendicular to the first grids, over four adjacent conductive strips.

[0030] Preferably, the manufacturing method may comprise, after the step of forming the second gates, a step of producing conductive vias coated with an electrically insulating material, each conductive via passing through an upper region of one of the second gates with a stop on a region of a barrier dielectric strip, the conductive via forming the drain of the conductive island defined vertically above the region of the barrier strip.

[0031] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0032] The figures are presented for information purposes only and in no way limit the invention. • [Fig.l] shows a schematic representation in top view of a quantum device according to a first embodiment of the invention, • [Fig.2] shows a schematic representation in cross-sectional view of the quantum device shown in [Fig.l], • [Fig.3A] shows a first schematic perspective representation of a part of the quantum device shown in [Fig.l], • [Fig.3B] shows a second schematic perspective representation of part of the quantum device shown in [Fig.l], • [Fig.3C] shows a third schematic perspective representation of part of the quantum device shown in [Fig.l], • [Fig.4] shows a schematic representation in cross-sectional view of an alternative quantum device to the quantum device shown in [Fig.l], making it possible to form as many charge detectors as quantum boxes, • [Fig.5] schematically represents in top view an alternative quantum device to the quantum device represented in [Fig.l], allowing the charge detectors to be positioned directly above the boxes quantum, • [Fig.6] schematically represents in top view an alternative quantum device to the quantum device shown in [Fig.5], • [Fig.7] is a block diagram illustrating the sequence of steps in a manufacturing process for the quantum device shown in [Fig.l], • [Fig.8] is a block diagram illustrating a preferred method of implementing the manufacturing process of [Fig.8], • [Fig.9] is a block diagram illustrating a preferred method of implementing the manufacturing process of [Fig.8], • [Fig. 10] is a block diagram illustrating a preferred method of implementing the manufacturing process of [Fig.8], • Figures 11A to 11I illustrate the steps or sub-steps of the manufacturing process shown in [Fig.7], each figure showing a perspective view and a sectional view of one of the steps or sub-steps.

[0033] Unless otherwise specified, the same element appearing in different figures has a single reference. DETAILED DESCRIPTION

[0034] The present invention falls within the context of quantum electronic devices and their manufacturing method. More particularly, the invention aims to enable, via charge detectors read in transport, efficient detection of the charge state of the quantum dots formed on the quantum devices. In particular, again, the invention aims to reduce the space occupied by these charge detectors on the quantum device to provide an architecture making it possible to produce large-scale spin qubits.

[0035] Figures 1, 2, 3 and 4 represent, in a schematic form, a quantum device 100 (also referred to as “device 100” hereinafter) according to a first embodiment.

[0036] [Fig.l] shows, in schematic form, a top view of a part of the quantum device 100 according to this first embodiment.

[0037] [Fig. 2] and Figures 3A to 3C respectively show a cross-sectional view and a perspective view of a first alternative embodiment of the quantum device 100 shown in [Fig. 1].

[0038] [Fig.4] shows a cross-sectional view, along the same sectional plane as that of [Fig.2], of a second variant embodiment of the quantum device 100 of [Fig.1].

[0039] With reference to [Fig.l], and in a manner common to the two embodiment variants illustrated in figures 2, 3 and in [Fig.4], the quantum device 100 extends in a plane {X,Y} and is formed from a semiconductor layer 110. The device 100 further comprises a dielectric 121, first and second gates 131, 132 and charge detectors 140. These elements are described in detail below.

[0040] In the remainder of the description, the terms “thickness” or “height” designate dimensions measured perpendicular to the plane {X; Y}. The expression “lateral dimension” designates a dimension measured in the plane {X; Y}.

[0041] The semiconductor layer 110 has a front face 110a, illustrated in [Fig.2].

[0042] The semiconductor layer 110 is adapted to form a matrix 115 of quantum dots 1151. In other words, the semiconductor layer 110 has characteristics making it possible to form a matrix 115 of quantum dots 1151 within it. These quantum dots are represented by hatched circles in [Fig.l].

[0043] The term “matrix” here designates an arrangement of quantum boxes according to rows 115a and columns 115b (cf. [Fig.l]).

[0044] With reference to [Fig.2] or to figures 3A to 3C, the semiconductor layer 110 has a thickness of between 5 nm and 35 nm and preferably between 10 nm and 20 nm, for example equal to 15 nm.

[0045] The semiconductor layer 110 is preferably a silicon layer 110.

[0046] Preferably, this silicon layer 110 comes from a substrate 10 of the silicon on insulator or SOI type (acronym for “Silicon On insulator” in English).

[0047] Such a substrate 10 is illustrated in [Fig. 2]. It comprises a stack, from bottom to top, of a bulk semiconductor layer 107, an insulating layer 105, and the silicon semiconductor layer 110. The insulating layer 105 is disposed between the bulk semiconductor layer 107 and the semiconductor layer 110. The polarization of such a substrate 10 makes it possible to electrostatically control the confinement of charges in the semiconductor layer 110 and therefore offers an additional level of potential control for the device 100.

[0048] The semiconductor layer 110 may, alternatively, be a solid silicon layer.

[0049] The semiconductor layer 110 may, alternatively, be a semiconductor heterostructure comprising a quantum well or a two-dimensional electron gas (2DEG). Such structures have interfaces with low defect densities, facilitating charge confinement and electrostatic control.

[0050] The semiconductor layer 110 may advantageously have holes 117. These holes 117 are illustrated by white circles in [Fig.l]. These holes 117 may for example be obtained by etching the semiconductor layer 110.

[0051] The holes 117 are preferentially arranged in rows and columns to form a matrix of holes 117. In [Fig.l], the rows of holes 117 are oriented in a first direction X corresponding to the direction of the rows 115a of quantum dots. 1151. Similarly, the columns of holes 117 are oriented in a second direction Y corresponding to the direction of the columns 115b of quantum dots 1151.

[0052] The holes 117 are arranged between the rows and columns of quantum boxes. Preferably, as illustrated in [Fig.l], four holes 117 frame each zone corresponding to a quantum box 1151.

[0053] The diameter of the holes 117 is preferably between 20 nm and 50 nm. Thus, the holes 117 structure the semiconductor layer 110 to confine charges in each non-etched zone, that is to say in the zone corresponding to the quantum box 1151. The presence of the holes 117 thus facilitates the formation of the quantum boxes 1151.

[0054] The dielectric 121 is arranged on the front face 110a of the semiconductor layer 110 and is formed of one or more layers, each layer being formed of a dielectric material (see [Fig.2], figures 3A to 3C, or [Fig.4]).

[0055] Preferably, as shown in [Fig.2], the dielectric 121 is made up of a single layer 120 of dielectric which covers the front face 110a of the semiconductor layer 110. The dielectric layer 120 has a thickness preferably between 5 nm and 10 nm and is electrically insulating. The dielectric layer 120 is for example made of silicon oxide (SiO2).

[0056] According to a variant, not shown in the figures, the dielectric layer 120 may be partially covered, i.e. covered between the first gates 131, by another dielectric layer, called the “second dielectric layer”. According to this variant, the dielectric 121 is then made up of the dielectric layer 120 and the second dielectric layer covering this dielectric layer 120. The second dielectric layer may then be formed from SiO2 or an aluminium oxide (A12O3). The maximum thickness of the second dielectric layer depends on the material chosen: when the material is SiO2, the thickness is for example 5 nm; when the material is AL2O3, the maximum thickness of the spacer layer may be between 10 nm and 15 nm.

[0057] The first grids 131 and the second grids 132 are conductive strips formed from a conductive material chosen from the following materials: doped crystalline silicon (or doped Poly-Si), tungsten (W), titanium nitride (TiN).

[0058] The first grids 131 extend entirely over the dielectric layer 120 of the dielectric 121, in a first direction X, illustrated in [Fig.l], which corresponds to the orientation of the lines 115a of quantum dots 1151.

[0059] Each first grid 131 has a section whose height is preferably between 5 nm and 50 nm, and preferably equal to 25 nm. The dimension lateral and the height of the section are preferably substantially identical. The section of each first grid 131 is then a square section.

[0060] Each first gate 131 is further covered, or coated, on its sides (i.e. its lateral faces) and its upper face (i.e. the face opposite the dielectric layer 120) with a spacer layer 133 (see [Fig.2]). This spacer layer 133 is formed from a dielectric material, for example SiO2 or Al2O3. Its maximum thickness depends on the material chosen: when the material is SiO2, the thickness is for example 5 nm; when the material is Al2O3, the maximum thickness of the spacer layer can be between 10 nm and 15 nm.

[0061] When the dielectric 121 is formed from the dielectric layer 120 and the second dielectric layer, this second dielectric layer and the spacer layer 133 come from a single continuous layer 133. Thus, in this case, the spacer layer 133 extends continuously around the periphery of the first gates and over the dielectric layer 120. This embodiment variant is easier to produce than the variant in which the dielectric 121 consists of the dielectric layer 120 only. Indeed, it is then not necessary to structure the spacer layer 133, once it has been deposited on the first gates 131 and the dielectric layer 120. This variant therefore makes it possible to dispense with an anisotropic etching step of the spacer layer 133 after its deposition (since this etching is not necessary).In return, as will be better understood later, the second grids 132 are a little further away from the semiconductor layer 110 and therefore from the quantum dots 1151. The electrostatic control of the quantum dots as well as the coupling of the charge detectors 140 to the quantum dots 1151 can then be significantly less efficient.

[0062] The second grids 132 are oriented in a second direction Y different from the first direction X. This direction Y corresponds to the direction of the columns 115b of quantum boxes 1151 (cf. [Fig.l]).

[0063] In [Fig.l], the second direction is here oriented at 90° relative to the first direction X. Naturally, this second direction Y can be oriented at an angle other than 90° relative to the first direction X.

[0064] Each second grid 132 extends directly over the dielectric 121, which is therefore a grid dielectric and crosses the first grids 131 at the level of crossing zones (denoted IGi,g2 in [Fig.l]) according to a so-called “nested” configuration.

[0065] This “nested” configuration is described in detail below, in relation to [Fig.2],

[0066] According to this nested configuration, each second grid 132 has a height which is greater than the height of the first grids 131. Preferably, the height of the second grids 132 is greater by 20 nm to 50 nm than that of the first grids 131. The lateral dimension of the second grids is preferably identical to that of the first grids.

[0067] In addition, each second grid 132 extends: • directly on the dielectric 121 (in [Fig.2], this dielectric 121 is the layer 120 of dielectric) between two adjacent first grids (or, in other words, in the spaces between the first grids), and • on the spacer layer 133 covering the sides and the upper face of the first grids at the crossing zones IGi,g2 (see figures 1 and 2).

[0068] In other words, each second grid 132 passes over, or overlaps, the first grids 131 coated with the spacer layer 133 at the crossing zones IGi,g2- This overlapping makes it possible not to physically cut the first grids 131 at the crossing zones IGi,g2-

[0069] Thanks to the spacer layer 133, which is interposed between the first grids 131 and the second grids 132, each second grid 132 crosses the first grids 131 without there being any electrical contact with them.

[0070] Furthermore, since the height of the second grids 132 is greater than that of the first grids 131, we obtain, at the crossing zones IGi,G2, first grids 131 which are housed under insulating recesses of the second grids 132.

[0071] These insulating recesses are visible in [Fig.2] since the cross-section illustrated in this figure is along a section plane passing through a second grid 132 at a crossing zone IGi,G2. These recesses are noted with the reference 133R in [Fig.2]. Each recess 133R forms an insulating bridge under which a first grid 131 passes.

[0072] As shown in [Fig.2], the recesses 133R define in each second grid 132 a lower stage 136, and an upper stage 137 which are conductive.

[0073] The lower stage 136 has a pattern comprising a plurality of lower conductive zones 1361 (these lower conductive zones are also denoted 1361-1, 1361-2, 1362-3, 1361-4 in [Fig.2]).

[0074] Each lower conductive region 1361 is separated from adjacent lower conductive areas by one of the insulating recesses 133R.

[0075] The upper stage 137 forms a continuous upper conductive region 137. The nested configuration therefore makes it possible to maintain electrical continuity along each first grid 131 and along each second grid 132.

[0076] As will be described later in the description, these lower conductive areas 136 and the upper conductive region 137 are advantageously used to form the charge detectors 140.

[0077] As shown in [Fig.l], the arrangement of the first and second grids 131, 132 also makes it possible to define on the surface of the dielectric (here the layer 120 of dielectric) a network of regular spaces (also called “two-dimensional meshes” hereinafter). Each two-dimensional mesh corresponds to the area of ​​a quantum box 1151.

[0078] Each two-dimensional mesh comprises the free dielectric space defined at the intersection between two adjacent first grids and two adjacent second grids and the closed contour formed by the portions of the grids of the intersection.

[0079] In the example of [Fig.l], the X, Y directions of the first and second grids 131, 132 here are orthogonal to each other. The two-dimensional meshes are square in shape.

[0080] The X, Y directions of the first and second grids 131, 132 can alternatively be oriented with an angle other than 90°.

[0081] When the semiconductor layer 110 comprises holes 117 as illustrated in [Fig.l], the X and Y directions of the first grids and second grids also correspond, respectively, to the directions of the rows and columns of holes 117. The first and second grids are, moreover, arranged so that there is a hole 117 opposite each crossing zone Igi,g2- Thus, a hole 117 is arranged at each vertex of the two-dimensional meshes.

[0082] The independent control of each first and second grid 131, 132 makes it possible to electrostatically control and with short-range interactions a quantum box 1151 in each region of the semiconductor layer 110 located directly above a two-dimensional mesh.

[0083] This control is facilitated by the presence of the holes 117 since these make it possible to confine (in a non-electrostatic manner) charges at the level of the regions of the semiconductor layer forming the quantum dots 1151.

[0084] Each region of the semiconductor layer 110 forming a quantum dot has lateral dimensions, defined in the plane {X,Y}, which are preferably between 5 nm and 100 nm, and preferably equal to 50 nm. The thickness of the region of the semiconductor layer 110 forming a quantum dot is furthermore preferably between 5 nm and 30 nm, and preferably equal to 15 nm.

[0085] The distance between two neighboring quantum dots, that is to say two quantum dots formed opposite two neighboring two-dimensional meshes, is preferably between 25 nm and 125 nm.

[0086] More precisely, the control of the first and second grids makes it possible to control by field effect the conduction of tunnel barriers 1152a, 1152b located on either side (along the X and Y directions) of each two-dimensional mesh.

[0087] On the part of [Fig.l] representing an enlarged view of a two-dimensional mesh ional, these tunnel barriers 1152a, 1152b are represented by dotted rectangles. Each tunnel barrier denoted 1152a is here located opposite a second grid 132 and connects the quantum box 115 Cj to the adjacent quantum box 115 lij i (or 115 lij+i) formed on the same row of the two-dimensional mesh network. Each tunnel barrier denoted 1152b is here located opposite a first grid 131 and connects the quantum box 115 Cj to the adjacent quantum box 1151iij (1151i+ij) or formed on the same column of the two-dimensional mesh network.

[0088] The tunnel barriers 1152a, 1152b preferably have lateral dimensions smaller than those of the quantum dots 1151, for example lateral dimensions between 5 nm and 30 nm. Their thickness is, however, similar to that of the quantum dots 1151.

[0089] According to the above, the first grids 131 are arranged directly above first tunnel barriers 1152b, and the second grids are arranged directly above second tunnel barriers 1152a. Each first tunnel barrier 1152b connects two neighboring quantum dots arranged in the same column 115b of the quantum dot matrix, while each second tunnel barrier 1152a connects two neighboring quantum dots arranged in the same row of this matrix 115.

[0090] Each charge detector 140 comprises a conductive quantum island 141 (also referred to as island 141 hereinafter) and two electrically independent charge reservoirs: a drain 142 and a source 143. It should be noted that, in the remainder of the description, drain 142 and source 143 are interchangeable.

[0091] Since the drain and the source are independent, each charge detector 140 can be measured in transport. Such a measurement is for example described in the document “Observation of spin-space quantum transport induced by an atomic quantum point contact” by Koki Ono et al., Nature Communications 12, 2021.

[0092] As shown in Figures 2 and 3A to 3C, the island 141 of each charge detector 140 is formed between two adjacent first grids 131 and directly on the dielectric 121, 120.

[0093] Thus, this island 141 is formed at the same level as that of the first and second grids 131, 132. This makes it possible to obtain a compact quantum device 100 (in terms of height). The expression “at the same level” means that each island 141 is formed between the lower face of the first grids and the upper face of the second grids.

[0094] Furthermore, as will be described later in the description in relation to the manufacturing method, the fact of forming the conductive islands 141 between first grids 131 offers the advantage of being able to use these first grids 131 as an alignment reference mark at the time of the steps of manufacturing the conductive islands 141. In other words, the first grids make it possible to “self-align” the islands 141. This self-alignment facilitates these manufacturing steps.

[0095] Compactness and simplicity of manufacturing are assets for scaling quantum processors.

[0096] In a manner common to the two embodiment variants illustrated respectively in [Fig.2] and 4, each island 141 is formed in one of the lower conductive zones 1361 of a second grid 132. These lower conductive zones 1361 are, as described previously, comprised between two first grids 131.

[0097] The island 141 of each charge detector 140 is thus “placed” on the dielectric directly above a tunnel barrier 1152a and is coupled to one and the other of the quantum dots 1151 arranged, in the plane of the semiconductor layer 110, on either side of this tunnel barrier 1152a. This coupling is shown by arrows on the part of [Fig.l] representing an enlarged view of a two-dimensional mesh. Each charge detector 140 is then shared between at least two quantum dots 1151.

[0098] Several islands 141 are formed in the same second grid 132 (cf. [Fig.2]).

[0099] In this second grid 132, the lower conductive zones 1361 defining an island 141 are covered with a barrier layer 144 (see [Fig.2], in particular the left insert of this [Fig.2]). This barrier layer 144 is arranged within the second grid 132. This barrier layer 144 has the effect of electrically insulating the island 141 from the upper conductive stage 137 and from the other islands 141 of the second grid 132. It also has the effect of allowing the formation of a tunnel current within it.

[0100] All the charge detectors 140 of this second grid have a common source 143, formed by the upper stage 137 of this second grid. The common source 143 is connected by tunnel coupling to each conductive island 141 thanks to the barrier layer 144.

[0101] Finally, each charge detector 140 of this second gate 132 has a drain 142, formed by a conductive via 1421 coated on its sides with an insulating layer 1422. This insulating layer 1422 is formed of an insulating material. For example, it is formed from silicon dioxide SiO2. The insulating layer 1422 of each drain 142 is wide enough to isolate the source 143 from the drain 142. For example, when the insulating layer 1422 is formed from SiO2, its width is 5 nm.

[0102] The coated conductive via 1421 has a lower end 1423 and an opposite upper end 1424. The coated conductive via 1421 passes through the upper stage 137 to the barrier layer 144. At least a portion of the barrier layer 144 is in contact with the lower end 1424 of the conductive via 1421.

[0103] By thus using regions 1361, 137 of the second grid 132 to, on the one hand, form the conductive island 141 and one of the charge reservoirs 143, and, on the other hand, incorporate the other charge reservoir 142, the overall footprint (lateral but also vertical) of the charge detector 140 in the quantum device 100. This therefore makes it possible to obtain a compact device 100, which is advantageous for the scaling of quantum processors.

[0104] The use, in particular, of the upper conductive zone 137 to form / incorporate the charge reservoirs 142, 143 offers an additional advantage for integrating the addressing functions of the charge detectors 140. Indeed, this upper conductive zone 137 is easily accessible for resuming electrical contact from above and / or for resuming electrical contact at the ends of the second grids 132.

[0105] The control of the source 143 can thus be carried out without vertical connection (via type) by one end of a second grid 132 coupled to a voltage source.

[0106] The measurement of the island 141 can be carried out via the upper end 1424 of the conductive via 1421. As shown in FIGS. 2 and 4, a metallization line 146 intended to polarize the drains of the same second gate 132 can extend over the upper ends 1424 of the conductive vias 1421 formed on this second gate 132. In this case, an encapsulation layer 147 is interposed between the metallization line 146 and the upper conductive region 137. This encapsulation layer 147 can be formed from the same material as the layer 1422 covering the conductive vias 1421. Note, in FIGS. 2 and 3, the presence of a hard mask layer 148 interposed between the encapsulation layer 147 and the upper conductive region 137. This hard mask layer 148 is related to the manufacturing process.

[0107] As shown in Figures 2 and 4, the quantum device 100 can also advantageously comprise grids 145 for controlling the chemical potential of the islands 141. These grids 145 are hereinafter called “charge detector control grids 145”.

[0108] Each control grid 145 of the charge detectors 140 is housed under an insulating recess 133R, where it extends over a first grid 131 covered with the spacer 133.

[0109] Each island 141 is then connected to the control grid 145 of the charge detectors via the recesses 133R.

[0110] By thus interposing the control grids 145 of the charge detectors 140 under the recesses 133R of the second grids 132, the number of electrical interconnections to be made to control the charge detectors 140 is reduced. This saved space leads to a quantum device 100 that is more compact than the solutions of the prior art which use superimposed semiconductor planes.

[0111] The number of conductive islands 141 formed in the same second grid 132 depends on the internal structure of this second grid 132.

[0112] According to the first variant embodiment, illustrated in [Fig.2] and in [Fig.3C], the internal structure of the second grid 132 is of a first type making it possible to form an island 141 in one lower conductive region 1361 out of two.

[0113] This first type also makes it possible to connect two adjacent conductive islands 141 to the same drain 142. Thus, there are fewer drains 142 (up to half as many) than charge detectors 140. This makes it possible to reduce the number of elements to be integrated into the quantum device 100 to form the charge detectors 140. This reduction in the number of elements contributes to reducing the footprint of the charge detectors in the quantum device 100.

[0114] According to this first type, the barrier layer 144 comprises a lower barrier layer 1441, also called tunnel layer 1441, and an upper barrier layer 1442.

[0115] The tunnel layer 1441 covers all the recesses 133R at the upper face of the first grids 131.

[0116] For reasons related to the manufacture of the quantum device 100, the tunnel layer 1441 is here interposed between the insulating layer 133 (of the recess 133R) and a hard mask layer 1443 (see [Fig.2]).

[0117] The tunnel layer 1441 has characteristics allowing tunnel coupling to be achieved within it.

[0118] In [Fig.2], the arrows show the direction of the current flowing in each island 141 of a single-electron transistor SET.

[0119] The lateral dimension of the tunnel layer 1441 corresponds to the lateral dimension of the first gate 131. In the example of a first gate with a lateral dimension of 20 nm, the tunnel layer 1441 is sufficiently narrow to allow the passage of a tunnel current.

[0120] The tunnel layer 1441 may be formed of aluminum oxide (A12O3). Alternatively, the tunnel layer 1141 may be a layer of undoped silicon.

[0121] Preferably, the tunnel layer 1441 is formed from a hafnium oxide (HfO2). This material in fact has a programmable resistance to be adjusted to a value between a few kiloohms and a few tens of kiloohms. The tunnel layer 1441 then preferably has a thickness between 5 nm and 10 nm.

[0122] The upper barrier layer 1442 is arranged on the tunnel layers 1441 so that: • a lower conductive region 1361-4 out of four extends the upper conductive region 137 towards the dielectric 121,120 (In [Fig.2], the three complementary regions are noted with the references 1361-1, 1361-2 and 1361-3), and • the lower conductive region 1361-2 located in the center of the three complementary lower conductive regions is extended by the through via 1421,1422 forming the drain 142.

[0123] In the remainder of the description, the lower conductive region 1361-2 located at the center of the three complementary lower conductive regions is called “central lower region 1361-2”, while the two regions located on either side of this central region are called “lateral lower regions 1361-1, 1361-3”.

[0124] The upper barrier layer 1442 thus covers the two lower lateral regions 1361-1, 1361-3.

[0125] On the two recesses 133R surrounding the central lower region 1361-2, the barrier layer 1442 is in contact with the insulating layer 1422 coating the through via 1441.

[0126] The lower lateral regions 1361-1 and 1361-3, covered with the upper barrier layer 1442, each form a conductive island 141.

[0127] The through via 1421 and the central lower region 1361-2 form a continuous conductive region. This forms the drain 142 of the two islands 141 formed in the lower side regions 1361-1 and 1361-3. The tunnel coupling between this drain 142 and the two islands 141 is performed in each of the tunnel layers 1441 arranged on both sides of the central conductive region 1361-2.

[0128] The upper layer 137 (and the lower conductive region 1361-4 that extends towards this upper layer 137) forms the source 143 of the two islands 141 formed in the lower side regions 1361-1 and 1361-3. The tunnel coupling between the source 143 and the two islands 141 is performed in each of the tunnel layers 1441 arranged on the recesses 133 delimiting the three complementary regions.

[0129] In [Fig.2], the drain-island and source-island tunnel couplings are represented by arrows.

[0130] As shown in Figures 3A to 3C, each second grid 132 may have this structure of the first type. Alternatively, a second grid 132 may have this structure of the first type.

[0131] The lower conductive regions 1361-1, 1361-3 chosen to define the islands 141 in a given second grid 132 are preferentially offset relative to those chosen for a neighboring second grid 132.

[0132] In this way, and with reference to [Fig.l], the islands 141 are arranged in a staggered manner relative to each other in the assembly formed by the second grids 132. Consequently, the charge detectors 140 are also arranged in a staggered manner relative to each other. This staggered arrangement makes it possible to guarantee good measurement sensitivity with a reduced number of charge detectors 140.

[0133] According to the second embodiment, illustrated in [Fig.4], the internal structure of the second grid 132 is of a second type making it possible to form an island 141 in each lower conductive region 1361. This second type thus makes it possible, compared to the first type, to double the number of charge detectors 140 formed in the same second grid 132. There are then as many charge detectors 140 as there are quantum dots 1151.

[0134] By thus increasing the number of charge detectors 140, it is possible to measure each quantum box 1151 as close as possible to it. This improves the sensitivity of the measurement of the quantum boxes.

[0135] This second type also makes it possible to connect a drain 142 to each island 141.

[0136] According to this second type, all the lower regions 1361 of the second grid 132 are covered with a barrier layer 144 formed from the tunnel layer 1441 described previously.

[0137] Thus, contrary to the structure of the first type, the tunnel layer 1441 extends both over the recesses 133R (opposite the upper face of the first grids 131) and above the lower conductive regions 1361. The tunnel layer 1441 is thus continuous.

[0138] The conductive vias 1421 coated with an insulating layer 1422 pass through the upper region 137 up to the barrier layer 144.

[0139] The lower end 1423 of each conductive via 1421 is disposed on the barrier layer 144, partly opposite a lower conductive region 1361 and partly opposite a recess 133R adjacent to the lower conductive region 1361. The insulating layer 1422 that coats the conductive via 1421 is in contact with the barrier layer 144.

[0140] Each conductive via 1421 forms the drain 142 of an island 141.

[0141] Furthermore, as for the structure of the first type, the upper conductive zone 137 forms the source 143 of all the islands 141 formed in this second grid 132.

[0142] Figures 5 and 6 show a second embodiment of the quantum device 100.

[0143] The second embodiment differs from the first embodiment, illustrated in Figures 1 to 4, in that the charge detectors 140 are not formed in the second grids 132 but in third grids 135 intended to control the chemical potential of the quantum dots 1151 and, thus, arranged directly above the quantum dots 1151.

[0144] This arrangement allows a more localized measurement of the state of charge of the quantum box 1151 than when the charge detector 140 is directly above a tunnel barrier. Indeed, a charge detector 140 arranged directly above a quantum box is more sensitive to the latter because it is closer than a charge detector arranged at the plumb line of a tunnel barrier. It is, however, less sensitive to neighboring quantum dots.

[0145] The second grids 132 are then covered, on their sides and their upper face, with a layer of insulating material forming a spacer similar to the spacer 133. The spacer 133 then makes it possible to electrically insulate the second grids 132 from the third grids 135.

[0146] The third grids 135 are conductive strips formed from a conductive material similar to that forming the first and second grids 131, 132.

[0147] As shown in Figures 5 and 6, these third grids 135 are distinct from the second grids 132 and are all oriented in a direction different from the first direction X of the first grids 131. In addition, the third grids 135 and extend directly above the quantum dots 1151.

[0148] [Fig.5] shows a first variant embodiment of the second mode of rea lization. According to this first variant, the third grids 135 are oriented at 90° relative to the first grids 131. In addition, each third grid 135 is arranged between two adjacent second grids 132, directly above the quantum dots 1151 arranged on the same column 115b of the matrix 115 of quantum dots.

[0149] The third grids 135 extend directly onto the dielectric (here the dielectric layer 120) and cross the first grids 131 (see [Fig.5]) in a nested configuration similar to the nested configuration described previously (in relation to the second grids 132). The crossing zones between the first grids and the third grids are denoted with the reference IGi>G3 in FIGS. 5 and 6.

[0150] Thus, each third grid 135 extends directly over the dielectric between two adjacent first grids 131 (or, in other words, in the inter-first grid spaces), and passes over, or overlaps, the first grids 131 coated with the spacer layer 133 at the level of the IGi>G3 crossing zones.

[0151] The height of the third grids 135 is greater than that of the second grids 132. Preferably, this height of the third grids is greater by 20 nm to 50 nm than that of the second grids 132.

[0152] This nested configuration makes it possible to define a two-stage structure (a continuous conductive upper stage and a lower stage formed of a plurality of lower conductive regions) analogous to the structure of the second grids 132 of the first embodiment.

[0153] This nested configuration thus makes it possible to form in each third grid 135, or in a third grid 135 out of two, the internal structure described previously in relation to the first embodiment.

[0154] In the example shown in [Fig.5], each third grid 135 has the internal structure of the first type, illustrated in [Fig.2].

[0155] Thus, in these third gates 135, one lower conductive region 1361 out of two forms a conductive island 141. In addition, the upper conductive region 137 forms the common source of all the islands formed in the third gate, and conductive vias coated with the insulating layer form the drains 142.

[0156] This configuration makes it possible to position the conductive islands directly above the quantum dots (unlike the first embodiment, where the islands 141 are directly above the tunnel barriers).

[0157] As in the first embodiment, the islands 141 are arranged in a staggered manner relative to each other.

[0158] Naturally, the third grids 135 can alternatively have the structure of the second type, illustrated in [Fig.4]. In this case, in the third grids 135, each lower conductive region 1361 forms a conductive island 141. A charge detector 140 is then arranged directly above each quantum box 1151.

[0159] [Fig.6] shows a second variant embodiment of the second embodiment. According to this second variant, the third grids are oriented at 45° relative to the first and second grids 131, 132. Each third grid 135 extends directly above the quantum dots arranged on the same diagonal 115c of the matrix 115 of quantum dots.

[0160] The third grids 135 extend directly over the dielectric (here the dielectric layer 120) and cross the first and second grids 131, 132 according to the same nested configuration as that described in relation to the first embodiment variant.

[0161] The crossing zones between the first grids and the third grids Igi.gs correspond to the crossing zones between the first and second grids IGi,g2-

[0162] In the example shown in [Fig.6], each third grid 135 has the internal structure of the second type, illustrated in [Fig.4].

[0163] Thus, in these third gates 135, each lower conductive region 1361 forms a conductive island 141. In addition, the upper conductive region 137 forms the common source of all the islands formed in the third gate, and conductive vias coated with the insulating layer form the drains 142.

[0164] This configuration allows a conductive island 141 to be positioned directly above each quantum box 1151.

[0165] Naturally, the third grids 135 may alternatively have the structure of the first type, illustrated in [Fig.5]. In this case, in the third grids 135, one out of every two lower conductive regions 1361 forms a conductive island 141. A charge detector 140 is then shared between two quantum boxes 1151.

[0166] From the above, the quantum device 100 comprises two sets of grids for controlling the quantum boxes 1151: the first set comprises the first grids 131; the second set comprises grids that extend over the dielectric 120 and cross the first grids 132. The second set comprises, at least, the second grids 132.

[0167] In addition, the conductive island 141 of each charge detector 140 is formed by a region of one of the grids of the second set, said region being comprised between two adjacent first grids 131 and arranged directly on the dielectric 120.

[0168] [Fig.7] shows a schematic representation of a block diagram of a method 800 for manufacturing the quantum device 100 illustrated in [Fig.2].

[0169] Figures 1 1A to 1 11A are schematic representations in perspective and in sectional view illustrating certain steps or sub-steps of the manufacturing method 800.

[0170] The manufacturing method 800 begins with a first step S801 of providing the substrate, for example the SOI substrate 10. This substrate 10 comprises on its front face 110a the semiconductor layer 110. This first step S801 is illustrated in [Fig. 11A].

[0171] With reference to [Fig.7], this step S801 is followed by a step S803 (of defining the arrangement of the matrix 115 of quantum dots 1151 and the tunnel barriers 1152a, 1152b in the semiconductor layer 110. In other words, this step S803 consists of determining the regions of the semiconductor layer 110 in which the quantum dots 1151 will be formed, as well as the regions in which the tunnel barriers 1152a, 1152b will be formed.

[0172] With reference to [Fig.7], the method 800 continues with a step S805 of depositing a first dielectric layer 120 intended to form the dielectric 120 of the device 100 (represented in [Fig.2]) on the entire front face 110a of the semiconductor layer 110.

[0173] This third step S805 is followed by a fourth step S810 aimed at jointly producing the first grids 131, the control grids 135 of the charge detectors 140 and the tunnel layer 1441 (cf. [Fig.2]).

[0174] With reference to [Fig.8], this step S810 comprises the successive sub-steps S810A and S810B. These sub-steps are also illustrated in [Fig.11B] and 11C.

[0175] With reference to [Fig. 11B], sub-step S810A is a sub-step of forming a first stack 803 over the entire surface of the dielectric 120, by: • Deposition, on the dielectric layer 120, of a first conductive layer 8031 ​​made with the conductive material intended to form the first grids 131, • Deposition, on the first conductive layer 8031, of a second dielectric layer 8032 made with the dielectric material forming the spacer 133. This second dielectric layer 8032 forms electrical insulation between the first conductive layer and the conductive layer next. • Deposition, on the second dielectric layer 8032, of a third conductive layer 8033 made with the conductive material intended to form the control grids 135 of the charge detectors 140, • Deposition, on the third conductive layer 8033, of a fourth dielectric layer 8034. This fourth dielectric layer 8034 is formed with the material of the spacer 133. It is intended to form the upper part of the insulating recesses 133R (see [Fig.2]), • Deposition, on the fourth dielectric layer 8034, of a fifth dielectric layer 8035 made with the dielectric material intended to form the tunnel layer 1441 of the charge detectors 140, • Deposition, on the fifth dielectric layer 8035, of a layer 8036 of a hard mask material. This hard mask is for example formed from silicon nitride (SiN). This hard mask layer is subsequently referred to as “first hard mask 8036”.

[0176] With reference to [Fig. 11C], the sub-step S810B is a sub-step of three-dimensional structuring of the first stack 803 to form first strips 801 parallel to each other, arranged on the dielectric 120 on either side of the regions defined for the quantum dots 1151. Specifically, the first strips 801 are arranged opposite the regions defined for the tunnel barriers 1152a connecting two adjacent quantum dots of the same line 115a of the matrix 115 of quantum dots.

[0177] The structuring sub-step S810B is carried out by successive etchings of the first hard mask 8036 and of the layers 8035, 8034, 8033 and 8032, and 8031 ​​with a stop on the dielectric 120.

[0178] In each first strip 801 thus formed, the first conductive layer 8031 ​​forms one of the first grids 131 and the second conductive layer 8033 forms one of the control grids 135 of the charge detectors 140. The second conductive layer 8032 provides insulation between these grids 131, 135.

[0179] Step S810 is followed by a fifth step S815, illustrated in [Fig. 11D], consisting of carrying out a conformal deposition of an encapsulation layer 8041 on the sides of the first strips 801. This encapsulation layer 8041 is produced with the material forming the spacer 133.

[0180] An anisotropic etching is then implemented in order to eliminate the encapsulation layer 8041 deposited on at least a portion of the sides of the fifth dielectric layers 8035. Thus, at least a portion of the sides of the fifth layer 8035 is accessible while the other layers 8034, 8033, 8032 and 8031 ​​are covered, on their sides, with the encapsulation layer 8041. The anisotropic etching is further configured to remove the encapsulation layer 8041 deposited the dielectric layer 120 between the first strips 801.

[0181] At the end of this step S815, the insulating recesses 133R of the second grids 132 are prepared.

[0182] The method 800 continues with a sixth step S820, the aim of which is to jointly form the first grids 131 and the islands 141 of the charge detectors 140.

[0183] With reference to [Fig.9], step S820 preferably comprises sub-steps S820A, S820B, S820C and S820D illustrated respectively in FIGS. 11E, 11F, HG and 11H.

[0184] With reference to [Fig. 11E], sub-step S820A consists of forming lower conductive strips 805 by filling with the conductive material intended to form the second grids 132 the zones 802 (cf. [Fig. 11C]) of the dielectric 120 located between the first strips 801. The filling is carried out up to the height of the hard mask layer 8036. The fifth layers of dielectric 8035 are thus embedded, and therefore integrated, in these lower conductive strips 805.

[0185] Thus, at the end of this first sub-step S820A, the lower conductive regions 1361 of the second gates 131 are produced. In addition, the tunnel layer 1441 of each charge detector 140 has been formed (by the fifth layer 8035). Each lower conductive region 1361 produced is thus prepared to form an island 141 of a charge detector 140.

[0186] It is noted that the first strips 801 advantageously provide an alignment mark for forming the islands 141. In other words, the islands 141 are defined in a self-aligned manner in the inter-first grid spaces, thanks to the first strips 801 and to this step S820. This self-alignment avoids the need for lithography steps.

[0187] The second sub-step S820B, illustrated in [Fig.l 1F], consists of depositing a layer 8061 of the material intended to form the upper barrier layer 1442 on the surface 805a (cf. [Fig.llE]) formed by all of the lower conductive strips 805 and the hard mask layers 8036. This deposition is followed by a three-dimensional structuring operation of this layer 8061 to form strips 806. With reference to [Fig. 11F], these upper barrier layer strips 806 are preferably parallel to each other and oriented at 45° relative to the first strips 801. Furthermore, in a direction XI perpendicular to the first strips 801, each upper barrier layer strip 806 covers three lower conductive strips 805 as well as the four complementary first strips 801.Each upper barrier layer strip 806 is further separated from adjacent upper barrier layer strips 806 by a gap corresponding to a lower conductive strip 805.

[0188] The orientation of the upper barrier layer strips 806 makes it possible to achieve the desired periodicity of the charge detectors 140 in the quantum device 100. Here, the 45° orientation makes it possible to achieve the periodicity of one island 141 formed in one lower conductive region 1361 out of two (i.e., one charge detector 140 for two quantum dots 1151).

[0189] The third sub-step S820C, illustrated in [Fig. 1 IG], consists first of depositing the conductive material intended to form the second gates 132 on all of the dielectric strips 806 and the lower conductive strips 805. This material is identical to the material of the lower strips 805. At the end of this step S820C, the device is thus covered with a conductive layer 807 which will be used to form the upper conductive stage 137 of the second gates 132.

[0190] This deposition operation is followed by a planarization operation of the upper conductive layer 807.

[0191] The planarization operation is then continued by a deposition operation, on the planarized upper conductive layer 807, of a hard mask layer 808.

[0192] The fourth sub-step S820D, illustrated in [Fig. 11H], consists of structuring the stack 80 formed by the lower conductive strips 805 and the upper conductive layer 807 to form the first and second grids 131, 132.

[0193] This structuring includes the definition of an etching mask in the second hard mask layer 808 (see [Fig. 11G]).

[0194] The etching mask defines bands corresponding to the first bands 801 and second bands 809 parallel to each other and oriented perpendicular to the first bands 801.

[0195] An etching of the stack 80 through the etching mask is then implemented. The etching stops on the dielectric layer 120 (between the first strips 801) and on the hard mask layer 8036 on the first strips 801.

[0196] At the end of this step S820, the first and second grids 131, 132 are formed according to the nested configuration described in relation to the first embodiment, and each second grid 132 forms a plurality of islands 141 of charge detectors 140 (in the regions corresponding to the lower conductive strips 805) and a common source 143 (in the region corresponding to the upper conductive layer 807).

[0197] Step S820 continues preferentially with a step S825, illustrated in [Fig.1II], of forming an encapsulation layer 811, for example by depositing a PMD dielectric layer (acronym for “Pre-metal Deposition” in English) on the dielectric 120 so as to embed the first strips 801 and the second strips 809.

[0198] Step S825 is extended by step S830 consisting of forming the drains 142 (or the sources 143) of the charge detectors 140. This step S830 comprises the sub-steps S830A, S830B and S830C illustrated in FIGS. 11J to 11L.

[0199] Sub-step S830A, illustrated in [Fig. 11 J], consists of making openings 812 through the encapsulation layer 811 (if the encapsulation step S825 is carried out) and through the second strips 809 so that each opening 812 opens into the lower conductive strip 805 arranged in the center of the three lower conductive strips covered by the upper barrier layer 806.

[0200] Sub-step S830B, illustrated in [Fig. 11K], consists of depositing, in a conformal manner and on the side walls of the openings 812, a layer 813 of the material forming the insulating layer 1422 coating the conductive vias 1421 (forming the drains 142). This insulating layer 813 forms an insulation between the upper conductive strip 807 and the interior volume of the opening 812.

[0201] Sub-step S830C, illustrated in [Fig. 11L], consists of filling the openings 812 with the conductive material intended to form the drains or sources 142, 143 of the charge detectors 140.

[0202] The openings 812 thus insulated and filled form the through-conductor vias 814, coated with insulation which define the drains 142 (or the sources 143) of the charge detectors 140.

Claims

Claims

1. Quantum device (100) comprising: - A semiconductor layer (110) adapted to form a two-dimensional matrix (115) of quantum dots (1151), the semiconductor layer (110) having a front face (HOa), - a dielectric (121), arranged on the front face (110a) of the semiconductor layer (110), - First gates (131) and second gates (132) for controlling the quantum dots (1151), the first gates (131) and the second gates (132) extending directly over the dielectric (121), each second gate (132) crossing the first gates (131), the first and second gates (131, 132) defining a two-dimensional mesh network, each two-dimensional mesh facing a quantum dot (1151), - Charge detectors (140), each charge detector (140) comprising a conductive island (141), a source (143) and a drain (142),the conductive island (141) of each charge detector (140) being formed at the level of a two-dimensional mesh, between two adjacent first grids (131) and directly on the dielectric (121).,

2. Quantum device (100) according to claim 2, wherein the drain (142) of each charge detector (140) comprises a conductive via (1421) coated with an electrically insulating material (1422), the coated conductive via (1421) having an end (1423) arranged in contact with a barrier layer (144) arranged directly above the conductive island (141) of said charge detector (140).

3. Quantum device (100) according to one of claims 1 to 2, wherein the conductive island (141) of each charge detector (140) is formed in a grid (132, 135) for controlling the quantum dots (1151) distinct from the first grids (131), said grid (132, 135) crossing the first grids (131) and extending directly on the dielectric (121), said grid (132, 135) having recesses (1 33r) covered with an electrically insulating layer, the recesses insulating recesses (133R) being arranged at the intersections (IGi,g2, Igi.gs) of said grid (132, 135) with the first grids (131), each insulating recess (133R) housing a first grid (131), the insulating recesses (133r) defining, in said grid (132,135), a plurality of lower conductive regions (1361) extending directly on the dielectric (120), and a continuous upper conductive region (137).

4. The quantum device (100) of claim 3, wherein said gate is one of the second gates (132).

5. A quantum device (100) according to claim 3, wherein said grid is a third grid (135) of a set of third grids (135) for controlling the chemical potential of the quantum dots (1151), each third grid (135) being arranged directly above the quantum dots (1151) formed along a column (115b) or a diagonal (115c) of the matrix (115) of quantum dots.

6. Quantum device (100) according to one of claims 3 to 5, wherein said gate has an internal structure of a first type comprising: - a tunnel layer (1441) covering each insulating recess (133r) of said gate, - a lower conductive region (1361-4) out of four extending the upper conductive region (137) towards the dielectric (121), said lower conductive region out of four (1361-4) defining three complementary lower regions (1361-1, 1361-2, 1361-3), - the two lower conductive regions (1361-1, 1361-3) located at the ends of the three complementary lower regions being covered with an upper barrier layer (1442), the upper barrier layer (1442) being arranged partly on the tunnel layers (1441),- the lower conductive region (1361-3) located at the center of the three complementary lower regions being extended by a conductive via (1421) coated with an electrically insulating material (1422), said coated conductive via (1421,1422) crossing the upper conductive region (137) to the upper barrier layer (1442).,

7. Quantum device (100) according to one of claims 3 to 5, wherein the internal structure of said second gate is of a second type comprising: - a barrier layer (144) covering all the lower conductive regions (1361) of said gate, the barrier layer being continuous and arranged on the insulating recesses (133R) of said gate, - Conductive vias (1421) coated with an electrically insulating material (1422) passing through the upper conductive region (137) to the barrier layer (144), each conductive via having an end (1423) arranged, for one part, directly above a lower conductive region 1361, and for the other part, directly above one of the insulating recesses (133R) adjacent to said lower conductive region (1361).

8. Quantum device (100) according to claims 4 to 7, wherein the quantum device (100) comprises grids (145) for controlling the chemical potentials of the conductive islands (141), each grid (145) for controlling the chemical potentials extending over one of the first grids (131) and being housed under the insulating recesses (133R) of the second grids at the crossings of the first and second grids.

9. A quantum device (100) according to claims 1 to 8, wherein the semiconductor layer (110) comprises holes (117) to form the quantum dots (1151).

10. A method of manufacturing (8) a quantum device (100) comprising charge detectors (140), each charge detector (140) comprising a conductive island (141), a drain (142) and a source (143), the method (8) comprising the following steps: - Providing (S801, S810) a semiconductor layer adapted to form a two-dimensional array (115) of quantum dots (1151), said semiconductor layer (110) having a front face (110a), said semiconductor layer (110) comprising a dielectric (120) arranged on the front face (110a) and first gates (131) for controlling the quantum dots (1151), the first gates (131) extending directly over the dielectric (120), - Coating (S815) the sides and the upper face of each first grid (131) to house each first grid (131) under an insulating recess (133R), - Defining (S820A, S820B, S820C) the conductive islands (141) from the coated first grids, each conductive island (141) extending between two adjacent first grids (131) and directly on the dielectric (120), - Forming (S820D), from the defined conductive islands (141), second grids (132) to control, with the first grids, the quantum dots, each second grid extending directly on the dielectric (120) and crossing the first grids (131), the first and second grids (131, 132) forming a two-dimensional mesh network on the dielectric (120).

11. Manufacturing method according to claim 10, wherein the step (S820A, S820B, S820C) of defining the conductive islands comprises the following sub-steps: - Filling (S820A) with a conductive material the spaces (805) of the dielectric delimited by two first adjacent coated grids, the filling stopping at the height of the insulating recesses, - Forming (S820B) a barrier layer (8061) over the entire surface obtained after the filling (S820A), - Structuring (S820C) the barrier layer to form barrier strips (806) oriented at a predetermined angle relative to the first grids.

12. A manufacturing method (8) according to claim 11, wherein the predetermined angle is such that the barrier strips are oriented at 45° relative to the direction of the first grids, the barrier strips extending, in the direction perpendicular to the first grids, over four adjacent conductive strips.

13. Manufacturing method (8) according to claims 10 to 12, comprising, after the step (S820D) of forming the second gates, a step (S830) of producing conductive vias coated with an electrical material electrically insulating, each conductive via crossing an upper region of one of the second gates with a stop on a region of a barrier dielectric strip, the conductive via forming the drain of the conductive island defined vertically above the region of the barrier strip.

Images