QUANTUM DEVICE AND ASSOCIATED MANUFACTURING METHOD

Abstract

One aspect of the invention relates to a quantum device (100) comprising: A semiconductor layer (110) adapted to form a two-dimensional array (115) of quantum dots (1151), the semiconductor layer (110) having a front face (110a), a dielectric (120), arranged on the front face (110a) of the semiconductor layer (110), First gates (131) and second gates (132) for controlling the quantum dots (1151), the first gates (131) and the second gates (132) extending directly over the dielectric (120), each second gate (132) intersecting the first gates (131), Charge detectors (140), each charge detector (140) comprising a conductive island (141) and a charge reservoir (142), the conductive island (141) of each charge detector (140) being formed between two adjacent first grids (131) and directly on the dielectric (120). Figure to be published with the abstract: Figure 1

Description

Title of the invention: QUANTUM DEVICE AND ASSOCIATED MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of quantum electronics and more particularly of quantum electronic devices and the manufacture of the latter. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] The use of measurable two-level quantum states as information vectors, also called "qubits" for "quantum bits" in English, and the laws of quantum mechanics (superposition, entanglement, measurement) offers the possibility of developing quantum algorithms that surpass certain classes of classical algorithms in performance. To implement them, thousands of qubits are required. Finally, three types of operations must be able to be performed on the qubits: initialization in a known state, manipulation (logic gates on one or more qubits), and reading these qubits.

[0003] Semiconductor technologies capable of enabling the manipulation of qubits include islands, also called quantum dots, made in nanometric-sized confinement structures defined, for example, electrostatically within a semiconductor layer. Quantum dots ensure the confinement of elementary charges, electrons or holes, and quantum information is, for example, coded on the spin of these particles.

[0004] For a quantum box to be functional, that is to say for it to be able to be initialized, manipulated and read, it must be coupled to reading electronics capable of determining the number of charges in the quantum box.

[0005] The use of additional devices coupled to reading electronics, such as charge detectors measured in current or in reflectometry, makes it possible to achieve more efficient detection of the charge number than in-situ detection methods.

[0006] Single Electron Transistors (SET) are among the most efficient charge detectors.

[0007] In general, a SET comprises a quantum dot, or island, two charge reservoirs, also called drain and source, and a gate contact.

[0008] The island is connected to each of the tanks by at least one tunnel junction, or tunnel coupling, defined electrostatically.

[0009] The load reservoirs (drain and source) are considered as mechanical materials massive metals whose electrons obey Fermi-Dirac statistics, and the island is for example a grain of metal whose size is a few nanometers. The gate contact is typically a layer of dielectric material. The tunnel junction is made by another layer of dielectric material, called a tunnel junction, arranged so as to separate the island from the charge reservoirs and the gate contact.

[0010] One or more electrodes are further connected to the charge reservoirs and to the gate contact to apply a voltage to these elements.

[0011] The operation of SETs is based on a capacitive coupling with the quantum box, a fluctuation in the number of charges of the quantum box modifying for example the conduction of the SET and can therefore be measured.

[0012] This detection, or reading, of the resulting charge is generally carried out in current (in transport) or by reflectometry with the use of an LC resonator.

[0013] When the SET is read in current, its drain and its source are polarized independently of each other. In other words, two independent charge reservoirs (source and drain) are necessary.

[0014] When the SET is read by reflectometry, it is not necessary for it to be crossed by a static current. Its drain and its source are therefore polarizable at the same potential, and a single charge reservoir (drain or source) is sufficient. In this case, the SET, which is no longer entirely equivalent to a transistor, is also called a "single-reservoir quantum dot" or SLQD (for "Single Lead Quantum Dot" according to the commonly used acronym of Anglo-Saxon origin).

[0015] Integrating SETs as close as possible to the qubits would be advantageous for improving detection sensitivity, and preserving the space needed to implement qubit control functionalities.

[0016] However, SETs are expensive in terms of size due to the number of elements that constitute them. Their integration in the qubit plane reduces the number of qubits that can be integrated per unit area and requires longer-range interactions between neighboring qubits.

[0017] To overcome this difficulty, it is proposed to integrate the SETs at the periphery of the qubit matrix. The disadvantage is that the size of this matrix must be reduced to a few quantum boxes per side to allow the qubits arranged in the center of the matrix to be read.

[0018] It is also proposed to integrate and connect the charge detectors in planes different from the plane comprising the quantum dots. In this case, we speak of circuits with non-planar architecture, also called "3D" for "3 dimensions".

[0019] Patent application FR 3 066 297 thus proposes a parallel-controlled quantum electronic circuit comprising a semiconductor layer receiving a matrix of qubits, a network of electrodes arranged on each side of this semiconductor layer, and a stacked plane on the semiconductor layer comprising an array of charge detectors.

[0020] This solution has the advantage that each charge detector is arranged near a qubit, regardless of the qubit considered in the matrix.

[0021] However, the architecture of this circuit is particularly complex, in particular due to the high density of vias and interconnections. As a result, certain manufacturing steps can be difficult to carry out.

[0022] Thus, there is currently no satisfactory solution for integrating SETs into high-density 2D quantum electronic circuits.

[0023] There thus remains a need for a solution for integrating charge detectors measured by reflectometry into two-dimensional quantum dot matrices, which allows good capacitive coupling between these charge detectors and these quantum dots, while being simple to implement. Summary of the invention

[0024] The present invention offers a solution to the problems mentioned above by making it possible to reduce, on the electronic chip, the size and complexity of charge detectors read by reflectometry.

[0025] More particularly, a first aspect of the invention proposes a quantum device comprising: • A semiconductor layer suitable for forming a two-dimensional matrix of quantum dots, the semiconductor layer having a front face, • A dielectric, placed on the front face of the semiconductor layer, • First grids and second grids to control the boxes quantum, the first grids and the second grids extending directly over the dielectric, each second grid crossing the first grids, the first and second grids defining a two-dimensional mesh network, each mesh facing a quantum box, • Charge detectors, each charge detector comprising a conductive charge reservoir and a conductive island, the conductive island of each charge detector being formed at the level of a two-dimensional mesh, between two first adjacent grids and directly on the dielectric.

[0026] Thus, advantageously according to the invention, the conductive island of each charge detector is formed at the same level as that of the first and second grids (the expression “same level” here means in the level between a lower face of the first grids and an upper face of the second grids). This allows for a compact quantum device (in terms of height). This also allows for a quantum device that uses only a single semiconductor substrate and whose manufacturing does not require bonding steps.

[0027] In addition, thanks to the conductive island which is placed on the dielectric in a two-dimensional mesh, there is a good capacitive coupling between the quantum dot formed directly above the two-dimensional mesh and the neighboring quantum dots. This proximity improves the sensitivity of the detection of the quantum device. It should be added that the fact of forming the conductive islands between first grids offers the advantage of being able to use these first grids as an alignment reference during the manufacturing steps of the conductive islands. In other words, the first grids make it possible to “self-align” the islands. This self-alignment facilitates these manufacturing steps.

[0028] The quantum device according to the invention thus offers an integration solution compatible with industrial manufacturing processes and the integration of quantum dots on a large scale, while allowing the required proximity between the charge detectors read in current and the quantum dots.

[0029] In addition to the characteristics which have just been mentioned in the preceding paragraph, the quantum device according to the first aspect of the invention may have one or more complementary characteristics among the following, considered individually or according to all technically possible combinations: • Each charge detector comprises a gate terminal, said gate terminal being formed by a barrier layer covering the conductive island corresponding to the charge detector. • the conductive island of each charge detector is formed in a quantum dot control grid distinct from the first grids, said grid crossing the first grids and extending directly onto the dielectric, said grid having recesses covered with an electrically insulating layer, the insulating recesses being arranged at the intersections of said grid with the first grids, each insulating recess housing a first grid, the insulating recesses defining in said grid a plurality of lower conductive regions extending directly onto the dielectric, and a continuous upper conductive region. • said grid is one of the second grids. • Alternatively, said grid is a third grid of a set of third grids intended to control the chemical potential of the quantum dots, each third grid being arranged directly above the quantum dots formed along a column or a diagonal of the matrix of quantum dots. Whatever said grid, said grid has an internal structure of a first type comprising: • one lower conductive region out of two extending the upper conductive region towards the dielectric and defines a complementary lower conductive region, • the complementary lower conductive region covered with a lower barrier layer, called tunnel layer, the tunnel layer being arranged on the insulating recesses adjacent to the complementary lower conductive region, • a dielectric pattern forming an upper barrier layer extending through the upper conductive region of the tunnel layer to the upper face of said gate, the dielectric pattern being coated by the upper conductive region and arranged directly above at least part of the complementary lower conductive region. a second grid out of two, or a third grid out of two, can then present the internal structure of the first type. the conductive islands are then arranged in a staggered pattern relative to each other. Alternatively, every second grid, or every third grid, may have the internal structure of the first type. Alternatively, said grid has an internal structure of a second type in which: • All lower conductive regions of said grid are covered with a tunnel layer, the tunnel layer being continuous and arranged on the recesses of said grid, • Each lower conductive region is surmounted by a dielectric pattern, each dielectric pattern forming with the tunnel layer a barrier layer, each dielectric pattern crossing the upper conductive region of the tunnel layer arranged on the associated lower conductive region up to the upper face of said grid, the dielectric pattern being coated by the upper conductive region and arranged directly above at least part of the associated lower conductive region. a second grid out of two, or a third grid out of two, can then present the internal structure of the second type. Alternatively, every second grid, or every third grid, may have the internal structure of the first type. • the upper region of said grid can be coupled to a voltage source for addressing the sources of the charge detectors formed in said grid. • Each dielectric pattern can be extended, above said grid, by a conductive via, called a grid via. • The quantum device may comprise charge detector control lines, each line being coupled on the one hand to the gate vias arranged on the same line of the quantum dot matrix and, on the other hand, to a voltage source. • The quantum device may comprise metallization lines, called the reading line of the charge detectors, each reading line being coupled, on the one hand to the upper region of a grid defining conductive islands, and on the other hand to a reading circuit, said reading circuit comprising an inductance and a capacitance forming a resonant circuit whose resonant frequency depends on the impedance of the charge detectors, allowing measurements in reflectometry. • Each reading line couples conductive portions located on the same line of the quantum dot matrix, or couples conductive portions located on the same diagonal of the quantum dot matrix. • The semiconductor layer includes holes to form the quantum dots, • The holes are arranged directly above the meshes of the two-dimensional mesh network defined by the first and second grids.

[0030] A second aspect of the invention relates to a method of manufacturing a quantum device comprising charge detectors, each charge detector comprising a conductive island and a charge reservoir, the method comprising the following steps: • Providing a semiconductor layer suitable for forming a two-dimensional array of quantum dots, said semiconductor layer having a front face, said semiconductor layer comprising a dielectric disposed on the front face and first gates for controlling the quantum dots, the first gates extending directly over the dielectric, • Coating of the sides and the upper face of each first grid to house each first grid under an insulating recess, • Definition of conductive islands from the first coated grids, each conductive island extending between two adjacent first grids and directly on the dielectric, • Formation, from the defined conductive islands, of second grids to control, with the first grids, the quantum dots, each second grid extending directly on the dielectric and crossing the first grids, the first and second grids forming a two-dimensional mesh network on the dielectric.

[0031] Preferably, the step of defining the conductive islands may comprise the following sub-steps: • Filling with a conductive material the spaces of the dielectric delimited by two first adjacent coated grids, the filling stopping at the height of the insulating recesses, • Formation of a barrier layer over the entire surface obtained after filling, • Structuring the barrier layer to form barrier strips oriented at a predetermined angle relative to the first grids.

[0032] Preferably, the predetermined angle is such that the barrier strips are oriented at 45° relative to the direction of the first grids, the barrier strips extending, in the direction perpendicular to the first grids, over four adjacent conductive strips.

[0033] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0034] The figures are presented for information purposes only and in no way limit the invention. • [Fig.l] shows a schematic representation in top view of a quantum device according to a first embodiment of the invention, • [Fig.2] shows a schematic representation in cross-sectional view of the quantum device shown in [Fig.l], • [Fig.3] shows a schematic representation of part of the quantum device shown in [Fig.2], • [Fig.4] shows a schematic representation in perspective view of a part of the quantum device shown in [Fig.l], • [Fig.5] shows a schematic representation in top view of an alternative quantum device to the quantum device shown in [Fig.l], making it possible to form as many charge detectors as quantum boxes, • [Fig.6] shows a schematic representation in cross-sectional view of the quantum device shown in [Fig.5], • [Fig.7] schematically represents in top view an alternative quantum device to the quantum device shown in [Fig.l], allowing the charge detectors to be positioned directly above the quantum dots, • [Fig.8] schematically represents in top view an alternative quantum device to the quantum device shown in [Fig.7], • [Fig.9] shows a first schematic representation in cross-sectional view of the quantum device shown in [Fig.8], • [Fig. 10] is a block diagram illustrating the sequence of steps in a manufacturing process for the quantum device shown in [Fig.l], • Figures 11A to 11I illustrate steps or sub-steps of the manufacturing process shown in [Fig. 10], each figure showing a perspective view and a sectional view of the quantum device produced during one of the steps or sub-steps.

[0035] Unless otherwise specified, the same element appearing in different figures has a single reference. DETAILED DESCRIPTION

[0036] The present invention falls within the context of quantum electronic devices and their manufacturing method. More particularly, the invention aims to enable, via charge detectors read by reflectometry, efficient detection of the charge state of the quantum dots formed on the quantum devices. In particular, again, the invention aims to reduce the space occupied by these charge detectors on the quantum device to provide an architecture making it possible to produce large-scale spin qubits.

[0037] Figures 1, 2, 3 and 4 represent, in a schematic form, a quantum device 100 according to a first embodiment.

[0038] [Fig.l] shows, in schematic form, a top view of a part of the quantum device 100 according to this first embodiment.

[0039] Figures 2 to 4 show different views of a first variant embodiment of the quantum device 100 shown in [Fig.l].

[0040] Figures 5 to 6 show different views of a second alternative embodiment of the quantum device 100 shown in [Fig.l].

[0041] With reference to [Fig.l], and in a manner common to the two embodiment variants illustrated in figures 2 to 4 and in figures 5 to 6, the quantum device 100 extends in a plane {X,Y} and is formed from a semiconductor layer 110. The device 100 further comprises a dielectric 121, first and second gates 131, 132 and charge detectors 140. These elements are described in detail below.

[0042] In the remainder of the description, the terms “thickness” or “height” designate dimensions measured perpendicular to the plane {X; Y}. The expression “dimension “lateral” means a dimension measured in the plane {X;Y}.

[0043] The semiconductor layer 110 has a front face 110a, illustrated in [Fig.2].

[0044] The semiconductor layer 110 is adapted to form a matrix of quantum dots. In other words, the semiconductor layer 110 has characteristics making it possible to form a matrix 115 of quantum dots 1151 within it. These quantum dots are represented by hatched circles in [Fig.l].

[0045] The term “matrix” here designates an arrangement of the quantum boxes according to rows 115a and columns 115b.

[0046] With reference to [Fig.2] or [Fig.6], the semiconductor layer 110 has a thickness of between 5 nm and 35 nm and preferably between 10 nm and 20 nm, for example equal to 15 nm.

[0047] The semiconductor layer 110 is preferably a silicon layer 110.

[0048] Preferably, this silicon layer 110 comes from a substrate 10 of the silicon on insulator or SOI type (acronym for “Silicon On insulator” in English).

[0049] Such a substrate 10 is notably illustrated in [Fig.2]. It comprises a stack, from bottom to top, of a massive semiconductor layer 105, an insulating layer 107, and the silicon semiconductor layer 110. The insulating layer 107 is arranged between the massive semiconductor layer 105 and the semiconductor layer 110. The polarization of such a substrate 10 makes it possible to electrostatically control charge confinements in the semiconductor layer 110.

[0050] The semiconductor layer 110 may, alternatively, be a solid silicon layer.

[0051] The semiconductor layer 110 may, alternatively, be a semiconductor heterostructure comprising a quantum well or a two-dimensional electron gas (2DEG). Such structures have interfaces with low defect densities, facilitating charge confinement and electrostatic control.

[0052] The semiconductor layer 110 may advantageously have holes 117. These holes 117 are illustrated by white circles in [Fig.l]. These holes 117 may for example be obtained by etching the semiconductor layer 110.

[0053] The holes 117 are preferentially arranged in rows and columns to form a matrix of holes 117. In [Fig.l], the rows of holes 117 are oriented in a first direction X corresponding to the direction of the rows 115a of quantum dots 1151. Similarly, the columns of holes 117 are oriented in a second direction Y corresponding to the direction of the columns 115b of quantum dots 1151.

[0054] The holes 117 are arranged between the rows and columns of quantum boxes. Preferably, four holes 115 frame each zone corresponding to a quantum box 1151.

[0055] The diameter of the holes 117 is preferably between 20 nm and 50 nm. Thus, the holes 117 structure the semiconductor layer 110 to confine charges in each non-etched zone, that is to say in the zone corresponding to the quantum box 1151. The presence of the holes 117 thus facilitates the formation of the quantum boxes 1151.

[0056] The dielectric 121 is arranged on the front face 110a of the semiconductor layer 110 and is formed of one or more layers, each layer being formed of a dielectric material (see [Fig.2] or [Fig.6]).

[0057] According to a variant, shown in [Fig.9], the dielectric 121 consists of a single layer 120 of dielectric which covers the front face 110a of the semiconductor layer 110. The dielectric layer 120 has a thickness preferably between 5 nm and 10 nm and is electrically insulating. The dielectric layer 120 is for example made of silicon oxide (SiO2).

[0058] According to another variant, illustrated in [Fig.2] and [Fig.6], the dielectric layer 120 is covered, between the first gates 131, by another dielectric layer, called spacer layer 133 (in [Fig.2], these portions of spacer layer 133 arranged on the dielectric layer 120 are denoted 133D). In this configuration, the dielectric 121 is the stack consisting of the dielectric layer 120 and the spacer layer 133D arranged on this dielectric layer 120. This embodiment variant is easier to produce than the variant in which the dielectric 121 consists of the dielectric layer 120 only. Indeed, it is then not necessary to structure the spacer layer 133, once it has been deposited on the first grids 131 and the dielectric layer 120.This variant thus makes it possible to dispense with an anisotropic etching step of the spacer layer 133 after its deposition (since this etching is not necessary). In exchange, as will be better understood later, the second grids 132 are a little further away from the semiconductor layer 110 and thus from the quantum boxes 1151. The electrostatic control of the quantum boxes as well as the coupling of the charge detectors 140 to the quantum boxes 1151 can then be significantly less efficient.

[0059] The spacer layer 133 is formed of a dielectric material. This material is for example SiO2 or aluminum oxide (Al2O3).

[0060] The spacer layer 133 has a maximum thickness which depends on the material chosen: when the material is SiO2, the maximum thickness is for example 5 nm; when the material is Al2O3, the maximum thickness can be between 10 nm and 15 nm.

[0061] The first grids 131 and the second grids 132 are conductive strips formed from a conductive material chosen from the following materials: doped crystalline silicon (or doped Poly-Si), tungsten (W), titanium nitride (TiN).

[0062] The first grids 131 extend entirely over the dielectric 121 (precisely, they extend directly over the layer 120 of dielectric which therefore constitutes a grid dielectric), in a first direction X, illustrated in [Fig.l], which corresponds to the orientation of the lines 115a of quantum dots 1151.

[0063] Each first grid 131 has a section whose height is preferably between 5 nm and 50 nm, and preferably equal to 25 nm. The lateral dimension and the height of the section are preferably substantially identical. The section of each first grid 131 is then a square section.

[0064] Each first grid 131 is further covered, or coated, on its sides (i.e. its lateral faces) and its upper face (i.e. the face opposite the dielectric layer 120) with the spacer layer 133 (see [Fig.2]).

[0065] The spacer layer 133 makes it possible to avoid electrical contact between the first gates 131 and the second gates 132, or more generally between the first gates 131 and higher gate levels. Thus, these higher gate levels are insulated from each other.

[0066] The second grids 132 are oriented in a second direction Y different from the first direction X. This direction Y corresponds to the direction of the columns 115b of quantum dots 1151.

[0067] In [Fig. 1], the second direction is oriented here at 90° with respect to the first direction X. Naturally, this second direction Y can be oriented at an angle different from 90° with respect to the first direction X.

[0068] Each second grid 132 extends directly over the dielectric 121 (in the example of [Fig. 2], over the spacer layer 133 of the dielectric 121) and crosses the first grids 131 at crossing zones (denoted IGi,g2 in [Fig. 1]) according to a so-called "interleaved" configuration.

[0069] This interleaved configuration is described below in relation to [Fig. 2].

[0070] According to this nested configuration, each second grid 132 has a height which is greater than the height of the first grids 131. Preferably, the height of the second grids 132 is 20 nm to 50 nm greater than that of the first grids 131. The lateral dimension of the second grids is preferably identical to that of the first grids.

[0071] In addition, each second grid 132 extends: • directly on the dielectric 121 between two adjacent first grids (or, in other words, in the spaces between the first grids), and • on the spacer layer 133 covering the sides and the upper face of the first grids at the level of the crossing zones IG1, G2.

[0072] In other words, each second grid 132 passes over, or overlaps, the first grids 131 covered by the spacer layer 133 at the crossing zones IGi,g2. This overlap prevents physically cutting the first grids 131 at the crossing zones 133.

[0073] Thanks to the spacer layer 133 interposed between the first grids 131 and the second grids 132, each second grid 132 crosses the first grids 131 without there being an electrical contact between them.

[0074] Moreover, since the height of the second grids 132 is greater than that of the first grids 131, at the crossing zones 133, the first grids 131 are housed under the insulating recesses 133R of the second grids 132.

[0075] These insulating recesses (also noted more simply as "recesses 133R" hereafter) are visible in [Fig.2]. Each insulating recess 133R forms an insulating bridge under which a first grid 131 passes.

[0076] [Fig.3] shows an enlarged view of two consecutive 133R insulating recesses.

[0077] The insulating recesses 133R here have a hard mask layer 1331 linked to the manufacturing process.

[0078] As shown in [Fig.3], the insulating recesses 133R define in each second grid 132 a lower stage 136, and an upper stage 137 which are conductive.

[0079] The lower stage 136 has a pattern comprising a plurality of lower conductive zones 1361 (see [Fig.2]).

[0080] Each lower conductive region 1361 is separated from adjacent lower conductive areas by one of the insulating recesses 133R.

[0081] The upper stage 137 forms a continuous upper conductive region 137. The nested configuration therefore makes it possible to maintain electrical continuity along each first grid 131 and along each second grid 132.

[0082] As will be described later in the description, these lower conductive areas 136 and the upper conductive region 137 are advantageously used to form the charge detectors 140.

[0083] As shown in [Fig.l], the arrangement of the first and second grids also makes it possible to define on the surface of the dielectric 121 a network of regular spaces (also referred to as “two-dimensional meshes” hereinafter). Each two-dimensional mesh corresponds to the area of ​​a quantum box 1151.

[0084] Each two-dimensional mesh comprises the free dielectric space defined at the intersection between two adjacent first grids and two adjacent second grids. Each two-dimensional mesh also comprises the closed contour formed by the portions of the grids of the intersection.

[0085] In the example of [Fig.l], the X, Y directions of the first and second grids 131, 132 here are orthogonal to each other. The two-dimensional meshes- ionals are square in shape.

[0086] The X, Y directions of the first and second grids 131, 132 can alternatively be oriented with an angle other than 90°.

[0087] When the semiconductor layer 110 comprises holes 117 as illustrated in [Fig.l], the X and Y directions of the first grids and second grids also correspond, respectively, to the directions of the rows and columns of holes 117. The first and second grids are further arranged so that there is a hole opposite each crossing zone IGi,g2- Thus, a hole 117 is arranged at each vertex of the two-dimensional meshes.

[0088] The independent control of each first and second grid 131, 132 makes it possible to electrostatically control and with short-range interactions a quantum box 1151 in each region of the semiconductor layer 110 located directly above a two-dimensional mesh.

[0089] This control is facilitated by the presence of the holes 117 since these make it possible to confine (in a non-electrostatic manner) charges at the level of the regions of the semiconductor layer forming the quantum dots 1151.

[0090] Each region of the semiconductor layer 110 forming a quantum dot has lateral dimensions, defined in the plane {X,Y}, which are preferably between 5 nm and 100 nm, and preferably equal to 50 nm. The thickness of the region of the semiconductor layer 110 forming a quantum dot is furthermore preferably between 5 nm and 30 nm, and preferably equal to 15 nm.

[0091] The distance between two neighboring quantum dots, that is to say two quantum dots formed opposite two neighboring two-dimensional meshes, is preferably between 25 nm and 125 nm.

[0092] More precisely, the control of the first and second grids makes it possible to control by field effect the conduction of tunnel barriers 1152a, 1152b located on either side (along the X and Y directions) of each quantum box.

[0093] In the part of [Fig.l] representing an enlarged view of a two-dimensional mesh, these tunnel barriers 1152a, 1152b are represented by dotted rectangles. Each tunnel barrier denoted 1152a is here located opposite a second grid 132 and connects the quantum box 115 Cj to the adjacent quantum box 115 Cij (or 115 Cij) formed on the same line (115a) of the two-dimensional mesh network. Each tunnel barrier denoted 1152b is here located opposite a first grid 131 and connects the quantum box 115 Cj to the adjacent quantum box 115 Cj+i (or 115 Cj i) formed on the same column (115b) of the two-dimensional mesh network.

[0094] The tunnel barriers 1152a, 1152b preferably have lateral dimensions smaller than those of the quantum dots 1151, for example dimensions lateral between 5 nm and 30 nm. Their thickness is, however, similar to that of 1151 quantum dots.

[0095] According to the above, the first grids 131 are arranged directly above first tunnel barriers 1152b, and the second grids are arranged directly above second tunnel barriers 1152a. Each first tunnel barrier 1152b connects two neighboring quantum dots arranged in the same column 115b of the quantum dot matrix, while each second tunnel barrier 1152a connects two neighboring quantum dots arranged in the same row of this matrix 115.

[0096] Each charge detector 140 comprises a conductive quantum island 141 (also referred to as island 141 hereinafter) and a charge reservoir 142.

[0097] Each charge detector 140 can be measured by reflectometry.

[0098] As shown in Figures 2 and 6, the island 141 of each charge detector 140 is formed between two adjacent first grids 131 and directly on the dielectric 121.

[0099] Thus, this island 141 is formed at the same level as that of the first and second grids 131, 132. The expression “at the same level” means that each island 141 is formed between the lower face of the first grids and the upper face of the second grids. This makes it possible to obtain a compact quantum device 100 (in terms of height).

[0100] Furthermore, as will be described later in the description in relation to the manufacturing method, the fact of forming the conductive islands 141 between first grids 131 offers the advantage of being able to use these first grids 131 as an alignment reference mark at the time of the steps of manufacturing the conductive islands 141. In other words, the first grids make it possible to “self-align” the islands 141. This self-alignment facilitates these manufacturing steps.

[0101] Compactness and simplicity of manufacturing are assets for scaling quantum processors.

[0102] In a manner common to the two embodiment variants illustrated respectively in [Fig.2] and 5, each island 141 is formed in one of the lower conductive zones 1361 of a second grid 132. These lower conductive zones 1361 are, as described previously, comprised between two first grids 131.

[0103] The island 141 of each charge detector is thus “placed” on the dielectric 121 directly above a tunnel barrier 1152a. Each island 141 is thus coupled to one and the other of the quantum dots 1151 arranged, in the plane of the semiconductor layer 110, on either side of this tunnel barrier 1152a. This coupling is shown by arrows on the part of [Fig.l] representing an enlarged view of a two-dimensional mesh. Each charge detector 140 is then shared between at least two quantum dots 1151.

[0104] Several islands 141 (cf. [Fig.2]) are formed in the same second grid 132.

[0105] In this second grid 132, the lower conductive zones 1361 defining an island 141 are covered with a tunnel layer 1441. This tunnel layer 1441 is arranged within the second grid 132. This tunnel layer 1441 has the effect of electrically insulating the island 141 from the upper conductive stage 137 and from the other islands 141 of the second grid 132. It also has the effect of allowing the formation of a tunnel current within it.

[0106] All the charge detectors 140 of this second grid have a common charge reservoir 142, formed, at least, by the upper stage 137 of this second grid 132. The common charge reservoir 142 is connected by tunnel coupling to each conductive island thanks to the tunnel layer 1441.

[0107] Finally, each charge detector 140 of this second grid 132 comprises a grid terminal 144, formed by the tunnel layer 1441 and a dielectric pattern called barrier pattern 1442.

[0108] This barrier pattern 1442 crosses the upper conductive region 137 from the tunnel layer 1141 to the upper face of the gate 132. This barrier pattern 1442 is directly above a part of the conductive island 141. It is, moreover, coated with the upper conductive region 137.

[0109] Thus, the conductive island 141, the charge reservoir 142 and the grid terminal of each detector 140 are formed in a second grid 132.

[0110] The shared use of the second grids 132 makes it possible to reduce the overall footprint (lateral and vertical) of the charge detector 140 in the quantum device 100.

[0111] The use, in particular, of the upper conductive zone 137 to form / incorporate the charge reservoirs 142, 143 offers an additional advantage for integrating the addressing and reading functions of the charge detectors 140. Indeed, this upper conductive zone 137 is easily accessible for resuming electrical contact from above and / or for resuming electrical contact at the ends of the second grids.

[0112] A structure for controlling the polarization of the gate terminal 144 of each island 141 can thus comprise gate conductive vias 1433 (also referred to as gate vias 1433 hereinafter). As shown in [Fig.2], each gate via 1433 has a lower end arranged on the upper face of the second gate 132, in contact with a barrier pattern 1442.

[0113] A reading structure of each island 141 may further comprise one or more conductive reading vias 1421 (also referred to as reading vias 1421 hereinafter). Each reading via 1421 has an end arranged on the upper face of the second gate 132, in contact with the upper conductive region 137. In the example of [Fig.2], several reading vias 1421 are arranged on the same second grid 132.

[0114] In this case, an encapsulation layer 148 is arranged on the upper face of the second gate to coat the gate vias 1443 and the reading vias 1421. This encapsulation layer 148 can be formed from a dielectric, for example SiO2. [Fig.2] shows the presence of a hard mask layer 1332 interposed within the encapsulation layer 148. This hard mask layer 1332 is linked to the manufacturing process.

[0115] The number of conductive islands 141 formed in the same second grid 132 depends on the internal structure of this second grid 132.

[0116] According to the first variant embodiment, illustrated in FIGS. 1, 2, 3 and 4, the internal structure of the second grid 132 is of a first type making it possible to form an island 141 in one lower conductive region 1361 out of two.

[0117] According to this first type of internal structure, and with reference to [Fig.2], a lower conductive region 1361-1 out of two extends the upper conductive region 137 towards the dielectric 121.

[0118] This region 1361-1 defines a complementary lower conductive region 1361-2 (also referred to as complementary lower region 1361-2 hereinafter).

[0119] The complementary lower region 1361-2 is covered with a lower barrier layer, called tunnel layer 1441. This tunnel layer 1441 is arranged on the recesses 133R adjacent to the complementary lower region 1361-2. In other words, the tunnel layer 1441 forms a cover on the complementary lower region, this cover resting on the adjacent recesses 133R.

[0120] The tunnel layer 1441 has characteristics allowing tunnel coupling to be achieved within it.

[0121] The tunnel layer 1441 may be formed from aluminum oxide (A12O3).

[0122] The tunnel layer 1441 may be formed of silicon oxide (SiO2). In this case, the tunnel layer 1441 has a thickness between 1 nm and 3 nm.

[0123] Preferably, the tunnel layer 1441 is formed from a hafnium oxide (HfO2). This material in fact has a programmable resistance to be adjusted to a value between a few kiloohms and a few tens of kiloohms. The tunnel layer 1441 then preferably has a thickness between 5 nm and 10 nm.

[0124] The tunnel layer 1441 makes it possible to define an island 141 in the complementary lower region 1361-2.

[0125] The upper stage 137 and the lower conductive region 1361-1 which extends towards this upper stage 137 form the charge reservoir 142 of the island 141 formed in the complementary lower region 1361-1. The tunnel coupling between this reservoir of load 143 and islands 141 is performed in tunnel layer 1441.

[0126] The first type of internal structure also provides that a barrier pattern 1442 forming an upper barrier layer 1442 extends through the upper conductive region 137, from the tunnel layer 1441 to the upper face of the second gate 132.

[0127] This barrier pattern 1442 is coated by the upper conductive region 137. Thus, the upper conductive region 137 remains continuous along the second grid 132. The barrier pattern 1442 is arranged in line with at least a portion of the complementary lower conductive region 1361-2.

[0128] The barrier pattern 1442 is formed of a material similar to that forming the tunnel layer 1441. In this way, it is suitable for achieving tunnel coupling within it. The barrier pattern is preferably formed of a material chosen from the following materials: SiO2, Al2O3, HfO2.

[0129] The barrier pattern 1442 forms, with the portion of the corresponding tunnel layer 1441, the gate terminal 144 of the island 141 formed in the complementary lower region 1361-2.

[0130] As shown in [Fig.4], each second grid 132 may have this structure of the first type. Alternatively, a second grid 132 may have this structure of the first type.

[0131] The lower conductive regions 1361-2 chosen to define the islands 141 in a given second grid 132 are preferentially offset relative to those chosen for a neighboring second grid 132.

[0132] In this way, and with reference to [Fig.l], the islands 141 are arranged in a staggered manner relative to each other in the assembly formed by the second grids 132. Consequently, the charge detectors 140 are also arranged in a staggered manner relative to each other. This staggered arrangement makes it possible to guarantee good measurement sensitivity with a reduced number of charge detectors 140.

[0133] Returning to [Fig.2], the structure for controlling the polarization of the gate terminals 144 preferably comprises metallization lines, called reading lines 1445, which are coupled to an LC reflectometry circuit 1446. Each reading line 1445 is electrically connected to the reading vias 1421 arranged on the same second gate 132.

[0134] Each reading line 1145 can couple conductive portions 137 located on the same line 115a of the matrix 115 of quantum dots 1151.

[0135] Alternatively, each read line 1145 can couple conductive portions 137 located on the same diagonal 115c of the quantum dot matrix 1151.

[0136] In addition, the polarization control structure of the grid terminals 144 can include metallization lines 1444, called grid lines 1444, coupled to a voltage source. Each grid line 1444 is preferably connected to the grid vias 1443 arranged on the same line of the quantum dot matrix 115.

[0137] The combination of the read and grid terminal control structures enables individual reading of the charge detectors 140.

[0138] According to the second embodiment variant, illustrated in Figures 5 and 6, the internal structure of the second grid 132 is of a second type making it possible to form an island 141 in each lower conductive region 1361. This second type thus makes it possible, compared to the first type, to double the number of charge detectors 140 formed in the same second grid 132. As shown in [Fig.5], there are then as many charge detectors 140 as there are quantum dots 1151.

[0139] By thus increasing the number of charge detectors 140, it is possible to measure each quantum box as close as possible to it. This improves the sensitivity of the measurement of the quantum boxes.

[0140] The second type of internal structure differs from the first type in that all the lower conductive regions 1361 of the second grid 132 are covered with the tunnel layer 1441. The tunnel layer 1441 then extends throughout the plane of the second grid, at the level of the upper face of the recesses 133R of this second grid (cf. [Fig.6]).

[0141] On the other hand, there is a barrier pattern 1442 directly above each lower conductive region 1361. As in the structure of the first type, the barrier pattern 1442 passes through the upper conductive region 137 to the tunnel layer 1441 and is coated with the upper conductive region 137.

[0142] Figures 7, 8 and 9 show a second embodiment of the quantum device 100.

[0143] The second embodiment differs from the first embodiment, illustrated in Figures 1 to 6, in that the charge detectors 140 are not formed in the second grids 132 but in third grids 135 intended to control the chemical potential of the quantum dots 1151.

[0144] As shown in [Fig.9], the second grids 132 are then covered, on their sides and their upper face, with a layer 133' of insulating material forming a spacer 133' similar to the spacer 133. The spacer 133' then makes it possible to electrically insulate these second grids from the third grids 135.

[0145] Note that in this [Fig.9], the dielectric 121 is the dielectric layer 120.

[0146] The third grids are conductive strips formed from a material conductor similar to that forming the first and second grids.

[0147] As shown in Figures 7 and 8, these third grids 135 are distinct from the second grids 132 and are all oriented in a direction Y' different from the first X direction of the first grids 131. The third grids and extend directly above the quantum boxes 1151.

[0148] [Fig.7] shows a first variant embodiment of the second embodiment. According to this first variant, the third grids are oriented at 90° relative to the first grids 131. In addition, each third grid 135 is arranged between two adjacent second grids, directly above the quantum dots arranged on the same column 115b of the matrix 115 of quantum dots.

[0149] The third grids 135 extend directly over the dielectric 121 and intersect the first grids 131 (see [Fig.7]) in a nested configuration similar to the nested configuration described previously (in relation to the second grids 132). The crossing zones between the first grids and the third grids are denoted with the reference IGi>G3 in FIGS. 7 and 8.

[0150] [Fig.8] shows a second variant embodiment of the second embodiment. According to this second variant, the third grids are oriented at 45° relative to the first and second grids 131, 132. Each third grid 135 extends directly above the quantum dots arranged on the same diagonal 115c of the matrix 115 of quantum dots.

[0151] The third grids 135 extend directly over the dielectric 121 and intersect the first and second grids in the same nested configuration as previously described.

[0152] The crossing zones between the first grids and the third grids Igi.gs correspond to the crossing zones between the first and second grids IGi,g2-

[0153] [Fig.9] shows, in schematic form, a sectional view of a third grid of the device shown in [Fig.8].

[0154] As shown in [Fig.9], each third grid 135 extends directly over the dielectric 121 between two adjacent first grids 131 (or, in other words, in the inter-first grid spaces), and passes over, or overlaps, the first grids 131 coated with the spacer layer 133 at the crossing zones I G1,G3*

[0155] The height of the third grids 135 is greater than that of the second grids 132. Preferably, this height of the third grids is greater by 20 nm to 50 nm than that of the second grids 132.

[0156] This nested configuration makes it possible to define a two-stage structure (a continuous conductive upper stage 137 and a lower stage formed from a plurality of lower conductive regions 1361) analogous to the structure of the second grids illustrated in [Fig.6].

[0157] This nested configuration thus makes it possible to form in each third grid 135, or in a third grid 135 out of two, the internal structure described above. previously in relation to the first embodiment.

[0158] In the example shown in [Fig.7], each third grid has the internal structure of the first type, illustrated in [Fig.2].

[0159] Thus, in these third grids 135, one lower conductive region 1361 out of two forms a conductive island 141. In addition, the upper conductive region 137 forms the charge reservoir 142 common to all the islands formed in the third grid 135, and barrier patterns 1442 coated with the upper conductive region 137 form the grid terminals 144 (see [Fig.9]).

[0160] This configuration makes it possible to position each conductive island 141 directly above a quantum dot (unlike the first embodiment, where the islands 141 are directly above the tunnel barriers).

[0161] This arrangement allows a more localized measurement of the state of charge of the quantum box 1151 than when the charge detector 140 is directly above a tunnel barrier 1152b. Indeed, a charge detector 140 arranged directly above a quantum box is more sensitive to the latter because it is closer than a charge detector arranged directly above a tunnel barrier. It is, however, less sensitive to neighboring quantum boxes.

[0162] As in the first embodiment, the islands 141 are here arranged in a staggered pattern relative to each other.

[0163] Naturally, the third grids 135 can alternatively have the structure of the second type, illustrated in [Fig.4]. In this case, in the third grids 135, each lower conductive region 1361 forms a conductive island 141. A charge detector 140 is then arranged directly above each quantum box 1151.

[0164] In the example shown in [Fig.8], every third grid has the internal structure of the second type, illustrated in [Fig.6].

[0165] Thus, as in the first embodiment illustrated in [Fig.7], each lower conductive region 1361 forms a conductive island 141. In addition, the upper conductive region 137 forms the charge reservoir common to all the islands formed in the third grid, and barrier patterns coated with the upper conductive region form the drains 142.

[0166] This configuration makes it possible to position a conductive island directly above each quantum box.

[0167] Naturally, the third grids can alternatively have the structure of the first type, illustrated in [Fig.2]. In this case, in the third grids 135, one lower conductive region 1361 out of two forms a conductive island 141. A charge detector 140 is then shared between two quantum dots 1151.

[0168] According to the above, the quantum device 100 comprises two sets of control grids of the quantum boxes 1151: the first set comprises the first grids 131; the second set comprises grids which extend directly over the dielectric 121 and intersect the first grids 132. The second set comprises, at least, the second grids 132.

[0169] In addition, the conductive island 141 of each charge detector 140 is formed by a region of one of the grids of the second set, said region being comprised between two adjacent first grids 131 and arranged directly on the dielectric 121.

[0170] [Fig. 10] shows a schematic representation of a block diagram of a method 800 for manufacturing the quantum device 100 illustrated in [Fig.l] and 2.

[0171] Figures 1 1A to 1 11A are schematic representations in perspective and in sectional view illustrating certain steps or sub-steps of the manufacturing method 800.

[0172] The manufacturing method 800 begins with a first step S801 of providing the SOI substrate 10 comprising on one of its faces the semiconductor layer 110. This first step S801 is illustrated in [Fig. 11A].

[0173] This step S801 is followed by a step S802 (see [Fig. 10]) of defining the arrangement of the matrix of quantum dots 115 and the tunnel barriers 1152 in the semiconductor layer 110. In other words, this step S802 consists of determining the regions of the semiconductor layer 110 in which the quantum dots 1151 will be formed, as well as the regions in which the tunnel barriers 1152a, 1152b will be formed.

[0174] This step S802 can be followed by a step of etching the semiconductor layer 110 to obtain the holes 117.

[0175] The method 800 continues with a step S803 (see [Fig. 10]) of depositing, on the entire upper face of the semiconductor layer 110, a first dielectric layer 121 with the material of the dielectric layer 120 of the dielectric 121

[0176] This third step S803 is followed by a fourth step S804 aimed at jointly forming the first grids 131, and the tunnel layer 1441.

[0177] With reference to [Fig. 10], this step S804 comprises the successive sub-steps S804A and S804B. These sub-steps are also illustrated in [Fig. 11B] and 11C.

[0178] With reference to [Fig. 1 IB], sub-step S804A is a sub-step of forming a first stack 801 over the entire surface of the spacer 120, by:

[0179] Deposition, on the dielectric layer 120, of a first conductive layer 8011 of the conductive material of the first grids 131,

[0180] Deposition, on the first conductive layer 8011, of a second dielectric layer 8012 of the material forming the spacer 133,

[0181] Deposition, on the second dielectric layer 8012, of a first hard mask layer 8013.

[0182] Sub-step S804B is a sub-step of three-dimensional structuring of the first stack 801 to form first strips 802 parallel to each other. others, arranged on the dielectric layer 120 opposite the first tunnel barriers 1152a defined previously.

[0183] The structuring sub-step S804B is carried out by defining an etching mask in the first hard mask layer 8013, then by successive etchings, through the etching mask, of the second dielectric layer 8012 and the first conductive layer 8011, with a stop on the dielectric layer 120.

[0184] The device obtained at the end of this sub-step S804B is shown in [Fig. 11C]. As shown in this [Fig. 11C], the strips 802 obtained are separated by free spaces 803 of the dielectric layer 120.

[0185] Step S804 is followed by a fifth step S805 consisting of carrying out a conformal deposition of an encapsulation layer 8041 so as to cover the external limits of the first strips 802 and the free spaces 803. The encapsulation layer 8041 is produced with the material of the spacer 133. This deposition can be followed by a planarization of the encapsulation layer 8041 on the upper faces of the first strips 801.

[0186] At the end of this step S805, the insulating recesses 133R of the second grids 132 are prepared.

[0187] The method 800 continues with a sixth step S806, the aim of which is to jointly form the second grids 132 and the islands 141 in these second grids 132.

[0188] With reference to [Fig. 10], step S806 preferably comprises the successive sub-steps S806A, S806B, S806C, S806D, S806E, S806F, S806G and S806H illustrated respectively in FIGS. 11D, 11E, 11F, 11G, 11H, 11I, 11J, and 11K.

[0189] With reference to [Fig. 11D], sub-step S806A consists of forming lower conductive strips 805 by filling the inter-first strip spaces 803 with the conductive material intended to form the second grids 132. The filling is carried out up to the height of the encapsulation layer 8041 arranged on the upper face of the first strips 802. This filling is advantageously followed by planarization of the deposited conductive layer to leave a flat upper surface 805a flush with the first strips 802.

[0190] With reference to [Fig. 11E], sub-step S806B consists of depositing, over the entire upper surface 805a formed at the end of step S806A, a stack 806 of barrier layers comprising: a lower barrier layer 8061 formed with the material of the tunnel layer 1441 and an upper barrier layer 8062 formed with the material of the barrier patterns 1442.

[0191] Sub-step S806C which extends sub-step S806B consists of structuring in three dimensions the stack of dielectric layers 806 to form strips barriers 807. With reference to [Fig. 11F], these barrier strips 807 are preferably parallel to each other and oriented at 45° relative to the first strips 801. Furthermore, in a direction Xi perpendicular to the first strips 802. Furthermore, each barrier strip 807 covers a lower conductive strip 803 as well as the two adjacent first strips 801.

[0192] The orientation of the barrier strips 807 makes it possible to achieve the desired periodicity of the charge detectors 140 in the quantum device 100. Here, the 45° orientation makes it possible to achieve the periodicity of one island 141 formed in one lower conductive region 1361 out of two (i.e. one charge detector 140 for two quantum dots 1151).

[0193] The resulting structure is illustrated in [Fig.l 1F].

[0194] These barrier strips 807 define the tunnel layer 1441 and make it possible to define the islands 141.

[0195] The following sub-step S806D consists of carrying out an anisotropic etching of the upper barrier layer 8062 from the barrier strips 807, and with a stop on the lower barrier layer 8061. The final structure is illustrated in [Fig.l 1 G]. In each dielectric strip 807 thus structured, the upper barrier layer 8062 forms an upper dielectric strip 807a whose lateral dimensions (along the X direction) are smaller than the dimension of the lower conductive strip 805c, and which is positioned in a central zone 8051 of this lower conductive strip 805c. The fourth dielectric layer 8061 forms a lower barrier strip 707b.

[0196] Sub-step S806E, illustrated in [Fig. 11H] consists of forming an upper conductive layer 808 by depositing the conductive material intended to form the second gates 132 on all of the lower and upper dielectric strips 807a, 807b and up to the level of these upper dielectric strips 807a. This sub-step S806E may further comprise an operation of planarizing the upper conductive layer 808.

[0197] The sub-steps S806F, S806G and S806H aim to structure in three dimensions the stack 808a formed by the lower conductive strips 805 and the upper conductive layer 808 to form second conductive strips 809 parallel to each other and oriented perpendicular to the first strips 802, extending over the dielectric layer 120 and crossing the first strips by forming insulating bridges over these first strips 802.

[0198] Sub-step S806F, illustrated in [Fig.l II] consists of forming one or more layers 809a, 809b intended to form a hard mask 809 over the entire planarized surface.

[0199] Sub-step S806G, illustrated in [Fig. 1 IJ], consists of defining an etching mask in the hard mask layer 809, so as to define second bands 810 pa aligned with each other and oriented perpendicularly with respect to the first strips 802, extending opposite the second tunnel barriers 1152b (not shown in [Fig.l 1 J]), and each coating a plurality of portions of the barrier layers 807a, 807b.

[0200] Sub-step S806H consists of carrying out selective etching through the hard mask 809, the structured dielectric strips 807a and 807b, the upper conductive strip 808 and the lower conductive strips 805, with a stop on the dielectric layer 120.

[0201] The structure thus formed is illustrated in [Fig.l 1 K].

[0202] At the end of this sub-step S806H, the second bands 810 are formed. These second bands 810 correspond to the second grids with the charge detectors 140 formed within them.

[0203] The manufacturing method can further continue with a step S807 consisting of removing the hard mask 809 remaining on the upper face of the second strips 810, then carrying out siliciding, for example by depositing a layer 813 of SiN on the second strips 810. [Fig. 111] illustrates the quantum device 100 obtained at the end of this step S807.

[0204] The manufacturing method which has just been described makes it possible to manufacture the quantum device 100 according to the first embodiment (see [Fig.l]).

[0205] To produce the quantum device 100 according to the second embodiment (cf. [Fig.7]), the steps are identical except for:

[0206] Substep S806C of structuring the dielectric strips 807 which is modified so that only the upper dielectric layer 8062 is structured, and so that the resulting structure defines dielectric strips which extend not at 45° relative to the first strips, but at 90°. In this way, the dielectric strips define an island in each lower conductive strip,

[0207] Substep S806D is deleted.

[0208] This way of carrying out the structuring of the dielectric strips is advantageous in that it reduces the number of steps to be carried out.

Claims

Claims

1. Quantum device (100) comprising: - A semiconductor layer (110) adapted to form a two-dimensional matrix (115) of quantum dots (1151), the semiconductor layer (110) having a front face (HOa), - a dielectric (121), arranged on the front face (110a) of the semiconductor layer (110), - First gates (131) and second gates (132) for controlling the quantum dots (1151), the first gates (131) and the second gates (132) extending directly over the dielectric (121), each second gate (132) crossing the first gates (131), the first and second gates (131, 132) defining a two-dimensional mesh network, each two-dimensional mesh facing a quantum dot (1151), - Charge detectors (140), each charge detector (140) comprising a conductive charge reservoir (142) and a conductive island (141),the conductive island (141) of each charge detector (140) being formed at the level of a two-dimensional mesh, between two adjacent first grids (131) and directly on the dielectric (121).,

2. A quantum device (100) according to claim 1, wherein each charge detector (140) comprises a gate terminal (144), said gate terminal being formed by a barrier layer (1441,1442) covering the conductive island (141) corresponding to the charge detector (140).

3. Quantum device (100) according to one of claims 1 to 2, wherein the conductive island (141) of each charge detector (140) is formed in a control grid (132, 135) of the quantum dots (1151) distinct from the first grids (131), said grid (132, 135) crossing the first grids (131) and extending directly on the dielectric (121), said grid (132, 135) having recesses (1 33r) covered with an electrically insulating layer, the insulating recesses (1 33r) being arranged at the crossings (IGi.g2, Imm)

4.

5.

6.

7. of said grid (132, 135) with the first grids (131), each insulating recess (133r) housing a first grid (131), the insulating recesses (133r) defining, in said grid (132, 135), a plurality of lower conductive regions (1361) extending directly on the dielectric (121), and a continuous upper conductive region (137). The quantum device (100) of claim 3, wherein said gate is one of the second gates (132). Quantum device (100) according to claim 3, wherein said grid is a third grid (135) of a set of third grids (135) intended to control the chemical potential of the quantum dots (1151), each third grid (135) being arranged in line with the quantum dots (1151) formed along a column (115b) or a diagonal (115c) of matrix (115) of quantum dots. Quantum device (100) according to one of claims 3 to 5, wherein said grid has an internal structure of a first type comprising: - one lower conductive region (1361-1) out of two extending the upper conductive region (137) towards the dielectric (120) and defining a complementary lower conductive region (1361-2), - the complementary lower conductive region (1361-2) covered with a lower barrier layer, called tunnel layer (1141), the tunnel layer (1441) being arranged on the insulating recesses (133R) adjacent to the complementary lower conductive region (1361-2), - a dielectric pattern (1142) forming an upper barrier layer (1142) extending through the upper conductive region (137) of the tunnel layer (1141) to the upper face of said gate, the dielectric pattern being coated by the upper conductive region (137) and arranged directly above at least part of the complementary lower conductive region (1361-2). Quantum device (100) according to one of claims 3 to 5, wherein the internal structure of said second grid is of a second type in which: All lower conductive regions (1361) of said grid are covered with a tunnel layer (1441), the tunnel layer (1441) being continuous and arranged on the recesses (133r) of said grid, Each lower conductive region is surmounted by a dielectric pattern (1442), each dielectric pattern forming, with the tunnel layer (1141), a barrier layer (144), each dielectric pattern passing through the upper conductive region (137) of the tunnel layer (1441) disposed on the associated lower conductive region up to the upper face of said grid, the dielectric pattern being surrounded by the upper conductive region (137) and being disposed vertically above at least a part of the associated lower conductive region (1361-2).

8. Quantum device (100) according to claims 3 to 7, comprising metallization lines (1445), called reading lines (1145) of the charge detectors (140), each reading line (1445) being coupled, on the one hand to the upper conductive region (137) of a grid (132, 135) forming conductive islands, and on the other hand to a reading circuit (1446), said reading circuit (1446) comprising an inductance and a capacitance forming a resonant circuit whose resonant frequency depends on the impedance of the charge detectors (140), allowing measurements in reflectometry.

9. A quantum device (100) according to claims 1 to 8, wherein the semiconductor layer (110) comprises holes (117) to form the quantum dots (1151).

10. A method of manufacturing (8) a quantum device (100) comprising charge detectors (140), each charge detector (140) comprising a conductive island (141) and a charge reservoir (142), the method (8) comprising the following steps: - Providing (S801, S810) a semiconductor layer adapted to form a two-dimensional array (115) of quantum dots (1151), said semiconductor layer (110) having a front face (110a), said semiconductor layer (110) comprising a dielectric (121) disposed on the front face (110a) and first gates (131) for controlling the quantum dots (1151), the first gates (131) extending directly on the dielectric (121), - Coating (S815) the sides and the upper face of each first grid (131) to house each first grid (131) under an insulating recess (133R), - Defining (S820A, S820B, S820C) the conductive islands (141) from the coated first grids, each conductive island (141) extending between two adjacent first grids (131) and directly on the dielectric (121), - Forming (S820D), from the defined conductive islands (141), second grids (132) to control, with the first grids, the quantum dots, each second grid extending directly on the dielectric (121) and crossing the first grids (131), the first and second grids (131, 132) forming a two-dimensional mesh network on the dielectric (121).

11. Manufacturing method according to claim 10, wherein the step (S820A, S820B, S820C) of defining the conductive islands comprises the following sub-steps: - Filling (S820A) with a conductive material the spaces (803) of the dielectric (121) delimited by two first adjacent coated grids (802), the filling stopping at the height of the insulating recesses, - Forming (S820B) a barrier layer (806) over the entire surface obtained after the filling, - Structuring (S820C) the barrier layer (806) to form barrier strips (807) oriented at a predetermined angle relative to the first grids.

12. Manufacturing method (8) according to one of claims 10 to 11, wherein the predetermined angle is such that the barrier strips (807) are oriented at 45° relative to the direction of the first grids, the barrier strips extending, in the direction perpendicular to the first grids, over four adjacent conductive strips.

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