QUANTUM DEVICE AND ASSOCIATED MANUFACTURING PROCESS

Abstract

One aspect of the invention relates to a quantum device (100) comprising: A semiconductor layer (110) adapted to form a two-dimensional array (115) of quantum dots (1151), the semiconductor layer (110) having a front face (110a), a dielectric (120) disposed on the front face (110a) of the semiconductor layer (110), First gates (131) and second gates (132) for controlling the quantum dots (1151), the first gates (131) and second gates (132) extending directly onto the dielectric (120), each second gate (132) intersecting the first gates (131), Charge detectors (140), each charge detector (140) comprising a conductive island (141) and a charge reservoir (142), the conductive island (141) of each charge detector (140) being formed between two first adjacent grids (131) and directly on the dielectric (120). Figure to be published with the abbreviation: Figure 1

Description

Title of the invention: QUANTUM DEVICE AND ASSOCIATED MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of quantum electronics and more particularly of quantum electronic devices and the manufacture of the latter. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] The use of two-level measurable quantum states as an information vector, also called "qubits" for "quantum bits," and the laws of quantum mechanics (superposition, entanglement, measurement) offers the possibility of developing quantum algorithms that surpass certain classes of classical algorithms in performance. Thousands of qubits are required to implement them. Finally, three types of operations must be able to be performed on the qubits: initialization in a known state, manipulation (logic gates on one or more qubits), and reading from these qubits.

[0003] Semiconductor technologies capable of manipulating qubits include islands, also called quantum dots, fabricated in nanometer-sized confinement structures defined, for example, electrostatically within a semiconductor layer. Quantum dots ensure the confinement of elementary charges, electrons or holes, and quantum information is, for example, encoded on the spin of these particles.

[0004] For a quantum dot to be functional, that is to say for it to be initialized, manipulated and read, it must be coupled to a read electronics capable of determining the number of charges in the quantum dot.

[0005] The use of additional devices coupled with readout electronics, such as current-measured or reflectometric charge detectors, makes it possible to achieve more efficient charge number detection than in-situ detection methods.

[0006] Single electron transistors (SETs) are among the most efficient charge detectors.

[0007] In general, a SET comprises a quantum dot, or island, two charge reservoirs, also called drain and source, and a gate contact.

[0008] The island is connected to each of the tanks by at least one tunnel junction, or tunnel coupling, defined electrostatically.

[0009] The charging reservoirs (drain and source) are considered as materials The cells are massive, with electrons obeying Fermi-Dirac statistics, and the island is, for example, a metal grain a few nanometers in size. The gate contact is typically a layer of dielectric material. The tunnel junction is formed by another layer of dielectric material, called a tunnel junction, arranged to separate the island from the charge reservoirs and the gate contact.

[0010] One or more electrodes are also connected to the charge reservoirs and the grid contact to apply a voltage to these elements.

[0011] The operation of the SET is based on a capacitive coupling with the quantum dot, a fluctuation in the number of charges of the quantum dot modifies for example the conduction of the SET and can therefore be measured.

[0012] This detection, or reading, of the resulting charge is generally carried out by current (in transport) or by reflectometry with the use of an LC resonator.

[0013] When the SET is read in current, its drain and source are biased independently of each other. In other words, two independent charge reservoirs (source and drain) are required.

[0014] When the SET is read by reflectometry, it does not need to be traversed by a static current. Its drain and source are therefore biasable at the same potential, and a single charge reservoir (drain or source) is sufficient. In this case, the SET, which is no longer quite equivalent to a transistor, is also called a "single-reservoir quantum dot" or SLQD (for "Single Lead Quantum Dot," according to the commonly used Anglo-Saxon acronym).

[0015] Integrating the SETs as close as possible to the qubits would be advantageous to improve the sensitivity of the detection, and preserve the space necessary for the implementation of the qubit control functionalities.

[0016] However, SETs are expensive in terms of space due to the number of elements that constitute them. Their integration into the qubit plane reduces the number of qubits that can be integrated per unit area and requires longer-range interactions between neighboring qubits.

[0017] To overcome this difficulty, it is proposed to integrate the SETs around the periphery of the qubit matrix. The drawback is that the size of this matrix must be reduced to a few quantum dots per side to allow reading the qubits located at the center of the matrix.

[0018] It is also proposed to integrate and connect the charge detectors in planes different from the plane containing the quantum dots. In this case, we speak of circuits with a non-planar architecture, also called "3D" for "3-dimensional".

[0019] French patent application FR 3 066 297 thus proposes a parallel-controlled quantum electronic circuit comprising a semiconductor layer receiving a qubit matrix, an electrode array arranged on each side of this semiconductor layer, and a plane stacked on the semiconductor layer comprising a charge detector array.

[0020] This solution has the advantage that each charge detector is placed close to a qubit, regardless of which qubit is considered in the matrix.

[0021] However, the architecture of this circuit is particularly complex, notably due to the high density of vias and interconnections. As a result, certain manufacturing steps may be difficult to perform.

[0022] Thus, there is currently no satisfactory solution for integrating SETs into high-density 2D quantum electronic circuits.

[0023] There remains a need for a solution for integrating charge detectors measured by reflectometry into two-dimensional quantum dot matrices, which allows good capacitive coupling between these charge detectors and these quantum dots, while being simple to implement. Summary of the invention

[0024] The present invention offers a solution to the problems mentioned above by making it possible to reduce, on the electronic chip, the size and complexity of charge detectors read by reflectometry.

[0025] More specifically, a first aspect of the invention proposes a quantum device comprising: • A semiconductor layer adapted to form a two-dimensional matrix of quantum dots, the semiconductor layer having a front face, • A dielectric, arranged on the front face of the semiconductor layer, • First grids and second grids to control the boxes quantum, the first and second grids extending directly onto the dielectric, each second grid intersecting the first grids, the first and second grids defining a two-dimensional mesh network, each mesh being opposite a quantum dot, • Load detectors, each load detector comprising a conductive load tank and a conductive island, the conductive island of each charge detector being formed at the level of a two-dimensional mesh, between two first adjacent grids and directly on the dielectric.

[0026] Thus, advantageously according to the invention, the conductive island of each charge detector is formed at the same level as that of the first and second grids (the expression "same level" here means in the level between a lower face of the first grids and an upper face of the second grids). This This allows for a compact quantum device (in terms of height). It also allows for a quantum device that uses only a single semiconductor substrate and whose fabrication does not involve bonding steps.

[0027] Furthermore, thanks to the conductive island placed on the dielectric in a two-dimensional lattice, there is good capacitive coupling between the quantum dot formed directly above the two-dimensional lattice and the neighboring quantum dots. This proximity improves the detection sensitivity of the quantum device. It should be added that forming the conductive islands between initial grids offers the advantage of being able to use these initial grids as alignment references during the fabrication steps of the conductive islands. In other words, the initial grids allow the islands to be "self-aligned." This self-alignment facilitates these fabrication steps.

[0028] The quantum device according to the invention thus offers an integration solution compatible with industrial manufacturing processes and the integration of large-scale quantum dots, while allowing the required proximity between the current-read charge detectors and the quantum dots.

[0029] In addition to the characteristics mentioned in the preceding paragraph, the quantum device according to the first aspect of the invention may have one or more additional characteristics from among the following, considered individually or in all technically possible combinations: • Each load detector includes a grid terminal, said grid terminal being formed by a barrier layer covering the conductive island corresponding to the load detector. • the conducting island of each charge detector is formed in a control grid of quantum dots distinct from the first grids, said grid crossing the first grids and extending directly over the dielectric, said grid having recesses covered with an electrically insulating layer, the insulating recesses being arranged at the crossings of said grid with the first grids, each insulating recess housing a first grid, the insulating recesses defining in said grid a plurality of lower conducting regions extending directly over the dielectric, and a continuous upper conducting region. • said grid is one of the second grids. • Alternatively, said grid is a third grid of a set of third grids intended to control the chemical potential of the quantum dots, each third grid being positioned directly above the quantum dots formed along a column or diagonal of the quantum dot matrix. Regardless of the grid in question, said grid has an internal structure of a first type comprising: • every other lower conductive region extending the upper conductive region towards the dielectric and defining a complementary lower conductive region, • the complementary lower conductive region covered with a lower barrier layer, called the tunnel layer, the tunnel layer being disposed on the insulating recesses adjacent to the complementary lower conductive region, • a dielectric pattern forming an upper barrier layer extending through the upper conductive region of the tunnel layer to the upper face of said grid, the dielectric pattern being enclosed by the upper conductive region and positioned vertically above at least part of the complementary lower conductive region. a second grid out of two, or a third grid out of two, may then present the internal structure of the first type. The conductor islands are then arranged in a staggered pattern relative to each other. Alternatively, each second grid, or each third grid, may exhibit the internal structure of the first type. Alternatively, the said grid has an internal structure of a second type in which: • All lower conductive regions of said grid are covered with a tunnel layer, the tunnel layer being continuous and arranged over the recesses of said grid, • Each lower conductive region is surmounted by a dielectric pattern, each dielectric pattern forming with the tunnel layer a barrier layer, each dielectric pattern passing through the upper conductive region of the tunnel layer disposed on the associated lower conductive region to the upper face of said grid, the dielectric pattern being enveloped by the upper conductive region and disposed vertically over at least part of the associated lower conductive region. a second grid out of two, or a third grid out of two, may then present the internal structure of the second type. Alternatively, each second grid, or each third grid, may exhibit the internal structure of the first type. • the upper region of said grid can be coupled to a voltage source to address the sources of the charge detectors formed in said grid. • Each dielectric motif can be extended, above said grid, by a conductive via, called a grid via. • The quantum device may include control lines for charge detectors, each line being coupled on one side to grid vias arranged on the same line of the quantum dot matrix and, on the other side, to a voltage source. • The quantum device may include metallization lines, called charge detector readout lines, each readout line being coupled, on the one hand, to the upper region of a grid defining conductive islands, and on the other hand, to a readout circuit, said readout circuit comprising an inductance and a capacitance forming a resonant circuit whose resonance frequency depends on the impedance of the charge detectors, allowing measurements in reflectometry. • Each reading line pairs conducting portions located on the same line of the quantum dot matrix, or pairs conducting portions located on the same diagonal of the quantum dot matrix. • The semiconductor layer contains holes to form quantum dots, • The holes are arranged vertically above the meshes of the two-dimensional mesh network defined by the first and second grids.

[0030] A second aspect of the invention relates to a method for manufacturing a quantum device comprising charge detectors, each charge detector comprising a conductive island and a charge reservoir, the method comprising the following steps: • Provision of a semiconductor layer suitable for forming a two-dimensional matrix of quantum dots, said semiconductor layer having a front face, said semiconductor layer comprising a dielectric disposed on the front face and first gates for controlling the quantum dots, the first gates extending directly on the dielectric, • Coating of the sides and top face of each first grid to house each first grid under an insulating recess, • Definition of conductive islands starting from the first coated grids, each conductive island extending between two adjacent grids and directly onto the dielectric, • Formation, from the defined conducting islands, of second grids to control, with the first grids, the quantum dots, each second grid extending directly on the dielectric and crossing the first grids, the first and second grids forming a network of two-dimensional meshes on the dielectric.

[0031] Preferably, the step of defining the conducting islands may include the following sub-steps: • Filling the spaces in the dielectric delimited by the first two adjacent coated grids with a conductive material, the filling stopping at the height of the insulating recesses, • Formation of a barrier layer over the entire surface obtained after filling, • Structuring the barrier layer to form barrier bands oriented at a predetermined angle relative to the first grids.

[0032] Preferably, the predetermined angle is such that the barrier strips are oriented at 45° with respect to the direction of the first grids, the barrier strips extending, in the direction perpendicular to the first grids, over four adjacent conductive strips.

[0033] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0034] The figures are presented for illustrative purposes only and are in no way limiting of the invention. • Figure [1] shows a schematic top-view representation of a quantum device according to a first embodiment of the invention, • Fig. 2 shows a schematic cross-sectional view of the quantum device shown in Fig. 1. • Fig. 3 shows a schematic representation of part of the quantum device shown in Fig. 2. • Fig. 4 shows a schematic perspective view representation of part of the quantum device shown in Fig. 1. • Figure [5] shows a schematic top-view representation of an alternative quantum device to the quantum device shown in Figure [1], allowing for the formation of as many charge detectors as there are quantum dots. • Fig. 6 shows a schematic cross-sectional view of the quantum device shown in Fig. 5. • Fig. 7 schematically represents, in top view, an alternative quantum device to the quantum device shown in Fig. 1. allowing the charge detectors to be positioned directly above the quantum dots, • Figure [Fig.8] schematically represents, in top view, an alternative quantum device to the quantum device shown in Figure [Fig.7]. • Fig. 9 shows a first schematic cross-sectional representation of the quantum device shown in Fig. 8. • Fig. 10 is a synoptic diagram illustrating the sequence of steps in a manufacturing process for the quantum device shown in Fig. 1. • Figures 11A to 1 IL illustrate steps or substeps of the manufacturing process shown in [Fig. 10], each figure showing a perspective view and a cross-sectional view of the quantum device produced during one of the steps or substeps.

[0035] Unless otherwise specified, the same element appearing on different figures has a unique reference. DETAILED DESCRIPTION

[0036] The present invention relates to quantum electronic devices and their fabrication process. More specifically, the invention aims to enable, via charge detectors read by reflectometry, efficient detection of the charge state of quantum dots formed on quantum devices. In particular, the invention also aims to reduce the space occupied by these charge detectors on the quantum device to provide an architecture enabling the realization of spin qubits on a large scale.

[0037] Figures 1, 2, 3 and 4 represent, in schematic form, a quantum device 100 according to a first embodiment

[0038] Fig. 1 shows, in schematic form, a top view of a part of the quantum device 100 according to this first embodiment.

[0039] Figures 2 to 4 show different views of a first variant of the embodiment of the quantum device 100 shown in [Fig.1].

[0040] Figures 5 to 6 show different views of a second variant embodiment of the quantum device 100 shown in [Fig.1].

[0041] With reference to [Fig. 1], and in common to the two embodiment variants illustrated in Figures 2 to 4 and in Figures 5 to 6, the quantum device 100 extends in a plane {X,Y} and is formed from a semiconductor layer 110. The device 100 further comprises a dielectric 121, first and second gates 131, 132 and charge detectors 140. These elements are described in detail below.

[0042] In the following description, the terms "thickness" or "height" refer to dimensions measured perpendicular to the {X; Y} plane. The expression "dimension" "lateral" denotes a dimension measured in the {X;Y} plane.

[0043] The semiconductor layer 110 has a front face 110a, illustrated in [Fig.2].

[0044] The semiconductor layer 110 is adapted to form a matrix of quantum dots. In other words, the semiconductor layer 110 has characteristics that allow the formation of a matrix 115 of quantum dots 1151 within it. These quantum dots are represented by hatched circles in [Fig. 1].

[0045] The term "matrix" here refers to an arrangement of quantum dots along rows 115a and columns 115b.

[0046] With reference to [Fig.2] or [Fig.6], the semiconductor layer 110 has a thickness between 5 nm and 35 nm and preferably between 10 nm and 20 nm, for example equal to 15 nm.

[0047] The semiconductor layer 110 is preferably a silicon layer 110.

[0048] Preferably, this silicon layer 110 is derived from a silicon-on-insulator or SOI (acronym for "Silicon On insulator") substrate 10.

[0049] Such a substrate 10 is illustrated in particular in [Fig. 2]. It comprises a stack, from bottom to top, of a bulk semiconductor layer 105, an insulating layer 107, and the silicon semiconductor layer 110. The insulating layer 107 is arranged between the bulk semiconductor layer 105 and the semiconductor layer 110. The polarization of such a substrate 10 makes it possible to electrostatically control charge confinement within the semiconductor layer 110.

[0050] The semiconductor layer 110 can, alternatively, be a bulk silicon layer.

[0051] The semiconductor layer 110 can alternatively be a semiconductor heterostructure comprising a quantum well or a two-dimensional electron gas (2DEG). Such structures exhibit interfaces with low defect densities, facilitating charge confinement and electrostatic control.

[0052] The semiconductor layer 110 may advantageously have holes 117. These holes 117 are shown as white circles in [Fig. 1]. These holes 117 can, for example, be obtained by etching the semiconductor layer 110.

[0053] The 117 holes are preferentially arranged in rows and columns to form a matrix of 117 holes. In [Fig. 1], the rows of 117 holes are oriented in a first direction X corresponding to the direction of the rows 115a of quantum dots 1151. Similarly, the columns of 117 holes are oriented in a second direction Y corresponding to the direction of the columns 115b of quantum dots 1151.

[0054] The 117 holes are arranged between the rows and columns of quantum dots. Preferably, four 115 holes frame each area corresponding to a 1151 quantum dot.

[0055] The diameter of the holes 117 is preferably between 20 nm and 50 nm. Thus, the holes 117 structure the semiconductor layer 110 to confine charges in each unetched region, i.e. in the region corresponding to the quantum dot 1151. The presence of the holes 117 thus facilitates the formation of the quantum dots 1151.

[0056] The dielectric 121 is disposed on the front face 110a of the semiconducting layer 110 and is formed of one or more layers, each layer being formed of a dielectric material (see [Fig.2] or [Fig.6]).

[0057] According to one embodiment, shown in [Fig. 9], the dielectric 121 consists of a single layer 120 of dielectric which covers the front face 110a of the semiconductor layer 110. The dielectric layer 120 has a thickness preferably between 5 nm and 10 nm and is electrically insulating. The dielectric layer 120 is, for example, made of silicon dioxide (SiO2).

[0058] According to another embodiment, illustrated in [Fig. 2] and [Fig. 6], the dielectric layer 120 is covered, between the first grids 131, by another dielectric layer, called the spacer layer 133 (in [Fig. 2], these portions of the spacer layer 133 arranged on the dielectric layer 120 are denoted 133D). In this configuration, the dielectric 121 is the stack consisting of the dielectric layer 120 and the spacer layer 133D arranged on this dielectric layer 120. This embodiment is easier to produce than the one in which the dielectric 121 consists solely of the dielectric layer 120. Indeed, it is then unnecessary to structure the spacer layer 133 once it has been deposited on the first grids 131 and the dielectric layer 120.This variant therefore eliminates the need for an anisotropic etching step of the spacer layer 133 after its deposition (since this etching is unnecessary). However, as will be better understood later, the second grids 132 are slightly further from the semiconductor layer 110 and therefore from the quantum dots 1151. The electrostatic control of the quantum dots, as well as the coupling of the charge detectors 140 to the quantum dots 1151, may then be significantly less efficient.

[0059] The spacer layer 133 is formed of a dielectric material. This material is, for example, SiO2 or aluminium oxide (Al2O3).

[0060] The spacer layer 133 has a maximum thickness which depends on the material chosen: when the material is SiO2, the maximum thickness is for example 5 nm; when the material is AL2O3, the maximum thickness can be between 10 nm and 15 nm.

[0061] The first grids 131 and the second grids 132 are conductive strips formed from a conductive material selected from the following materials: doped crystalline silicon (or doped Poly-Si, tungsten (W), titanium nitride (TiN).

[0062] The first grids 131 extend entirely over the dielectric 121 (precisely, they extend directly over the layer 120 of dielectric which constitutes, therefore, a grid dielectric), along a first direction X, illustrated in [Fig.1], which corresponds to the orientation of the lines 115a of quantum dots 1151.

[0063] Each first grid 131 has a cross-section whose height is preferably between 5 nm and 50 nm, and preferably equal to 25 nm. The lateral dimension and the height of the cross-section are preferably substantially identical. The cross-section of each first grid 131 is then a square cross-section.

[0064] Each first grid 131 is further covered, or coated, on its sides (i.e. its lateral faces) and its upper face (i.e. the face opposite the dielectric layer 120) with the spacer layer 133 (cf. [Fig.2]).

[0065] The spacer layer 133 prevents electrical contact between the first grids 131 and the second grids 132, or more generally between the first grids 131 and higher grid levels. Thus, these higher grid levels are isolated from each other.

[0066] The second grids 132 are oriented along a second direction Y different from the first direction X. This direction Y corresponds to the direction of the columns 115b of quantum dots 1151.

[0067] In [Fig.1], the second direction is oriented here at 90° with respect to the first direction X. Naturally, this second direction Y can be oriented at a different angle of 90° with respect to the first direction X.

[0068] Each second grid 132 extends directly onto the dielectric 121 (in the example of [Fig.2], onto the spacer layer 133 of the dielectric 121) and crosses the first grids 131 at crossing zones (denoted IGi,g2 on [Fig.1]) according to a so-called "nested" configuration.

[0069] This nested configuration is described below in relation to [Fig.2].

[0070] According to this nested configuration, each second grid 132 has a height that is greater than the height of the first grids 131. Preferably, the height of the second grids 132 is 20 nm to 50 nm greater than that of the first grids 131. The lateral dimension of the second grids is preferably identical to that of the first grids.

[0071] Moreover, every second grid 132 extends: • directly on the dielectric 121 between two adjacent first grids (or, put another way, in the inter-first grid spaces), and • on the spacer layer 133 covering the sides and the top face of the first grids at the crossing areas IG1,G2.

[0072] In other words, every second grid 132 passes over, or overlaps, the first grids 131 coated with the spacer layer 133 at the crossing areas IGi,g2- This overlap makes it possible not to physically cut the first grids 131 at the crossing areas 133.

[0073] Thanks to the spacer layer 133 which is interposed between the first grids 131 and the second grids 132, each second grid 132 crosses the first grids 131 without there being any electrical contact between them.

[0074] Moreover, as the height of the second grids 132 is greater than that of the first grids 131, at the crossing zones 133, the first grids 131 are housed under insulating recesses 133R of the second grids 132.

[0075] These insulating recesses (also referred to more simply as "recesses 133R" hereafter) are visible in [Fig.2]. Each insulating recess 133R forms an insulating bridge under which a first grid 131 passes.

[0076] Fig. 3 shows an enlarged view of two consecutive insulating recesses 133R.

[0077] The insulating recesses 133R here have a hard mask layer 1331 related to the manufacturing process.

[0078] As shown in [Fig.3], the insulating recesses 133R define in each second grid 132 a lower stage 136, and an upper stage 137 which are conductive.

[0079] The lower stage 136 has a pattern comprising a plurality of lower conducting zones 1361 (cf. [Fig.2]).

[0080] Each lower conductive region 1361 is separated from the adjacent lower conductive regions by one of the insulating recesses 133R.

[0081] The upper stage 137 forms a continuous upper conductive region 137. The nested configuration therefore allows electrical continuity to be maintained along each first grid 131 and along each second grid 132.

[0082] As will be described later in the description, these lower conductive areas 136 and the upper conductive region 137 are advantageously used to form the charge detectors 140.

[0083] As shown in [Fig. 1], the arrangement of the first and second grids also makes it possible to define on the surface of the dielectric 121 a network of regular spaces (also referred to as "two-dimensional meshes" hereafter). Each two-dimensional mesh corresponds to the area of ​​a quantum dot 1151.

[0084] Each two-dimensional unit cell comprises the free dielectric space defined at the intersection between two adjacent first grids and two adjacent second grids. Each two-dimensional unit cell also comprises the closed contour formed by the portions of the grids at the intersection.

[0085] In the example of [Fig. 1], the X, Y directions of the first and second grids 131, 132 here are orthogonal to each other. The two-dimensional meshes- The sionelles are square in shape.

[0086] The X, Y directions of the first and second grids 131, 132 can alternatively be oriented with an angle other than 90°.

[0087] When the semiconductor layer 110 has holes 117 as illustrated in [Fig.1], the X and Y directions of the first and second grids also correspond, respectively, to the directions of the rows and columns of holes 117. The first and second grids are further arranged so that there is a hole opposite each crossing zone IG1,g2- Thus, a hole 117 is arranged at each vertex of the two-dimensional meshes.

[0088] Independent control of each first and second grid 131, 132 allows electro-static control and with short-range interactions of a quantum dot 1151 in each region of the semiconductor layer 110 located above a two-dimensional mesh.

[0089] This control is facilitated by the presence of the holes 117 since these allow to confine (in a non-electrostatic manner) charges at the level of the regions of the semiconductor layer forming the quantum dots 1151.

[0090] Each region of the semiconductor layer 110 forming a quantum dot has lateral dimensions, defined in the {X,Y} plane, which are preferably between 5 nm and 100 nm, and preferably equal to 50 nm. The thickness of the region of the semiconductor layer 110 forming a quantum dot is also preferably between 5 nm and 30 nm, and preferably equal to 15 nm.

[0091] The distance between two neighboring quantum dots, that is to say two quantum dots formed opposite two neighboring two-dimensional lattices, is preferentially between 25 nm and 125 nm.

[0092] More specifically, the control of the first and second grids allows the conduction of tunnel barriers 1152a, 1152b located on either side (along the X and Y directions) of each quantum dot to be controlled by field effect.

[0093] In the portion of [Fig. 1] representing an enlarged view of a two-dimensional mesh, these tunnel barriers 1152a, 1152b are represented by dashed rectangles. Each tunnel barrier, denoted 1152a, is located opposite a second grid 132 and connects the quantum dot 115 Cj to the adjacent quantum dot 115 Cij (or 115 Cij) formed on the same row (115a) of the two-dimensional mesh network. Each tunnel barrier, denoted 1152b, is located opposite a first grid 131 and connects the quantum dot 115 Cj to the adjacent quantum dot 115 Cj+i (or 115 Cj i) formed on the same column (115b) of the two-dimensional mesh network.

[0094] The tunnel barriers 1152a, 1152b preferentially have lateral dimensions smaller than those of the quantum dots 1151, for example dimensions lateral dimensions between 5 nm and 30 nm. Their thickness, however, is similar to that of 1151 quantum dots.

[0095] According to the above, the first grids 131 are arranged directly above first tunnel barriers 1152b, and the second grids are arranged directly above second tunnel barriers 1152a. Each first tunnel barrier 1152b connects two neighboring quantum dots arranged in the same column 115b of the quantum dot matrix, while each second tunnel barrier 1152a connects two neighboring quantum dots arranged in the same row of this matrix 115.

[0096] Each charge detector 140 comprises a conducting quantum island 141 (also referred to as island 141 hereafter) and a charge reservoir 142.

[0097] Each charge detector 140 can be measured by reflectometry.

[0098] As shown in Figures 2 and 6, the island 141 of each charge detector 140 is formed between two first adjacent grids 131 and directly on the dielectric 121.

[0099] Thus, this island 141 is formed at the same level as the first and second grids 131, 132. The expression "at the same level" means that each island 141 is formed between the lower face of the first grids and the upper face of the second grids. This makes it possible to obtain a compact quantum device 100 (in terms of height).

[0100] Furthermore, as will be described later in the description in relation to the manufacturing process, forming the conductive islands 141 between first grids 131 offers the advantage of being able to use these first grids 131 as alignment references during the manufacturing steps of the conductive islands 141. In other words, the first grids allow the islands 141 to "self-align". This self-alignment facilitates these manufacturing steps.

[0101] Compactness and ease of manufacture are advantages for scaling up quantum processors.

[0102] Common to the two embodiment variants illustrated respectively in [Fig.2] and 5, each island 141 is formed in one of the lower conductive zones 1361 of a second grid 132. These lower conductive zones 1361 are, as described previously, contained between two first grids 131.

[0103] The island 141 of each charge detector is thus "placed" on the dielectric 121 directly above a tunnel barrier 1152a. Each island 141 is thus coupled to one or the other of the quantum dots 1151 arranged, in the plane of the semiconductor layer 110, on either side of this tunnel barrier 1152a. This coupling is shown by arrows in the part of [Fig. 1] representing an enlarged view of a two-dimensional unit cell. Each charge detector 140 is then shared between at least two quantum dots 1151.

[0104] Several islands 141 (cf. [Fig.2]) are formed in the same second grid 132.

[0105] In this second grid 132, the lower conducting zones 1361 defining an island 141 are covered by a tunnel layer 1441. This tunnel layer 1441 is arranged within the second grid 132. This tunnel layer 1441 has the effect of electrically isolating the island 141 from the upper conducting stage 137 and from the other islands 141 of the second grid 132. It also has the effect of allowing the formation of a tunnel current within it.

[0106] All the charge detectors 140 of this second grid have a common charge reservoir 142, formed, at least, by the upper stage 137 of this second grid 132. The common charge reservoir 142 is connected by tunnel coupling to each conducting island through the tunnel layer 1441.

[0107] Finally, each charge detector 140 of this second grid 132 has a grid terminal 144, formed by the tunnel layer 1441 and a dielectric pattern called barrier pattern 1442.

[0108] This barrier pattern 1442 crosses the upper conductive region 137 from the tunnel layer 1141 to the upper face of the grid 132. This barrier pattern 1442 is vertically aligned with a portion of the conductive island 141. It is, moreover, embedded in the upper conductive region 137.

[0109] Thus, the conductor island 141, the charge tank 142 and the grid terminal of each detector 140 is formed in a second grid 132.

[0110] The shared use of the second grids 132 makes it possible to reduce the overall footprint (lateral and vertical) of the charge detector 140 in the quantum device 100.

[0111] The use, in particular, of the upper conductive area 137 to form / incorporate the charge reservoirs 142, 143 offers an additional advantage for integrating the addressing and reading functions of the charge detectors 140. Indeed, this upper conductive area 137 is easily accessible for re-establishment of electrical contact from above and / or for re-establishment of electrical contact at the ends of the second grids.

[0112] A structure for controlling the polarization of the grid terminal 144 of each island 141 can thus include grid-conducting vias 1433 (also referred to as grid vias 1433 hereafter). As shown in [Fig. 2], each grid via 1433 has a lower end disposed on the upper face of the second grid 132, in contact with a barrier motif 1442.

[0113] A readout structure for each island 141 may further comprise one or more readout conductive vias 1421 (also referred to hereafter as readout vias 1421). Each readout via 1421 has an end disposed on the upper face of the second grid 132, in contact with the upper conductive region 137. In In the example of [Fig.2], several reading vias 1421 are arranged on the same second grid 132.

[0114] In this case, an encapsulation layer 148 is disposed on the upper face of the second grid to encapsulate the grid vias 1443 and the read vias 1421. This encapsulation layer 148 can be formed of a dielectric, for example SiO2. [Fig. 2] shows the presence of a hard mask layer 1332 interposed within the encapsulation layer 148. This hard mask layer 1332 is related to the manufacturing process.

[0115] The number of conducting islands 141 formed in the same second grid 132 depends on the internal structure of this second grid 132.

[0116] According to the first embodiment, illustrated in figures 1, 2, 3 and 4, the internal structure of the second grid 132 is of a first type allowing the formation of an island 141 in one lower conductive region 1361 out of two.

[0117] According to this first type of internal structure, and with reference to [Fig.2], one lower conductive region 1361-1 on two extends the upper conductive region 137 towards the dielectric 121.

[0118] This region 1361-1 defines a complementary lower conducting region 1361-2 (also referred to as complementary lower region 1361-2 hereafter).

[0119] The complementary lower region 1361-2 is covered by a lower barrier layer, called tunnel layer 1441. This tunnel layer 1441 is disposed on the recesses 133R adjacent to the complementary lower region 1361-2. In other words, the tunnel layer 1441 forms a lid on the complementary lower region, this lid resting on the adjacent recesses 133R.

[0120] The tunnel layer 1441 has characteristics enabling tunnel coupling within it.

[0121] Tunnel layer 1441 can be formed of aluminium oxide (Al2O3).

[0122] The tunnel layer 1441 can be formed of silicon dioxide (SiO2). In this case, the tunnel layer 1441 has a thickness between 1 nm and 3 nm.

[0123] Preferably, the tunnel layer 1441 is formed from hafnium oxide (HfO2). This material exhibits a programmable resistance that can be adjusted to a value between a few kiloohms and a few tens of kiloohms. The tunnel layer 1441 then preferably has a thickness between 5 nm and 10 nm.

[0124] Tunnel layer 1441 allows an island 141 to be defined in the lower complementary region 1361-2.

[0125] The upper stage 137 and the lower conducting region 1361-1 extending towards this upper stage 137 form the charge reservoir 142 of the island 141 formed in the complementary lower region 1361-1. The tunnel coupling between this reservoir of charge 143 and islands 141 is carried out in tunnel layer 1441.

[0126] The first type of internal structure also provides that a barrier pattern 1442 forming an upper barrier layer 1442 extends through the upper conductive region 137, from the tunnel layer 1441 to the upper face of the second grid 132.

[0127] This barrier pattern 1442 is enveloped by the upper conductive region 137. Thus, the upper conductive region 137 remains continuous along the second grid 132. The barrier pattern 1442 is and disposed in line with at least part of the complementary lower conductive region 1361-2.

[0128] The barrier motif 1442 is formed of a material similar to that forming the tunnel layer 1441. In this way, it is suitable for achieving tunnel coupling within it. The barrier motif is preferably formed of a material selected from the following: SiO2, Al2O3, HfO2.

[0129] The barrier pattern 1442 forms, with the corresponding portion of the tunnel layer 1441, the grid terminal 144 of the island 141 formed in the complementary lower region 1361-2.

[0130] As shown in [Fig. 4], each second grid 132 can exhibit this structure of the first type. Alternatively, a second grid 132 can exhibit this structure of the first type.

[0131] The lower conducting regions 1361-2 chosen to define the islands 141 in a given second grid 132 are preferentially offset with respect to those chosen for a neighboring second grid 132.

[0132] Thus, and with reference to [Fig. 1], the islands 141 are arranged in a staggered pattern relative to each other within the assembly formed by the second grids 132. Consequently, the load cells 140 are also arranged in a staggered pattern relative to each other. This staggered arrangement ensures good measurement sensitivity with a reduced number of load cells 140.

[0133] Returning to [Fig.2], the control structure for the polarization of the grid terminals 144 preferentially comprises metallization lines, called readout lines 1445, which are coupled to an LC reflectometry circuit 1446. Each readout line 1445 is electrically connected to the readout vias 1421 arranged on the same second grid 132.

[0134] Each reading line 1145 can couple conducting portions 137 located on the same line 115a of the matrix 115 of quantum dots 1151.

[0135] Alternatively, Each reading line 1145 can couple conducting portions 137 located on the same diagonal 115c of the matrix 115 of quantum dots 1151.

[0136] Furthermore, the control structure for the polarization of the gate terminals 144 can including 1444 metallization lines, called 1444 grid lines, coupled to a voltage source. Each 1444 grid line is preferably connected to 1443 grid vias arranged on the same line of the 115 matrix of quantum dots.

[0137] The association of the reading and control structures of the grid terminals allows for individual reading of the charge detectors 140.

[0138] According to the second embodiment, illustrated in Figures 5 and 6, the internal structure of the second grid 132 is of a second type allowing the formation of an island 141 in each lower conducting region 1361. This second type thus makes it possible, compared to the first type, to double the number of charge detectors 140 formed in the same second grid 132. As shown in [Fig. 5], there are then as many charge detectors 140 as there are quantum dots 1151.

[0139] By increasing the number of charge detectors in this way, it is possible to measure each quantum dot more closely to it. This improves the sensitivity of the quantum dot measurements.

[0140] The second type of internal structure differs from the first type in that all the lower conducting regions 1361 of the second grid 132 are covered by the tunnel layer 1441. The tunnel layer 1441 then extends in the entire plane of the second grid, at the level of the upper face of the recesses 133R of this second grid (cf. [Fig.6]).

[0141] On the other hand, there is a barrier pattern 1442 in the vertical position of each lower conductive region 1361. As in the structure of the first type, the barrier pattern 1442 crosses the upper conductive region 137 up to the tunnel layer 1441 and is coated with the upper conductive region 137.

[0142] Figures 7, 8 and 9 show a second embodiment of the quantum device 100.

[0143] The second embodiment differs from the first embodiment, illustrated in figures 1 to 6, in that the charge detectors 140 are not formed in the second grids 132 but in third grids 135 intended to control the chemical potential of the quantum dots 1151.

[0144] As shown in [Fig.9], the second grids 132 are then covered, on their sides and their upper face, with a layer 133' of insulating material forming a spacer 133' analogous to the spacer 133. The spacer 133' then makes it possible to electrically isolate these second grids from the third grids 135.

[0145] It is noted that on this [Fig.9], the dielectric 121 is the dielectric layer 120.

[0146] The third grids are conductive strips formed from a material conductor similar to that forming the first and second grids.

[0147] As shown in Figures 7 and 8, these third grids 135 are distinct from the second grids 132 and are all oriented in a direction Y' different from the first direction X of the first grids 131. The third grids and extend directly above the quantum dots 1151.

[0148] Figure 7 shows a first variant of the second embodiment. According to this first variant, the third grids are oriented at 90° with respect to the first grids 131. In addition, each third grid 135 is arranged between two adjacent second grids, directly above the quantum dots arranged on the same column 115b of the matrix 115 of quantum dots.

[0149] The third grids 135 extend directly onto the dielectric 121 and intersect the first grids 131 (see [Fig. 7]) in a nested configuration analogous to the nested configuration described previously (in relation to the second grids 132). The crossing zones between the first and third grids are denoted with the reference IGi>G3 in Figures 7 and 8.

[0150] Figure 8 shows a second variant of the second embodiment. According to this second variant, the third grids are oriented at 45° with respect to the first and second grids 131, 132. Each third grid 135 extends vertically above the quantum dots arranged on the same diagonal 115c of the matrix 115 of quantum dots.

[0151] The third grids 135 extend directly onto the dielectric 121 and cross the first and second grids in the same nested configuration as previously described.

[0152] The crossing zones between the first grids and the third grids Igi.gs correspond to the crossing zones between the first and second grids IGi,g2-

[0153] Fig. 9 shows, in schematic form, a cross-sectional view of a third grid of the device shown in Fig. 8.

[0154] As shown in [Fig. 9], each third grid 135 extends directly over the dielectric 121 between two adjacent first grids 131 (or, in other words, in the inter-first grid spaces), and passes over, or overlaps, the first grids 131 coated with the spacer layer 133 at the crossing zones I G1, G3*

[0155] The height of the third grids 135 is greater than that of the second grids 132. Preferably, this height of the third grids is 20 nm to 50 nm greater than that of the second grids 132.

[0156] This nested configuration allows us to define a two-stage structure (a continuous conducting upper stage 137 and a lower stage formed of a plurality of lower conducting regions 1361) analogous to the structure of the second grids illustrated in [Fig.6].

[0157] This nested configuration thus makes it possible to form in each third grid 135, or in one out of every two third grids 135, the internal structure described above. previously related to the first embodiment.

[0158] In the example shown in [Fig.7], each third grid has the internal structure of the first type, illustrated in [Fig.2].

[0159] Thus, in these third grids 135, one lower conductive region 1361 out of two forms a conductive island 141. In addition, the upper conductive region 137 forms the charge reservoir 142 common to all the islands formed in the third grid 135, and barrier patterns 1442 coated with the upper conductive region 137 form the grid terminals 144 (cf. [Fig.9]).

[0160] This configuration allows each conducting island 141 to be positioned directly above a quantum dot (unlike the first embodiment, where the islands 141 are directly above the tunnel barriers).

[0161] This arrangement allows for a more localized measurement of the charge state of the quantum dot 1151 than when the charge detector 140 is directly above a tunnel barrier 1152b. Indeed, a charge detector 140 positioned directly above a quantum dot is more sensitive to the latter because it is closer than a charge detector positioned directly above a tunnel barrier. However, it is less sensitive to neighboring quantum dots.

[0162] As in the first embodiment, the islands 141 are here arranged in a staggered pattern relative to each other.

[0163] Naturally, the third grids 135 can alternatively have the structure of the second type, illustrated in [Fig.4]. In this case, in the third grids 135, each lower conducting region 1361 forms a conducting island 141. A charge detector 140 is then arranged directly above each quantum dot 1151.

[0164] In the example shown in [Fig.8], each third grid exhibits the internal structure of the second type, illustrated in [Fig.6].

[0165] Thus, as in the first embodiment illustrated in [Fig.7], each lower conductive region 1361 forms a conductive island 141. In addition, the upper conductive region 137 forms the common charge reservoir for all the islands formed in the third grid, and barrier patterns embedded in the upper conductive region form the drains 142.

[0166] This configuration allows a conducting island to be positioned directly above each quantum dot.

[0167] Naturally, the third grids can alternatively have the structure of the first type, illustrated in [Fig.2]. In this case, in the third grids 135, one lower conducting region 1361 out of two forms a conducting island 141. A charge detector 140 is then shared between two quantum dots 1151.

[0168] According to the above, the quantum device 100 comprises two sets of control grids for the quantum dots 1151: the first set comprises the first grids 131; the second set includes grids which extend directly over the dielectric 121 and cross the first grids 132. The second set includes, at least, the second grids 132.

[0169] Furthermore, the conductive island 141 of each charge detector 140 is formed by a region of one of the grids of the second set, said region being contained between two first adjacent grids 131 and disposed directly on the dielectric 121.

[0170] Fig. 10 shows a schematic representation of a block diagram of a process 800 for manufacturing the quantum device 100 illustrated in Fig. 1 and 2.

[0171] Figures 1 IA to 1 IL are schematic perspective and sectional views illustrating certain steps or substeps of the manufacturing process 800.

[0172] The manufacturing process 800 begins with a first step S801 of supplying the substrate SOI 10 comprising on one of its faces the semiconductor layer 110. This first step S801 is illustrated in [Fig.llA].

[0173] This step S801 is followed by a step S802 (cf. [Fig. 10]) of defining the arrangement of the matrix of quantum dots 115 and the tunnel barriers 1152 in the semiconductor layer 110. In other words, this step S802 consists of determining the regions of the semiconductor layer 110 in which the quantum dots 1151 will be formed, as well as the regions in which the tunnel barriers 1152a, 1152b will be formed.

[0174] This S802 step can be followed by a step of etching the semiconductor layer 110 to obtain the holes 117.

[0175] The process 800 continues with a step S803 (see [Fig. 10]) of deposition, over the entire upper surface of the semiconductor layer 110, of a first dielectric layer 121 with the material of the dielectric layer 120 of the dielectric 121

[0176] This third stage S803 is followed by a fourth stage S804 aimed at jointly forming the first grids 131, and the tunnel layer 1441.

[0177] With reference to [Fig. 10], this step S804 comprises the successive substeps S804A and S804B. These substeps are also illustrated in [Fig. 11B] and [Fig. 11C].

[0178] With reference to [Fig. 1 IB], substep S804A is a substep for forming a first stack 801 over the entire surface of the spacer 120, by:

[0179] Deposition, on the dielectric layer 120, of a first conductive layer 8011 of the conductive material of the first grids 131,

[0180] Deposition, on the first conductive layer 8011, of a second dielectric layer 8012 of the material forming the spacer 133,

[0181] Deposition, on the second layer of dielectric 8012, of a first layer of hard mask 8013.

[0182] Substep S804B is a three-dimensional structuring substep of the first stacking 801 to form first strips 802 parallel to each other others, arranged on the 120 dielectric layer opposite the first tunnel barriers 1152a defined previously.

[0183] The S804B structuring substep is carried out by defining an etching mask in the first hard mask layer 8013, then by successive etchings, through the etching mask, of the second dielectric layer 8012 and the first conductive layer 8011, stopping on the dielectric layer 120.

[0184] The device obtained at the end of this substep S804B is shown in [Fig. IIC]. As shown in [Fig. IIC], the bands 802 obtained are separated by free spaces 803 in the dielectric layer 120.

[0185] Step S804 is followed by a fifth step S805 consisting of a conformal deposition of an encapsulation layer 8041 so as to cover the outer limits of the first bands 802 and the free spaces 803. The encapsulation layer 8041 is made with the spacer material 133. This deposition can be followed by a planarization of the encapsulation layer 8041 on the upper faces of the first bands 801.

[0186] At the end of this step S805, the insulating recesses 133R of the second grids 132 are prepared.

[0187] The process 800 is extended with a sixth step S806 whose purpose is to jointly form the second grids 132 and the islands 141 in these second grids 132.

[0188] With reference to [Fig. 10], step S806 preferentially comprises the successive substeps S806A, S806B, S806C, S806D, S806E, S806F, S806G and S806H illustrated respectively in Figures 11D, 11E, 11F, 11G, 11H, 11J, and 11K.

[0189] With reference to [Fig. 11D], substep S806A consists of forming lower conductive strips 805 by filling the inter-first strips 803 with the conductive material intended to form the second grids 132. The filling is carried out up to the level of the encapsulation layer 8041 disposed on the upper face of the first strips 802. This filling is advantageously followed by a planarization of the deposited conductive layer to leave a flat upper surface 805a flush with the first strips 802.

[0190] With reference to [Fig. 11E], substep S806B consists of depositing, over the entire upper surface 805a formed at the end of step S806A, a stack 806 of barrier layers comprising: a lower barrier layer 8061 formed with the material of the tunnel layer 1441 and an upper barrier layer 8062 formed with the material of the barrier patterns 1442.

[0191] Substep S806C, which extends substep S806B, consists of structuring the stack of dielectric layers 806 in three dimensions to form bands barriers 807. With reference to [Fig. 11F], these barrier strips 807 are preferably parallel to each other and oriented at 45° to the first strips 801. In addition, in a direction Xi perpendicular to the first strips 802. Furthermore, each barrier strip 807 covers a lower conductive strip 803 as well as the first two adjacent strips 801.

[0192] The orientation of the barrier bands 807 makes it possible to achieve the desired periodicity of the charge detectors 140 in the quantum device 100. Here, the 45° orientation makes it possible to achieve the periodicity of an island 141 formed in a lower conducting region 1361 on two (that is to say of one charge detector 140 for two quantum dots 1151).

[0193] The resulting structure is illustrated in [Fig.1 1F].

[0194] These barrier strips 807 define the tunnel layer 1441 and allow the islands 141 to be defined.

[0195] The next substep S806D consists of anisotropic etching of the upper barrier layer 8062 from the barrier strips 807, stopping at the lower barrier layer 8061. The final structure is illustrated in [Fig. 11G]. In each dielectric strip 807 thus structured, the upper barrier layer 8062 forms an upper dielectric strip 807a whose lateral dimensions (along the X direction) are smaller than the dimension of the lower conductive strip 805c, and which is positioned in a central region 8051 of this lower conductive strip 805c. The fourth dielectric layer 8061 forms a lower barrier strip 707b.

[0196] Substep S806E, illustrated in [Fig. 11H], consists of forming an upper conductive layer 808 by depositing the conductive material intended to form the second grids 132 over the entirety of the lower and upper dielectric bands 807a, 807b and up to the edge of these upper dielectric bands 807a. This substep S806E may further include a planarization operation of the upper conductive layer 808.

[0197] The substeps S806F, S806G and S806H aim to structure in three dimensions the stack 808a formed by the lower conductive strips 805 and the upper conductive layer 808 to form second conductive strips 809 parallel to each other and oriented perpendicularly to the first strips 802, extending over the dielectric layer 120 and crossing the first strips by forming insulating bridges over these first strips 802.

[0198] Substep S806F, illustrated in [Fig.1 II] consists of forming one or more layers 809a, 809b intended to form a hard mask 809 over the entire planarized surface.

[0199] Substep S806G, illustrated in [Fig. 1 IJ], consists of defining an etching mask in the hard mask layer 809, so as to define second bands 810 pa parallel to each other and oriented perpendicularly to the first bands 802, extending opposite the second tunnel barriers 1152b (not shown on [Fig.1 1 J]), and each enveloping a plurality of portions of the barrier layers 807a, 807b.

[0200] The substep S806H consists of performing a selective etching through the hard mask 809, of the structured dielectric strips 807a and 807b, of the upper conductive strip 808 and of the lower conductive strips 805, with stopping on the dielectric layer 120.

[0201] The structure thus formed is illustrated in [Fig.1 1 K].

[0202] At the end of this substep S806H, the second bands 810 are formed. These second bands 810 correspond to the second grids with the charge detectors 140 formed within them.

[0203] The manufacturing process can further be carried out with a step S807 consisting of removing the hard mask 809 remaining on the upper face of the second bands 810, and then carrying out a silicification, for example by depositing a layer 813 of SiN on the second bands 810. [Fig.1 IL] illustrates the quantum device 100 obtained at the end of this step S807.

[0204] The manufacturing process just described makes it possible to manufacture the quantum device 100 according to the first embodiment (cf. [Fig.l]).

[0205] To realize the quantum device 100 according to the second embodiment (cf. [Fig.7]), the steps are identical except for:

[0206] The S806C substep for structuring the dielectric bands 807 is modified so that only the upper dielectric layer 8062 is structured, and so that the resulting structure defines dielectric bands extending not at 45° to the first bands, but at 90°. In this way, the dielectric bands define an island in each lower conductive band,

[0207] Substep S806D is deleted.

[0208] This method of structuring dielectric bands is advantageous in that it reduces the number of steps to be carried out.

Claims

Demands

1. A quantum device (100) comprising: - A semiconductor layer (110) adapted to form a two-dimensional array (115) of quantum dots (1151), the semiconductor layer (110) having a front face (HOa), - a dielectric (121) disposed on the front face (110a) of the semiconductor layer (110), - First grids (131) and second grids (132) for controlling the quantum dots (1151), the first grids (131) and second grids (132) extending directly onto the dielectric (121), each second grid (132) intersecting the first grids (131), the first and second grids (131, 132) defining a two-dimensional mesh network, each two-dimensional mesh being opposite a quantum dot (1151), - Charge detectors (140), each detector charging (140) including a conductive charging tank (142) and a conductive island (141),the conducting island (141) of each charge detector (140) being formed at the level of a two-dimensional mesh, between two first adjacent grids (131) and directly on the dielectric (121).

2. Quantum device (100) according to claim 1, wherein each charge detector (140) comprises a gate terminal (144), said gate terminal being formed by a barrier layer (1441,1442) covering the conductive island (141) corresponding to the charge detector (140).

3. Quantum device (100) according to any one of claims 1 to 2, wherein the conducting island (141) of each charge detector (140) is formed in a quantum dot control grid (132, 135) distinct from the first grids (131), said grid (132, 135) crossing the first grids (131) and extending directly over the dielectric (121), said grid (132, 135) having indentations (133r) covered with an electrically insulating layer, the insulating indentations (133r) being arranged at the crossings (IGi.g2, Imm)

4.

5.

6.

7. of said grid (132, 135) with the first grids (131), each insulating recess (133r) housing a first grid (131), the insulating recesses (133r) defining, in said grid (132,135), a plurality of lower conducting regions (1361) extending directly over the dielectric (121), and a continuous upper conducting region (137). Quantum device (100) according to claim 3, wherein said grid is one of the second grids (132). Quantum device (100) according to claim 3, wherein said grid is a third grid (135) of a set of third grids (135) intended to control the chemical potential of the quantum dots (1151), each third grid (135) being arranged vertically above the quantum dots (1151) formed along a column (115b) or a diagonal (115c) of matrix (115) of quantum dots. Quantum device (100) according to any one of claims 3 to 5, wherein said grid has an internal structure of a first type comprising: - a lower conducting region (1361-1) on two extending the upper conducting region (137) towards the dielectric (120) and defining a complementary lower conducting region (1361-2), - the lower complementary conductive region (1361-2) covered with a lower barrier layer, called tunnel layer (1141), the tunnel layer (1441) being disposed on the insulating recesses (133R) adjacent to the lower complementary conductive region (1361-2), - a dielectric pattern (1142) forming an upper barrier layer (1142) extending through the upper conductive region (137) of the tunnel layer (1141) to the upper face of said grid, the dielectric pattern being enclosed by the upper conductive region (137) and disposed vertically above at least a portion of the complementary lower conductive region (1361-2). Quantum device (100) according to any one of claims 3 to 5, wherein the internal structure of said second grid is of a second type in which: All the lower conducting regions (1361) of said grid are covered with a tunnel layer (1441), the tunnel layer (1441) being continuous and disposed on the recesses (133r) of said grid, Each lower conductive region is surmounted by a dielectric pattern (1442), each dielectric pattern forming with the tunnel layer (1141) a barrier layer (144), each dielectric pattern passing through the upper conductive region (137) of the tunnel layer (1441) disposed on the associated lower conductive region to the upper face of said grid, the dielectric pattern being enveloped by the upper conductive region (137) and disposed vertically over at least a portion of the associated lower conductive region (1361-2).

8. Quantum device (100) according to claims 3 to 7, comprising metallization lines (1445), referred to as read lines (1145) of the charge detectors (140), each read line (1445) being coupled, on the one hand, to the upper conductive region (137) of a grid (132, 135) forming conductive islands, and on the other hand, to a read circuit (1446), said read circuit (1446) comprising an inductance and a capacitance forming a resonant circuit whose resonant frequency depends on the impedance of the charge detectors (140), allowing measurements in reflectometry.

9. Quantum device (100) according to claims 1 to 8, wherein the semiconductor layer (110) comprises holes (117) to form quantum dots (1151).

10. A method for manufacturing (8) a quantum device (100) comprising charge detectors (140), each charge detector (140) comprising a conducting island (141) and a charge reservoir (142), the method (8) comprising the following steps: - Providing (S801, S810) a semiconductor layer adapted to form a two-dimensional array (115) of quantum dots (1151), said semiconductor layer (110) having a front face (110a), said semiconductor layer (110) comprising a dielectric (121) disposed on the front face (110a) and first grids (131) for controlling the quantum dots (1151), the first grids (131) extending directly onto the dielectric (121), - Coating (S815) of the sides and top face of each first grid (131) to house each first grid (131) under an insulating recess (133R), - Definition (S820A, S820B, S820C) of the conducting islands (141) from the coated first grids, each conducting island (141) extending between two adjacent first grids (131) and directly onto the dielectric (121), - Formation (S820D), from the defined conducting islands (141), of second grids (132) to control, with the first grids, the quantum dots, each second grid extending directly onto the dielectric (121) and crossing the first grids (131), the first and second grids (131, 132) forming a network of two-dimensional meshes on the dielectric (121).

11. A manufacturing method according to claim 10, wherein the step (S820A, S820B, S820C) of defining the conductive islands comprises the following substeps: - Filling (S820A) with a conductive material of the spaces (803) of the dielectric (121) delimited by two first adjacent coated grids (802), the filling stopping at the height of the insulating recesses, - Formation (S820B) of a barrier layer (806) over the entire surface obtained after filling, - Structuring (S820C) of the barrier layer (806) to form barrier strips (807) oriented with a predetermined angle with respect to the first grids.

12. A manufacturing method (8) according to any one of claims 10 to 11, wherein the predetermined angle is such that the barrier strips (807) are oriented at 45° with respect to the direction of the first grids, the barrier strips extending, in the direction perpendicular to the first grids, over four adjacent conductive strips.