Analog to digital conversion

Abstract

Analog-to-digital conversion The present description relates to a device (1) comprising an analog-to-digital converter (100) having a first input (101) receiving an analog signal (sigi) to be converted, and a generator (103) providing ramps (VR) to a second input (105) of the analog-to-digital converter. The analog-to-digital converter (100) comprises: - a comparator (113) having a first input (115) connected to the first input (101) of the analog-to-digital converter, - a capacitive digital-to-analog converter (121) having an output (123) connected to a second input (117) of the comparator (113), and - a switch (IT) connected between the second input (117) of the comparator and the second input (105) of the analog-to-digital converter. Figure for abstract: Fig. 1

Description

Title of the invention: Analog-to-digital conversion Technical field

[0001] The present description relates generally to electronic circuits, devices and systems, and, more particularly, to analog-to-digital conversion and analog-to-digital conversion devices. Prior art

[0002] Analog-to-digital conversion devices are known. For example, analog-to-digital conversion devices configured to implement analog-to-digital conversion by comparison to a staircase ramp and then by successive approximations are known. For example, WO 2013 / 127751 A1 describes an example of such an analog-to-digital conversion device.

[0003] However, known analog-to-digital conversion devices have various drawbacks. Summary of the invention

[0004] There is a need to overcome some or all of the disadvantages of known analog-to-digital conversion devices. For example, it would be desirable to reduce the noise of known analog-to-digital conversion devices.

[0005] One embodiment overcomes some or all of the disadvantages of known analog-to-digital conversion devices. For example, one embodiment provides an analog-to-digital conversion device having reduced noise compared to known analog-to-digital conversion devices.

[0006] In a first aspect, an embodiment provides a device comprising: an analog-to-digital converter; a sampling circuit comprising: - a capacitive element having a first electrode connected to a first input of the converter, the first input being configured to receive an analog signal to be converted into a digital signal, - a first switch having a first conduction terminal configured to receive an input voltage and a second conduction terminal connected to a second electrode of the capacitive element, - a second switch having a first conduction terminal configured to receive a direct voltage and a second conduction terminal connected to the second electrode of the capacitive element, and - a third switch having a first conduction terminal configured to receive said direct voltage and a second conduction terminal connected to the first input of the converter; and a switch control circuit configured, during an input voltage sampling phase, to successively: - turn on the third switch, turn on the first switch and turn off the second switch, - setting the third switch to the off state while the first switch is in the on state and the second switch is in the off state, and - put the first switch in the off state and the second switch in the on state while the third switch is in the off state.

[0007] According to one embodiment, the DC voltage has a value equal to (VNR+VPR) / 2, with VNR a minimum voltage of a conversion dynamic of the analog-digital converter and VPR a maximum voltage of said conversion dynamic.

[0008] According to one embodiment, a capacitance value of the capacitive element is greater than or equal to a value Cmin defined by: Cmin = (Kb*Tmax*12) / (Qs*Qs), with Kb the Boltzmann constant, Tmax a maximum operating temperature of the converter in Kelvin, and Qs a quantization step of the converter defined by: Qs = dyn / (Bit_nb)A2, with dyn an amplitude in Volts of a conversion dynamic of the converter and Bit_nb the number of bits of said digital signal.

[0009] According to one embodiment, the converter comprises a comparator having a first input connected to the first input of the converter.

[0010] According to one embodiment: the device comprises a ramp generator configured to provide ramps to a second input of the analog-to-digital converter, each ramp having a succession of predetermined values ​​in a staircase; the comparator of the analog-to-digital converter comprises a second input coupled to the second input of the analog-to-digital converter; and the analog-to-digital converter comprises a capacitive digital-to-analog converter having an output connected to the second input of the comparator.

[0011] According to one embodiment: each predetermined value of each ramp is determined by a corresponding combination of states of a set of high-order bits; the analog-to-digital converter includes a switch coupling its second input to the second input of the comparator; the analog-to-digital converter comprises a first circuit configured to receive an output from the comparator; the first circuit is configured, during a first conversion phase analog to digital where one of said ramps is provided to the second input of the analog to digital converter, for: - detect a switching of the comparator output, - maintaining said switch on until said detection and switching said switch to the off state following said detection, and - store the most significant bits corresponding to the predetermined value of the ramp having caused said switching of the comparator output.

[0012] According to one embodiment: the digital-to-analog converter comprises capacitive elements each having a first electrode selectively coupled to a first reference voltage or a second voltage and a second electrode coupled to the output of the digital-to-analog converter, each of said capacitive elements corresponding to a bit of a set of least significant bits; the first circuit is configured, during said first phase, to couple the first electrode of that of said capacitive elements which corresponds to the highest of the least significant bits to the second voltage, the first electrode of at least one other of said elements to the second voltage and the first electrodes of all the other capacitive elements to the first reference voltage.

[0013] According to one embodiment, the digital-to-analog converter comprises an additional capacitive element connected between a first node of the digital-to-analog converter and the output of the digital-to-analog converter, each of said capacitive elements having its second electrode connected to said first node or to said output, preferably to said first node.

[0014] According to one embodiment, the first circuit is configured, after switching to the blocked state of said switch of the analog-digital converter, to: coupling the first electrode of said at least one other of said capacitive elements to the first reference voltage so as to cause an offset on the output of said digital-to-analog converter; then, during a second phase of analog-to-digital conversion, controlling the digital-to-analog converter to determine by successive approximations said least significant bits; and store the least significant bits determined by successive approximations.

[0015] According to one embodiment, the first circuit is configured to provide the digital signal by assembling the stored high-order bits with the stored low-order bits and taking into account said offset.

[0016] According to one embodiment, said offset determines a redundancy between the stored high-order bits and the stored low-order bits, and the first circuit is configured, during said assembly, to concatenate the stored high-order bits and the least significant bits stored taking into account said redundancy.

[0017] According to one embodiment, the sampling circuit further comprises: a fourth switch having a first conduction terminal configured to receive said ramps and a second conduction terminal connected to the second electrode of the capacitive element of the sampling circuit; and a fifth switch having a first conduction terminal configured to receive a calibration voltage and a second conduction terminal connected to the first electrode of said capacitive element.

[0018] According to one embodiment, the switch control circuit is configured, during a calibration phase, to: keep the first, second and third switches locked throughout the calibration phase; switching the fifth switch to the off state while a first of said ramps has a given value among said predetermined values ​​and the fourth switch is on, then switching the fourth switch to the off state while the first ramp has a value equal to that of said predetermined values ​​which immediately follows said given value; and keep the fourth and fifth switches blocked until the end of the first ramp and during a subsequent analog-to-digital conversion implemented by the analog-to-digital converter.

[0019] Another embodiment provides a system for converting analog signals, present respectively on a plurality of channels, into digital signals, the system comprising, for each channel, a device as described above for the first aspect and configured to receive the analog signal of said channel on the first conduction terminal of the first switch of its sampling circuit.

[0020] Another embodiment provides a system for converting analog signals, present respectively on a plurality of channels, into digital signals, the system comprising, for each channel, a device as described above for the first aspect and configured to receive the analog signal of said channel on the first conduction terminal of the first switch of its sampling circuit, the ramp generator of each device being implemented by a single ramp generator shared by all the devices.

[0021] In a second aspect, an embodiment provides a device comprising: an analog-to-digital converter having a first input configured to receive an analog signal to be converted and a second input configured to receive voltage ramps each having a succession of predetermined values ​​in a staircase; and a sampling circuit comprising: - a capacitive element connected between the first input of the analog-digital converter and a first node, - a first switch connected between the first node and a second node configured to receive said voltage ramps, and - a second switch connected between the first input of the analog-to-digital converter and a third node configured to receive a calibration voltage.

[0022] According to one embodiment, the device comprises a circuit for controlling the switches of the sampling circuit configured, during a calibration phase, to: switching the second switch to the off state while a first of said ramps has a given value among said predetermined values ​​and the first switch is on, then switching the first switch to the off state while the first ramp has a value equal to that of said predetermined values ​​which immediately follows said given value; and keep the first and second switches blocked until the end of the first ramp and during a subsequent analog-to-digital conversion implemented by the analog-to-digital converter.

[0023] According to one embodiment, the analog-digital converter comprises: a comparator having a first input connected to the first input of the analog-to-digital converter; a digital-to-analog converter having an output connected to a second input of the comparator; and a switch connected between the second input of the analog-to-digital converter and the second input of the comparator.

[0024] According to one embodiment: each predetermined value of each ramp is determined by a corresponding combination of states of a set of high-order bits; and the digital-to-analog converter comprises first capacitive elements each having a first electrode selectively coupled to a first reference voltage or a second voltage and a second electrode coupled to the output of the digital-to-analog converter, each of said capacitive elements corresponding to a bit of a set of least significant bits.

[0025] According to one embodiment, the digital-to-analog converter comprises a second capacitive element connected between a first node of the digital-to-analog converter and the output of the digital-to-analog converter, each first capacitive element having its second electrode connected to said first node. or at said output, preferably at said first node.

[0026] According to one embodiment: the device comprises a first circuit connected to an output of the comparator; and the first circuit is configured, during each analog-digital conversion, For : - detecting a switching of the comparator output while one of said ramps is supplied to the second input of the analog-to-digital converter, - keeping the switch of the analog-to-digital converter on until said detection, and switching said switch to the off state following said detection, - store the most significant bits corresponding to the predetermined value of the ramp having caused said switching of the comparator output, and - after switching said switch to the off state, to control the digital-to-analog converter to determine by successive approximations said least significant bits, and - memorize the low-order bits determined by successive approximations.

[0027] According to one embodiment, the first circuit is configured, during each analog-digital conversion, to: coupling, at least until said switch is switched to the off state, the first electrode of that of said capacitive elements which corresponds to the highest of the least significant bits to the second voltage, the first electrode of at least one other of said capacitive elements to the second voltage and the first electrodes of all the other capacitive elements to the first reference voltage; then coupling, before the implementation of said successive approximations, the first electrode of said at least one other of said capacitive elements to the first reference voltage so as to cause an offset on the output of said digital-analog converter.

[0028] According to one embodiment, the first circuit is configured to provide a digital signal by assembling the stored high-order bits with the stored low-order bits and taking into account said offset.

[0029] According to one embodiment, the sampling circuit further comprises: - a third switch connected between the first node and an input of the device configured to receive an input voltage, - a fourth switch connected between the first node and a fourth node configured to receive a direct voltage, and - a fifth switch connected between the first input of the analog-to-digital converter and the fourth node.

[0030] According to one embodiment: the sampling circuit further includes: - a third switch connected between the first node and an input of the device configured to receive an input voltage, - a fourth switch connected between the first node and a fourth node configured to receive a direct voltage, and - a fifth switch connected between the first input of the analog-to-digital converter and the fourth node; and the control circuit of the switches of the sampling circuit is further configured, during a sampling phase of the input voltage, to successively: - put the fifth switch in the on state, the third switch in the on state and the fourth switch in the off state, - setting the fifth switch to the off state while the third switch is in the on state and the fourth switch is in the off state, and - set the third switch to the off state and the fourth switch to the on state while the fifth switch is in the off state.

[0031] According to one embodiment, the control circuit of the switches of the sampling circuit is further configured, throughout the duration of said calibration phase, to keep the third, fourth and fifth switches open.

[0032] According to one embodiment, the device comprises a ramp generator configured to provide said ramps to the second input of the analog-digital converter.

[0033] Another embodiment provides a system for converting analog signals present respectively on a plurality of channels, into digital signals, the system comprising, for each channel, a device as described above for the second aspect, the input of said device being configured to receive the analog signal.

[0034] According to one embodiment, the ramp generator of each device is implemented by a single ramp generator shared by all the devices.

[0035] In a third aspect, one embodiment provides a device comprising: an analog-to-digital converter having a first input configured to receive an analog signal to be converted; and a generator configured to provide ramps to a second input of the analog-to-digital converter, the analog-digital converter comprising: - a comparator having a first input connected to the first input of the analog-to-digital converter, - a capacitive digital-to-analog converter having an output connected to a second input of the comparator, and - a switch connected between the second input of the comparator and the second input of the analog-to-digital converter.

[0036] According to one embodiment: each of said ramps has a succession of predetermined values ​​in a staircase, each associated with a corresponding combination of states of a set of high-weight bits; and the digital-to-analog converter comprises capacitive elements each having a first electrode selectively coupled to a first reference voltage or a second voltage and a second electrode coupled to the output of the digital-to-analog converter, each of said capacitive elements corresponding to a bit of a set of least significant bits.

[0037] According to one embodiment, the digital-to-analog converter comprises an additional capacitive element connected between a first node of the digital-to-analog converter and the output of the digital-to-analog converter, each of said capacitive elements having its second electrode connected to said first node or to said output, preferably to said first node.

[0038] According to one embodiment: the analog-to-digital converter comprises a first circuit coupled to the output of the comparator; the first circuit is configured, during a first phase of analog-digital conversion where one of said ramps is received by the second input of the analog-digital converter, to: - detect a switching of the comparator output, - maintaining said switch in the on state until said detection, and switching said switch to the off state following said detection, - coupling the first electrode of the one of said capacitive elements which corresponds to the highest of the least significant bits to the second voltage, the first electrode, the first electrode of at least one other of said capacitive elements to the second voltage and the first electrodes of all the others of said capacitive elements to the first reference voltage, at least until said switch switches to the off state, and - memorize the most significant bits corresponding to the predetermined value of the ramp having caused said switching of the comparator output; and the first circuit is configured, after switching to the off state of said switch, to: - coupling the first electrode of said at least one other of said capacitive elements to the first reference voltage so as to cause an offset on the output of said digital-analog converter, then - during a second phase of analog-to-digital conversion, controlling the digital-to-analog converter to determine by successive approximations said least significant bits, and - memorize the low-order bits determined by successive approximations.

[0039] According to one embodiment, the first circuit is configured, after said second conversion phase, to provide a digital output signal from the analog-to-digital converter by assembling the stored high-order bits with the stored low-order bits and taking into account said offset.

[0040] According to one embodiment, said offset determines a redundancy between the stored high-order bits and the stored low-order bits, and the first circuit is configured, during said assembly, to concatenate the stored high-order bits and the stored low-order bits and taking into account said redundancy.

[0041] According to one embodiment, a conversion dynamic of the analog-to-digital converter extends from a low voltage VNR to a high voltage VPR, each two successive predetermined values ​​being separated by a step equal to (VPR-VNR) / (2AMSB_nb), with MSB_nb a total number of bits of the set of most significant bits.

[0042] According to one embodiment, the first reference voltage is greater than the second voltage, the second voltage is equal to the low voltage VNR and an output dynamic of the digital-to-analog converter is greater than or equal to the ramp step.

[0043] According to one embodiment: the device further comprises a sampling circuit; and the sampling circuit includes: - a first capacitive element having a first electrode connected to the first input of the analog-digital converter, - a first switch having a first conduction terminal configured to receive an input voltage and a second conduction terminal connected to a second electrode of the first capacitive element, - a second switch having a first conduction terminal configured to receive a direct voltage and a second conduction terminal connected to the second electrode of the first capacitive element, and - a third switch having a first conduction terminal configured to receive said direct voltage and a second conduction terminal connected to the first input of the analog-digital converter.

[0044] According to one embodiment, the device comprises a circuit for controlling the switches of the sampling circuit configured, during a sampling phase of the input voltage, to successively: - turn on the third switch, turn on the first switch and turn off the second switch, - setting the third switch to the off state while the first switch is in the on state and the second switch is in the off state, and - put the first switch in the off state and the second switch in the on state while the third switch is in the off state.

[0045] According to one embodiment, the DC voltage has a value equal to (VNR+VPR) / 2.

[0046] According to one embodiment, the sampling circuit further comprises: a fourth switch having a first conduction terminal configured to receive said ramps and a second conduction terminal connected to the second electrode of the first capacitive element; and a fifth switch having a first conduction terminal configured to receive a calibration voltage and a second conduction terminal connected to the first electrode of said first capacitive element.

[0047] According to one embodiment, the control circuit of the switches of the sampling circuit is configured, during a calibration phase, to: keep the first, second and third switches locked throughout the calibration phase; switching the fifth switch to the off state while a first of said ramps has a given value among said predetermined values ​​and the fourth switch is on, then switching the fourth switch to the off state while the first ramp has a value equal to that of said predetermined values ​​which immediately follows said given value; and keep the fourth and fifth switches blocked until the end of the first ramp and during a subsequent analog-to-digital conversion implemented by the analog-to-digital converter.

[0048] Another embodiment provides a system for converting analog signals, present respectively on a plurality of channels, into digital signals, the system comprising, for each channel: a device as described above for the third aspect having the first input of its analog-to-digital converter configured to receive the analog signal of said channel, the ramp generator of each device being implemented by a single ramp generator shared by all the devices; or a device as described above for the third aspect having the first conduction terminal of the first switch of its sampling circuit configured to receive the analog signal of said channel, the ramp generator of each device being implemented by a single ramp generator shared by all the devices.

[0049] In a fourth aspect, one embodiment provides a device comprising an analog-to-digital converter having a first input configured to receive an analog signal to be converted, the analog-to-digital converter comprising: - a comparator having a first input connected to the first input of the analog-to-digital converter, and - a capacitive digital-to-analog converter having an output connected to a second input of the comparator, the digital-to-analog converter comprising: first capacitive elements each having a first electrode selectively coupled to a first reference voltage or to a second voltage and a second electrode coupled to the output of the digital-to-analog converter; and a second capacitive element connected between a first node of the digital-to-analog converter and the output of the digital-to-analog converter, each first capacitive element having its second electrode connected to said first node or to said output.

[0050] According to one embodiment, the first capacitive elements all have their first electrodes connected to the first node.

[0051] According to one embodiment, the digital-to-analog converter comprises a switch selectively coupling the first node of the digital-to-analog converter to a reset voltage of the digital-to-analog converter.

[0052] According to one embodiment, the second capacitive element is implemented by a metal-insulator-metal or metal-oxide-metal type capacitor resting on a semiconductor layer, an electrode of the capacitor closest to the semiconductor layer being connected to the first node of the digital-analog converter.

[0053] According to one embodiment, the analog-to-digital converter further comprises a switch connected between the second input of the comparator and a second input of the analog-to-digital converter, the device further comprising a generator configured to provide ramps to the second input of the analog-to-digital converter.

[0054] According to one embodiment: each of the first capacitive elements corresponds to a bit of a set of low-order bits; and each of said ramps has a succession of predetermined values ​​in steps, each associated with a corresponding combination of states of a set of high-weight bits.

[0055] According to one embodiment: the analog-to-digital converter comprises a first circuit coupled to the output of the comparator; the first circuit is configured, during a first phase of analog-digital conversion where one of said ramps is received by the second input of the analog-digital converter, to: - detect a switching of the comparator output, - maintaining said switch in the on state until said detection, and switching said switch to the off state following said detection, - coupling to couple the first electrode of that of said capacitive elements which corresponds to the highest of the least significant bits to the second voltage, the first electrode of at least one other of said first capacitive elements to the second voltage and the first electrodes of all the other first capacitive elements to the first reference voltage, at least until switching to the blocked state of said switch, and - memorize the most significant bits corresponding to the predetermined value of the ramp having caused said switching of the comparator output; and the first circuit is configured, after switching to the off state of said switch, to: - coupling the first electrode of said at least one other of said first capacitive elements to the first reference voltage so as to cause an offset on the output of said digital-analog converter, then - during a second phase of analog-to-digital conversion, controlling the digital-to-analog converter to determine by successive approximations said least significant bits, and - memorize the low-order bits determined by successive approximations.

[0056] According to one embodiment, the first circuit is configured, after said second conversion phase, to provide a digital output signal from the analog-to-digital converter by assembling the stored high-order bits with the stored low-order bits and taking into account said offset.

[0057] According to one embodiment, said offset determines a redundancy between the stored high-order bits and the stored low-order bits, and the first circuit is configured, during said assembly, to concatenate the stored high-order bits and the stored low-order bits taking into account said redundancy.

[0058] According to one embodiment: the device further comprises a sampling circuit; and the sampling circuit includes: - a capacitive element having a first electrode connected to the first input of the analog-digital converter, - a first switch having a first conduction terminal configured to receiving an input voltage and a second conduction terminal connected to a second electrode of said capacitive element, - a second switch having a first conduction terminal configured to receive a direct voltage and a second conduction terminal connected to the second electrode of said capacitive element, and - a third switch having a first conduction terminal configured to receive said direct voltage and a second conduction terminal connected to the first input of the analog-digital converter.

[0059] According to one embodiment, the sampling circuit further comprises: - a fourth switch having a first conduction terminal configured to receive said ramps and a second conduction terminal connected to the second electrode of the capacitive element of the sampling circuit, and - a fifth switch having a first conduction terminal configured to receive a calibration voltage and a second conduction terminal connected to the first electrode of said capacitive element.

[0060] According to one embodiment, the device comprises a control circuit of the sampling circuit configured, during a sampling phase of the input voltage, to successively: - turn on the third switch, turn on the first switch and turn off the second switch, - setting the third switch to the off state while the first switch is in the on state and the second switch is in the off state, and - put the first switch in the off state and the second switch in the on state while the third switch is in the off state.

[0061] According to one embodiment, the control circuit is configured, during a calibration phase, to: keep the first, second and third switches locked throughout the calibration phase; switching the fifth switch to the off state while a first of said ramps has a given value among said predetermined values ​​and the fourth switch is on, then switching the fourth switch to the off state while the first ramp has a value equal to that of said predetermined values ​​which immediately follows said given value; and keep the fourth and fifth switches blocked until the end of the first ramp and during a subsequent analog-to-digital conversion implemented by the analog-to-digital converter.

[0062] Another embodiment provides a system for converting analog signals present respectively on a plurality of channels, into digital signals. merics, the system comprising, for each channel: - a device as described above for the fourth aspect and having the first input of its analog-to-digital converter configured to receive the analog signal of said channel, the ramp generator of each device being implemented by a single ramp generator shared by all the devices; or - a device as described above for the fourth aspect and having the first conduction terminal of the first switch of its sampling circuit configured to receive the analog signal of said channel, the ramp generator of each device being implemented by a single ramp generator shared by all the devices. Brief description of the drawings

[0063] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0064] [Fig.l] represents, in the form of blocks, an embodiment of a device configured to implement an analog-digital conversion;

[0065] [Fig.2] represents, in more detail than in [Fig.l], an exemplary embodiment of a block of [Fig.l];

[0066] [Fig.3] represents an alternative embodiment of the block described in relation to [Fig.2];

[0067] [Fig.4] represents, in more detail than in [Fig.l], an exemplary embodiment of another block of [Fig.l];

[0068] [Fig.5] represents an alternative embodiment of the block described in relation to [Fig.4]; and

[0069] [Fig.6] represents, in block form, an example of an embodiment of an electronic system comprising a plurality of devices as described in relation to [Fig.1]. Description of the embodiments

[0070] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0071] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the known circuits and applications in which at least one analog-digital conversion device is implemented have not been detailed, the embodiments and variants described below being compatible with these known circuits and applications.

[0072] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0073] In the remainder of the description, unless otherwise indicated, the voltage of a node corresponds to the potential of this node referenced to ground GND.

[0074] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0075] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0076] [Fig.l] represents, in the form of blocks, an embodiment of a device 1 configured to implement an analog-digital conversion.

[0077] The device 1 comprises an analog-to-digital converter 100 (delimited by dotted lines in [Fig.l]). The converter or circuit 100 comprises an input 101. The input 101 is configured to receive an analog signal sigi, preferably a voltage, to be converted.

[0078] The device 1 further comprises a ramp generator 103 (block "R_Gen"). The generator 103 is configured to provide ramps VR to an input 105 of the converter 100. For example, the generator 103 comprises an output 107 coupled, preferably connected, to the input 105 of the converter 100.

[0079] The VR ramps are, for example, voltage ramps. The VR ramps are, for example, all identical. For example, the VR ramps are decreasing, although in other examples these VR ramps may be increasing.

[0080] By way of example, the ramps VR have a maximum value or voltage VPR and a minimum value or voltage VNR. The values ​​VPR and VNR define, for example, the conversion dynamics of the device 1. For example, the device 1 can convert, without saturating, the signal sigi into a digital signal sigi_num as long as the signal sigi has a value in a range from VPR inclusive to VNR inclusive, i.e. as long as the signal sigi is within the conversion dynamics of the device 1. The voltage VPR is, for example, greater than the voltage VNR. By way of example, the ramp generator 103 comprises an input 109 configured to receive the DC voltage VPR and an input 111 configured to receive the DC voltage VNR. Although this is not illustrated in [Fig.l], the voltages VPR and VNR are, for example, provided by respective voltage generators of a system comprising one or more devices 1.

[0081] The VR ramps each have a succession of predetermined values ​​in a staircase. Each predetermined value of the VR ramps is associated with a corresponding combination of states of most significant bits, or, more simply put, with most significant bits. For example, the generator 103 is controlled by a digital signal ctrll. The signal ctrll is, for example, received by an input 131 of the generator 103. For example, the set of most significant bits comprises, in total, a number MSB_nb of bits. In this case, the step (or plateau) between two successive values ​​of each VR ramp is equal to (VPR-VNR) / (2AMSB_nb). Furthermore, each VR ramp then takes 2AMSB_nb predetermined values. The number MSB_nb and the voltages VPR and VNR determine a search range of each VR ramp.

[0082] The generator 103 is for example controlled by a circuit 141 (block "NUM") of the device 1. The circuit 141 is, for example, configured to provide the signal ctrll. By way of example, the circuit 141 comprises an output 145 configured to provide the signal ctrll, the output 145 being coupled, preferably connected, to an input 131 of the circuit 103.

[0083] The circuit 141 is a digital circuit. The circuit 141 is, for example, clocked by a clock signal clk. For example, the circuit 141 comprises an input 143 configured to receive the signal clk. For example, the signal ctrll is updated on the rising edges of the signal clk, so that, during each ramp VR, the current predetermined value of the ramp VR is updated at each rising edge of the signal clk.

[0084] By way of example, the circuit 141 comprises an input 147 configured to receive a start signal, for example a binary signal, requesting an analog-to-digital conversion of the signal sigi by the device 1. For example, when the start signal is in a first binary state, corresponding for example to a high level of the start signal, the device 1 is in a phase of initializing an analog-to-digital conversion, this analog-to-digital conversion starting for example with the switching to a second binary state of the start signal, corresponding for example to a low level. By way of example, during the first binary state of the start signal, the generator 103 initializes its output 107 to VPR (decreasing VR ramps) or to VPN (increasing VR ramps), under the control of the signal ctrll, or even directly under the control of the start signal.

[0085] The converter 100 comprises a comparator 113 (block "CMP"). The comparator 113 has an input 115, an input 117 and an output 119. The output 119 provides a bit cmp_out in a first state when the input 117 has a value greater than that of the input 115, and in a second state when the input 117 has a value less than that of the input 115. For example, the comparator 113 is clocked by the clock signal clk, the comparator 113 being for example sensitive (or active) on a second type of edges of the clk signal, for example falling edges. In other words, the comparator 113 updates its output 119 according to the state of its inputs 117 and 115 at each edge of the second type of the clk signal.

[0086] Input 115 of comparator 113 is connected to input 101 of the converter. Input 115 therefore receives the signal sigi to be converted.

[0087] The converter 100 further comprises a digital-to-analog converter 121 ("DAC" block). The converter 121 is of the capacitive type. The converter 121 has an output 123 configured to provide an analog output signal of the converter 123, the output 123 being connected to the input 117 of the comparator 113. The input 117 of the comparator is further coupled to the input 105 of the converter 100 by a switch IT of the converter 100. For example, the switch IT has a first conduction terminal connected to the input 117 and to the output 123, and a second conduction terminal connected to the input 105.

[0088] The digital-to-analog converter 121 comprises capacitive elements, for example a number LSB_nb of capacitive elements. Each of the LSB_nb capacitive elements has a first electrode selectively coupled to a VPD voltage or a VND voltage and a second electrode coupled to the output 123 of the converter 121. The VPD voltage is, for example, greater than the VND voltage, the latter being, for example, equal to the VNR voltage. Each of the LSB_nb capacitive elements corresponds to a bit of a set of least significant bits. The set of least significant bits comprises LSB_nb least significant bits in total. More precisely, each of the LSB_nb capacitive elements corresponds to one of the LSB_nb least significant bits which is in a first state when the first electrode of the corresponding capacitive element is coupled to the voltage VPD, and in a second state when the first electrode of the corresponding capacitive element is coupled to the voltage VND.For example, the voltages VPD and VND are received by respective inputs 125 and 127 of the converter 121.

[0089] The voltages VPD and VND determine the output dynamics of the converter 121. According to one embodiment, the output dynamics of the converter 121 is at least equal to the pitch of the VR ramps, for example equal to two VR ramp steps.

[0090] The VPD and VND voltages determine a search range by successive approximations.

[0091] The converter 100 comprises a circuit 133 (block "NUMi"). The circuit 133 is a digital circuit clocked by the signal clk. For example, the circuit 133 is active or sensitive on the first type of edges of the signal clk, for example on the rising edges of the signal clk. For example, the circuit 133 comprises an input 135 configured to receive the signal clk.

[0092] For example, during an initialization phase of the device 1, for example controlled by the start signal, the circuit 133 is also in an initialization phase. As an example, although this is not shown in [Fig.l], the circuit 133 receives the start signal. As another example, the circuit receives a control signal indicating the state of the start signal and therefore controlling an initialization of the circuit 133 when the start signal controls an initialization of the device 1.

[0093] Circuit 133 is a control circuit of converter 100. Circuit 133 is coupled to output 119 of comparator 113, so as to receive the output bit cmp_out of the comparator. For example, circuit 133 includes an input 137 coupled, preferably connected, to output 119 of comparator 113.

[0094] The circuit 133 is configured to control the switch IT. For example, the circuit 133 comprises an output 139 configured to provide a control signal ctrl2 to the switch IT, the output 139 being coupled, preferably connected, to a control terminal of the switch IT. More particularly, during a first phase of an analog-to-digital conversion of the signal sigi by the device 1, while a ramp VR is provided to the input 105 of the converter 100, the circuit 133 is configured to switch the switch IT to the on state at the start of the ramp VR, for example during an initialization phase of the analog-to-digital conversion, and to switch the switch IT to the off state following the detection of a switching of the signal cmp_out.Furthermore, following detection of the switching of the cmp_out signal, the circuit 133 is configured to store the MSB_nb most significant bits corresponding to the predetermined value of the VR ramp which caused the switching of the cmp_out signal, i.e. to store the combination of states of the MSB_nb most significant bits corresponding to this predetermined value.

[0095] As an example, to know when a VR ramp begins and what are the MSB_nb most significant bits corresponding to the current predetermined value of the VR ramp which is present on the input 105 of the converter, for example to be able to memorize the MSB_nb most significant bits corresponding to the predetermined value of the VR ramp having caused the switching of the output 119 of the comparator 113, the circuit 133 receives a signal ctrl3 from the circuit 141. For example, the circuit 141 has an output 151 configured to provide the signal ctrl3, the output 151 being for example coupled, preferably connected, to an input 153 of the circuit 133. The signal ctrl3 is a signal indicating at what point in the analog-digital conversion the device 1 is located. For example, the signal ctrl3 is an output signal of a counter (not shown in [Fig.l]) of circuit 141, which is initialized at the start of each analog-to-digital conversion, for example during an initialization phase of the analog-to-digital conversion, and which is incremented at each period of the clk signal, for example at each falling edge of the clk signal. Preferably, the counter is a gray counter having less digital noise than a conventional counter.

[0096] The circuit 133 is further configured to control the digital-to-analog converter 121. For example, the circuit 133 controls the circuit 121 by means of a DAC_ctrl signal. For example, the circuit 133 comprises an output 155 configured to provide the DAC_ctrl signal, the output 155 being coupled, for example connected, to an input 157 of the circuit 121.

[0097] During the first phase of an analog-digital conversion corresponding to the reception of a ramp VR by the input 105 of the converter 100, for example from the start of the ramp VR and at least until the opening of the switch IT, the circuit 133 controls the circuit 121 so that the first electrodes of the LSB_nb capacitive elements of the circuit 121 are coupled to the voltage VPD with the exception of the first electrodes of the capacitive elements corresponding to the strongest and second strongest of the LSB_nb least significant bits which are coupled to the voltage VND.

[0098] After switching the switch IT to the off state and before a second phase of the analog-digital conversion, for example between the first phase and the second phase, the circuit 133 controls the converter 121 so as to shift the voltage on the output 123 of the converter 121. This shift is configured to create a redundancy between the search range of the ramp VR and the search range by successive approximations, the successive approximations being implemented during the second phase of the analog-digital conversion, by means of the converter 121, the comparator 113 and the circuit 133.

[0099] To implement this shift, after switching the switch IT to the off state and before the second phase of the analog-to-digital conversion, the circuit 133 controls the converter 121 so that each of the LSB_nb capacitive elements has its first electrode coupled to the voltage VPD, with the exception of the first electrode of the capacitive element corresponding to the highest of the LSB_nb least significant bits which remains coupled to the voltage VND. In other words, the circuit 133 controls the converter 121 so that the voltage to which the first electrode of the capacitive element corresponding to the second highest of the LSB_nb is coupled switches from the voltage VND to the voltage VPD.

[0100] After the implementation of this shift, the LSB_nb capacitive elements of the converter 121 all have their first electrodes coupled to the same voltage VPD, this voltage being called the reference voltage of the converter 121, with the exception of the first electrode of the capacitive element corresponding to the highest of the LSB_nb least significant bits which is coupled to the voltage VND. For example, when the dynamics of the converter 121 is equal to two ramp steps VR, the shift is then half a ramp step.

[0101] During the second phase of analog-to-digital conversion, the circuit 133 controls the converter 121, based on the state of the signal cmp_out, to de terminate by successive approximations the LSB_nb least significant bits, that is to say the combination of states of the LSB_nb least significant bits corresponding to the voltage on the output 123 of the circuit 121 which is closest to the voltage sigi. These least significant bits are then memorized by the circuit 133. The implementation of the analog to digital conversion by successive approximations is within the reach of the person skilled in the art.

[0102] During the second phase of analog-digital conversion, the switch IT is kept in the open state by the circuit 133.

[0103] For example, during the second phase of analog-digital conversion, the signal DAC_ctrl, and therefore the voltage on the output 123 of the converter 121, are updated under the control of the circuit 133 at each period of the signal clk, for example at each edge of a first type of the signal clk, for example at each rising edge of the signal clk.

[0104] At the end of the second phase of analog-to-digital conversion, according to one embodiment, the circuit 133 is configured to assemble the MSB_nb high-order bits stored during the first phase with the LSB_nb low-order bits stored during the second phase. This assembly is implemented by taking into account the shift made on the output 123 of the converter 121 before the implementation of the second phase of the analog-to-digital conversion. The circuit 133 then provides the digital signal sigi_num which corresponds to, or is representative of, this assembly of bits. The signal sigi_num is, for example, the digital output signal of the converter 100, and is, for example, provided by an output 126 of the circuit 133, the output 126 being for example connected to an output 128 of the device 1.

[0105] According to one embodiment, this assembly of bits consists of concatenating the stored MSB_nb high-order bits with the stored LSB_nb low-order bits, taking into account the shift previously performed on the output 123 of the converter 121, i.e. taking into account the redundancy between the search range of each VR ramp and the successive approximation search range, or, in other words, taking into account the redundancy between the stored MSB_nb high-order bits and the stored LSB_nb low-order bits. The signal sigi_num is then a digital signal comprising, for example, MSB_nb + LSB_nb - 1 bits.

[0106] As an example, taking the example above where the offset is half a VR ramp step and the output dynamics of the converter 121 is two VR ramp steps, the assembly of the stored high-order bits with the stored low-order bits consists of concatenating the LSB_nb stored low-order bits, except for the highest, with the MSB_nb stored high-order bits to which the highest of the low-order bits has been added, then subtracting, from this concatenation of bits, a bit having a weight just less than that of the highest of the least significant bits. For example, we consider that: - MSB_nb is equal to 6, - LSB_nb is equal to 9, - the MSB_nb high-weight bits correspond to the code "010101", i.e. the decimal value 21, - the LSB_nb low-order bits correspond to the code "100000001", i.e. the decimal value 257. In this example, the highest bit of the stored LSB_nb least significant bits is '1', and is added to the code of the stored MSB_nb most significant bits, which gives a first intermediate code "010110". This first intermediate code "010110" is concatenated with the code of the stored LSB_nb least significant bits except the highest, that is to say with the code "00000001", which gives a second intermediate code "01011000000001". We then subtract from this second intermediate code a bit having a weight just lower than that of the highest of the low-order bits, that is to say a bit of weight LSB_nb-2 equal to 7 in this example, and we obtain the final code "01010110000001" which corresponds to the decimal value 5505, the signal sigi_num being for example equal to this final code.In other words, in decimal, this amounts to implementing the following calculation (val_MSB*2A(LSB_nb - 1)) + val_LSB - 2A(LSB_nb - 2), with val_MSB the decimal value corresponding to the stored MSB_nb high-weight bits, and val_LSB the decimal value corresponding to the stored LSB_nb low-weight bits, which amounts to 21*256 + 257 - 128 = 5505.

[0107] In the device 1, the predetermined value of the ramp VR having caused the switching of the signal cmp_out is therefore stored directly on the output of the converter 121 following the opening of the switch IT, then the output voltage of the converter 121 is shifted to create a redundancy between the search range of the ramp and the finer search range by successive approximations, before implementing these successive approximations. The assembly of the stored high-order bits with the stored low-order bits is then implemented taking into account the redundancy determined by this shift, to provide the signal sigi_num.

[0108] In the device 1, there is no need to provide a capacity dedicated to storing a difference between a predetermined value of the ramp close to the signal to be converted and the value of the signal to be converted, unlike what is implemented in the document WO 2013 / 127751 A1. Furthermore, the noise in the device 1 is reduced compared to the noise in the analog-digital conversion device of the document WO 2013 / 127751 A1.

[0109] Although the case where the dynamics has been described above as a particular example output of the converter 121 is equal to two ramp steps VR, and where the offset of the voltage on the output of the converter 121 is half a ramp step and is implemented by controlling the coupling of the first electrodes of the capacitive elements of the converter 121 in the manner described above, the person skilled in the art is able to adapt the above example to the case where the output dynamics of the converter 121 is more generally equal to at least one ramp step VR and / or the offset of the voltage on the output 123 of the converter 121 is different from half a ramp step VR.

[0110] In particular, the person skilled in the art is able to adapt, as a function of the pitch of the VR ramps and the output dynamics of the converter 121, which of the LSB_nb capacitive elements are controlled or used to implement the shift, i.e. the capacitive element(s) of the converter 121 for which the voltage to which their first electrodes are coupled switches from the VPD voltage to the VND voltage to implement the shift, so that, after the shift has been implemented, the signal sigi to be converted is within the successive approximation search range. The person skilled in the art will also be able to adapt the way in which the assembly of the stored high-order bits with the stored low-order bits is implemented, taking into account the shift, i.e. taking into account the redundancy between the stored MSB_nb high-order bits and the stored LSB_nb low-order bits.

[0111] According to one embodiment, the device 1 further comprises a sampling circuit 153 (block "S / H"). The circuit 153 is configured to receive an input voltage Vi from the device 1, and to provide the signal sigi to the converter 100, the signal sigi being representative of a sampled value of the voltage Vi. By way of example, the circuit 153 comprises an input 155 configured to receive the voltage Vi, and an output 157 configured to provide the signal sigi to be converted, the output 157 being for example connected to the input 101 of the converter 100. The device 1 then comprises a control circuit (not shown in [Fig.l]) for the sampling circuit 153. For example, the control circuit of the sampling circuit 153 is configured to provide at least one control signal ctrl4 to the circuit 153, for example to an input 159 of the circuit 153.The control circuit of the sampling circuit 153 is, for example, part of the circuit 133 and the circuit 133 comprises, for example, an output 161 configured to provide said at least one ctrl4 signal. In other examples not illustrated, the control circuit of the circuit 153 is not part of the circuit 133, and is, for example, directly part of the circuit 153.

[0112] The circuit 153 is configured to implement a sampling phase of the voltage Vi, at the end of which the signal sigi is stable and representative of the sampled value of the voltage Vi.

[0113] According to one embodiment, the circuit 153 is further configured to allow the implementation of a calibration phase of the device 1. In this case, the circuit 153 is further configured to receive the VR ramps. For example, the circuit 153 then comprises an input 163 configured to receive the VR ramps, the input 163 being for example connected to the output 107 of the circuit 103. Alternatively, the circuit 153 does not allow the implementation of this calibration phase, and the input 163 is omitted.

[0114] [Fig.2] represents, in more detail than in [Fig.l], an exemplary embodiment of the converter 121 of the device 1.

[0115] As previously described in relation to [Fig.l], the converter 121 comprises for example the inputs 125 and 127 configured to receive the respective voltages VPD and VND determining the output dynamics of the converter 121. The converter 121 comprises the output 123 configured to provide the analog output voltage of the converter 121, the output 123 being connected to the input 117 of the comparator 113 (see [Fig.l]). The converter 121 also comprises the input 157 configured to receive the DAC_ctrl control signal of the converter 121.

[0116] Furthermore, as also previously described in relation to [Fig.l], the converter comprises exactly LSB_nb capacitive elements Cj, with j an integer index ranging from 0 to LSB_nb - 1. As an example, each element Cj is implemented from one or more unitary capacitive elements each having the same Cunit value. For example, each element Cj comprises exactly 2Aj unitary capacitive elements coupled or connected in parallel. In other words, each capacitive element Cj has a value equal to 2Aj times Cunit.

[0117] Each element Cj has a first electrode or terminal 200 selectively coupled to the input 127, i.e. to the voltage VND, or to the input 125, i.e. to the voltage VPD. In addition, each element Cj has a second electrode 202 or terminal coupled to the output 123 of the converter 121.

[0118] In the embodiment illustrated by [Fig.2], the electrode 202 of each element Cj is connected to the output 123.

[0119] For example, each element Cj is selectively coupled to input 127 or 125 by a circuit 204. Each circuit 204 is controlled by the signal DAC_ctrl.

[0120] For example, each circuit 204 includes an input 208 coupled, preferably connected, to terminal 200 of a corresponding capacitive element Cj. Furthermore, each circuit 204 has an output 210 connected to input 125 (voltage VPD) and an output 212 connected to input 127 (voltage VND).

[0121] In another example not illustrated, each of the unitary capacitive elements which constitutes an element Cj is selectively coupled to the input 127 or 125 by a circuit 204 dedicated, or corresponding, to this unitary capacitive element. All the circuits 204 dedicated to the unitary capacitive elements of the same element Cj are then controlled in the same way, for example by the signal DAC_ctrl. For example, each circuit 204 has its input 208 which is coupled, for example connected, to one electrode or terminal of the corresponding unitary capacitive element, the other electrode or terminal of this unitary capacitive element being coupled to the output 123, for example connected to this output 123 in the embodiment of [Fig.2].

[0122] The converter 121 further comprises a capacitive element CO' having the same value as the capacitive element CO. This capacitive element CO' has an electrode 214 coupled to the input 125 receiving the reference voltage VPD of the converter 121, and an electrode 216 coupled to the output 123, for example connected to the output 123 in the embodiment of [Fig.2].

[0123] In the example of [Fig.2], the electrode 214 of the capacitive element CO' is connected to the input 125 receiving the reference voltage VPD from the converter 121.

[0124] In another example not illustrated, the electrode 214 of the capacitive element C0' is coupled to the input 125 receiving the reference voltage VPD from the converter 121 by a circuit 204, the latter being controlled or configured to maintain the electrode 214 coupled to the input 125.

[0125] When each unitary capacitive element is associated with its own circuit 204, it is possible to choose which unitary capacitive element(s) each element Cj is made of. This choice can be made randomly, and be, for example, modified on command or periodically. This choice can also be fixed, and be, for example, the result of a calibration phase of the converter 121 making it possible to reduce the impact of manufacturing dispersions of the Cunit value of the unitary capacitive elements on the values ​​of the LSB_nb capacitive elements Cj.

[0126] Taking the particular example described in relation to [Fig. 1] where the output dynamics of the converter 121 is equal to two VR ramp steps and the shift implemented before the second phase of each analog-to-digital conversion is half a VR ramp step, [Fig. 2] illustrates more particularly the state of the converter 121 during the first phase of an analog-to-digital conversion of the signal sigi and before the shift of the voltage on the output 123 of the converter 121 is implemented. Thus, as illustrated in [Fig. 2], the circuit 204 of the element CLSB_nb-2, which corresponds to the second highest of the LSB_nb least significant bits, couples its input 208 to its output 212, and the circuit 204 of the element CLSB_nb-1, which corresponds to the highest of the LSB_nb least significant bits, couples its input 208 to its output 212, while all the other circuits 204 couple their inputs 208 to their outputs 210.The implementation of the shift then consists of controlling the circuit 204 of the CLSB_nb-2 element so that it couples its input 204 to its output 210, so that the voltage on the output 123 increases by half a VR ramp step.

[0127] [Fig. 3] represents an alternative embodiment of the converter 121 described in relation to [Fig.2]. Only the differences between the converter 121 of [Fig.2] and that of [Fig.3] are highlighted here.

[0128] In the converter 121 of [Fig.2], the electrodes 202 of all the elements Cj and the electrode 216 of the element CO' when the latter is present, are all connected to the output 123.

[0129] On the other hand, the converter 121 of [Fig.3] comprises an additional capacitive element Cseg, for example called a capacitive segmentation element. The element Cseg has an electrode, or terminal, 300 connected to the output 123, and an electrode, or terminal, 302 connected to a node 304 of the converter 121. Furthermore, at least some of the elements Cj have their electrodes 202 connected to the node 304, the other elements Cj, if any, having their electrodes 202 connected to the output 123. For example, K elements Cj, namely the elements Cj of index i ranging from 0 to K-1, have their electrodes 202 connected to the node 304, and LSB_nb-K elements Cj, namely the elements Cj of index j ranging from K to LSB_nb-1 have their electrodes 202 connected to the output 123, K being a strictly positive integer and less than or equal to LSB_nb.

[0130] Preferably, all elements Cj have their electrodes 202 connected to node 304 as illustrated in the example of [Fig.3].

[0131] When the converter 121 comprises the element C0', the electrode 216 of the latter is then connected to the node 302.

[0132] The provision of the capacitive element Cseg makes it possible to reduce the equivalent capacitance value of the converter 121 seen by the ramp generator 103 ([Fig.l]) when the switch IT is on. However, the reduction in the equivalent capacitance value of the converter 121 results in greater sensitivity to the parasitic capacitances present on the output 123.

[0133] According to one embodiment, the capacitive element Cseg is implemented from a metal-insulator-metal (MIM) or metal-oxide-metal (MOM) capacitor resting on a semiconductor layer, for example made of silicon. In this case, and according to one embodiment, the electrode of this capacitor which is closest to the semiconductor layer, i.e. the lower electrode of the capacitor, is arranged on the side of the node 304, i.e. it corresponds to the electrode 302. Indeed, the lower electrode of such a capacitor comprises more parasitic capacitances and the effect of the parasitic capacitances is more critical on the output 123 of the converter 121 than on the node 304.

[0134] The converter 121 further comprises, optionally, a switch or commutator 306 configured to selectively couple the node 304 to a reset voltage of the converter 121, for example the voltage VDN in the example of [Fig.3].

[0135] For example, switch 306 is configured to initialize the voltage on node 304 at the start of each VR ramp, by being turned on at the start of each VR ramp, for example in an initialization phase of each analog-to-digital conversion where the voltage on the output 107 of the generator 103 ([Fig.l]) is set to the voltage VP when the VR ramps are decreasing, or to the voltage VN when the VR ramps are increasing. For example, the switch 306 is controlled by the circuit 133, by the circuit 141 or directly by the start signal ([Fig.l]). During this initialization phase, the switch IT ([Fig.l]) is controlled to the on state.

[0136] [Fig.4] represents, in more detail than in [Fig.l], an exemplary embodiment of the sampling circuit 153 of [Fig.l], it being understood that the device 1 can be implemented with other circuits 153 than that described here, or even without circuit 153.

[0137] The circuit 153 comprises a capacitive element Csample, for example implemented from one or more MOM type capacitors and / or one or more MIM type capacitors.

[0138] The element Csample has an electrode 400 connected to the output 157 of the circuit 153, that is to say connected to the input 101 of the converter 100 which receives the signal sigi to be converted. The element Csample also has an electrode 402.

[0139] Circuit 153 comprises a switch IT1, a switch IT2 and a switch IT3.

[0140] The switch IT1 couples the input 155 to the electrode 402. In other words, the switch IT1 has a conduction terminal configured to receive the input voltage Vi from the device 1, and another conduction terminal connected to the electrode 402 of the capacitive element Csample.

[0141] Switch IT2 couples a node 404 to electrode 402, node 404 being configured to receive a DC voltage Vcm, voltage Vcm being, for example, called common mode voltage. In other words, switch IT2 has a conduction terminal connected to node 404 configured to receive voltage Vcm and another conduction terminal connected to electrode 402 of capacitive element Csample

[0142] Switch IT3 couples electrode 400 of capacitive element Csample, i.e. output 157 of circuit 153, to node 404. In other words, switch IT3 has a conduction terminal connected to node 404 and another conduction terminal connected to electrode 403.

[0143] As already indicated previously in relation to [Fig.l], the device 1 comprises a control circuit of the circuit 153, that is to say a control circuit of the switches of the circuit 153.

[0144] This control circuit is configured, during a sampling phase of the voltage Vi, to first put the switches IT3 and IT1 in the on state, and the switch IT2 in the off state. As long as the switches IT1, IT2 and IT3 are maintained in these states, the voltage on the electrode 400 is equal to Vcm and the voltage on the electrode 402 is equal to Vi, from which it follows that the voltage across the terminals of the element Csample is equal to Vcm-Vi taking for example the electrode 402 as reference.

[0145] The control circuit is then configured to switch switch IT3 to the off state, while switch IT1 is in the on state and switch IT2 is in the off state, or, in other words, while maintaining switch IT1 in the on state and switch IT2 in the off state. As long as switches IT1, IT2 and IT3 are maintained in these states, electrode 400 is floating and the voltage across element Csample remains unchanged compared to the previous step.

[0146] The control circuit is then configured to switch switch IT1 to the off state and switch IT2 to the on state while switch IT3 is in the off state, or, in other words, by maintaining switch IT3 in the off state. As a result, electrode 402 then receives voltage Vcm, which causes a shift of an amplitude Vcm in the voltage on electrode 400. Thus, at the end of this step, the voltage on electrode 400, i.e. voltage sigi, is equal to 2*Vcm-Vi. For example, the switching of switch IT1 to the off state and that of switch IT2 to the on state can be implemented simultaneously, or the switching of switch IT2 to the on state can be implemented after switching switch ITL to the off state.

[0147] At the end of the sampling phase, the voltage sigi is equal to 2*Vcm - Vi, and is therefore representative of the sampled value of the voltage Vi.

[0148] For example, each sampling phase as described above is implemented during a corresponding initialization phase of an analog-to-digital conversion.

[0149] The circuit 153 described here makes it possible to sample the voltage Vi with less noise than a conventional sample / hold circuit comprising a capacitor having one electrode coupled to ground and another electrode coupled to the voltage Vi by a switch.

[0150] For example, to control the switches IT1, IT2 and IT3, the control circuit of these switches supplies the signal ctrl3 to the circuit 153, for example to the input 159 of the circuit 153. The signal ctrl3 is, for example, a control signal on three bits respectively ctrl41, ctrl42 and ctrl43, the signal or bit ctrl41 controlling the switch IT1, the signal or bit ctrl42 controlling the switch IT2 and the signal or bit ctrl43 controlling the switch IT3. For example, the signal ctrl41 corresponds to the delayed signal ctrl43, so that, when the signal ctrl43 switches, the signal ctrl41 switches in the same direction but with a delay. For example, the signal or bit ctrl42 corresponds to the complement of the signal or bit ctrl41. For example, the ctrl43 signal is determined by the start signal ([Fig.l]), for example corresponds to the start signal or the complement of the start signal.

[0151] According to one embodiment, the voltage Vcm is chosen to be equal to (VPR+VNR) / 2, i.e. to the common mode voltage of the device 1. Thus, if the voltage Vi is included in the conversion dynamics of the device 1, i.e. between VPR and VPN, the voltage sigi is also included between VPR and VPN and is in phase opposition with the voltage Vi relative to the voltage Vcm. The digital signal corresponding to the analog-to-digital conversion of the voltage Vi by the device 1 is then more easily determined from the signal sigi_num than if the voltage Vcm had been arbitrary.

[0152] According to one embodiment, the capacitance value of the capacitive element Csample is chosen by taking into account the noise KT / C, so that the power of this noise is less than or equal to the power of the quantization noise of the device 1. In other words, the capacitance value of the capacitive element Csample is chosen to be greater than or equal to, preferably greater than, a value Cmin defined by: Cmin = (Kb*Tmax*12) / (Qs*Qs), with Kb the Boltzmann constant, Tmax a maximum operating temperature of the converter in Kelvin, and Qs a quantization step of the converter 100 defined by: Qs = dyn / (Bit_nb)A2, with dyn an amplitude in Volts of a conversion dynamic of the converter 100 equal to VPR-VNR and Bit_nb the number of bits of the digital signal sigi_num output of the converter 100.

[0153] [Fig.5] represents an alternative embodiment of the circuit 153 described in relation to [Fig.4],

[0154] In the illustrated example, the circuit 153 of [Fig.5] comprises the same elements IT1, IT2, IT3 and Csample as the circuit 153 of [Fig.5]. Furthermore, compared to the circuit 153 described in relation to [Fig.4], the circuit 153 described in relation to [Fig.5] is configured to allow the implementation of a calibration phase. Thus, the circuit 153 of [Fig.6] comprises the input 163 receiving the VR ramps.

[0155] Circuit 153 of [Fig.5] includes a switch IT4 coupling node 402 to input or node 163 configured to receive the VR ramps. In other words, switch IT4 has a conduction terminal connected to input 163 and another conduction terminal connected to node 402.

[0156] The circuit 153 of [Fig.5] comprises a switch IT5 coupling the electrode or node 400 to a node 500 configured to receive a direct voltage Vcal, for example called a calibration voltage. In other words, the switch IT5 has a conduction terminal connected to the node 500 and another conduction terminal connected to the node 400.

[0157] The control circuit of the switches of the circuit 153 is configured, during a calibration phase, so that the circuit 153 provides a signal sigi representative of the difference (or step or level) between two successive values ​​of a first VR ramp received by the circuit 153 (first step), so that, upon receipt of a following VR ramp by the converter 100, the signal sigi is converted into the signal sigi_num (second step).

[0158] For example, by implementing the two steps above for each pair of two successive predetermined values ​​of the VR ramps, it is then possible to determine, for each pair of two successive predetermined values ​​of the VR ramps, the value of the difference which separates these two values. When this difference is not equal to the expected step of the VR ramps (equal to (VPR-VNR) / (2AMSB_nb)), a correction can be applied to the sigi_num signal. This correction is, for example, implemented by a digital processing circuit not shown which receives the sigi_num signal.

[0159] Thus, the calibration method implemented is based, for each pair of two successive predetermined values, on an analog-digital conversion of a signal determined by, or representative of, the difference between these two values, rather than on an analog-digital conversion of a first of the two values, followed by an analog-digital conversion of the other of the two values. This latter solution has drawbacks linked to the accumulation of the error on the sampled predetermined value with the errors of the predetermined values ​​used to carry out the analog-digital conversion of the sampled predetermined value.This is not the case in the proposed method, since the value to be converted is always substantially equal to a VR ramp step, which means that the predetermined VR ramp value causing the switching of the cmp_out signal during the analog-digital conversion of the value to be converted is always the same, hence there is no error accumulation.

[0160] More particularly, during a calibration phase, the control circuit of the switches of the circuit 153 is configured to keep the switches IT1, IT2 and IT3 open.

[0161] In an alternative embodiment not illustrated, where the voltage Vi is supplied directly to the input 101 of the circuit 100, for example by a switch coupling the input 101 to a node on which the voltage Vi is available, the switches IT1, IT2 and IT3 and the capacitor Csample can be omitted. In this case, the circuit 153 is then only used during a calibration phase. Furthermore, during the calibration phase, the switch coupling the input 101 to the voltage Vi is kept open.

[0162] At a prior stage of the calibration phase, the device 1 is used, or controlled, so as to implement an analog-digital conversion of the voltage Vcal, i.e. so as to convert the voltage Vcal into a digital word (or binary code) sigi_num of MSB_nb + LSB_nb - 1 bits.

[0163] For this, the switch IT5 is put in the on state, the other switches IT1 to IT4 being kept blocked. In this way, the voltage sigi is then equal to the voltage Vcal. An analog-digital conversion by the device 1 is then implemented so as to obtain, at the end of this conversion, a digital signal sigi_num, that is to say a first digital code Vcal_num, representative of, or determined by, the value of the voltage Vcal. The first digital code Vcal_num obtained at the end of this preliminary phase of the calibration phase is recorded in the device 1, for example in the circuit 141 of the device 1, or in a processing circuit receiving the output signal sigi_num from the device 1.

[0164] This preliminary step may comprise several conversions of the voltage Vcal into a corresponding sigi_num signal, for example at least 100 conversions, preferably at least 1000 conversions, and the first digital code Vcal_num then corresponds to the average digital value of the digital signals sigi_num obtained during these conversions. Averaging the digital value Vcal_num of the voltage Vcal over several conversions makes it possible to average the conversion noise.

[0165] Alternatively, the first digital code Vcal_num corresponding to the value of the voltage Vcal was determined during the design of the device 1, and is pre-recorded in the device 1, for example in a memory of the circuit 141, or in a processing circuit receiving the output signal sigi_num of the device 1. Furthermore, for a given pair of two successive predetermined values ​​of the ramps VR, for example two successive values ​​VRj-1 and VRj where j is an integer index ranging from 1 to 2AMSB_nb - 1 and where, for each ramp, the index j increases between a current value and a following value of the ramp, upon receipt of a first of two successive ramps VR, while the first ramp VR is at the first value VRj-1, the control circuit of the switches of the circuit 153 controls the switches IT4 and IT5 to the on state.The circuit then controls the switching of switch IT5 to the off state, before updating the current value of the VR ramp. Thus, when the VR ramp goes from the first value VRj-1 to the second value VRj, the voltage on node 402 is shifted by the value of the step Aj separating these two successive predetermined values ​​VRj-1 and VRj. As a result, the voltage sigi on node 400 is then equal to Vcal-Aj, with Aj the step between the two values ​​VRj-1 and VRj. The switch control circuit then switches switch IT4 to the off state before the value of the first VR ramp is updated again, i.e. before the first VR ramp goes to the value VRj+1.Then, while all the switches of the circuit 153 are kept blocked, a second ramp VR is supplied to the converter 100 which implements an analog-to-digital conversion of the signal sigi, therefore of the value Vcal-Aj corresponding to the pair of values ​​VRj-1 and VRj. In other words, the control circuit of the circuit 153 keeps the switches IT1 to IT5 blocked until the end of the first ramp and during a conversion. analog-digital conversion implemented by the converter 100, this conversion comprising the reception of the second VR ramp. When receiving the first of the two successive VR ramps, circuits of the converter 100, for example the comparator 113 and / or the circuit 121, can be deactivated or switched off, so as to obtain a signal sigi, equal to Vcal-Aj, which is less noisy.

[0166] By implementing these steps for each pair of successive values ​​of the VR ramps, it is possible to evaluate, for example with a processing circuit receiving the sigi_num signal, the error on the value of the step between the two successive predetermined values ​​of each pair of successive predetermined values ​​with respect to the expected value Ath of this step. A correction can then be implemented on the digital signal sigi_num delivered at the end of a conversion of the sigi signal corresponding to a sampled value of the voltage Vi.

[0167] For example, for two successive predetermined values ​​VRj-1 and VRj, the signal sigi is equal to Vcal-Aj, with Aj the difference between these two values. This difference Aj is equal to Ath + errj, where j is the integer index ranging from 1 to 2AMSB_nb - 1, Ath is the ideal (or theoretical) difference between the two successive values ​​which is equal to (VPR-VNR) / (2AMSB_nb), and errj is the error that we wish to correct. Knowing that sigi is equal to Vcal-Aj, then -errj = sigi + Ath - Vcal. The digital code, or binary coding, coeffj corresponding to -errj is then equal to the digital code sigi_num to which is added the digital code Ath_num corresponding to the binary coding of the value Ath, and subtracted the digital code Vcal_num. The digital code coeffj is then recorded in the device 1, for example in the circuit 141 of the device 1, or in a processing circuit receiving the output signal sigi_num from the device 1. The coefficient coeffj can be negative and is therefore a signed digital code.By implementing these steps or calculations for each of the values ​​of the index j between 1 and MSB_nb-l, we obtain 2AMSB_nb - 1 coefficients coeffj corresponding to the 2AMSB_nb - 1 steps (or not) of the VR ramps. In the same way as for the voltage Vcal, for each step Aj, it is possible to implement several conversions, for example at least 100, preferably at least 1000, of the sigi signal equal to Vcal - Aj into a corresponding sigi_num signal, so that the coefficient coeffj is equal to sigi_num_moy + Ath_num -Vcal_num, with sigi_num_moy the digital code corresponding to the average of the sigi_num codes obtained during these conversions.

[0168] For example, during an analog-digital conversion of the voltage Vi by the device 1, the correction is implemented: - by calculating a DMSB+LSB binary code corresponding to the concatenation of the stored MSB_nb high-weight bits with the stored LSB_nb low-weight bits, - by calculating a binary code DMSB+LSB_cal corresponding to the sum of the code DMSB+LSB with the sum of the coefficients coeffj for j ranging from 1 to 2AMSB_nb -MSB_val, where MSB_val is the decimal value corresponding to the stored MSB_nb high-weight bits, - by obtaining MSB_nb calibrated high-weight bits corresponding to the MSB_nb high-weight bits of the DMSB+LSB_val code, and LSB_nb calibrated low-weight bits corresponding to the MSB_nb high-weight bits of the DMSB+LSB_val code, and - by replacing the stored MSB_nb high-order bits with the calibrated MSB_nb high-order bits and the stored LSB_nb low-order bits with the calibrated LSB_nb low-order bits, so that the assembly of the MSB_nb high-order bits with the LSB_nb low-order bits to obtain the sigi signal is implemented using the calibrated MSB_nb high-order bits and the calibrated LSB_nb low-order bits.

[0169] To correct the sigi_num signal provided following an analog-to-digital conversion of a sigi signal representative of a sampling of the voltage Vi, the person skilled in the art will be able to provide other ways of using the errors determined for the steps of the VR ramps during the calibration phase.

[0170] The person skilled in the art is able, from the description given above, to determine the value of the voltage Vcal used for the calibration phase.

[0171] According to one embodiment, the value of the voltage Vcal is chosen to allow the measurement of errors on the value of the steps of the VR ramps which are as large as possible (in absolute value because the error calculated for a given step can be negative) while ensuring that the same step of the VR ramps is used during the conversion of the signals sigi equal to Vcal-Aj, with j ranging from 1 to 2AMSB_nb - 1. In other words, the voltage Vcal determines the maximum value of the error (in absolute value) which can be measured, and therefore then corrected, for each step of the VR ramp.

[0172] For example, it is preferable to choose a voltage Vcal which is close to the VPR or VNR end of the VR ramps. Preferably, the voltage Vcal is chosen close to the VPR or VNR end where the VR ramps are the cleanest, i.e. the most stable and / or the least noisy, and / or the VPR or VNR end of the VR ramps where the comparator 113 works best.

[0173] For example, in the case where the offset implemented during a conversion phase is equal to half a VR ramp step and where Vcal is chosen close to VPR, it is desirable that all the sigi signals provided during the calibration phase, i.e. the sigi signals equal to Vcal-Aj, with j ranging from 1 to 2AMSB_nb - 1, are between VPR-A and VPR+(A / 2). It is desirable that the sigi signals are around the middle of the VPR-A and VPR+(A / 2) range, i.e. around VPR-(A / 4). Knowing that in the absence of error on the sigi = Vcal-A steps, Vcal is then preferably chosen equal to VPR + 3*A / 4.

[0174] According to another example where the offset implemented during a conversion phase is equal to half a VR ramp step and where Vcal is chosen close to VNR, it is desirable that all the sigi signals supplied during the calibration phase are between VNR+A and VNR-(A / 2). In a similar manner to the previous example, the voltage Vcal is then preferably chosen equal to VNR + 5*A / 4.

[0175] For example, the switches IT4 and IT5 are controlled from the signal ctrl4. For example, the signal ctrl4 is a five-bit control signal respectively ctrl41, ctrl42, ctrl43, ctrl44 and ctrl45, the signals or bits ctrl41 to ctrl43 controlling the respective switches IT1 to IT3, the signal or bit ctrl44 controlling the switch IT4 and the signal or bit ctrl45 controlling the switch IT5.

[0176] Although not detailed here, during a sampling phase of the voltage Vi, the switches IT1, IT2 and IT3 are controlled in the manner described in relation to [Fig.4], and, in addition, the switches IT4 and IT5 are controlled in the blocked state. More generally, outside of a calibration phase, the switches IT4 and IT5 are kept in the blocked state.

[0177] Exemplary embodiments and variants of an analog-to-digital conversion device 1 have been described above in relation to [Fig.l], [Fig.2], [Fig.3], [Fig.4] and [Fig.5]. Due to its small size and low noise, for example compared to known analog-to-digital conversion devices, this device 1 is particularly suitable for parallel implementation, for example for converting in parallel a plurality of sigi signals present on a plurality of respective channels.

[0178] According to one embodiment, the VR ramp generator 103, and, for example, its control circuit 141, are common to all the devices 1. In other words, the generator 103 of each device 1 is implemented by a single generator 103 and, for example, its control circuit 141 is shared by all the devices 1, that is to say that each VR ramp delivered by this single generator is supplied simultaneously to all the converters 100 of the devices 1. By way of example, the signal ctrl3 delivered by the control circuit 141 of the shared generator 103 is then supplied to the circuits 133 of all the devices 1 simultaneously.

[0179] By way of example, in a system comprising a plurality of devices 1 sharing a single generator 103, when a calibration phase is implemented, it can be implemented for each device 1, so as to determine, for each device 1, a correction corresponding to this device 1 in particular which is then applied to it, or so as to determine a correction averaged over all the devices 1 and applied identically to all the devices 1. According to another example, the calibration can only be implemented for one of the devices 1. positive 1, so as to determine a correction specific to this device but which is then applied identically to all devices 1.

[0180] In alternative embodiments, a generator 103 may be shared between only some devices 1, or a dedicated generator 103 may be provided per device 1.

[0181] For example, the channels providing the sigi signals correspond to the output channels of a sensor matrix, for example to the column outputs of the matrix, the sensors being for example photodetectors or bolometers. For example, devices 1 in parallel are used to read output channels of a matrix of a motion sensor in visible imaging by taking advantage of the conversion speed of the devices 1, or of an infrared light sensor by taking advantage of the low conversion noise of the devices 1.

[0182] [Fig.6] illustrates in block form an example of an embodiment of an electronic system 6 comprising a plurality of devices 1.

[0183] In the example shown, a single generator 103, and, for example, a single control circuit 141, are shared by all of the devices 1.

[0184] In the example shown, the system 6 comprises P=10 channels channeli, with i an integer index ranging from 0 to P-1. However, the person skilled in the art is able to adapt the description given here of the system 6 to the case where P is strictly greater than 1 and different from 10. In the example shown, each device 1 comprises a circuit 153, only one of these circuits 153 being referenced in [Fig.6] so as not to overload the figure. Thus, in this example, each channel channeli provides a voltage Vi corresponding to the circuit 153 of the device 1 which is associated with this channel, and more particularly to the input 155 of this circuit 153, only the inputs 155 of the two circuits 153 referenced in [Fig.6], so as not to overload the [Fig.6]. In each device 1, the input 155 of the circuit 153 of the device 1 then constitutes an input of this device 1. In each device 1, the circuit 153 of the device 1 provides the signal sigi to the converter 100 of the device 1.For example, the circuit 153 of the device 1 associated with the channel channelO receives the signal V0 on its input 155 and provides the signal sigO on its output 157 which is connected to the input 101 of the converter 100 of this device 1.

[0185] In this example, the circuits 153 allow the implementation of a calibration phase and therefore receive all the VR ramps. The person skilled in the art will be able to adapt the example described to the case where the circuits 153 do not allow the implementation of a calibration phase.

[0186] Furthermore, in another example not illustrated, the devices 1 do not include a circuit 153. In this case, each channel channeli provides a signal sigi rather than a signal Vi, this signal sigi being directly provided to the input 101 of the converter 100 of the device 1 associated with this channel channeli.

[0187] For each channel channeli, the converter 100 of the device 1 associated with this channel provides the sigi_num signal from the sigi signal. For example, the converter 100 of the device 1 associated with the channel channelO provides the sigO-num signal from the sigi signal.

[0188] For example, in the system 6, the devices 1 operate in a synchronized manner. For example, for each analog-to-digital conversion, the devices 1 are all simultaneously in the first phase of this analog-to-digital conversion, then all simultaneously in the second phase of this analog-to-digital conversion, the devices being furthermore, for example, all simultaneously in the initialization phase of this analog-to-digital conversion.

[0189] As a very specific example of implementation, we consider that: - the output dynamics of the converters 121 ([Fig.l]) is equal to twice the step of the VR ramps; - the shift implemented on the output 123 of the converters 121 is equal to half a VR ramp step and is implemented in one period of the clk signal; - the initialization phase of each analog-digital conversion has a duration of X periods of the clk signal; - switching the IT switch ([Fig.l]) to the off state following switching of the cmp_out signal takes one period of the clk signal; and - the assembly of the MSB_nb high-order bits with the LSB_nb low-order bits takes one period of the clk signal. In such an example, an analog-to-digital conversion of the sigi signal into the sigi_num signal takes at most X (initialization) + 2AMSB_nb (duration of a VR ramp) + 1 (switching of the IT switch) + 1 (shifting of the output 123 of the converter 121) + LSB_nb (maximum duration of successive approximations) + 1 (assembly of the bits) periods of the clk signal, for example 76+X periods of the clk signal in an example where MSB_nb equals 6 and LSB_nb equals 9.

[0190] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, although the circuit 153 of [Fig. 4] has been described as part of a device 1, this circuit 153 can be used as a sampling circuit of other analog conversion devices, for example of an analog-to-digital conversion device comprising an analog-to-digital converter having an input configured to receive a signal sigi to be converted and connected to the output 157 of the circuit 153.For example, the circuit 153 can be configured to provide the signal Vi to the input 6 of the comparator 5 of the circuit CLi of the document WO 2013 / 127751 A1, the other input 13 of the comparator 5 being coupled to an input of the circuit CLi configured to receive voltage ramps provided by a generator 3 and to an output of a digital-analog converter 12 of the circuit CLi.

[0191] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Device (1) comprising: an analog-to-digital converter (100) having a first input (101) configured to receive an analog signal (sigi) to be converted; and a generator (103) configured to provide ramps (VR) to a second input (105) of the analog-to-digital converter, the analog-to-digital converter (100) comprising: - a comparator (113) having a first input (115) connected to the first input (101) of the analog-to-digital converter, - a capacitive digital-to-analog converter (121) having an output (123) connected to a second input (117) of the comparator (113), and - a switch (IT) connected between the second input (117) of the comparator and the second input (105) of the analog-to-digital converter.

2. Device according to claim 1, wherein: each of said ramps (VR) has a succession of predetermined values ​​in a staircase, each associated with a corresponding combination of states of a set of most significant bits; and the digital-analog converter (121) comprises capacitive elements (C0, CLSB_nb-l) each having a first electrode (200) selectively coupled to a first reference voltage (VPD) or to a second voltage (VND) and a second electrode (202) coupled to the output (123) of the digital-analog converter (121), each of said capacitive elements corresponding to a bit of a set of least significant bits.

3. Device according to claim 2, wherein the digital-analog converter (121) comprises an additional capacitive element (Cesg) connected between a first node (302) of the digital-analog converter (121) and the output (123) of the digital-analog converter (121), each of said capacitive elements (C0, CLSB_nb-l) having its second electrode (202) connected to said first node (302) or to said output (123), preferably to said first node.

4. A device according to claim 2 or 3, wherein: the analog-to-digital converter (100) comprises a first circuit (133) coupled to the output (119, cmp-out) of the comparator (113); the first circuit (133) is configured, during a first phase of analog-digital conversion where one of said ramps (VR) is received by the second input (105) of the analog-digital converter (100), for: - detect a switching of the output of the comparator (113), - maintaining said switch (IT) in the on state until said detection, and switching said switch (IT) to the off state following said detection, - coupling the first electrode (200) of that of said capacitive elements which corresponds to the highest of the least significant bits to the second voltage (VND), the first electrode, the first electrode (200) of at least one other of said capacitive elements (C0, CLSB_nb-l) to the second voltage (VDN) and the first electrodes (200) of all the others of said capacitive elements (C0, CLSB_nb-l) to the first reference voltage (VPD), at least until switching to the blocked state of said switch (IT), and - memorize the most significant bits corresponding to the predetermined value of the ramp (VR) having caused said switching of the output of the comparator (113); and the first circuit is configured, after switching to the off state of said switch (IT), to: - coupling the first electrode (200) of said at least one other of said capacitive elements (C0, CLSB_nb-l) to the first reference voltage (VPD) so as to cause an offset on the output (123) of said digital-to-analog converter (121), then - during a second phase of analog-to-digital conversion, controlling the digital-to-analog converter (121) to determine by successive approximations said low-weight bits, and - storing the low-weight bits determined by successive approximations.

5. Device according to claim 4, in which the first circuit (133) is configured, after said second conversion phase, to provide a digital signal (sigi_num) output from the analog-to-digital converter (100) by assembling the stored high-weight bits with the stored low-weight bits and taking into account said offset.

6. The device of claim 5, wherein said offset determines a redundancy between the stored high-order bits and the stored low-order bits, and the first circuit (133) is configured, during said assembly, to concatenate the stored high-order bits and the stored low-order bits and taking into account said redundancy.

7. Device according to any one of claims 2 to 6, in which a conversion dynamic of the analog-digital converter (100) extends from a low voltage VNR to a high voltage VPR, each two successive predetermined values ​​being separated by a step equal to (VPR-VNR) / (2AMSB_nb), with MSB_nb a total number of bits of the set of most significant bits.

8. Device according to claim 7, wherein the first reference voltage (VPD) is greater than the second voltage (VND), the second voltage is equal to the low voltage VNR and an output dynamic of the digital to analog converter (121) is greater than or equal to the ramp step.

9. A device according to any one of claims 1 to 8, wherein: the device (1) further comprises a sampling circuit (153);and the sampling circuit (153) comprises: - a first capacitive element (Csample) having a first electrode (400) connected to the first input (101) of the analog-to-digital converter (100), - a first switch (IT1) having a first conduction terminal configured to receive an input voltage (Vi) and a second conduction terminal connected to a second electrode (402) of the first capacitive element (Csample), - a second switch (IT2) having a first conduction terminal configured to receive a DC voltage (Vcm) and a second conduction terminal connected to the second electrode (402) of the first capacitive element (Csample), and - a third switch (IT3) having a first conduction terminal configured to receive said DC voltage (Vcm) and a second conduction terminal connected to the first input (101) of the analog-to-digital converter (100).;

10. Device according to claim 9, in which the device (1) comprises a circuit for controlling the switches of the sampling circuit (153) configured, during a sampling phase of the input voltage (Vi), to successively: - put the third switch (IT3) in the on state, the first switch (IT1) in the on state and the second switch (IT2) in the off state, - putting the third switch (IT3) in the off state while the first switch (IT1) is in the on state and the second switch (IT2) is in the off state, and - putting the first switch (IT1) in the off state and the second switch (IT2) in the on state while the third switch (IT3) is in the off state.

11. Device according to claim 9 or 10 taken in its dependence on claim 7 or 8, in which the direct voltage (Vcm) has a value equal to (VNR+VPR) / 2.

12. Device according to any one of claims 9 to 11, wherein the sampling circuit (153) further comprises: a fourth switch (IT4) having a first conduction terminal configured to receive said ramps (VR) and a second conduction terminal connected to the second electrode (402) of the first capacitive element (Csample); and a fifth switch (IT5) having a first conduction terminal configured to receive a calibration voltage (Vcal) and a second conduction terminal connected to the first electrode (400) of said first capacitive element (Csample).

13. Device according to claim 12 taken in its dependence on claim 10, in which the control circuit of the switches of the sampling circuit (153) is configured, during a calibration phase, to: keep the first, second and third switches (IT1, IT2, IT3) blocked during the entire calibration phase; switch the fifth switch (IT5) to the blocked state while a first of said ramps (VR) has a given value among said predetermined values ​​and the fourth switch (IT4) is conducting, then switch the fourth switch (IT4) to the blocked state while the first ramp has a value equal to that of said predetermined values ​​which immediately follows said given value;and keeping the fourth and fifth switches (IT4, IT5) blocked until the end of the first ramp (VR) and during a following analog-digital conversion implemented by the analog-digital converter (100).;

14. System for converting analog signals (sigO, sig9; V0, V9), present respectively on a plurality of channels (channelO, channel9), into digital signals (sigO-num, sig9-num), the system (6) comprising, for each channel: a device (1) according to any one of claims 1 to 8 having the first input (101) of its analog-to-digital converter (100) configured to receive the analog signal (sigO, sig9) of said channel, the ramp generator (103) of each device being implemented by a single ramp generator shared by all the devices; or a device according to any one of claims 9 to 13 having the first conduction terminal (155) of the first switch (IT1) of its sampling circuit (153) configured to receive the analog signal (V0, V9) of said channel, the ramp generator (103) of each device being implemented by a single ramp generator shared by all the devices.

Images