METHOD FOR PREPARING AN ANTI-FERROELECTRIC MULTILAYER DEVICE

Abstract

The present invention relates to a method for preparing an anti-ferroelectric multilayer device, in particular an ultra-thin one, comprising an alternation of at least one layer of a first type and at least one layer of a second type. (no figure)

Description

Title of the invention: METHOD FOR PREPARING AN ANTI-FERROELECTRIC MULTILAYER DEVICE

[0001] The present invention relates to a method for preparing an anti-ferroelectric multi-layer device, in particular an ultra-thin one, comprising an alternation of at least one layer of a first type and at least one layer of a second type.

[0002] The advent of microelectronic, nanoelectronic and optronic applications involving the Internet of Things has created a frantic race for the manufacture of increasingly complex integrated circuits.

[0003] The basic criteria of these new devices are their very high integrability, compatibility with complementary metal-oxide-semiconductor (CMOS) technology combined with very low energy consumption.

[0004] To meet these requirements, the use of advanced materials that are scalable in terms of thickness and performance in the construction and manufacturing of these devices has become essential. Among the materials that can be used in this type of microelectronic devices, there is the family of so-called antiferroelectric (AF) materials. AF antiferroelectric materials and layers are pyroelectric materials with a non-centrosymmetric crystallographic class. From a macroscopic point of view, AF materials form a subset of antipolar crystals unlike ferroelectric materials which form a single subset of polar crystals. The experimental expression of antiferroelectric behavior is a double hysteresis cycle of the polarization as a function of the electric field.From a structural point of view, the elementary mesh of AF materials is generally characterized by the dominance of a tetragonal crystallographic phase.

[0005] From an application point of view and unlike ferroelectric materials where the enthusiasm has increased significantly since the discovery of ferroelectricity in ultrathin hafnium oxide HfO2 layers in 2011, the use of anti-ferroelectric materials in thin layers (clOOnm) remains limited. In practice, it is possible to use MIM (Metal-Insulator-Metal) stacks integrating an anti-ferroelectric layer acting as a high permittivity insulating dielectric as an energy storage device. This case corresponds to "MAFM" type structures for Metal-Anti Ferroelectric-Metal. In certain configurations, it is possible to use AF anti-ferroelectric layers for the manufacture of very high density capacitances in coupling with transistors for embedded memory applications such as DRAM (for Dynamic Random Access Memory).

[0006] In recent years, several developments have introduced layers anti-ferroelectric AF layers in the production of a number of these devices. However, the proposed devices employ AF layers with thicknesses generally greater than critical values ​​(8 to 10 nm) at the risk of degrading the anti-ferroelectric properties. This limitation in thickness reduces the scope of application of anti-ferroelectric layers in devices such as gates for advanced node transistors or the fabrication of very high density energy storage capacitances in substrates with very high topography.

[0007] However, in the case of a dielectric layer whose physicochemical and structural composition is uniform and homogeneous, the reduction in the thickness of said layer intended for anti-ferroelectric purposes is accompanied by an increase in the overall thermal budget beyond 500°C in order to guarantee the formation of the crystallographic phase necessary to attribute the anti-ferroelectric properties to the manufactured capacitance. And this increase in the overall thermal budget beyond 500°C is not compatible with the thermal budget requirement for BEOL (for Back End Of Line) processes whose maximum permitted temperatures are less than 450°C.

[0008] The aim of the invention is to enable the implementation of a method for preparing an anti-ferroelectric device which avoids the aforementioned drawbacks.

[0009] Thus, one aim of the invention is to provide a method for preparing an anti-ferroelectric device, in particular an ultra-thin one, while allowing the preservation of a thermal budget compatible with BEOL technology.

[0010] A more particular aim of the invention is to provide a method for preparing an anti-ferroelectric device allowing a reduction in the thickness of the anti-ferroelectric “AF” layers in a “MAFM” type capacitance stack, while allowing the preservation of a thermal budget compatible with BEOL technology.

[0011] Thus, according to a first aspect, the invention relates to a method for preparing an anti-ferroelectric multilayer device M with n layers, n being greater than or equal to 2, consisting of or comprising an alternation of at least one layer A and at least one layer B,

[0012] said at least one layer A being, independently, made of or comprising a compound chosen from zirconium oxides (ZrO2), hafnium and zirconium oxides (HZO) enriched in zirconium and perovskites,

[0013] said at least one layer B being, independently, made of or comprising a compound chosen from hafnium oxides (HfO2), hafnium-enriched hafnium and zirconium oxides (HZO), aluminum-doped hafnium and zirconium oxides (HZO), lanthanum-doped hafnium and zirconium oxides (HZO), gadolinium-doped hafnium and zirconium oxides (HZO), yttrium-doped hafnium and zirconium oxides (HZO), silicon-doped zirconium (HZO), and silicon-doped hafnium oxides (HSO),

[0014] said method comprising the following steps: i. a step of preparing on a substrate or a lower metal electrode a multilayer device M' with n' layers, n' being greater than or equal to 3, comprising an alternation of said layers A and B, the first of the n' layers, in contact with the lower metal electrode, being a layer A, ii. a step of depositing on said multilayer device M' obtained at the end of step (i), opposite said lower metal electrode, an upper metal electrode, iii. a step of annealing the device obtained at the end of step (ii), iv. a step of removing the upper metal electrode from the device obtained at the outcome of step (iii), v. selective etching of the n' - n upper layers, opposite the lower metal electrode, in particular the total one, to obtain on said lower metal electrode the multilayer device M, vi. optionally, a step of depositing on said multilayer device M' obtained at the end of step (v), opposite said lower metal electrode, an upper metal electrode.

[0015] According to another aspect, the invention relates to a method for preparing an anti-ferroelectric multilayer device M with n layers, n being from 2 to 100, preferably from 2 to 25, consisting of or comprising an alternation of at least one layer A and at least one layer B,

[0016] said at least one layer A being, independently, made of or comprising a compound chosen from zirconium oxides (ZrO2), hafnium and zirconium oxides (HZO) enriched in zirconium and perovskites,

[0017] said at least one layer B being, independently, made of or comprising a compound chosen from hafnium oxides (HfO2), hafnium-enriched hafnium and zirconium oxides (HZO), aluminum-doped hafnium and zirconium oxides (HZO), lanthanum-doped hafnium and zirconium oxides (HZO), gadolinium-doped hafnium and zirconium oxides (HZO), yttrium-doped hafnium and zirconium oxides (HZO), silicon-doped hafnium and zirconium oxides (HZO), and silicon-doped hafnium oxides (HSO),

[0018] said method comprising the following steps: i. a preparation step on a substrate or a lower metal electrode of a multilayer device M' with n' layers, n' being from 3 to 101, with n' > n, preferably between 3 and 26, comprising an alternation of said layers A and B, the first of the n' layers, in contact with the lower metal electrode, being a layer A, ii. a step of depositing on said multilayer device M' obtained at the end of step (i), opposite said lower metal electrode, an upper metal electrode, iii. a step of annealing the device obtained at the end of step (ii), iv. a step of removing the upper metal electrode from the device obtained at the outcome of step (iii), v. selective etching of the n' - n upper layers, opposite the lower metal electrode, in particular the total one, to obtain on said lower metal electrode the multilayer device M, vi. optionally, a step of depositing on said multilayer device M' obtained at the end of step (v), opposite said lower metal electrode, an upper metal electrode.

[0019] According to a particular embodiment, said method comprises the following steps: i. a preparation step on a substrate or a lower metal electrode of a multilayer device M' with n' layers, n' being from 3 to 101, with n' > n, preferably between 3 and 26, comprising an alternation of said layers A and B, the first of the n' layers, in contact with the lower metal electrode, being a layer A, ii. a step of depositing on said multilayer device M' obtained at the end of step (i), opposite said lower metal electrode, an upper metal electrode, iii. a step of annealing the device obtained at the end of step (ii), iv. a step of removing the upper metal electrode from the device obtained at the outcome of step (iii), v. selective etching of the n' - n upper layers, opposite the lower metal electrode, in particular the total one, to obtain on said lower metal electrode the multilayer device M, vi. a step of depositing on said multilayer device M' obtained at the end of step (v), opposite said lower metal electrode, an upper metal electrode.

[0020] By "zirconium-enriched hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising more than 50% at (atomic concentration) of ZrO2.

[0021] Among the perovskites, we can for example cite lead zirconate (PbZrO3), and lead hafniate (PbHfO3).

[0022] Among the perovskites, we can for example cite lead zirconate (PbZrO3), lead hafniate (PbHfO3), PZT / PZO type perovskites for Pb(Zr, Ti)O3, barium strontium titanates (BST), and lead-free perovskites (e.g. LNO for LiNbO3, BFO for BiFeO3, NBT for Na0.5Bio.5Ti03)

[0023] By "hafnium-enriched hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising more than 50% at HfO2.

[0024] By "aluminum-doped hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising from 0.1 to 10% at, preferably approximately 1% at, of Al2O3.

[0025] By "lanthanum-doped hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising from 0.1 to 10% at, preferably approximately 1% at, of lanthanum.

[0026] By "gadolinium-doped hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising from 0.1 to 10 at%, preferably approximately 1 at%, of gadolinium.

[0027] By "yttrium-doped hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising from 0.1 to 10 at%, preferably approximately 1 at%, of yttrium.

[0028] By "silicon-doped hafnium and zirconium oxides (HZO)" is meant in particular hafnium and zirconium oxides comprising from 0.1 to 10% at, preferably approximately 1% at, of SiO2.

[0029] By "silicon-doped hafnium oxides (HSO)" is meant in particular hafnium oxides comprising from 0.1 to 10% at, preferably approximately 1% at, of SiO2.

[0030] By "anti-ferroelectric multilayer device M" is meant in particular that the multilayer device is, when considered as a whole, anti-ferroelectric. The device is thus globally anti-ferroelectric, even if this is not necessarily the case for all the layers of said device.

[0031] Surprisingly, it has also been highlighted that the multilayer device M is anti-ferroelectric, despite the presence of layers which may not be anti-ferroelectric, or even be ferroelectric.

[0032] Without wishing to be restricted to any theory, annealing makes it possible to promote the formation of a crystallographic phase with tetragonal dominance for the unit layer A and monoclinic dominance for the unit layer B.

[0033] By "anti-ferroelectric" is meant in particular a device which has antiparallel dipole moments. The hysteresis loop is for this type of material typically, and by definition, extremely narrow.

[0034] Direct measurement of the anti-ferroelectricity of a material generally consists of electrically exciting the material to be characterized nested between two electrodes to highlight the presence and characteristics of a hysteresis cycle.

[0035] By “a layer A (or B) being, independently, made up of or comprising...”, it is understood in particular that the layers A may be different from each other, while always being made up of or comprising a compound chosen from the group defined above.

[0036] According to a particular embodiment, layers A (when there is more than one) and / or layers B (when there is more than one) are made up of or comprise the same compound as defined previously.

[0037] Thus, the device M, after step (iii) and after step (vi), when step (vi) is carried out, corresponds to a MAFM device (for “Metal Anti-Ferroelectric Metal”), the preparation of which consists of depositing an anti-ferroelectric multilayer material, in particular by ALD, between two metal electrodes.

[0038] According to a particular embodiment, n is from 2 to 25, in particular from 2 to 20, n being for example 3.

[0039] According to a particular embodiment, n' is from 3 to 26, in particular from 3 to 21, n' being for example 5.

[0040] According to a particular embodiment, the last layer of the multi-layer device M is a layer A.

[0041] By "last layer of the multilayer device M" is meant in particular the layer furthest from the substrate or from the lower metal electrode.

[0042] According to a particular embodiment, the substrate is a substrate made of or comprising silicon.

[0043] According to a particular embodiment, the multilayer device M' is prepared by successive deposition of layers A and B, in particular by an atomic layer deposition (ALD) technique.

[0044] The atomic layer deposition technique is capable of developing conformal, homogeneous thin layers while controlling their thickness with a precision of less than a nanometer.

[0045] Typically, the ALD process begins by flooding the reaction chamber with a precursor that covers (or “adsorbs”) the exposed surface of the substrate. This process is called self-limiting because the precursor can only adsorb to the exposed areas; once all of these are covered, adsorption stops. A second gas is then introduced and reacts with the precursor to form the desired material. This second step is also self-limiting: once the available precursor sites are exhausted, the reaction stops. Both steps are repeated until the desired film thickness is achieved. The growth rate is usually quantified by growth per cycle (GPC). The typical ALD cycle consists of two half-cycles, of sequential doses of precursor and co-reactant, which are separated by purge and pump steps, leading to self-limiting layer growth.Co-reactants and oxidants are generally sources. oxygen (H2O or oxygen plasma). To obtain the multilayer material, different ALD monolayers are manufactured, alternating the precursor pulses.

[0046] According to a particular embodiment, the precursors of hafnium and zirconium oxides, during deposition by an atomic layer deposition technique, are halogenated precursors, in particular HfCl4 and ZrCl4rcspccti veinent.

[0047] According to another particular embodiment, organometallic precursors, such as TDMAZ (for Tetrakis-dimethylamino-zirconium-IV) can be used.

[0048] According to another embodiment, the multilayer device M' is prepared by successive deposition of layers A and B, in particular by a PVD (Physical Vapor Deposition) or PLD (Pulsed Laser Deposition) deposition technique.

[0049] According to a particular embodiment, the layers A and / or B of the multilayer device M and / or of the multilayer device M' have a thickness of from 0.5 to 5 nm, in particular approximately 2 nm.

[0050] According to a particular embodiment, the layers A have a thickness of from 0.5 to 5 nm, preferably approximately 2 nm, and the layers B have a thickness of from 0.5 to 5 nm, preferably approximately 2 nm.

[0051] According to a particular embodiment, the multilayer device M and / or the multilayer device M' have a thickness less than 50 nm, in particular less than or equal to 15 nm, in particular less than or equal to 10 or 6 nm.

[0052] The removal of step (iv) can be carried out using state-of-the-art techniques such as inductively coupled plasma reactive ion etching (ICP-RIE), for example using halogenated gas (Cl2, BC13, CHF3) chemistry in association with other gases (Ar, N2, O2, He).

[0053] Other chemical removal techniques may be employed, for example to remove the titanium nitride layer, such as the mixture formed by the chemical elements of ammonia hydroxide (NH4OH), hydrogen peroxide H2O2 and deionized water H2O heated to 60°C.

[0054] The etching of step (v) makes it possible to reduce the thickness of the total stack.

[0055] Without wishing to be restricted to any theory, the etching of layers A and B during step (v) is selective because it exploits the difference in orientation / structure of said layers A and B. This selectivity is on the contrary not obtained for a standard, uniform and homogeneous ferroelectric material, for which the components of layers A and B would be mixed.

[0056] Experimentally, and as well known to those skilled in the art, the thicknesses of the structures can be controlled as a function of the immersion or etching time and the chemical composition of the liquids used.

[0057] According to a particular embodiment, the selective etching of step (v) is a total etching of the n' - n upper layers, opposite the lower metal electrode (200).

[0058] According to another particular embodiment, the selective etching of step (v) is partial (it is therefore not total). In this case, part or all of the n' - n upper layers is only partially etched and remains present on the device M.

[0059] According to a particular embodiment, the selective etching of step (v) is a wet or dry etching, in particular an etching (ALE), for example by plasma (anisotropic), or thermal (isotropic).

[0060] In general, and as well known to those skilled in the art, there are mainly two classes of etching processes: wet etching where the material is dissolved when immersed in a chemical solution. And dry etching where the material is sprayed or dissolved using reactive ions or a vapor phase etchant. When said material is dissolved, and without wishing to be restricted to any theory, it is typically the reaction of the material with ions or the like that creates volatile species.

[0061] The speed at which the etching process occurs is called the etch rate. The etching process is said to be isotropic if it proceeds in all directions at the same rate. If it proceeds in only one direction and depends strongly on the crystal structure of the material, then it is anisotropic. An important consideration in any etching process is the "selectivity" of the etchant. Selectivity is achieved when two different materials have different etch rates under the same conditions or when one material etches while the other does not. Selectivity is measured as the ratio between the different etch rates of the etchant for different materials. Anisotropic etching is possible because of the distinct crystal structures and orientations of the different materials that make up the multilayer structure.Exposure to different etching rates or chemical compositions is carried out depending on the crystallinity of the material.

[0062] For example, in the case of a multilayer structure of HfO2 and ZrO2, a thermal atomic layer etching (ALE) type etching can in particular be carried out using fluorination and ligand exchange reactions. HF can for example be used for fluorination and Sn(acac)2, A1C1(CH3)2 [dimethylaluminum chloride (DMAC)] or TiCl4 used as metal precursors for ligand exchange. The so-called "Atomic layer etching" (ALE) method is a method used to remove thin films with Angstrom-level precision using sequential and self-limiting surface reactions.

[0063] According to a particular embodiment, the invention relates to a method as described previously, in which: - Layer A of the M' device is predominantly tetragonal; - Layer A of device M is predominantly tetragonal. - Layer B of the device M' is predominantly amorphous; - Layer B of device M is predominantly orthorhombic and / or mono clinical.

[0064] By "dominantly amorphous, orthorhombic or tetragonal" is meant in particular that the layer is more than 50% amorphous, orthorhombic or tetragonal, respectively.

[0065] According to a particular embodiment, part of the annealing step (iii) can be combined with step (ii). Indeed, and by way of example, the thermal budget of the ALD process (400°C for 15 min) typically necessary for the deposition of a 10 nm TiN upper electrode layer can be sufficient for the crystallization of the last layer A or B, in particular A.

[0066] Annealing may be carried out by any technique well known to those skilled in the art, for example rapid thermal annealing (RTA), or annealing using a furnace, a hot plate, assisted by radiation, or using a laser.

[0067] According to a particular embodiment, the annealing of step (iii) is carried out at a temperature of 300 to 600°C, in particular of 300 to 500°C, in particular at approximately 400°C.

[0068] According to a particular embodiment, step (vi) is carried out.

[0069] According to a particular embodiment, step (vi) is not followed by a step of annealed.

[0070] According to a particular embodiment, the metal electrode mentioned in relation to step (ii) and / or the metal electrode mentioned in relation to step (vi) are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0071] According to a particular embodiment, the lower metal electrode mentioned in relation to step (i) is in contact, opposite layer A, with a substrate.

[0072] According to a particular embodiment, the substrate is a substrate made of or comprising silicon.

[0073] According to a particular embodiment, the metal electrode mentioned in relation to step (i) is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

[0074] According to a particular embodiment, the metal electrode mentioned in relation to step (i), the metal electrode mentioned in relation to step (ii) and / or the metal electrode mentioned in relation to step (vi) are made of or comprise a metal notably chosen from titanium, gold, aluminum, platinum, ruthenium, molybdenum, copper, and tungsten, a material comprising said metal, in particular a metal nitride, for example TiN, WN, TaN, or MoN, or mixtures thereof.

[0075] According to a particular embodiment, the metal electrode mentioned in relation to step (i), the metal electrode mentioned in relation to step (ii) and / or the metal electrode mentioned in relation to step (vi) have a thickness of from 2 to 500 nm, in particular from 2, 5 or 10 to 100 nm, in particular from 2 or 5 to 20 nm.

[0076] The substrate, or when it is absent, the lower metal electrode, may be planar or non-planar. Since the set of layers described above (the at least one layer A, the at least one layer B, and when they are present, the lower metal electrode and / or the upper metal electrode) generally has a constant thickness (typically a thickness being ±10%, in particular ±1%, of its average value), the set of layers described above has the same structural geometry as the substrate on which this set rests, or when it is absent, as the lower metal electrode on which it rests.

[0077] According to another aspect, the present invention also relates to a method for preparing three-dimensional structures comprising at least one device M as described previously, in particular a plurality of devices M, which is prepared according to the steps as described previously.

[0078] The device M according to the invention can be used in the preparation of anti-ferroelectric capacitances, in particular in a microelectronic or nanoelectronic device, for example in the field of energy storage, memories, transistors. Definitions

[0079] As used herein, the value ranges in the form of "xy" or "from x to y" or "between x and y" include the bounds x and y, the integers between these bounds, as well as all other real numbers between these bounds. For example, "1-5", or "from 1 to 5" or "between 1 and 5" designates the integers 1, 2, 3, 4 and 5, as well as all other real numbers between 1 and 5. Preferred embodiments include each individual integer in the value range, as well as any subcombination of these integers and any set of real numbers between these integers. For example, preferred values ​​for "1-5" might include the integers 1, 2, 3, 4, 5, 1-2, 1-3, 1-4, 1-5, 2-3, 2-4, 2-5, etc.

[0080] As used herein, the term "about" refers to a range of values ​​within ± 10% of a specific value. For example, the term "about 20" includes values ​​of 20 ± 10%, or values ​​from 18 to 22.

[0081] By layer is meant in particular a stratum of superimposed elements. This stratum generally refers to a layer whose physicochemical properties and structural are uniform and homogeneous, on the plane and on its depth.

[0082] By first layer, we mean in particular a layer in contact with a second layer and, optionally, with a substrate.

[0083] By second layer, we mean in particular a layer in contact with the first layer and with, when it exists, the third layer.

[0084] By third layer, we mean in particular a layer in contact with the second layer and with, when it exists, the fourth layer, and so on. FIGURES

[0085] [Fig.l] illustrates a device obtained according to a method according to the invention as described in example 1, step 1.

[0086] [Fig.2], 4 and 5 illustrate a device obtained according to a method according to the invention as described in example 1, step 2.

[0087] [Fig.3] illustrates the Grazing Incident X-ray Diffraction (GIXRD) spectrum of a device as described in Example 1, Step 2.

[0088] [Fig.6] and 7 illustrate a device obtained according to a method according to the invention as described in example 1, step 3.

[0089] [Fig.8] and 9 illustrate a device obtained according to a method according to the invention as described in example 1, step 4. EXAMPLES

[0090] Example 1: Preparation of a device according to a method of the invention

[0091] Step 1: Production of the lower electrode layer

[0092] This step shown diagrammatically in [Fig.l] relates to the production of a conductive layer (200) acting as a lower electrode on a standard substrate generally made of silicon (100). The layer (200) is chosen for its electrical conduction properties in the family of metals (Titanium, Gold, Platinum, Aluminum, Tungsten, Ruthenium, Molybdenum, Copper, etc.) or metal nitrides (TiN, WN, TaN, MoN, etc.) or a mixture of several elements. In the example of [Fig.l], the layer (200) made of titanium nitride TiN with a thickness of 2 to 20nm, in particular 100nm, is manufactured using state-of-the-art techniques. In particular, it is manufactured using the thermal ALD (Atomic Layer Deposition) process at 400°C by sequentially injecting / purging the chemical precursors TiCl4 and NH3.Optionally, it is possible to fabricate the 10nm TiN layer at a temperature of 200°C using the plasma-assisted ALD mode and the precursors TDMAT (for tetrakis-dimethylamino-titanium) and NH3. Other thin-film deposition techniques (CVD for Chemical Vapor Deposition, PVD for Physical Vapor Deposition) known by the state of the art can be used for the fabrication of the . lower electrode layer.

[0093] Step 2: Production of the anti-ferroelectric layer

[0094] First, step 2 shown schematically in [Fig.2] consists of depositing over the lower electrode layer (200) a unit layer (310) with a thickness of between 0.5 nm and 10 nm. In this embodiment, the thickness of the layer (310) is set at 2 nm. Said layer is generally characterized by a crystalline structure. It is formed from a metal oxide or the combination of several metal oxides. Preferably, it is a layer of zirconium oxide ZrO2 deposited by thermal ALD at 300°C using the precursor ZrCl4, used as a metal reactant, and water H2O used as an oxidant.Optionally, organometallic precursors (such as TDMAZ for Tetrakis-dimethylamino-zirconium-IV) or alternative techniques to ALD such as PVD (for Physical Vapor Deposition) or PLD (Pulsed Laser Deposition) can be used for the deposition of the ZrO2 layer allowing to have a dominant crystalline phase after the deposition step. A tetragonal crystalline structure of the ZrO2 unit layer (310) can be defined by the presence of the characteristic peaks according to the GIXRD graphical representation of [Fig.3] (the Grazing Incident X-ray Diffraction technique, GIXRD for Grazing Incident X-ray Diffraction: it is often used to characterize the crystalline structure of thin and ultra-thin layers by measuring the intensity of an X-ray beam with respect to the diffraction angle).

[0095] Second, the construction of the anti-ferroelectric layer requires the deposition of a second unit layer (320) in direct contact with the unit layer (310) according to the diagram of [Fig.4]. With a thickness of between 0.5 nm and 10 nm (and preferably 2 nm), this second layer (320) has an amorphous or predominantly amorphous mesh structure after the deposition step. It is formed from a metal oxide or the combination of several metal oxides. In the preferred embodiment, it is a layer of hafnium oxide HfO2 deposited by thermal ALD at 300°C using the precursor HfCl4, used as a metal reactant, and water H2O used as an oxidant.Optionally, organometallic precursors (such as TDMAH for Tetrakis-dimethylamino-hafnium-IV) or alternative techniques to ALD such as PVD (for Physical Vapor Deposition) or PLD (Pulsed Laser Deposition) can be used for the deposition of the HfO2 layer allowing to have a dominant amorphous phase after the deposition step. Experimentally, a unit layer is said to be amorphous in the case of total absence or minimal presence of crystallization peaks of the elementary mesh structure. This is particularly the case for the HfO2 layer whose characteristic peaks after the deposition step are represented by the spectrum in [Fig.3].

[0096] Step 2 of this embodiment aims to construct a multilayer structure (300) using an elementary brick of two different materials denoted “A” and “B” in this document and corresponding, respectively, to the unit layers (310) and (320). According to the preferred embodiment, the unit layers (310) and (320) are alternated and iterated (3 times for layer 310 and 2 times for layer 320) while respecting the order of the diagram in [Fig. 5] to have a pentalayer system (300). Thus, in our example the unit layers (310), (330) and (350) are identical from the point of view of technological embodiment and intrinsic properties. It is the same for the unit layers (320) and (340).

[0097] Step 3: Formation and removal of the first upper electrode layer

[0098] This step can be subdivided into 2 or 3 sub-steps: deposition, possibly annealing and removal. The first makes it possible to have a conductive layer which can be identical or different to the lower electrode layer. In this example, the choice is made on a conductive layer (400) of titanium nitride TiN with a thickness of 2 to 20 nm, in particular 10 nm, whose intrinsic properties and embodiments are identical to the lower electrode described in step 1. The layer (400) is arranged on the pentalayer system (300) according to the diagram in [Fig.6].

[0099] The deposition of the upper electrode (400) is followed by a thermal annealing step at 400°C for 1 h under a nitrogen atmosphere. Other annealing conditions and modes compatible with BEOL technology can be envisaged, such as rapid annealing or laser annealing. The objective of the annealing step is to confer a crystalline structure to the pentalayer system (300) under the combined effect of the thermal budget and the mechanical stress induced by the presence of the upper electrode layer (400). The preliminary phase of the predominantly amorphous HfO2 unit layer is such as to promote a transformation towards a predominantly monoclinic phase after the thermal annealing step. One of the particularities of the present invention is to be able to associate each unit layer (310, 330, 350) and (320, 340) composing the multilayer structure (300) with a particular crystalline orientation.Thus after the annealing step, the majority phases observed are orthogonal and monoclinic, respectively, for the unit layer (3100, 3300, 3500) in ZrO2 and the unit layer (3200, 3400) in HfO2.

[0100] Removal of the unit layer (400) is achievable using state-of-the-art techniques such as inductively coupled plasma reactive ion etching (ICP-RIE) using halogenated gas (Cl2, BC13, CHF3) chemistry in combination with other gases (Ar, N2, O2, He). Other chemical removal techniques may be used to remove the titanium nitride layer such as the mixture formed by the chemical elements of ammonia hydroxide (NH4OH), hydrogen peroxide H2O2 and deionized water H2O heated to 60°C.

[0101] In this embodiment ([Fig.7]), it is possible to etch a layer (400) of TiN selectively, with respect to the unit layer (3500) in particular and to the multilayer system (3000) in general, in a duration of 60s with the ICP-RIE technique using a CHF3 / Ar mixture (30%Ar, a gas flow of 120 sccm) at a temperature of 85°C under a total pressure of 8 mTorr and a plasma power of IkW.

[0102] Step 4: Thinning of the anti-ferroelectric layer

[0103] One of the major advantages of the present invention lies in the use of a multilayer system whose basic unit layers (310, 330 and 350 on one side defining the material "A"; and 320 and 340 on the other side defining the material "B") are characterized by a very different crystalline orientation. Concretely at the end of step 3, the initial unit layers (310, 330, 350) in ZrO2 are crystalline with a predominantly tetragonal phase which remains dominant after the annealing step. On the other hand, the predominantly amorphous HfO2 unit layers (320, 340) have become crystalline with a predominantly monoclinic phase and will be noted. The unit layers obtained after the annealing operation will be noted respectively (3100, 3200, 3300, 3400, 3500) thus forming a multilayer system noted (3000) characterized by a crystalline phase with tetragonal and / or orthorhombic dominance.

[0104] Selective removal of the layer (400) allows direct access to the multilayer system. Thinning the anti-ferroelectric layer is the step for reducing the final thickness of the multilayer system. According to one of the configurations ([Fig.8]), step 4 aims to remove the unit layer (3500) and the unit layer (3400) from the stack forming the initial multilayer system (3000).

[0105] Experimentally, step 4 uses ALE (Atomic Layer Etching) techniques which are very suitable for ultra-thin unit layers. This technique is based on a sequential injection of reactive gases separated by purge times according to a number of cycles established according to the thickness of the unit layer to be removed. According to one of the embodiments, the selective elimination of the ZrO2 and HfO2 unit layers uses SF4 chemistry (fluorination gas modifying the composition of the layer to be removed) and TiCl4 (metal precursor for the exchange of ligands and the removal of the desired layer).For a pressure of 1 Torr under a neutral gas flow (N2 or Ar) and a temperature fixed at 250°C, it is necessary to consider approximately 50 cycles and 300 cycles of SF4 (exposure time 1s and a purge of 30s) and TiCl4 (exposure time 1s and a purge of 30s) to remove respectively and completely the unit layers (350) in ZrO2 and (340) in HfO2 with a thickness of 2 nm each. The experimental conditions of the ALE etching are given as an example and depend mainly on the physicochemical and crystalline nature and the thickness of the layers to be etched and the type of . the ALE equipment used.

[0106] Alternatively, the thinning and removal of the unit layers (3400 and 3500) can be carried out selectively in a suitable liquid solution since the etching rates of the materials forming the two unit layers are significantly different. For example, the unit layer (3500) of ZrO2 with a thickness of 2 nm can be removed after 30 s of exposure to a 2.5% concentrated hydrofluoric acid (HF) solution heated to 80°C. On the other hand, only 5 s of exposure in the same solution is required to remove 2 nm of the unit layer (3400) of HfO2.

[0107] The result of step 4 is a crystalline multilayer (3000) whose intrinsic properties are preserved compared to the layer (300) formed at the end of step 3 (deposition and thermal annealing). The anti-ferroelectric multilayer (3000), itself, with the targeted properties is finally obtained after the steps of thermal annealing, removal of the first upper electrode layer and the thinning step. The MAFM capacitance structure of [Fig.9] is constructed after deposition of a new upper electrode layer (4000) identical to the layer (400) without resorting to a new thermal annealing operation.

Claims

Claims

1. A method for preparing an anti-ferroelectric multilayer device M with n layers, n being from 2 to 100, preferably from 2 to 25, consisting of or comprising an alternation of at least one layer A and at least one layer B, said at least one layer A being, independently, consisting of or comprising a compound chosen from zirconium oxides (ZrO2), hafnium and zirconium oxides (HZO) enriched in zirconium and perovskites, said at least one layer B being, independently, consisting of or comprising a compound chosen from hafnium oxides (HfO2), hafnium and zirconium oxides (HZO) enriched in hafnium, hafnium and zirconium oxides (HZO) doped with aluminum, hafnium and zirconium oxides (HZO) doped with lanthanum, oxides gadolinium-doped hafnium and zirconium oxides (HZO), yttrium-doped hafnium and zirconium oxides (HZO), silicon-doped hafnium and zirconium oxides (HZO),and silicon-doped hafnium oxides (HSO), said method comprising the following steps:, i. a step of preparing on a substrate or a lower metal electrode (200) a multilayer device M' with n' layers, n' being from 3 to 101, with n' > n, preferably between 3 and 26, comprising an alternation of said layers A and B, the first of the n' layers, in contact with the lower metal electrode (200), being a layer A, ii. a step of depositing on said multilayer device M' obtained at the end of step (i), opposite said lower metal electrode, an upper metal electrode, (400) iii. a step of annealing the device obtained at the end of step (ii), iv. a step of removing the upper metal electrode (400) of the device obtained at the end of step (iii), v. selective etching of the n' - n upper layers, opposite the lower metal electrode (200), in particular total, to obtain on said lower metal electrode the multilayer device M, vi. optionally, a step of depositing on said multi-layer device M' obtained at the end of step (v), opposite said lower metal electrode, an upper metal electrode (400).

2. A method according to any preceding claim, wherein the last layer of the multilayer device M is a layer A

3. 2A. Method according to any one of the preceding claims, in which the multilayer device M' is prepared by successive deposition of the layers A and B, in particular by an atomic layer deposition (ALD) technique, in which the precursors of the hafnium and zirconium oxides are in particular halogenated precursors, in particular HfCl4 and ZrCl^ respectively.

4. Method according to any one of the preceding claims, in which the layers A and / or B of the multilayer device M and / or of the multilayer device M' have a thickness of from 0.5 to 5 nm, in particular approximately 2 nm.

5. Method according to any one of the preceding claims, in which the multilayer device M and / or the multilayer device M' have a thickness of less than 50 nm, in particular less than or equal to 15 nm, in particular less than or equal to 10 or 6 nm.

6. Method according to any one of the preceding claims, in which the selective etching of step (v) is a wet or dry etching, in particular an etching (ALE), for example by plasma (anisotropic), or thermal (isotropic).

7. Method according to any one of the preceding claims, wherein: - Layer A of device M' is predominantly tetragonal; - Layer A of device M is predominantly tetragonal. - Layer B of device M' is predominantly amorphous; - Layer B of device M is predominantly orthorhombic and / or monoclinic.

8. A method according to any preceding claim, wherein the annealing of step (iii) is carried out at a temperature of 300 to 600°C, especially from 300 to 500°C, especially around 400°C.

9. A method according to any preceding claim, wherein the metal electrode mentioned in relation to step (ii) and / or the metal electrode mentioned in relation to step (vi) are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

10. Method according to any one of the preceding claims, in which the lower metal electrode (200) mentioned in relation to step (i) is in contact, opposite the layer A, with a substrate, in particular a substrate made of or comprising silicon, said metal electrode being in particular deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

11. A method according to any one of the preceding claims, wherein the metal electrode mentioned in relation to step (i), the metal electrode mentioned in relation to step (ii) and / or the metal electrode mentioned in relation to step (vi) are made of or comprise a metal notably chosen from titanium, gold, aluminum platinum, ruthenium, molybdenum, copper, and tungsten, a material comprising said metal, notably a metal nitride, for example TiN, WN, TaN, or MoN, or mixtures thereof.

12. Method according to any one of the preceding claims, wherein the metal electrode mentioned in relation to step (i), the metal electrode mentioned in relation to step (ii) and / or the metal electrode mentioned in relation to step (vi) have a thickness of from 2 to 500nm, in particular from 2 or 10 to 100nm, in particular from 2 or 5 to 20nm.

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