Fabrication of a donor substrate for the fabrication of a POI structure

Abstract

The present invention relates to a method of manufacturing a donor substrate for manufacturing a piezoelectric-on-insulator, POI, structure, comprising providing a support substrate, forming a block of piezoelectric material on or above the support substrate, wherein the piezoelectric material comprises or consists of one of lithium tantalate and lithium niobate, chemical mechanical polishing, CMP, the block of piezoelectric material to obtain a piezoelectric substrate and implanting a species into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate. The CMP is carried out using a CMP pad comprising a secondary pad having a hardness of more than 45 shore A. Figure for abstract: Fig. 2

Description

Title of the invention: Fabrication of a donor substrate for the fabrication of a POI structure

[0001] The present invention relates to the method of manufacturing donor substrates for manufacturing piezoelectric on insulator, POI, structures, in particular POI structures usable for manufacturing microelectronic, micromechanical and photonic devices. Furthermore, the invention relates to the method of manufacturing POI structures using donor substrates thus manufactured.

[0002] In the field of microelectronics, micromechanics and photonics, POI structures are of increasing importance for example due to superior properties in terms of sensitivity and information propagation. For example, sensors such as surface acoustic wave (SAW) sensors, or bulk acoustic wave (BAW) sensors using the piezoelectric effect to convert an electrical signal into a mechanical / acoustic wave offer particularly advantageous options due to a wide variety of measurable ambient parameters, including for example temperature, pressure, strain and torque.

[0003] A typical POI structure comprises a layer of piezoelectric material, in particular a single-crystal material such as, for example, lithium niobate (LiNbO3) or lithium tantalate (LiTaO3), on a support substrate made of, for example, silicon. Various methods for forming a thin layer of piezoelectric material on the support substrate are known in the art. The application of Smart Cut™ technology has proven particularly advantageous. According to this technology (see, for example, WO 2020 / 200986 A1), light species are implanted into a piezoelectric substrate formed on a support substrate to form a weakened region in the piezoelectric substrate, and then the piezoelectric substrate is bonded to a target substrate. Via fracturing at the weakened region, the thin layer of piezoelectric material can be obtained on the support substrate.The transferred piezoelectric material layer is subjected to an annealing process and subsequently to a polishing process, in particular via chemical mechanical polishing, CMP, with the aim of improving the crystalline quality and achieving the desired thickness uniformity of a monodomain layer of piezoelectric material with substantially all dipole moments aligned parallel to each other in a given direction.

[0004] However, the quality of the piezoelectric layer to be transformed from a donor substrate comprising the piezoelectric substrate to a target substrate is not satisfactory in the art. In order to obtain the piezoelectric substrate, a solid block of a piezoelectric material is formed on the support substrate and ground and / or etched. It has been observed that the upper portion of the obtained piezoelectric substrate, and consequently the piezoelectric layer to be transformed, has some edge curl, which results in a higher level of thickness at the edge of the layer compared to the central region.During bonding and expansion of bonding melt across the bonding interface, gas regions that would normally escape from the bonded structure by being pushed outward during the closure of the bonding interface appear due to edge curl and result in edge bond voids formed in the final POI structure.

[0005] Therefore, an object of the present invention is to provide a technique for manufacturing a donor substrate comprising a piezoelectric layer for manufacturing a POI structure (based on Smart Cut™ technology) with a highly uniform layer of piezoelectric material to be transferred from the donor substrate to a target substrate.

[0006] The present invention achieves this goal by providing a method of manufacturing a donor substrate (pseudo-donor, PSD) for manufacturing a piezoelectric-on-insulator, POI, structure, comprising the steps of providing a support substrate (manipulator); forming a block of piezoelectric material on or above the support substrate, wherein the piezoelectric material comprises or consists of one of lithium tantalate and lithium niobate; performing chemical mechanical polishing, CMP, of the block of piezoelectric material to obtain a piezoelectric substrate; and implanting a species (e.g., hydrogen, optionally supplemented with helium) into the piezoelectric substrate to obtain a weakened layer in the piezoelectric substrate; and wherein the CMP is performed by means of a CMP pad comprising a secondary pad with a hardness greater than 45 shore A.

[0007] The shore A level can be defined / measured according to DIN ISO 48-4:2018.

[0008] Forming the block of piezoelectric material on or above the support substrate may include bonding the block of piezoelectric material to the support substrate using a dielectric bonding layer, e.g., a photo(UV) polymer layer or a layer made of or comprising silicon oxide. and / or silicon nitride. Grinding of the piezoelectric material block can be performed before CMP.

[0009] Unlike the prior art, the CMP of the piezoelectric and, consequently, of the upper piezoelectric layer thereof to be transferred to a target substrate in the method of manufacturing a POI structure is carried out by a fully hard CMP pad comprising a secondary pad with a hardness greater than 45 shore A, while an upper pad (for contacting the piezoelectric layer) of the CMP pad is used in a conventional manner (e.g., a rigid upper pad made of polyurethane). In the prior art, secondary pads with a hardness of only about 35 shore A are commonly used.Depending on the actual application, according to one embodiment, a CMP pad comprising a secondary pad with a hardness of more than 45 shore A, in particular more than 50 shore A, or with a hardness in the range of 45 shore A to 55 shore A, in particular in a range of 50 shore A to 55 shore A, can be used. The use of such hard secondary pads is somewhat counterintuitive in view of the risk of generating scratches on the surface of the piezoelectric layer to be transferred. However, it has been found that a uniform thickness of the piezoelectric layer to be transferred by significantly reducing edge wrapping by CMP using fully hard CMP pads can be achieved without causing scratches on the surface of the piezoelectric layer to be transferred. Therefore, more reliable bonding of the transferred piezoelectric layer to the target substrate without bonding voids can be reliably achieved.

[0010] Other parameters of the entire donor substrate manufacturing process may be chosen as is customary and known to those skilled in the art.

[0011] According to one embodiment, the secondary buffer has a density greater than 0.35 g / cm3, in particular greater than 0.4 g / cm3, or in the range of 0.35 g / cm3 to 0.45 g / cm3. These parameter ranges may prove advantageous in terms of thickness uniformity of the resulting polished piezoelectric layer of the donor substrate, in particular in combination with the parameter ranges mentioned above.

[0012] According to another embodiment, the secondary buffer has a compression force deflection in the range of 600 kPa to 670 kPa, in particular about 641,212 kPa. The compression force deflection can be defined / measured according to DIN ISO 48-4:2018. These parameter ranges can prove advantageous in terms of thickness uniformity of the resulting polished piezoelectric layer of the donor substrate, in particular in combination with the parameter ranges mentioned above.

[0013] According to another embodiment, the CMP is carried out by means of a CMP suspension consisting of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon of less than 20, in particular in the range of 10 to 18 or 12.5 to 17.5, in contrast to the parameter range of a conventionally used CMP suspension given by 25 to 35 wt%. The parameter ranges according to the embodiment may prove advantageous in terms of thickness uniformity of the resulting polished piezoelectric layer of the donor substrate, in particular in combination with the parameter ranges mentioned above. The amorphous silicon used for the CMP suspension may comprise or consist of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm.

[0014] Further, a method of manufacturing a piezoelectric-on-insulator, POI, structure is provided, comprising performing the steps of the method of manufacturing a donor substrate according to one of the examples described above and transferring a piezoelectric layer from the piezoelectric substrate to a target substrate, comprising bonding the donor substrate to the target substrate on the side of the piezoelectric substrate and fracturing the piezoelectric substrate at the weakened layer in an annealing process.

[0015] Thus, the piezoelectric layer can be reliably transferred to the target substrate without excessively heavy defects. Additional post-processing (annealing and polishing) may, however, still be necessary to provide a piezoelectric layer suitable for particular applications. It should be noted that naturally occurring silicon oxide may be present between the transferred piezoelectric layer and the target substrate. Furthermore, a dielectric assembly layer may be formed on or above a surface of the target substrate prior to transfer of the piezoelectric layer to that surface. This dielectric assembly layer may be made of or comprise silicon oxide and / or silicon nitride, or a stack of layers composed of these materials.Further, depending on the actual application, a charge trapping layer may be formed on or above a surface of the target substrate prior to transfer of the piezoelectric layer to that surface. The charge trapping layer may be made of or include polycrystalline silicon.

[0016] As mentioned above, post-processing of the transferred piezoelectric layer to the target substrate may be performed. The post-processing may include a thermal annealing step to increase the crystalline quality of the transferred piezoelectric layer and consolidate the bonding of the transferred piezoelectric layer to the target substrate. The post-processing may further include CMP of the transferred piezoelectric layer after the thermal annealing to increase thickness uniformity and surface quality and to eliminate multi-domain regions with different polarities caused by annealing.

[0017] It should be noted that other parameters of the entire POI structure manufacturing process, such as those described above with respect to the donor substrate manufacturing, may be chosen as is done in a customary manner known to those skilled in the art.

[0018] Further, a POI structure is provided, comprising a piezoelectric layer formed on or above a target substrate and obtainable by the method according to a certain of the examples described above, wherein the piezoelectric layer may have a thickness uniformity (thickness range across the diameter of the layer) of less than 50 nm, in particular less than 20 nm. Further, a microelectronic, micromechanical or photonic device is provided, or a microelectromechanical system (MEMS) comprising such a POI structure.

[0019] Additional features and advantages of the present invention will be described with reference to the drawings. In the description, reference is made to the accompanying drawings, which are intended to illustrate preferred embodiments of the invention. It should be understood that such embodiments do not represent the full scope of the invention.

[0020] [Fig.l] illustrates steps of a method of manufacturing a POI structure according to an embodiment of the present invention.

[0021] [Fig.2] illustrates the technical effect of a highly uniform piezoelectric layer to be transferred to a target substrate resulting from a donor structure manufacturing method for manufacturing a POI structure according to an embodiment of the present invention.

[0022] A method of manufacturing a donor substrate is provided herein, comprising a piezoelectric layer for manufacturing a POI structure. The piezoelectric layer to be transformed into a target substrate has high thickness uniformity resulting from polishing with a relatively hard CMP secondary polishing pad. The method may comprise a method of manufacturing a POI structure according to Smart Cut™ technology.

[0023] [Fig.l] illustrates steps of a method of manufacturing a POI structure according to an embodiment of the present invention. The method is similar to a method described in WO 2020 / 200986 A1, but differs therefrom by the inventive method of polishing the piezoelectric layer of the donor substrate to be transferred to a target substrate.

[0024] As shown in step i) of [Fig.l], a donor substrate 1 is provided, which comprises a piezoelectric substrate 1a formed on a support substrate (manipulator) 1b. The piezoelectric substrate 1a is made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). The support substrate 1b may be made of a material (or a plurality of materials) having a coefficient of thermal expansion close to that exhibited by a target substrate 7, i.e. the coefficient of thermal expansion of the support substrate 1b differs from that of the target substrate 7 by less than the difference in the coefficient of thermal expansion of the piezoelectric substrate 1a and that of the target substrate 7. The support substrate 1b and the target substrate 7 may have identical coefficients of thermal expansion and both substrates may, for example, be made of or comprise silicon. In addition, both substrates may have similar thicknesses.

[0025] In order to obtain the donor substrate 1, a solid block of piezoelectric material may be attached to the support substrate 1b, for example, using a molecular adhesion bonding technique. The bonding may be promoted by a dielectric bonding (adhesion) layer (not shown in [Fig.l]), for example, a photo (UV) polymer layer or a layer made of or comprising silicon oxide and / or silicon nitride. The bonding process may comprise the application of a low temperature heat treatment (for example, at a temperature between 50 and 300°C, typically 100°C) to sufficiently enhance the bonding energy to enable the following thinning step.

[0026] Next, the piezoelectric substrate 1a is formed by thinning. The thinning step is carried out such that the piezoelectric substrate 1a has a sufficiently low thickness so that the stresses generated during the heat treatment applied in a subsequent treatment step are reduced. On the other hand, the thickness must be sufficiently high to provide the piezoelectric layer 3 which is to be transferred to the target substrate 7 or to provide a plurality of such layers which are to be transferred one after the other in multiple transfer steps (after respective regeneration of the donor substrate 1) to respective target substrates. The thickness of the piezoelectric substrate 1a may, for example, be between 5 and 400 μm, for example 20 μm, or 100 μm, or 200 μm.

[0027] The thinning comprises chemical mechanical polishing (CMP). According to the invention, the CMP is carried out using a relatively hard secondary polishing pad. A polishing pad comprises a top pad for contacting the surface of the material to be polished and a secondary pad. While the top pad is chosen in a conventional manner (e.g., as a rigid top pad made of polyurethane), according to the invention, the secondary pad of the CMP pad used to polish the top portion of the piezoelectric substrate, and therefore the piezoelectric layer to be transferred to a target substrate in the process of manufacturing a POI structure, has a hardness of more than 45 shore A. Depending on the actual application, a material with a hardness of more of 45 shore A, in particular more than 50 shore A, or a hardness in the range of 45 shore A to 55 shore A, in particular in a range of 50 shore A to 55 shore A, can be chosen for the secondary buffer of the CMP buffer.

[0028] By using such a relatively hard secondary buffer, edge curling of the piezoelectric layer to be transferred, conventionally resulting in edge bonding voids formed in the final POI structure, can be significantly suppressed. Therefore, more reliable bonding of the transferred piezoelectric layer to the target substrate 7 can be achieved.

[0029] According to various embodiments, the secondary buffer used for the CMP of the piezoelectric layer 3 of the donor substrate 1 has a density greater than 0.35 g / cm3, in particular greater than 0.4 g / cm3, or in the range of 0.35 g / cm3 to 0.45 g / cm3, and the secondary buffer may have a compressive force deflection in the range of 600 kPa to 670 kPa, in particular of about 641.212 kPa.

[0030] For example, the secondary pad of a CMP used for CMP of the piezoelectric layer 3 of the donor substrate 1 may be made of thermoplastic polyurethane and have a hardness of 53 shore A, a density of 0.4 g / cm3, a compressive force deflection of 641.212 kPA (93 psi) and a thickness of 0.79 mm (35 mil) compared to a typical conventional secondary pad used for CMP of a piezoelectric layer of a donor substrate used in a Smart Cut™ process to obtain a POI structure made of polyurethane and having a hardness of 35 shore A.

[0031] According to one embodiment, the CMP is carried out by means of a CMP suspension consisting of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon of less than 20, in particular in the range of 10 to 18 or 12.5 to 17.5. The amorphous silicon used for the CMP suspension may comprise or consist of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm. For example, Klebosol 30HB50 having amorphous silicon for 25 to 35 wt% and an average diameter of the precipitated amorphous silicon particles of 50 nm may be suitably diluted with water, for example with a dilution of 1:1, in order to obtain the CMP suspension used for the CMP of the piezoelectric layer 3 of the donor substrate 1.

[0032] Other parameters of the entire CMP process as well as the entire POI structure manufacturing process illustrated in [Fig.l] can be chosen in the usual manner.

[0033] [Fig.2] illustrates a reduction in edge curl by using a CMP pad comprising a hard secondary pad according to one embodiment. For the results shown, a secondary pad made of thermoplastic polyurethane and exhibiting a hardness of 53 shore A, a density of 0.4 g / cm3, a compressive force deflection of 641.212 kPA (93 psi) and a thickness of 0.79 mm (31 mil), was used with a CMP suspension in the above-mentioned silicon concentration range. The abscissa of [Fig.2] 2 shows the distance from the edge of the piezoelectric layer 3 at the same, and the ordinate shows the deviation of edge thickness from the central thickness in Å. The three edge profiles obtained for a usual CMP (POR) pad for different wafers show the disadvantageous edge curl (see maxima of the curves). On the contrary, via two different inventive secondary pads used for CMP, such edge curl can clearly be suppressed.For the results presented, a secondary pad made of thermoplastic polyurethane and having a hardness of 53 shore A, a density of 0.4 g / cm3, a compressive force deflection of 641.212 kPA (93 psi) and a thickness of 0.79 mm (31 mil) was used, with a CMP suspension in the silicon concentration range mentioned above.

[0034] In step ii) of the method illustrated in [Fig.l], hydrogen (optionally supplemented with helium) is implanted into the piezoelectric substrate 1a through the exposed surface 4 to generate a weakened layer 2 which marks the separation of the piezoelectric layer 3 from the remaining part 5 of the donor substrate 1. The nature and dose of the implanted species and the implantation energy can be chosen depending on the thickness of the piezoelectric layer 3 which is to be transferred to the target substrate 7 and the physicochemical properties of the piezoelectric substrate 1a. For example, for a lithium tantalate substrate, a hydrogen ion dose between 1016 and 5«1017 at / cm2 with an energy between 30 keV and 300 keV can be implanted to delimit the piezoelectric layer 3 with a thickness of 200 nm to 2000 nm, for example.

[0035] According to the method illustrated in [Fig.l], the implantation step ii) is followed by the step of attaching iii) the donor substrate 1 to the support substrate 7 on the side of the piezoelectric substrate 1a by molecular adhesion and / or electrostatic bonding. A dielectric assembly layer 7b may be provided between the piezoelectric substrate 1a of the donor substrate 1 and the target substrate 7. The dielectric assembly layer 7b may comprise an oxide and may be made of or comprise silicon oxide and / or silicon nitride, or a stack of layers composed of these materials. Furthermore, a charge trapping layer made of or comprising polycrystalline silicon may for example be formed on or above the target substrate 7 in order to improve the electrical resistivity thereof if this is desired by an actual application.

[0036] The piezoelectric layer 3 is then detached from the remaining portion 5 of the donor substrate 1 to obtain iv) a POI structure 9 comprising the target substrate 7, the dielectric assembly layer 7b (if any) and the piezoelectric layer 3. Detachment at the weakened layer 2 is facilitated by heat treatment in a temperature range of about 100°C to 600°C, to allow transfer of the piezoelectric layer 3 to the target substrate 7. Alternatively or additionally, detachment at the weakened layer 2 may be facilitated by the application of a blade or jet of gaseous or liquid fluid, or any other mechanical force applied to the weakened layer 2.

[0037] Post-treatment of the transferred piezoelectric layer 3 is necessary to obtain a transferred piezoelectric layer 3 having satisfactory single-domain crystalline and surface quality (reduced roughness) and thickness uniformity as required by real applications. The post-treatment comprises a heat treatment v) of the piezoelectric layer 3, for example at approximately 500°C in a neutral atmosphere or an atmosphere comprising oxygen. This heat treatment makes it possible to treat the crystalline defects present in the piezoelectric layer, and consolidates the bonding between the piezoelectric layer 3 and the target substrate 7.

[0038] However, the heat treatment causes diffusion of the hydrogen contained in the piezoelectric layer 3, in particular in its upper part (with a thickness of approximately 50 nm or less, for example), and consequently the generation of a plurality of ferroelectric domains giving the upper part a multi-domain character. Indeed, the hydrogen implanted in the piezoelectric substrate 1a during the step of defining the piezoelectric layer 3 above the weakened layer 2 is distributed in this substrate according to a profile having a concentration peak at the weakening plane 2. After fracturing at the weakened layer 2, the piezoelectric layer 3 transferred to the target substrate 7 therefore has a significant concentration of hydrogen, and the heat treatment leads to the generation of multiple domains, i.e. a plurality of regions having different polarities.The performance of devices that are intended to be formed on / in the piezoelectric layer 3 would be greatly affected by such multiple domains.

[0039] In order to eliminate the multiple upper domains and increase the surface quality and thickness uniformity of the transferred piezoelectric layer 3, the post-processing comprises polishing the exposed surface of the piezoelectric layer 3 (see step vi) in [Fig.l]). For example, 100 to 300 nm of the upper portion of the piezoelectric layer 3 may be removed by the polishing process to achieve a predetermined target thickness of, for example, about 600 nm.

Claims

Claims

1. A method of manufacturing a donor substrate (1) for manufacturing a piezoelectric-on-insulator, POI, structure (9), comprising the steps of providing a support substrate (1b); forming a block of piezoelectric material on or above the support substrate (1b), wherein the piezoelectric material comprises or consists of one of lithium tantalate and lithium niobate; performing chemical mechanical polishing, CMP, of the block of piezoelectric material to obtain a piezoelectric substrate (1a); and implanting a species into the piezoelectric substrate (1a) to obtain a weakened layer (2) in the piezoelectric substrate (1a); and wherein the CMP is performed using a CMP pad comprising a secondary pad having a hardness greater than 45 shore A

2. rt. The method according to claim 1, wherein the CMP is carried out by means of a CMP pad comprising a secondary pad with a hardness of more than 50 shore A, or with a hardness in the range of 45 shore A to 55 shore A, in particular in a range of 50 shore A to 55 shore A.

3. The method according to claim 1 or 2, wherein the secondary buffer has a density greater than 0.35 g / cm3, in particular greater than 0.4 g / cm3, or in the range of 0.35 g / cm3 to 0.45 g / cm3.

4. The method of any preceding claim, wherein the secondary pad has a compressive force deflection in the range of 600 kPa to 670 kPa.

5. The method according to any one of the preceding claims, wherein the CMP is carried out using a CMP suspension consisting of an aqueous suspension of amorphous silicon with a weight percentage of the amorphous silicon of less than 20, in particular in the range of 10 to 18 or 12.5 to 17.

5.

6. The method of claim 5, wherein the amorphous silicon comprises or consists of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm.

7. The method of any preceding claim, further comprising grinding the block of piezoelectric material prior to CMP.

8. A method of manufacturing a piezoelectric-on-insulator, POI, structure (9), comprising the steps of performing the steps of any one of the preceding claims; and transferring a piezoelectric layer (3) from the piezoelectric substrate to a target substrate (7), comprising bonding the donor substrate (1) to the target substrate (7) on the side of the piezoelectric substrate (1a), and fracturing the piezoelectric substrate (1a) at the weakened layer (2).

9. The method of claim 8, further comprising performing a heat treatment followed by a CMP of the piezoelectric layer (3) transferred to the target substrate (7).

10. A piezoelectric-on-insulator structure, POI (9) comprising a piezoelectric layer (3) formed on or above a target substrate (7) and obtainable by the method according to any one of claims 8 and 9.

11. Microelectronic, micromechanical or photonic device, or microelectromechanical system comprising the POI structure (9) according to claim 10.

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