METHOD FOR THE REALIZATION OF A MICROELECTRONIC DEVICE ON AN FD-SOI SUBSTRATE, CORRESPONDING DEVICE AND INTEGRATED CIRCUIT INCORPORATING IT

Abstract

The fabrication of a microelectronic device on an FD-SOI substrate involves: the formation in the substrate (11) of a first wafer, of first boxes in insulating material adapted to form shallow insulation trenches (14) (STI); the formation, on a second wafer, of a film (23) of strained silicon (sSi) covered with a layer of oxide (24); the bonding of the second wafer on the first wafer, after vertical inversion, whereby the oxide layer becomes a buried oxide layer (BOX), covered by the sSi film which thus becomes a strained silicon film on insulator; the removal of the donor substrate while leaving the BOX layer and the sSi film; and the formation of second SSTI insulation trenches (34) by local oxidation of the silicon of the sSi film, which join the STIs via the BOX, to form complex insulation structures (STI-BOX-SSTI). Figure for the abridged version: [Fig.11]

Description

Title of the invention: METHOD FOR MAKING A MICROELECTRONIC DEVICE ON AN FD-SOI SUBSTRATE, CORRESPONDING DEVICE AND INTEGRATED CIRCUIT INCORPORATING IT technical field

[0001] The invention relates to the field of the microelectronics industry, or semiconductor industry, and concerns the fabrication of a microelectronic structure on a SOI substrate (acronym for "Silicon-On-Insulator"). The invention also relates to the microelectronic structure obtained by such a fabrication process.

[0002] It finds applications, in particular for the manufacture of integrated semiconductor devices, such as microelectromechanical systems (MEMS) or nanoelectromechanical systems (NEMS), or microelectronic or optoelectronic devices, such as for example an image sensor (or imager) in CMOS technology (from the English "Complementary Metal-Oxide-Semiconductor") or any other microelectronic device made in this technology. Prior art

[0003] Since the 1950s, the microelectronics industry has been engaged in a race to miniaturize microelectronic devices, the basic element of which is the field-effect transistor, and in particular the MOS transistor (from the English "Metal-Oxide-Semiconductor"), notably in CMOS technology, which is used as a switching element between two distinct electrical states corresponding to two opposite logic states (1 or 0 in binary logic). The miniaturization of MOS transistors has been accompanied by better control of their electrical properties, and in particular of the amount of current flowing per unit time through the conduction channel of these transistors, on which the speed of their switching depends.

[0004] However, the speed of the current is mainly determined by the material through which it passes. As manufacturers of microelectronic chips are more or less limited to the use of silicon (Si) substrates, they have focused on increasing the switching speed by reducing the size of transistors, for example MOS transistors, particularly in CMOS technology (from the English "Complementary Metal-Oxide-Semiconductor").

[0005] In this context, silicon-on-insulator substrates or SOI substrates (from the English "Silicon-On-Insulator") have become widely used nowadays for manufacturing of transistor-based microelectronic devices. But after a few decades of improvements in technological processes, the industry was finding it increasingly difficult to further reduce the size of transistors.

[0006] This is why the technique developed by Leti (a laboratory of the French Alternative Energies and Atomic Energy Commission (CEA)) and its partners some twenty years ago, and known as FD-SOI (from the English "Fully-Depleted Silicon-On-Insulator"), consisted of proposing a new architecture of ultrathin MOS transistors, with a channel that can therefore be completely "depleted" (FD), that is to say, without doping elements. The FD-SOI technique has made it possible to continue the challenge of miniaturization, while combining high performance and low power consumption, particularly in integrated circuits for analog applications in millimeter waves and radio frequencies (RF) up to 100 GHz, for example for 5G telephony. The FD-SOI technology makes it possible to reach even the most technologically advanced nodes. less than or equal to 10 nm, or even 7 nm.

[0007] FD-SOI technology differs from conventional, thicker SOI structures, such as classic MOS transistor technology where the channel is formed in a bulk silicon substrate, and Intel®'s FinFET (Fin Field-Effect Transistor) technology, in which a finned field-effect transistor, which is a non-planar transistor (or "3D transistor"), is built on a bulk substrate where the gate is placed on two, three, or four sides of the channel, forming a multi-gate structure. Compared to these technologies, FD-SOI technology allows for increased current flow rates because the components are formed not from a bulk silicon block but from an ultra-thin silicon layer deposited on a thin insulating oxide layer, itself deposited on the silicon substrate, which no longer requires doping.Thus, transistors made on an SOI substrate, which are planar transistors and therefore simpler to manufacture than FinFET transistors, are less sensitive to current leakage between the source and their drain on the one hand, and the silicon of the substrate on the other, which increases the speed at which they switch without it being necessary to make them smaller.

[0008] But it is also known that the current flow rate depends on the crystalline structure of silicon. This is why SOI substrates are currently evolving towards the use of strained silicon (Si) for the realization of active areas in microelectronic devices such as the channel of CMOS transistors. The use of strained silicon, or sSi, is currently one of the most important factors accelerating the development of silicon-based CMOS technology. The improved mobility of charge carriers electrical which is obtained by applying an appropriate constraint to the structure of the crystal lattice makes it possible to increase the speed of these charge carriers in the channel of the MOS transistor, which results in a higher current for a fixed supply voltage and gate oxide thickness.

[0009] In practice, strained silicon (sSi) is a silicon layer in which the silicon atoms are stretched (tensioned) or compressed (compressed) beyond their normal interatomic distance. A strained silicon layer can be obtained by placing a thin layer of silicon on a silicon-germanium (SiGe) substrate. When the atoms of the silicon layer align with the atoms of the underlying silicon-germanium layer (which are arranged slightly further apart than those of a bulk silicon crystal), the bonds between the silicon atoms are stretched, resulting in a deformed lattice of silicon atoms. This improves the mobility of these charge carriers, leading to better chip performance and lower power consumption.Electrons can thus move 70% faster, allowing NMOS transistors in sSi to have a switching speed increased by 35%.

[0010] FD-SOI technology and the use of sSi can be combined to bring together the respective advantages of these two major technological advances. This involves bonding a strained silicon (sSi) film over a very thin layer of buried oxide or BOX (from the English "Buried Oxide") formed on an undoped silicon substrate. The bonding of a strained silicon (sSi) film to such a substrate is described, for example, in the prior art documents EP 1923912 A1 and US 5691231 A.

[0011] The thinness of the oxide layer (BOX) beneath the strained silicon (sSi) film is a source of bonding problems when the thin film is continuous (i.e., pattern-free). This is due, in particular, to the fact that the hydrogen gas in the atmosphere under which the bonding operation is performed must be absorbed by the BOX for bonding to occur, and when the BOX is very thin, there is a risk of bonding defects. The solution disclosed in document EP 1923912 Al for bonding a portion of a donor wafer, including the active layer of the microelectronic device, to a substrate wafer provides a satisfactory solution to the bonding problems of the sSi film to the BOX.

[0012] However, it is observed that the subsequent fabrication of etched patterns forming shallow trench insulation (STI) between components fabricated in adjacent positions within the active layer of the microelectronic device, in turn, poses problems. Shallow trench insulation (STI), also known as box insulation, prevents electrical current leakage between components Adjacent components of a microelectronic device that are fabricated on the same semiconductor substrate are isolated from each other by such an insulating trench. The STI technique has been commonly used for many years in CMOS technologies of 250 nanometers and smaller.

[0013] However, when attempting to create active zones isolated from one another and each comprising a respective portion of a strained silicon film (in sSi), it is observed that the strain on the sSi tends to relax, that is, to decrease at the edges of the active zones created, where said sSi film is cut. This occurs when the patterns intended to be filled with the insulator to form the STI insulation trenches are etched, since said etching physically breaks the sSi film. Description of the invention

[0014] The invention aims to remedy at least in part the disadvantages of the prior art, and more particularly to propose an alternative to the formation of shallow insulation trenches (STI) in accordance with current practice, which avoids relaxing the stress of the silicon in disjoint portions of a continuous stressed silicon film due to the formation of said insulation trenches which separate said continuous film into said disjoint portions, in order to preserve its good electrical conductivity properties.

[0015] To this end, the object of the invention is a method for manufacturing a microelectronic device, said method comprising: • the supply of a first plate comprising a supporting substrate; • the formation, on the substrate supporting the first plate, of the first insulation trenches; • the supply of a second plate including a donor substrate; • the formation, on the donor substrate of the second plate, of a film of constrained silicon, • the bonding of the second plate onto the first plate, so that the strained silicon film is found on the first plate by means of at least one layer of insulating material formed, before bonding, on the first plate after the formation of the first trenches and / or on the second plate after the formation of the strained silicon film; • dismantling the donor substrate while preserving the insulating material layer and the silicon film constrained on the first plate; • the formation of secondary isolation trenches around and / or along portions of the strained silicon film.

[0016] Thus, some implementation methods of the invention are based on the combination: • the bonding of a donor wafer comprising a silicon film to be transferred onto a support wafer having insulation trench patterns (STI); on the one hand, and, • of the additional oxidation of the strained silicon film which occurs after the transfer of said film onto the support wafer, on the other hand, to create additional shallow insulation trenches (STIs) that connect to the insulation of existing, deeper STIs without cutting the strained silicon film. Advantageously, the strained silicon film is not cut, as it is simply transformed locally into silicon dioxide. Therefore, there is no stress relaxation of the silicon in the respective portions of the strained silicon film created by the formation of these insulation trenches.

[0017] Some preferred but not limiting aspects of this process are the following.

[0018] In some implementation modes, it may be foreseen that: • the first isolation trenches formed in the substrate supporting the first wafer are so-called "shallow trenches", or STIs, whose depth is greater than approximately 5 nm, or between approximately 5 nm and approximately 300 nm, preferably between approximately 50 nm and approximately 300 nm, and even more preferably between approximately 70 nm and approximately 300 nm; and / or • the second isolation trenches have a depth equal to or greater than the thickness of the strained silicon film, for example between about 10 nm and about 20 nm, for example on the order of 15 nm.

[0019] The insulating material of the first trenches, the insulating material of the second trenches and / or the insulating material of the insulating layer, may contain silicon dioxide (SiO2).

[0020] In embodiments, the formation of the first trenches in the donor substrate can be carried out by etching through a first mask previously made by photolithography in a layer of hard material such as, for example, a nitride, which covers the supplied support substrate via an associated insulating material layer, residues of said first mask and of said associated insulating material layer being removed from the support substrate after the formation of said first trenches.

[0021] In embodiments, the method further comprises the formation of third isolation trenches made through a second mask previously made by photolithography in a layer of hard material such as, for example, a nitride, which is deposited on top of an associated insulating material layer itself deposited on the strained silicon layer after the removal of the donor substrate, residues of said second mask and of said associated layer of insulating material being removed after the formation of said third trenches.

[0022] For example, the second insulation trenches join the first trenches via the layer of insulating material to form an insulation structure around and along the strained silicon film.

[0023] The second trenches can be made by local oxidation of the silicon of the strained silicon film, for example the local oxidation of the silicon of the strained silicon film is a thermal oxidation, for example a LOCOS type oxidation.

[0024] In embodiments, the dismantling of the donor substrate can be carried out by grinding, by selective removals or by implantation fracture, for example by implementation of the Smart-cut® process.

[0025] The donor substrate of the second plate may comprise a silicon-germanium layer, Si-Ge, adapted to constrain the silicon of the constrained silicon film.

[0026] In embodiments, at least one opening can be made further through the thickness of a trench among the second trenches and through the layer of insulating material to expose the underlying support substrate, in an area of ​​said support substrate in which there are no first trenches, and in which, furthermore, the silicon (Si) of the support substrate is grown upwards by epitaxial growth in the opening, at least up to and including the level of the layer of insulating material.

[0027] In embodiments, at least some of the second isolation trenches may have the same horizontal dimensions as associated first trenches, and are respectively aligned vertically with said associated first trenches.

[0028] According to a second aspect of the invention, a microelectronic structure obtained by implementing the manufacturing process according to the first aspect above is also proposed, said structure comprising disjoint active areas on the surface of the same carrier substrate and isolated from each other by deep and shallow isolation trenches, each active area having a respective portion of constrained silicon film, and said portions of constrained silicon film resting on the same insulating layer which is itself located above the carrier substrate.

[0029] The constrained silicon can, for example, be of the totally depleted silicon type on an insulator.

[0030] The insulating material of the first trenches, the insulating material of the second trenches and / or the insulating material of the insulating layer, may contain silicon dioxide (SiO2).

[0031] The second trenches may have non-vertical sides.

[0032] According to yet a third aspect, an integrated circuit is proposed comprising the microelectronic structure according to the second aspect above, and further comprising at least one MOS-type field-effect transistor made in an active area of ​​said microstructure, the portion of which is constrained silicon film serves as a totally depleted silicon substrate on insulator (FD-SOI) in which the channel of the MOS transistor is made. Brief description of the drawings

[0033] Other aspects, objectives, advantages and features of the invention will become clearer upon reading the following detailed description of preferred embodiments thereof, given by way of non-limiting example, and made with reference to the accompanying drawings in which: • Figures [Fig.1A] to [Fig.1C] are schematic vertical cross-sectional views, at respective stages of its preparation, of an example of a support plate having shallow insulation trenches (STI) made, in accordance with embodiments of the invention, before the bonding of the donor plate onto said support plate; • [Fig.2] is a schematic vertical cross-sectional view of an example of a donor wafer comprising a layer of strained silicon, intended to be transferred by bonding onto the support wafer of [Fig.1C]; • [Fig.3A] schematically illustrates the bonding, on the support wafer, of the donor wafer with its layer of strained silicon, after vertical flipping of said donor wafer; • [Fig.3B] is a schematic view showing, in vertical section, the new plate obtained after the bonding schematically illustrated by [Fig.3A]; • [Fig.4] is a schematic, vertical cross-sectional view of the wafer of [Fig.3B] after removal of the substrate from the (formerly) donor wafer; • [Fig.5] is a schematic, vertical section view of the plate of [Fig.4] after the formation of an oxide insulation layer followed by a nitride passivation and protection layer; • [Fig.6] shows, in vertical section, the wafer of [Fig.5] after the formation, through the oxide and nitride layers, of boxes exposing the strained silicon layer which has been transferred onto the support wafer; • Figure 7 is a schematic, vertical cross-sectional view of the wafer after the cells of Figure 6 have been filled with insulating material to form insulation trenches by local oxidation of the strained silicon, which isolation trenches join the deeper trenches already made in the substrate of the support wafer before the transfer of the silicon film constrained by bonding the donor wafer; • Figure 8 shows the microstructure of Figure 7 after removal of the hard mask in dielectric nitride; • [Fig.9] is a schematic, vertical cross-sectional view of the platelet finally obtained after removal of oxide residues and planarization; • Figure 10 is a step diagram schematically illustrating... example steps for implementing the process according to the invention; and, • Fig. 1 is a schematic, vertical cross-sectional view of an example of an electronic circuit obtained by the process, after making openings to access the silicon of the carrier substrate. Description of detailed embodiments

[0034] In the figures and throughout the description, the same reference numerals represent identical or similar elements. Furthermore, the various elements are not drawn to scale in order to enhance the clarity of the figures. Moreover, the different embodiments and variants are not mutually exclusive and may be combined.

[0035] In what follows, the terms "approximately", "around", or "in the order of" mean within 10%, and preferably within 5%. Furthermore, the terms "between ... and ...", or equivalent terms, mean that the bounds are inclusive, unless explicitly stated otherwise.

[0036] By the expression "formed from", used in reference to a material and an element of interest, it is understood that the material is a compound formed from a plurality of elements of which at least the said element of interest is included.

[0037] The expression "material comprising predominantly" an element of interest means a material of which at least 50% by volume is formed by, or comprises, said element of interest.

[0038] The term "wafer" refers to a very thin plate of single-crystal semiconductor material (also called a "wafer," borrowing this term from English), on which microelectronic devices can be fabricated. Wafers are used in the microelectronics industry as a substrate for manufacturing microstructures to fabricate microelectronic devices before their integration into a package to obtain an integrated circuit. Wafers comprise a base of doped semiconductor material, such as silicon (Si), gallium arsenide (GaAs), or indium phosphide (InP). This doped semiconductor material serves as a substrate for creating the microstructures that form the active microelectronic devices that make up the components of the Integrated circuits, transistors, power semiconductor products, MEMS or NEMS, etc. This manufacturing process employs design techniques such as, for example and without limitation: photolithography, doping, etching, deposition of other materials in layers or by diffusion or any other physico-chemical reaction, polishing, etc. Industrially produced wafers generally have dimensions between 25.4 mm (1" technology) and 300 mm (8" technology), with a thickness of approximately 0.7 mm.

[0039] By "layer", we mean an extent of a crystalline material whose thickness along the Z axis is less, for example ten times or even twenty times, than its longitudinal dimensions of width and length in the XY plane.

[0040] By "anisotropic etching" is meant that the etching speed of the silicon is not the same in all directions during the etching process. On the contrary, only the vertical direction of the silicon is etched during the etching process, the lateral direction not being etched. Conversely, "isotropic etching" does not favor any particular etching direction, so that all exposed surfaces are etched simultaneously, regardless of their orientation in space, i.e., whether they are horizontal, vertical, or inclined.

[0041] Chemical-mechanical polishing (CMP) is a surface smoothing process that uses the combined action of mechanical abrasion forces and chemical attack on the surface of a material to be treated. This is achieved by applying an abrasive polishing slurry, which removes the material(s) from the surface of the insert and eliminates any surface topography, resulting in the flattening of the insert surface exposed to this process. The duration of the CMP process is determined by the removal rate and the thickness of material to be removed before reaching any potential stop layer.

[0042] The term "photoresist" refers to a material used in photolithography, more particularly a polymer resin, which is light-sensitive and used to form a pattern on a wafer. This is done using an optical mask made up of opaque and transparent areas that define the pattern to be reproduced on the wafer, through which the photoresist is illuminated. The photoresist has its properties modified in the transparent areas of the optical filter as a result of this illumination.Thus, for example, a "positive" photoresist is a light-sensitive polymer which, when exposed to ultraviolet (UV) light, transforms into a soluble material: the areas exposed to this illumination can then be dissolved using a solvent, leaving behind (this is called development in the jargon of the person in the trade) a recessed patterned layer which can be used as a mask for the formation of a . structure through the mask thus formed. For example, the structure can be formed by etching a pre-existing underlying material that is selective to the mask material, or by ion implantation in such an underlying material, or by deposition of a new material in the areas exposed by the mask.

[0043] Finally, a three-dimensional orthogonal (X,Y,Z) direct frame of reference is defined here and for the remainder of the description, where the X and Y axes form a plane parallel to the principal plane of the support plate under consideration, and where the Z axis is oriented substantially orthogonally to the principal plane of the plate, this Z axis being oriented along the direction of the axis of gravity. In the remainder of the description, the terms "vertical" and "vertically" are understood to refer to an orientation substantially parallel to the Z axis, and the terms "horizontally" and "horizontally" to refer to an orientation substantially parallel to the (X,Y) plane.Furthermore, the terms "above" and "below" and their derivatives (such as "above" and "below", or "over" and "underneath"), as well as the terms "lower" and "upper", used to describe an element of the microstructure under consideration, are understood to be relative to an increasing positioning when moving away from the wafer upwards, i.e., along the vertical direction +Z.

[0044] The terms "rear" and "front," on the other hand, are used with reference to the face of a wafer through which the various treatments are, or have been, carried out to produce the microstructure in question. Since these treatments are systematically carried out from above when the wafer is placed flat in an enclosure used to perform the treatment, the "front" face is generally (and by default) the upper face of the wafer. However, when a wafer or a chip cut from a wafer is turned vertically, its front face becomes the lower face and its rear face becomes the upper face.The term "rear" applied to the semiconductor substrate of an individual wafer or chip is also used in reference to this convention, in the sense that it designates the part of the substrate that is furthest from the face of said wafer or chip where treatments have been carried out on the substrate, and which is always referred to as the rear face even if the wafer or chip has been turned vertically.

[0045] In the following description of embodiments of the process, the microelectronic device of interest is formed on a support wafer, from a base support wafer and a donor wafer which are bonded together after vertically flipping the donor wafer to form a new support wafer onto which a constrained silicon film has been transferred. This wafer is intended for the fabrication of an integrated semiconductor product, for example in CMOS technology, and the process aims to fabricate shallow insulation trenches (STIs) in a manner compatible with preserving the advantages of FD-SOI technology. The implementation methods of the process described can be adapted to the specific characteristics of each application concerned, without departing from the teachings of the invention.

[0046] As shown in [Fig. 1A], the support wafer 1 is based on a carrier substrate 11, for example a single-crystal silicon substrate. The carrier substrate 11 is lightly doped, for example with P-type doping. Such doping can be obtained by inserting electron-acceptor atoms, such as boron (B) atoms, into the substrate.

[0047] With reference to steps 101 and 102 of the step diagram in [Fig. 10], in step 101 a protective layer 12, typically based on oxide (Ox), is deposited on the substrate 11, followed in step 102 by the deposition of a layer of hard material, for example based on dielectric nitride (Nx), intended to form a hard mask for an etching operation which will follow in order to form shallow trench insulation or STI (“Shallow Trench Isolation”).

[0048] The oxide in layer 12 can be, for example, silicon dioxide (SiO2). The SiO2 deposition can be carried out chemically, such as low-pressure chemical vapor deposition (LPCVD) to form high-temperature oxide (HTO). It can also involve chemical deposition, for example plasma-enhanced chemical vapor deposition (PECVD), of tetraethyl orthosilicate (TEOS), with the chemical formula Si(OCH2CH3)4 or simply Si(OEt)4, as a precursor to silicon dioxide (SiO2), followed by simple hydrolysis to form SiO2 and release ethanol (CH3CH2OH).Alternatively, the deposition can also be carried out by a physical process, such as sputtering, or spin-off deposition methods.

[0049] The dielectric nitride of layer 13 can be, for example, silicon nitride or Si3N4 (abbreviated SiN for short). This hard material can be deposited by chemical vapor deposition (CVD), for example by low-pressure chemical vapor deposition (LPCVD). Such a process operates at a relatively high temperature. Alternatively, the silicon nitride layer 13 can be formed by plasma-enhanced chemical vapor deposition (PECVD), which operates at a relatively lower temperature and under vacuum. The SiN layer thus obtained can have a thickness, for example, of about one hundred nanometers (nm). Other dielectric materials, in particular titanium nitride (TiN) and tungsten nitride (TiN), as well as various types of nitride oxides, can also be used, either as an alternative to or in addition to silicon nitride (SiN).

[0050] With reference now to [Fig. 1B], the preparation of the support plate 1 continues with the creation of insulation trenches 14, namely shallow insulation trenches (STI), in the thickness of the substrate 11 of the plate 1. According to one embodiment, and with reference to the step diagram of [Fig. 10], this embodiment comprises the following sequence of steps: • a photolithography step 103 defining the areas to be etched in the Si3N4 layer 13 and the SiO2 protective layer 12, by the formation of a hard mask for this etching; • a step 104 of etching the Si3N4 and SiO2 layers 13 and 12, respectively, through the hard mask formed in step 103, to create channels for forming the insulation trenches 14 (STI) in the silicon 11; and, • a step 105 of filling the trenches with insulating material to form said STIs.

[0051] In step 103, the mask required for engraving is exposed by a standard photolithographic process

[0052] In step 104, the selective etching of the silicon nitride layer 13, and then of the silicon dioxide (SiO2) layer 12, can be anisotropic etching such as reactive ion etching (RIE). This is a variation of plasma etching (dry etching, highly anisotropic) combining the selectivity of chemical etching and the anisotropy of physical etching. The plasma can then be a fluorocarbon plasma, based on a gas such as carbon tetrafluoride (CF4), for example, or on sulfur hexafluoride (SF6), or on nitrogen trifluoride (NF3), or any combination of these gases. The insulating material layer to be etched, partially protected by the etching mask formed, for example, by a partially open silicon dioxide layer, is placed in a chamber in which a vacuum is created.This chamber is equipped with two horizontal and parallel electrodes, the lower electrode serving as a platform to receive the wafer. Once a vacuum has been created in the chamber, gas is introduced. Then, a strong radio frequency (RF) electric field, for example, one hundred volts per meter or more, is applied to the lower electrode. This generates a plasma in the chamber, that is, a partially ionized gas. Indeed, some electrons from the gas molecules are stripped by the electric field, which ionizes these molecules. The upper surface of the wafer is then bombarded with ions, which disintegrates it in the areas not protected by the hard mask. Alternatively, the selective etching of step 104 can be chemical etching (or wet etching) using a hydrofluoric acid (HF) solution. for example, or a physical engraving (or dry engraving), that is to say, an engraving by plasma.

[0053] In step 105, the gaps 14 previously formed in step 104 are gap-filled with a thick oxide, for example, silicon dioxide (SiO2). This step 105 allows the insulating material to be deposited from the upper surface of the microstructure to the bottom of the gaps 14. Chemical mechanical polishing (CMP) removes the excess SiO2 deposited on the surface and smooths the upper surface of the microstructure, as shown in [Fig. 1B], which illustrates the microstructure after the sequence of steps 103, 104, and 105. As those skilled in the art understand, the oxide deposited in step 105 in the gaps 14 allows the STI insulating gaps to be formed in the substrate 11 of the support wafer 1 even before the transfer-constrained silicon layer is depositioned from the donor wafer 2.

[0054] In some embodiments, the depth of the trenches 14 is greater than approximately 5 nm. It may be between approximately 5 nm and approximately 300 nm, preferably between approximately 50 nm and approximately 300 nm, and even more preferably between approximately 70 nm and approximately 300 nm.

[0055] Alternatively, the trenches 14 can be filled with a silicon nitride (SiN) for example Si3O4, instead of silicon dioxide SiO2.

[0056] With reference now to [Fig. 1C], the following step 106 is a chemical-mechanical polishing (CMP) step with a stop on the silicon of the substrate 11, which allows the simultaneous removal of the hard nitride mask from layer 13 and the silicon dioxide residues from layer 12. If necessary, a slight oxidation of the silicon of the substrate 11 is carried out after the CMP etching is stopped to restore protection by a thin layer of silicon dioxide (SiO2). Alternatively, the CMP etching can be stopped on the nitride. The nitride is then removed chemically, and the silicon dioxide is removed, for example, by wet chemical etching using a hydrofluoric acid (HF) solution.

[0057] The diagram in [Fig. 2] shows the donor wafer 2 comprising a strained silicon (sSi) film. For example, the sSi film is a thin silicon (Si) layer 23 in which the silicon atoms are stretched beyond their normal interatomic distance. This can be achieved by depositing the thin silicon layer 23 onto a silicon-germanium (SiGe) substrate 22, by any suitable silicon deposition process, said SiGe substrate 22 being itself formed on a silicon base substrate 21. When the atoms of the thin silicon layer 23 align with the atoms of the underlying silicon-germanium layer 22 (which are arranged somewhat further apart than those of a bulk silicon crystal), the bonds between the silicon atoms of the layer 23 are stretched, resulting in a A lattice of silicon atoms is deformed. The separation of these silicon atoms reduces the atomic forces that interfere with the movement of electrons through the channel of a MOS transistor formed in such a strained silicon (sSi) layer 23. This improves the mobility of these charge carriers, resulting in better transistor performance and lower power consumption. The donor wafer 2 also includes an oxide layer 24, based, for example, on silicon dioxide (SiO2). Alternatively, 1, instead of silicon dioxide SiO2, layer 24 can be made of another insulating material, in particular another oxide, for example a metal oxide such as aluminium oxide (Al2O3), germanium oxide (GeO2), tin oxide SnO2 is a semiconductor and lead oxide PbO2, hafnium oxide (HfO2) or tantalum oxide (Ta2O5).

[0058] It should be noted that the fabrication of the donor wafer 2 as shown in [Fig. 2] is not described in detail here, so as not to unnecessarily lengthen this presentation. Indeed, this fabrication is not specific to the implementation of the process of the invention. If necessary, those skilled in the art may refer to the literature available in the prior art concerning FD-SOI technology.

[0059] With reference to the schematic representation in [Fig. 3A], in step 107 the donor wafer 2 is turned vertically, then aligned and bonded to the support wafer 1, to give the microstructure 3 shown in [Fig. 3B] (which may sometimes be referred to as the new support wafer 3 in what follows). Those skilled in the art will appreciate that, from the point of view of the upper surface of the microstructure 3, the oxide of the oxide layer 24 of the donor wafer 2 becomes buried oxide or BOX. For the sake of simplicity of illustration, this BOX is shown in [Fig. 3A] as being only on the donor wafer 2, but the support wafer 1 may also have, in the same way, an oxide layer deposited after step 106 of CMP that concerns it, to promote bonding conditions. Alternatively, it can be predicted that only the support wafer 1 has this oxide layer, and not the donor wafer 2.

[0060] With reference to [Fig.4], the dismantling of the substrate 21-22 of (formerly) the donor wafer 1 is then carried out, as shown in step 108 of the step diagram in [Fig. 10].

[0061] In some embodiments, this can be achieved by implementing the SmartCut® process invented by the CEA, according to which the microstructure 3, consisting of the donor wafer 2 bonded to the original support wafer 1, is subjected to a heat treatment capable of creating a cleavage of the microstructure 3 at the level directly below the strained silicon (sSi) layer 23. The wafer 2 will have been previously implanted with Hydrogen (H) or Helium (He), etc., in order to create this zone of weakness.

[0062] Alternatively, the removal of the substrate 21-22 from the microstructure 3 can be carried out mechanically by grinding, or by mechanochemical means, for example by chemical-mechanical polishing (CMP). In still other variants, the removal can be carried out by a chemical wet etching process.

[0063] In step 109, an insulating layer 32 based on an oxide (Ox) is deposited onto the microstructure 3 of [Fig. 4], followed by the deposition of a nitride (Nx) layer 33 in step 110. This results in the microstructure 3 shown in [Fig. 5]. The oxide layer 32 can be made of silicon dioxide (SiO2). The nitride layer 33, formed on top of layer 32, can be made of silicon nitride (SiN). Layers 32 and 33 can be produced by the same technological processes as those described above with reference to [Fig. 1A] concerning layers 12 and 13, respectively, of the support wafer 1. These processes are not described again here.

[0064] With reference to [Fig. 6], by means of a photolithography step 111 and a selective etching step 112, boxes 34 are then created through the oxide layer 32 and the nitride layer 33, each having a bottom at the level of the upper face of the strained silicon (sSi) layer 23, in order to form shallow insulating trenches by oxidation of the sSi of said exposed layer 23. Again, the photolithography step 111 and the selective etching step 112 for obtaining this result are similar to steps 103 and 104 which have been previously described, and are therefore not described again in detail here.

[0065] In step 113, and in accordance with the embodiments of the invention, a local oxidation of the strained silicon (sSi) of the layer 23 exposed at the bottom of the cells 34 is carried out. This creates additional insulation trenches, denoted SSTI, based on silicon dioxide (SiO2) obtained by the local oxidation of the strained silicon (sSi). In the following figures, these thin buried oxide trenches 34 are labeled "SSTI". The oxidation can be carried out using the oxidation method known by the English acronym LOCOS. The resulting structure is shown in [Fig. 7], in which the SSTI join the STI initially formed in the substrate 11 of the original support wafer. A person skilled in the art will appreciate that, due to the implementation of the LOCOS method, the sides of trenches 34 are not vertical, but are slightly inclined along the vertical direction Z.

[0066] In embodiments, the SSTI additional insulation trenches 34 have a depth equal to or greater than the thickness of the strained silicon film 23, for example between about 10 nm and about 20 nm, for example on the order of 15 nm.

[0067] Local oxidation of silicon, or LOCOS (for "LOCal Oxidation of Silicon"), is a microfabrication process that forms silicon dioxide (SiO2) in defined areas of a silicon wafer, with the Si-SiO2 interface below the wafer surface. This technology was originally developed (before being superseded by shallow trench insulation, or STI) to isolate MOS-type field-effect transistors from one another, thereby limiting interference between transistors. The main advantage of this technique stems from the formation, localized around the MOS transistors, of silicon dioxide structures penetrating below the wafer surface, which is not easily achieved by etching.In the context of the embodiments of the invention, thermal oxidation of the strained silicon (sSi) regions exposed by the hard mask 33 is similarly employed at a temperature between 800 and 1200 °C, using either water vapor ("wet oxidation") or dioxygen ("dry oxidation"). In both cases, and under the effect of heat, the oxygen (O2) penetrates deep into the wafer, reacts with the strained silicon (sSi) it encounters there at the level of layer 23, and converts the latter into silica, forming a structure within the volume of the strained silicon (sSi).

[0068] Advantageously, the implementation of the LOCOS technique under the conditions of the embodiments of the invention makes it possible to form zones 100, 200 and 300 of the constrained silicon film 23 (sSi) which are disjoint and isolated from each other, without the sSi being relaxed, that is to say without the constraint of the sSi being released because it is never opened. The SSTI insulating oxide thus formed joins the deeper STI insulating oxide (i.e., the "Gapfill" forming the shallow STI insulating trenches that had been made in boxes 14 formed in the silicon substrate of the original support wafer 1 before the bonding of the donor wafer 2 for the transfer onto the support wafer 1 of the strained silicon film 23 (sSi). This advantageous feature, exploited in the embodiments of the invention, is documented, for example, in the scientific article by I. De Wolf, J. Vanhellemont, A. Romano-Rodriguez, H.Norstrôm, HE Maes; “Micro-Raman study of stress distribution in local isolation structures and correlation with transmission electron microscopy”, Journal of Applied Physics 71 (2), pp. 898-906 (1992); January 15, 1992 (https: / / doi.org / 10.1063 / L351311), to which the person skilled in the art may refer as needed.

[0069] In step 114, the silicon nitride (SiN) hard mask 33 and the silicon dioxide (SiO2) residues from the insulating layer 32 can then be removed to reveal the microstructure of [Fig. 8]. For example, the removal of the silicon nitride (Si3N4) hard mask can be carried out by a first chemical etching. The surface is wet-etched using a phosphoric acid (H3PO4) solution, for example, diluted to 85%, and heated to a temperature of approximately 180 °C. Then, the silicon dioxide (SiO2) can be removed from the insulating layer 32 by a second wet etching, for example, using hydrofluoric acid (HF). Alternatively, the hard mask 33 and the silicon dioxide can be removed from the insulating layer 32 by a single etching, for example, a wet etching using hydrofluoric acid (HF).

[0070] As those skilled in the art will have understood, regions 100, 200, and 300 of this microstructure are disjoint regions of strained silicon (sSi) on a thin layer of insulator, namely the insulator (SiO2 in the example) of the underlying buried oxide (BOX) layer 24. Thanks to the implementation of the proposed process, the strain on the sSi of regions 100, 200, and 300 has not been relaxed, although said regions 100, 200, and 300 are isolated from each other laterally and vertically by additional isolation trenches or SSTI formed in the vertical extension of the STI isolation trenches that had been formed deeper in the solid substrate 11 of the original support wafer before the bonding step 107.Microelectronic devices, such as MOS transistors or more complex devices in CMOS technology, can then be made in the active areas corresponding to regions 100, 200 and 300 by taking advantage of the combined benefits of FD-SOI technology and a constrained silicon substrate which were described in the introduction to this description.

[0071] In other words, the microelectronic structure 3 illustrated in [Fig.9] which is manufactured by embodiments of the manufacturing process according to the invention, comprises disjoint (i.e. non-continuous) active zones 100, 200 and 300 on the surface of the same carrier substrate 11 and isolated from each other by shallow isolation trenches 14 (STI) extended vertically by additional isolation trenches 34 (SSTI) via the buried oxide layer 24 (BOX), each active zone having a respective portion of strained silicon film 23 (sSi), and said portions of sSi film resting on the same insulating layer 24 which is itself located above the carrier substrate 11.

[0072] An integrated circuit may comprise the above microelectronic structure, and furthermore at least one MOS-type field-effect transistor fabricated in an active region such as regions 100, 200, and 300 of said microstructure, the portion of which, in which the strained silicon film 23 serves as a fully depleted silicon-on-insulator (FD-SOI) substrate in which the MOS transistor channel can be fabricated. This transistor then benefits from the combined advantages of FD-SOI technology and the good electrical conductivity properties provided by the strain on the silicon.

[0073] A person skilled in the art will appreciate that the junction between the insulating material, namely silicon dioxide (SiO2) which fills the boxes 34 to form trenches Additional insulation (SSTI) and the 14 shallow insulation trench boxes (STI) to form the final insulation structures are achieved through the buried oxide (BOX) layer 24 of silicon dioxide (SiO2), which is continuous. This is why we refer to the complex insulation structure as STI-BOX-SSTI.

[0074] At least some of the SSTI additional insulation trenches 34 have the same horizontal dimensions as associated shallow STI insulation trenches 14, and are respectively aligned horizontally with said associated trenches 14. In other words, each of these trenches 34 is exactly superimposed on a trench 14 along the vertical direction Z, without the vertical projection of either of them extending beyond the other along the longitudinal direction X or along the transverse direction Y. These trenches 34 and 14 are then said to be vertically aligned. An example of such aligned trenches is shown at the bottom right of the diagram of an example structure 3' shown in [Fig. 11] (see below).

[0075] According to another advantage of the method implementations, relatively deep isolations can be obtained by a single process, namely, for example, the STI between active zones 100 and 200, the thickness of which can preferably be between approximately 70 nm and approximately 300 nm, and at the same time, relatively shallow isolations, such as the SSTI between active zones 200 and 300, the thickness of which is between approximately 10 nm and approximately 20 nm. It should be noted that these depths are considered along the vertical Y direction. MOS transistors on an FD-SOI substrate can be formed at zones 200 and 300, respectively, in respective cells of the silicon substrate 11 which have identical doping (type of doping and level of doping).However, another MOS transistor on an FD-SOI substrate can be made at the level of zone 100 in a box in the silicon substrate 11 which can have a different doping, thanks to the presence of the relatively deep STI insulation which separates it from the box in the silicon substrate 11 which corresponds to zone 200 to zone 300.

[0076] According to another advantage, in addition, a device made on the wafer 2 on a silicon-on-insulator (SOI) substrate can be placed above an STI, so that it will then be extremely far from any silicon of the support wafer 1. As a result, in operation, it will be extremely far from a polarizing electric field, which makes it a unique structure.

[0077] Finally, nothing prevents the formation, by etching, of third isolation trenches distinct from the second SSTI additional isolation trenches 34. These third trenches can be made through a second mask, previously produced by photolithography in the hard material layer 33 of [Fig. 5], which in the example is a nitride, and which is deposited over the layer of associated insulating material 32, which is itself deposited on the strained silicon layer 23 after removal of the donor substrate 22. Residues of this second mask and said associated insulating material layer are removed after the formation of said third trenches. The formation of trenches by etching with a mask does indeed result in a loss of strain in the sSi film, but this loss may be acceptable in certain applications in which third insulation trenches can thus be created in addition to the second SSTI supplementary insulation trenches 34 already formed by oxidation, which allow the strain in the sSi film 23 to be maintained.

[0078] Finally, with reference to another example of a microelectronic structure 3' shown in [Fig. 11] (which would be obtained by the same process steps as structure 3 in [Fig. 9]) and as depicted by block 115 in the step diagram of [Fig. 10], at least one opening can be made through the thickness of one (or more) additional trench(s) 34 (SSTI) and through the buried oxide layer 24 (BOX) to expose the underlying bulk silicon substrate 11, as in region 400 and region 700 in the example shown. In [Fig. 11], the additional insulation trench 34 thus traversed is shown surrounded by a dashed outline.For example, openings 400 and 700 can be made by etching, through a hard mask obtained by photolithography, the insulating material (SSTI) of layer 34 and the insulating material (BOX) of layer 24 in order to expose the underlying support substrate 11, in respective areas of said support substrate 11 in which there are no shallow insulation trenches 14 (STI). Since the etching mask is made after the STI and SSTI trenches, the alignment patterns of any of these trenches can be aligned.

[0079] It should be noted that the opening 400 divides the relevant SSTI additional insulation trench 34 into two such derived SSTI trenches, of smaller horizontal dimensions, which are horizontally adjacent. In the example shown in [Fig. 11], the derived SSTI trench on the right is vertically aligned with an associated shallow STI insulation trench 14, with which it is materially continuous via a portion of the associated buried BOX oxide layer 24. This mutual alignment results from the alignment of the masks used to form these three respective elements, and gives a complex insulation structure (STLBOX-SSTI) in the form of a unitary SiO2 insulation trench.

[0080] Once the openings 400 and 700 are formed in the SSTI, the silicon (Si) of the support substrate 11 can be grown upwards, by epitaxial growth, in said openings 400 and 700, at least up to and including the level of the insulating material layer 24 (BOX). Access to the silicon (Si) of the substrate is thus achieved. carrier 11 without relaxing the stress of the film 23 of strained silicon (sSi) of the active areas 500 and 600 shown in [Fig.1 1].

[0081] More generally, if new trenches must be made on the surface of the microelectronic structure 3' to access the silicon of the carrier substrate 11, and knowing that this cannot be done by direct etching of the strained silicon (sSi) layer 23 without resulting in the loss of strain on said sSi film, then it can be done in an additional SSTI isolation trench 34 made as described above. Such etching in an SSTI trench does not, in fact, result in relaxing the sSi of the film 23, i.e., does not affect the strain on the sSi film 23.

[0082] This makes it possible, where appropriate, to fabricate NOSO (Not-On-SOI) type microelectronic devices in and / or on the substrate 11, which is a bulk substrate based on doped silicon, within these regions 400 and 700. Active components can thus be fabricated, for example using conventional CMOS technology on a bulk substrate, in active areas beneath the surface of the bulk substrate 11 shown, in region 400 or region 700, in addition to components, such as the transistor 601 shown, which can be fabricated in the active regions 500 and 600 using FD-SOI technology on a strained silicon film.

[0083] Another possibility offered by the silicon access zones 400 and 700 of the substrate 11 is, for example, to bias (via metallizations not shown) a cavity in the substrate 11 forming an active zone in which the source and drain of the transistor 601 are implemented. In [Fig. 11], this biasing via zone 400 is symbolized by arrow 401. Alternatively, the deep well between the shallow isolation trenches 14 (STI) can be biased via zone 700 of [Fig. 11], which is located on the opposite side of one of these trenches from the well in question. In [Fig. 11], this biasing via zone 700 is symbolized by arrow 701.

[0084] Specific embodiments have just been described. Various variations and modifications will be apparent to those skilled in the art. For example, the bulk substrate 11 of the support wafer 1 does not necessarily need to be doped. It can be an undoped silicon substrate if it is not necessary to fabricate components in this substrate, unlike the possibility described above with reference to regions 400 and 700.

Claims

Demands

1. A method for manufacturing a microelectronic device, said method comprising: • the supply of a first plate (1) comprising a sub trat support (11); • the formation, on the support substrate (11) of the first plate (1), of the first isolation trenches (14); • the supply of a second plate (2) comprising a donor subst rat (21-22); • the formation, on the donor substrate (21-22) of the second plate (2), of a constrained silicon film (23); • the bonding of the second plate (2) onto the first plate (1), so that the strained silicon film (23) is found on the first plate (1) by means of at least one layer of insulating material (24) formed, before the bonding, on the first plate (1) after the formation of the first trenches and / or on the second plate (2) after the formation of the strained silicon film (23); • dismantling the donor substrate (21-22) while retaining the insulating material layer (24) and the constrained silicon film (23) on the first plate (1); and, • the formation of secondary isolation trenches (34) around and / or along portions of the strained silicon film (23).

2. The method according to claim 1, wherein: • the first isolation trenches (14) formed in the substrate (11) of the first plate (1) are so-called "shallow trenches", or STI, the depth of which is greater than approximately 5 nm, or between approximately 5 nm and approximately 300 nm, preferably between approximately 50 nm and approximately 300 nm, and even more preferably between approximately 70 nm and approximately 300 nm; and / or • the second insulation trenches (34) have a depth equal to or greater than the thickness of the silicon film contra int (23), for example between about 10 nm and about 20 nm, for example on the order of 15 nm.

3. A method according to claim 1 or claim 2, wherein the insulating material of the first trenches (14), the insulating material of the second trenches (34) and / or the insulating material of the insulating layer (24), is silicon dioxide, SiO2.

4. A method according to any one of claims 1 to 3, wherein the formation of the first trenches (14) in the donor substrate (11) is carried out by etching through a first mask previously made by photolithography in a layer of hard material (13) such as a nitride, which covers the supplied support substrate via an associated layer of insulating material (12), residues of said first mask (13) and of said associated layer of insulating material (12) being removed from the support substrate (11) after the formation of said first trenches (14).

5. A method according to any one of claims 1 to 4, wherein it comprises the formation of third isolation trenches made through a second mask previously made by photolithography in a layer of hard material (33) such as a nitride, which is deposited over an associated layer of insulating material (32) itself deposited on the strained silicon layer (23) after dismantling the donor substrate, residues of said second mask (13) and of said associated layer of insulating material (12) being removed after the formation of said third trenches.

6. A method according to any one of claims 1 to 5, wherein the second insulation trenches (34) join the first trenches (14) via the insulating material layer (24) to form an insulation structure around and along the strained silicon film.

7. A method according to any one of claims 1 to 6, wherein the second trenches (34) are made by local oxidation of the silicon of the strained silicon film (23), for example the local oxidation of the silicon of the strained silicon film (23) is a thermal oxidation, for example a LOCOS type oxidation.

8. A method according to any one of claims 1 to 7, wherein the dismantling of the donor substrate (21-22) is carried out by grinding, by selective removals or by implantation fracture, for example by implementation of the Smart-cut® process.

9. A method according to any one of claims 1 to 8, wherein the donor substrate (21-23) of the second plate (2) comprises a silicon-germanium layer, Si-Ge, adapted to constrain the silicon of the constrained silicon film (23).

10. A method (1) according to any one of claims 1 to 9, wherein at least one opening (400) is made through the thickness of one of the second trenches (34) and through the insulating material layer (24) to expose the underlying support substrate (11), in an area of ​​said support substrate (11) in which there are no first trenches (14), and wherein, furthermore, the silicon (Si) of the support substrate (11) is grown upwards by epitaxial growth in the opening (400), at least up to and including the level of the insulating material layer (24).

11. A method according to any one of claims 1 to 10, wherein at least some of the second isolation trenches (34) have the same horizontal dimensions as associated first trenches (14), and are respectively aligned vertically with said associated first trenches (14).

12. Microelectronic structure obtained by implementing the manufacturing process according to any one of claims 1 to 11, said structure comprising active zones (100, 200, 300) separated on the surface of the same carrier substrate (11) and isolated from each other by deep and shallow isolation trenches (14-24-34), each active zone having a respective portion of constrained silicon film (23), and said portions of constrained silicon film resting on the same insulating layer (24) which is itself located above the carrier substrate (11).

13. Microelectronic structure according to claim 12, wherein the insulating material of the first trenches (14), the insulating material of the second trenches (34) and / or the insulating material of the insulating layer (24), is silicon dioxide, SiO2.

14. Microelectronic structure according to claim 12 or claim 13, wherein the second trenches (34) have non-vertical flanks.

15. Integrated circuit comprising the microelectronic structure according to any one of claims 12 to 14, and further comprising at least a MOS type field-effect transistor made in an active region (100,200,300) of said microstructure, the portion of which is constrained silicon film (23) serves as a totally depleted silicon substrate on insulator (FD-SOI) in which the channel of the MOS transistor is made.

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