Method of manufacturing an ultrasonic probe, and ultrasonic probe

Abstract

Method for manufacturing an ultrasonic probe, and ultrasonic probe The present description relates to a method for manufacturing an ultrasonic probe (200) comprising: - attaching a rear face of a chip (210) to an interconnection substrate (230) comprising first interconnection elements (232), the chip comprising a plurality of elementary chips each comprising a first pad (212) located on a first lateral edge on the front face (210A) of the chip, the first lateral edge having a common edge with a first lateral flank (210C) of the chip, and an ultrasonic transducer (340) comprising a first electrode (342) connected to the first pad; - forming a first dielectric layer (202A) to cover the first lateral flank; - forming a first metal portion on the first dielectric layer, the first pads and at least a portion of each of the first interconnection elements;then- cutting the chip so as to electrically separate the elementary chips, the cutting of the chip including the cutting of the first metal portion into a plurality of first metal tracks (241A) so that each elementary chip is electrically connected, via its first electrical connection pad, to one of the first interconnection elements by one of said first metal tracks. Figure for the abstract: Fig. 3A;

Description

Title of the invention: Method of manufacturing an ultrasonic probe f and ultrasound probe Technical field

[0001] The present description relates generally to the manufacture of ultrasonic probes, and aims in particular at the manufacture of small-sized ultrasonic probes.

[0002] An example of application relates to ultrasonic probes intended to be integrated into a catheter, for example for diagnostic or intravascular ultrasound treatment applications. Prior art

[0003] It has already been proposed to integrate small-sized ultrasonic probes into a catheter intended to be introduced into the body of a human or animal patient, for example for diagnostic applications or intravascular ultrasound treatment.

[0004] It would be desirable to have a method for manufacturing such a probe, this method at least partially overcoming some of the drawbacks of the known methods. Summary of the invention

[0005] One embodiment overcomes all or part of the drawbacks of known ultrasonic probes.

[0006] One embodiment provides a method of manufacturing an ultrasonic probe comprising the following steps: - attaching a rear face of a chip to a connection face of an interconnection substrate comprising first interconnection elements, the chip comprising a plurality of elementary chips each comprising a first electrical connection pad located on a first lateral edge on the front face of the chip, the first lateral edge having a common edge with a first lateral flank of the chip, and at least one ultrasonic transducer comprising a first electrode connected to the first electrical connection pad, each first interconnection element being adapted to be connected to the first electrical connection pad of one of the elementary chips; - forming a first layer of dielectric material so as to cover the first lateral side of the chip; - forming a first metallic portion on the first layer of dielectric material, the first electrical connection pads and at least one portion of each of the first interconnection elements, so as to electrically connect the first electrical connection pads and the first interconnection elements; then - cutting the chip to a given thickness so as to electrically separate the elementary chips, the cutting of said chip including the cutting of the first metal portion into a plurality of first metal tracks so that each elementary chip is electrically connected, via its first electrical connection pad, to one of the first interconnection elements by one of said first metal tracks.

[0007] According to embodiments: - the dielectric material of the first layer of dielectric material is a resin or a silicone; and / or - forming the first layer of dielectric material comprises a step of depositing a dielectric material and a step of curing the deposited dielectric material; and / or - the first layer of dielectric material does not extend onto the front face of the chip.

[0008] According to one embodiment, forming the first metal portion comprises: - forming a first mask on the chip and interconnection substrate assembly, the first mask being configured to mask the elementary chips with the exception of the first electrical connection pads which are left uncovered, and to leave each of the first interconnection elements at least partially uncovered; - depositing a first metal layer on the partially masked chip and interconnect substrate assembly; and - removing the first mask, the removal of the first mask also removing the portions of the first metal layer located on said first mask.

[0009] According to one embodiment, forming the first metal portion comprises a 3D printing step, for example by a metal binder jet technique.

[0010] According to embodiments, the cutting of the chip: - includes cutting of the first dielectric layer; and / or - includes a laser cutting step and / or a saw cutting step; and / or - excludes cutting of the interconnect substrate.

[0011] According to one embodiment, each elementary chip comprises a second electrode connected to a second electrical connection pad located on a second lateral edge on the front face of the chip, the second lateral edge having a common edge with a second lateral flank of the chip, and the interconnection substrate comprises second interconnection elements separate from the first interconnection elements, each second interconnection element being adapted to be connected to the second electrical connection pad of one of the elementary chips; the method further comprising: - forming a second layer of dielectric material so as to cover the second lateral side of the chip; - forming a second metal portion on the second layer of dielectric material, the second electrical connection pads and at least a portion of each of the second interconnection elements, so as to electrically connect the second electrical connection pads and the second interconnection elements; cutting the chip including cutting the second metal portion into a plurality of second metal tracks so that each elementary chip is electrically connected, via its second electrical connection pad, to one of the second interconnection elements by one of said second metal tracks.

[0012] According to embodiments: - the material of the second layer of dielectric material is a resin or a silicone; and / or - forming the second layer of dielectric material comprises a step of depositing a dielectric material and a step of curing the deposited dielectric material; and / or - the second layer of dielectric material does not extend onto the front face of the chip.

[0013] According to one embodiment, forming the second metal portion comprises: - depositing a second mask on the chip and interconnection substrate assembly, the second mask being configured to mask the elementary chips with the exception of the second electrical connection pads which are left uncovered and to leave each of the second interconnection elements at least partially uncovered; - depositing a second metal layer on the partially masked chip and interconnect substrate assembly; and - removing the second mask, the removal of the second mask also removing the portions of the second metal layer located on said second mask.

[0014] According to one embodiment, the first and second masks are the same mask, the first and second metal layers are the same metal layer, the first and second metal portions being produced simultaneously.

[0015] According to one embodiment, forming the second metal portion comprises a 3D printing step, for example by a metal binder jet technique.

[0016] According to embodiments, the cutting of the chip: - includes cutting of the second dielectric layer and / or - includes a laser cutting step and / or a saw cutting step; and / or - excludes cutting of the interconnect substrate.

[0017] According to one embodiment, the method further comprises a step of curving the interconnection substrate assembled to the elementary chips into a desired shape, for example a cylindrical shape.

[0018] One embodiment provides an ultrasonic probe comprising: - a chip comprising a plurality of elementary chips electrically separated from each other, each elementary chip comprising: a first electrical connection pad located on a first lateral edge on the front face of the chip, the first lateral edge having a common edge with a first lateral flank of the chip; and at least one ultrasonic transducer comprising a first electrode connected to the first electrical connection pad; - an interconnection substrate comprising a connection face on which a rear face of the chip, opposite the front face, is attached, the interconnection substrate comprising first interconnection elements; - a first layer of dielectric material covering the first lateral side of the chip; and - a plurality of first metal tracks on the first layer of dielectric material; each elementary chip being electrically connected, via its first electrical connection pad, to one of the first interconnection elements by one of said first metal tracks.

[0019] According to one embodiment, each elementary chip comprises a second electrode connected to a second electrical connection pad located on a second lateral edge on the front face of the chip, the second lateral edge having a common edge with a second lateral flank of the chip, and the interconnection substrate comprises second interconnection elements separate from the first interconnection elements, the probe further comprising: - a second layer of dielectric material covering the second lateral side of the chip; and - a plurality of second metal tracks on the second layer of dielectric material; each elementary chip being electrically connected, via its second electrical connection pad, to one of the second interconnection elements by one of said second metal tracks.

[0020] According to a particular embodiment, the first interconnection elements and the second interconnection elements are positioned laterally on either side of the chip.

[0021] According to one embodiment, each elementary chip comprises a second electrode connected to the rear face of the chip, itself connected to a metal plane or to a third electrical connection pad on the connection face of the interconnection substrate, the interconnection substrate further comprising second interconnection elements connected to said metal plane or to said third electrical connection pad, and separate from the first interconnection elements.

[0022] According to a particular embodiment, the first interconnection elements and the second interconnection elements are positioned laterally on the same side of the chip, for example alternating with each other.

[0023] According to a particular embodiment, the metal plane or the third electrical connection pad: - is disposed between the chip and the interconnect substrate and is connected to the rear face of the chip by an adhesive, for example a film or a glue, electrically conductive positioned between said metal plane or said third electrical connection pad and said rear face; or - is arranged near a lateral flank of the chip and is connected to the rear face of said chip by an adhesive, for example a glue, electrically conductive positioned between said lateral flank and said metal plane or said third electrical connection pad.

[0024] According to one embodiment, the interconnect substrate is flexible.

[0025] According to one embodiment, the ultrasonic transducers are transducers ultrasonic micromachined capacitive transducers, ultrasonic micromachined piezoelectric transducers or solid or composite piezoelectric transducers. Brief description of the drawings

[0026] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0027] [Fig.l] is a very schematic perspective view of an example of an ultrasonic probe;

[0028] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], [Fig.2F], [Fig.2G] and [Fig.2H] are perspective views illustrating successive steps of an example of a method of manufacturing an ultrasonic probe according to one embodiment;

[0029] [Fig.3A] is a sectional view showing details of the ultrasonic probe of [Fig.2H];

[0030] [Fig.3B] is a top view showing the ultrasonic probe of [Fig.3A];

[0031] [Fig.4A] is a sectional view showing details of an ultrasonic probe according to another embodiment;

[0032] [Fig.4B] is a top view showing the ultrasonic probe of [Fig.4A];

[0033] [Fig.5A] is a sectional view showing details of an ultrasonic probe according to another embodiment;

[0034] [Fig.5B] is a top view showing the ultrasonic probe of [Fig.5A];

[0035] [Fig.6] shows three examples of assembly of the monolithic chip to the substrate interconnection in an ultrasonic probe according to one embodiment; and

[0036] [Fig.7] is a sectional view showing an ultrasonic probe according to another embodiment. Description of the embodiments

[0037] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the production of the ultrasonic transducers of the described probes has not been detailed, the described embodiments being compatible with all or most of the known structures of ultrasonic transducers. Furthermore, the production of the control circuits of the ultrasonic transducers has not been detailed, the described embodiments being compatible with the usual control circuits of ultrasonic transducers or the production of the control circuits being within the scope of the person skilled in the art from the indications of the present description.

[0039] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0040] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0041] In the following description, when reference is made to conductive elements, unless otherwise specified, reference is made to electrically conductive elements.

[0042] In the following description, when reference is made to connection pads, respectively to interconnection elements, respectively to interconnection tracks, reference is made, unless otherwise specified, to connection pads. electrical, respectively to electrical interconnection elements, respectively to electrical interconnection tracks.

[0043] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0044] [Fig.l] is a very schematic perspective view of an example of an ultrasonic probe 100.

[0045] The ultrasonic probe 100 comprises a flexible interconnection substrate 101 on which are fixed a plurality of elementary chips 103 each comprising one or more ultrasonic transducers, not detailed in the figures. By way of example, each elementary chip 103 is an ultrasonic wave emission / reception chip, also called an "ultrasonic array", composed of one or more elementary ultrasonic transducers, for example aligned along an axis parallel to a longitudinal direction Z of the probe or arranged in a matrix on the plane of the array.

[0046] The flexible interconnection substrate 101 is wound around a cylinder (not visible in [Fig.l]), for example with a circular section, so as to obtain a probe of generally cylindrical shape, for example of small dimensions, for example with a diameter of between 1 and 5 millimeters (mm). The ultrasound probe 100 is for example intended to be integrated into a catheter. The elementary chips form facets adapted to emit ultrasound towards the outside of the cylindrical probe, in radial directions. In this example, the elementary chips have the shape of parallel rectangular strips, extending parallel to the longitudinal direction Z of the probe. By way of example, the probe comprises at least two, preferably at least four, preferably at least eight, elementary chips 103, for example regularly distributed around the interconnection substrate wound in the form of a cylinder.

[0047] Each elementary chip comprises electrical connection pads (not visible in [Fig.l]) connected to corresponding electrical connection elements (not visible in [Fig.l]) of the interconnection substrate 101.

[0048] The interconnection substrate 101 is for example a flexible printed circuit, comprising electrically conductive interconnection elements, for example interconnection tracks formed on a flexible dielectric support, for example made of a polymer material, for example a polyimide. The interconnection tracks may be metal tracks, for example made of copper. One or more electrically conductive wires, not detailed in [Fig.l], may electrically connect the interconnection substrate 101 to electronic circuits external to the probe, for example to control the elementary chips 103.

[0049] To produce such a probe, one possibility consists of fixing and electrically connecting to a connection face of the interconnection substrate 101, a single monolithic chip comprising all of the ultrasonic transducers of the probe, then cutting the chip into a plurality of elementary chips 103 each comprising one or more ultrasonic transducers. At the end of the cutting step, each elementary chip 103 remains fixed and electrically connected to the interconnection substrate 101. The interconnection substrate 101 can then be wound around a cylinder or another element adapted to give a desired shape to the probe.

[0050] The electrical connection between the monolithic chip and the interconnection substrate 101 can be made by means of conductive wires connecting the connection face of the interconnection substrate to the front face of the chip, opposite the interconnection substrate. An encapsulating resin, for example an epoxy resin, can be provided to protect the conductive wires. This protection is known as "glob-top" in English. This method of connection by conductive wires, also called "wire bonding" in English, however has certain drawbacks.In particular, the conductive wires and, where appropriate, the encapsulation resin, lead to an increase in the diameter of the probe. In addition, there is a risk of damaging the conductive wires during the step of cutting the monolithic chip into elementary chips 103. .

[0051] Alternatively, the monolithic chip and the interconnection substrate 101 can be assembled by a method called surface mounting ("flip chip" in English). In this case, the chip comprises electrical connection pads on its rear face, that is to say its face opposite the face for transmitting / receiving the ultrasonic waves. These pads are positioned directly on and in contact with corresponding electrical connection pads located on the connection face of the interconnection substrate 101. Thus, the size is reduced compared to a connection by conductive wires, and the risks of damaging the electrical connections during the step of cutting the monolithic chip are reduced.However, a disadvantage of this solution is that the manufacturing cost of the monolithic transducer chip is relatively high, due to the need to integrate conductive vias crossing the chip substrate to connect the ultrasonic transducers to the electrical connection pads on the back of the chip. This is particularly true in the case of transducers using MEMS (Micro Electro Mechanical System) technology.

[0052] Furthermore, the elementary chips can be very thin, for example have a width of the order of 100 micrometers (pm), and the pitch between two elementary chips can also be of this order of magnitude, or even less, the electrical connection having to connect each of these elementary chips to the interconnection substrate. In other words, the electrical connection must be compatible with the width of the elementary chips, as well as with the pitch between two elementary chips. The electrical connection must also be compatible with a possible winding of the interconnection substrate once assembled to the elementary chips, for example to form a cylindrical ultrasound probe.

[0053] Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G and 2H are perspective views illustrating successive steps of an example of a method for manufacturing an ultrasonic probe according to one embodiment.

[0054] For example, the ultrasonic probe may be configured to transmit and receive ultrasonic waves over a wide frequency band having a center frequency between 20 and 60 MHz.

[0055] [Fig.2A] illustrates a starting structure, in the form of a monolithic chip 210.

[0056] The monolithic chip 210 comprises several elementary chips 211, each elementary chip 211 being an ultrasonic wave emission / reception chip, also called an "ultrasonic array", or "array". Each array may comprise one or more ultrasonic transducers. For example, as shown, the elementary chips 211 are in a plane parallel to the plane of the monolithic chip 210 but extend longitudinally perpendicular to the longitudinal direction of the monolithic chip 210.

[0057] The transducers (not detailed in FIGS. 2A to 2H) are, for example, CMUT type transducers (from the English "capacitive micromachined ultrasonic transducers", or capacitive micromachined ultrasonic transducers, or capacitive membrane transducers), or PMUT type transducers (from the English "piezoelectric micromachined ultrasonic transducers", or piezoelectric micromachined ultrasonic transducers, or piezoelectric membrane transducers), or even solid or composite piezoelectric elements.

[0058] An ultrasonic transducer generally comprises two electrodes, a first electrode, for example an upper electrode, and a second electrode, for example a lower electrode. As described in more detail later, in a CMUT, an upper electrode is generally connected to, for example assembled on, a deformable membrane forming a cavity with a lower electrode. In a PMUT, a lower electrode attached to a deformable membrane is generally suspended above a cavity and an upper electrode is separated from the lower electrode by a layer of piezoelectric material.

[0059] The embodiments described are however not limited to these particular cases and apply more generally to all types of ultrasonic transducers, the location of the electrodes being able to depend on the type of transducers implemented. The production of the monolithic chip 210 has not been detailed, the embodiments described being compatible with all or most of the known methods of manufacturing an ultrasonic transducer chip, or the production of such a chip being within the reach of the person skilled in the art from the indications of the present des- description.

[0060] The monolithic chip 210 has, for example, a parallelepiped shape. For example, the monolithic chip 210 has a length of between 8 and 15 mm. For example, the monolithic chip 210 has a thickness equal to approximately 100 μm. For example, the monolithic chip 210 comprises approximately 80 strips.

[0061] The monolithic chip 210 comprises a substrate 214 which may be made of silicon (Si).

[0062] The monolithic chip 210 comprises a front face 210A corresponding to the face for transmitting / receiving ultrasonic waves, and a rear face 210B opposite its front face.

[0063] The monolithic chip 210 comprises connection pads 212, 212' (first connection pads) on its front face side, which are intended to be connected on the one hand to an electrode (first electrode) and on the other hand to a pad or a track, more generally to an interconnection element, of an interconnection substrate (described later). There is for example a connection pad 212 at one end of each elementary chip 211, and a connection pad 212' at another end of the same elementary chip 211, the connection pads 212, 212' of the same elementary chip 211 being for example substantially equipotential.

[0064] The first connection pads 212 of two different elementary chips 211 are preferably insulated from each other. The first connection pads 212' of two different elementary chips 211 are preferably insulated from each other.

[0065] According to a variant, there are first connection pads 212 only at one end of the elementary chips 211. Moreover, the first connection pads 212' located at the other end of the elementary chips 211 are not used in the method described in relation to FIGS. 2A to 2H.

[0066] The first connection pad 212 of an elementary chip 211 can be connected to at least one first electrode, for example an upper electrode, of this elementary chip.

[0067] The first connection pads 212 may be dedicated to the transmission of an electrical signal, without this being limiting.

[0068] The monolithic chip 210 shown in [Fig.2A] comprises two lateral portions 220, 220' in the form of lateral bars, one on each of the two lateral flanks 210C, 210D (references visible in [Fig.2C]) of the monolithic chip 210. Each lateral portion, or bar, 220, 220' comprises on the front face a plurality of connection pads 221, 221' (second connection pads). The second connection pads 221, 221' are preferably electrically insulated from the first connection pads 212, 212'.

[0069] The second connection pads 221 of two different elementary chips 211 are preferably insulated from each other. The second connection pads 221' of two 211 different elementary chips are preferably isolated from each other.

[0070] There is for example a second connection pad 221 at one end of each elementary chip 211, and a second connection pad 221' at another end of the same elementary chip 211, the connection pads 221, 221' being for example substantially equipotential.

[0071] [Fig.2B] illustrates a structure obtained after removing a side bar 220' from among the two side bars 220, 220', so that the first connection pads 212 are positioned on a first side edge on the front face 210A of the monolithic chip 210. This step of removing the side bar can be carried out by cutting.

[0072] Each second connection pad 221 of the side bar 220 which has not been removed is, for example, connected to at least one second electrode, for example a lower electrode, of this elementary chip. The second connection pad 221 can be connected on the other hand to a pad or a track, more generally to an interconnection element, of an interconnection substrate (described later).

[0073] The second connection pads 221 are positioned on a second lateral edge on the front face 210A of the monolithic chip, opposite the first lateral edge on which the first connection pads 212 are positioned.

[0074] The second connection pads 221 may be dedicated to grounding, without this being limiting.

[0075] Alternatively, the starting structure may be a monolithic chip having a single sidebar on only one of its sides, or even a monolithic chip without sidebars. According to this alternative, the step of removing a sidebar is not necessary and may be omitted. Thus, a starting structure may be a monolithic chip with first connection pads on a first side edge on the front face of the monolithic chip, and possibly, but not necessarily, second connection pads on a second side edge on the front face of the monolithic chip.

[0076] Other means of connecting a second electrode, for example a lower electrode, of each elementary chip to the interconnection substrate are described later.

[0077] [Fig.2C] illustrates a structure obtained at the end of a step of assembling the monolithic chip 210, on the side of its rear face 210B, on a connection face 230A of a flexible interconnection substrate 230.

[0078] At this stage of the method, the interconnection substrate 230 is substantially flat, for example unrolled. The interconnection substrate 230 may be positioned on a flat support, not shown.

[0079] Similar to the interconnection substrate 101 of [Fig.l], the substrate interconnection 230 of [Fig.2C] is, for example, a flexible printed circuit.

[0080] The interconnection substrate 230 comprises a front face (connection face) 230A intended to be assembled to the monolithic chip 210, and a rear face 230B opposite its front face.

[0081] The interconnection substrate 230 shown comprises on its connection face 230A first and second electrically conductive interconnection elements 232, 233, shown in the form of interconnection tracks, formed on a flexible dielectric support 231. The interconnection tracks 232, 233 may extend parallel to the longitudinal direction Z of the elementary chips 211. The interconnection tracks 232, 233 are for example metallic, for example made of copper. The flexible dielectric support 231 is for example made of a polymer material, such as a polyimide.

[0082] Alternatively, although this is not shown, the first interconnection tracks, and / or the second interconnection tracks may be positioned on the rear face 230B of the interconnection substrate 230, i.e. on the rear face of the flexible dielectric support 231. In this case, in general, at least interconnection tracks, or portions of interconnection tracks, are kept on the front face 230A of the interconnection substrate 230. For example, each interconnection track or portion of interconnection track on the front face of the interconnection substrate extends onto the rear face of the interconnection substrate by means of a conductive via.

[0083] Alternatively, the interconnection substrate may be a multilayer substrate, such as a multilayer flex, and extend interconnection tracks arranged on the front face of the interconnection substrate on several planes, or levels, separated by a dielectric layer, an interconnection track of one level being able to be connected to another interconnection track of another level by a conductive via.

[0084] The first interconnection elements 232 are intended to be connected to the first connection pads 212 and the second interconnection elements 233 are intended to be connected to the second connection pads 221.

[0085] In some cases, the first interconnection elements 232 are disjointed from one another, and the second interconnection elements 233 are also disjointed from one another so as to connect each elementary chip individually. In other cases, the first interconnection elements 232 or the second interconnection elements 233 are connected to one another and for example to the same electrical potential. Preferably, the first interconnection elements 232 are disjointed from the second interconnection elements 233, so as to avoid short circuits between them, for example between the ground and the electrical signal of each elementary chip. In the example shown, the first interconnection elements 232 are close of a first lateral flank 210C of the monolithic chip 210, while the second interconnection elements 233 are close to a second lateral flank 210D of the monolithic chip opposite the first lateral flank 210C. The first lateral flank 210C is connected to the first lateral edge (common edge) on which there are the first connection pads 212 on the front face 210A, and the second lateral flank 210D is connected to the second lateral edge (common edge) on which there are the second connection pads 221 on the front face 210A.

[0086] For example, the first and second interconnection elements 232, 233 are not present on a portion 230C of the interconnection substrate 230 covered by the monolithic chip 210.

[0087] The interconnection tracks 232, 233 may be connected to another flex, to a rigid printed circuit, to a cable harness, or any other element making it possible to connect the electrodes of the transducers to electronic circuits external or internal to the ultrasound probe. One or more electrically conductive wires, not detailed in [Fig.2C], may electrically connect the interconnection substrate 230, for example to control the elementary chips 211.

[0088] The interconnect substrate 230 may be assembled to the monolithic die 210 using an adhesive film, such as a die attach film, known by the acronym DAF, for "Die Attach Film" in English. The adhesive film may be conductive or insulating. The interconnect substrate 230 may also be assembled to the monolithic die 210 using an adhesive, for example a conductive adhesive.

[0089] [Fig.2D] illustrates a structure obtained after forming a layer of dielectric material 202A, 202B (dielectric layer) against each lateral flank 210C, 210D of the monolithic chip 210 of [Fig.2C]: a first dielectric layer 202A against the first lateral flank 210C and a second dielectric layer 202B against the second lateral flank 210D. The dielectric layers 202A, 202B also cover portions of the interconnect substrate 230 located around the lateral flanks 210C, 210D of the monolithic chip. The dielectric layers 202A, 202B form, for example, strips of dielectric material covering the lateral flanks of the monolithic chip.

[0090] The dielectric material may be a resin, for example an epoxy resin, or a silicone, or any other material suitable for polymerization and hardening. The formation of the dielectric layers 202A, 202B may be carried out using a "dispenser", for example a syringe, suitable for depositing the dielectric material in a calibrated manner, and which is moved along the lateral flank to carry out the deposition over the entire flank. Alternatively, the formation of the dielectric layers 202A, 202B may be carried out by PVD deposition (from the English "physical vapor deposition"). These examples of materials, as well as this deposition method, are not limiting. Alternatively, the dielectric layer may be formed by a 3D printing technique, using any suitable dielectric material.

[0091] The dielectric layers 202A, 202B do not extend onto the front face 210A of the monolithic chip 210 and thus do not cover the first and second connection pads 212, 221, and are adapted to leave at least a portion of each of the first and second interconnection elements 232, 233 uncovered, so that the first and second interconnection elements 232, 233 can be connected respectively to the first connection pads 212 and to the second connection pads 221.

[0092] The dielectric layers 202A, 202B also make it possible to expose non-vertical faces to the metallization step described below. In addition, the dielectric layers 202A, 202B make it possible, by properly covering the sides 210C, 210D of the monolithic chip 210, to avoid a short circuit between electrodes of the same elementary chip 211, for example when one of the electrodes of an elementary chip is connected to the substrate 214.

[0093] [Fig.2E] illustrates a structure obtained after depositing a mask 203 on the structure of [Fig.2D].

[0094] The mask 203 is configured to hide the areas that must not be metallized in the following step, for example to avoid short circuits, in particular the active areas, the transducers of the elementary chips 211, and the connection pads 212' when there are any. An active area of ​​an elementary chip is an area from, respectively towards, which the ultrasonic waves are emitted, respectively received. The mask 203 is also configured to leave uncovered the first electrical connection pads 212 and the second connection pads 221, the dielectric layers 202A, 202B, as well as a portion of each of the first and second interconnection elements 232, 233.

[0095] The mask thus makes it possible to precisely make the electrical connection of the first and second interconnection elements 232, 233 with respectively the first connection pads 212 and the second connection pads 221 by the metal layer described below.

[0096] The mask 203 is for example an adhesive, a resin obtained by photolithography, or any other material suitable for forming a mask.

[0097] [Fig.2F] illustrates a structure obtained after the formation of a metal layer 204 on the structure of [Fig.2E], in particular on the mask 203, the first connection pads 212, the second connection pads 221, the dielectric layers 202A, 202B, as well as on the uncovered portions of the first and second interconnection elements 232, 233.

[0098] The metal layer 204 may comprise a stack of layers, for example a primer layer on which a metallization layer is positioned. The primer layer, optional, may comprise titanium (Ti), chromium (Cr). The primer layer, optional, may have a thickness of approximately 10 nanometers (nm). The metallization layer may comprise gold (Au), copper (Cu), or aluminum (Al). The metallization layer may have a thickness of between approximately 100 and 200 nm.

[0099] The formation of the metal layer 204 can be carried out by PVD deposition.

[0100] Alternatively, the metal layer may be formed by a 3D printing technique, for example a metal binder jetting technique. In this case, the metal layer may be deposited locally, more precisely than by PVD, in order to make the electrical connection of the first and second interconnection elements 232, 233 with the first connection pads 212 and the second connection pads 221 respectively, without connecting the connection pads 212' when they are present, and without covering the transducers of the elementary chips 211. The step of depositing the mask may then be omitted, as well as the step of removing the mask described below.

[0101] [Fig.2G] illustrates a structure obtained at the end of a step of removing the mask 203.

[0102] By removing the mask 203, the portions of metal layer located on this mask are also removed, by a technique called "lift-off" in English. The portions of the metal layer 204 which are not removed form two metal strips, or portions, covering the dielectric layers 202A, 202B. A first metal strip 240A (first metal portion) covering the first dielectric layer 202A provides an electrical connection between the first connection pads 212 and the first interconnection elements 232, and a second metal strip 240B (second metal portion) covering the second dielectric layer 202B provides an electrical connection between the second connection pads 221 and the second interconnection elements 233.

[0103] [Fig.2H] illustrates an ultrasonic probe 200 obtained at the end of a step of cutting the monolithic chip 210 over a given thickness so as to single out the elementary chips 211, the cutting step including the cutting of the first and second metal strips 240A, 240B into a plurality of respectively first and second metal tracks 241A, 241B. Preferably, the dielectric support 231 of the interconnection substrate 230 is not cut over its entire thickness in order to maintain mechanical strength of the assembly. However, the cutting may include a thickness of this support 231. The precision of the cutting method generally makes it possible to obtain this. This cutting step generally comprises several cuts, each made between two elementary chips elements in a direction parallel to the longitudinal direction of the elementary chips, in the example in a direction perpendicular to the longitudinal direction of the monolithic chip.

[0104] For example, each elementary chip 211 can then be connected: - to a signal pad via one of the first interconnection elements 232, one of the first metal tracks 241A and the first connection pad 212 of said elementary chip; and - to ground via one of the second interconnection elements 233, one of the second metal tracks 241B and the second connection pad 221 of said elementary chip.

[0105] The cutting can be carried out by any method of cutting a chip into a plurality of elementary chips, for example using a saw or by laser cutting.

[0106] The step of cutting the monolithic chip 210 can be carried out over a minimum thickness to distinguish the electrical connections of each elementary chip. In certain cases, for example to facilitate the winding of the interconnection substrate 230 once assembled with the elementary chips 211, it is possible to leave an uncut chip thickness which makes it possible to maintain the rigidity of the assembly and this uncut thickness can then break at the time of winding. In other cases, the monolithic chip 210 can be cut over its entire thickness.

[0107] At the end of the cutting step, the interconnection substrate 230 can in fact be wound around an axis to form a cylindrical probe of the type described in relation to [Fig.l]. The winding axis, corresponding to the longitudinal direction of the final cylindrical ultrasonic probe, can be substantially parallel to the longitudinal direction Z of the elementary chips 211. More generally, the interconnection substrate 230 assembled to the elementary chips 211 can be curved into a desired shape.

[0108] Alternatively, the interconnection substrate 230 can be kept substantially flat. According to this alternative, the cutting of the monolithic chip 210 can be carried out over the minimum thickness to single out the electrical connections of each elementary chip.

[0109] [Fig.3A] is a sectional view showing details of the ultrasonic probe 200 of [Fig.2H]. [Fig.3B] is a top view showing the ultrasonic probe 200 of [Fig.3A]. The ultrasonic probe shown comprises several elementary chips 211 and each elementary chip comprises several ultrasonic transducers 340. This is not limiting and an elementary chip could only comprise one transducer.

[0110] The ultrasonic transducers shown in Figures 3A and 3B are trans CMUT type transducers, or capacitive membrane transducers. Each transducer 340 comprises a cavity 341, a first electrode 342, or upper electrode, surmounting the cavity 341, and a second electrode 343, or lower electrode, arranged under the cavity 341. An insulating layer 344, for example made of silicon dioxide SiO2, forming the membrane of the transducers 340, is positioned between the cavities 341 and the upper electrodes 342. The upper electrodes 342 of the transducers of the same elementary chip 211 are connected to each other by a conductive track 302.

[0111] Each elementary chip 211 further comprises a first connection pad 212 connected to the conductive track 302, and thus to the upper electrodes 342, of this elementary chip, and a second connection pad 221 connected to the lower electrode 343.

[0112] In the example shown, the lower electrode 343 is formed by metallization of a portion located under the cavities 341 of the substrate 214 of the monolithic chip 210. The contact resumption of the lower electrode 343 with the second connection pad 221 can be formed by a conductive via 306 passing through the insulating layer 344 as well as the substrate 214 over a partial thickness. This example can be applied for an undoped silicon substrate, that is to say a little or no conductive one. This example is not limiting and other variants will appear to those skilled in the art.According to a variant, when the substrate is conductive, for example when it is made of doped silicon, the metallization can be omitted, and the lower electrode can be formed by a portion of the conductive substrate 214, the resumption of contact of the lower electrode with the second connection pad 221 being ensured by the conductive via 306 then passing through the insulating layer 344 to the substrate 214.

[0113] The dielectric layers 202A, 202B in the form of strips are formed on each of the two lateral flanks 210C, 210D of the elementary chips 211. The interconnection substrate 230 comprises the flexible dielectric support 231 surmounted by the first interconnection elements 232 and the second interconnection elements 233. The first interconnection elements 232 are connected to the first connection pads 212 by the first metal tracks 241A electrically insulated from the first lateral flank 210C by the first dielectric layer 202A, and the second interconnection elements 233 are connected to the second connection pads 221 by the second metal tracks 241B electrically insulated from the second lateral flank 210D by the second dielectric layer 202B.

[0114] The transducers of Figures 3A and 3B could be adapted by a person skilled in the art to form PMUT type transducers, or piezoelectric membrane transducers.

[0115] The method of manufacturing an ultrasonic probe described in connection with FIGS. 2A to 2H can be implemented to make the electrical connections of the electrodes. upper electrodes, for example to transmit an electrical signal, and lower electrodes, for example to be grounded. Alternatively, the method of manufacturing an ultrasonic probe can be applied only for the electrical connections of the upper electrodes or only for the electrical connections of the lower electrodes.

[0116] In the implementation example described in relation to FIGS. 2A to 2H, 3A and 3B, electrical connections have been described only on the front face of the monolithic chip (i.e. on the front face of the elementary chips), which is not limiting.

[0117] Alternatively, it is possible to provide electrical connections on both sides, front side and rear side, of the monolithic chip, i.e. on the front and rear sides of the elementary chips. For example, the electrical connections for the electrical signal can be made on the front side, and the ground connections on the rear side, provided that the manufacturing method is adapted. Examples of such variants are described in the following figures.

[0118] [Fig.4A] is a sectional view showing details of an ultrasonic probe 400 according to another embodiment. [Fig.4B] is a top view showing the ultrasonic probe 400 of [Fig.4A]. The elementary chips 411 shown each comprise several ultrasonic transducers 440. This is not limiting and an elementary chip could comprise only one transducer. The ultrasonic transducers 440 shown in FIGS. 4A and 4B are CMUT type transducers similar to those described in relation to FIGS. 3A and 3B, except that the lower electrodes 443 are not formed by metallization, but are formed by a portion of the substrate 414 of the monolithic chip which is then a conductive substrate.

[0119] Thus, the ultrasonic probe 400 of FIGS. 4A and 4B differs from that of FIGS. 3A and 3B mainly in that the lower electrodes 443 of the elementary chips 411 are formed in portions (in dotted lines) of the conductive substrate 414, and in that the lower electrodes 443 are connected to the second interconnection elements 433 on the rear face of the elementary chips 411, by conductive vias 406 (in dotted lines) formed in other portions of the conductive substrate 414, as well as by a metal plane 434, for example made of copper, formed on the connection face 430A of the interconnection substrate 430. Instead of a single metal plane, it could be a question of several third connection pads, each third connection pad being connected to a lower electrode for example by means of a conductive via similar to the conductive via 406.

[0120] Instead of extending on either side of the elementary chips 411, the first interconnection elements 432, connected to the first connection pads 212, and the second interconnection elements 433, connected to the metal plane 434, can extend from the same lateral flank 21 OC (first lateral flank) of the elementary chips 411. The first interconnection elements 432 and the second interconnection elements 433 can be arranged alternately with each other, being isolated from each other, as illustrated in [Fig.4B]. In this embodiment, a single dielectric layer 202A is sufficient to isolate the first lateral flank 210C, and the first metal tracks 241A (coming from the first cut metal strip 240A) connect the first connection pads 212 to the first interconnection elements 432. There is no second dielectric layer, nor second metal tracks, since the connections of the lower electrodes to the second interconnection elements are made on the rear face of the monolithic chip, that is to say on the rear face of the elementary chips.

[0121] In the examples described in relation to FIGS. 3A, 3B, 4A and 4B, each upper electrode 342 has been described with a surface area substantially equal to the surface area of ​​the cavity 341 that it surmounts. This is not limiting and each upper electrode 342 may for example have a surface area smaller than the surface area of ​​the cavity 341 that it surmounts.

[0122] [Fig.5A] is a sectional view showing details of an ultrasonic probe 500 according to another embodiment. [Fig.5B] is a top view showing the ultrasonic probe of [Fig.5A].

[0123] The ultrasonic probe 500 of FIGS. 5A and 5B differs from that of FIGS. 4A and 4B mainly in that each elementary chip 511 comprises a transducer 540 comprising a layer of solid or composite piezoelectric material. The interconnect substrate of FIGS. 5A and 5B may be similar to the interconnect substrate 430 of FIGS. 4A and 4B. Although this is not shown, the transducer generally comprises other layers in addition to the layer of piezoelectric material, for example an acoustic adaptation layer, or blade, on the front face and an absorbent layer, or backing, on the rear face.

[0124] The substrate 514 of the monolithic chip, and therefore of the elementary chips 511, is made of a piezoelectric material. The substrate 514 is metallized, partially or totally, on its front and rear faces to form respectively the upper electrodes 542 and the lower electrodes 543 of the elementary chips 511. The upper electrode 542 of each elementary chip 511 is connected to the first connection pad 212 of the chip, itself connected to the first interconnection elements 432 via the first metal tracks 241 A. The lower electrode 543 of each elementary chip 511 is connected to the metal plane 434 of the interconnection substrate 430, and the metal plane 434 is connected to the second interconnection elements 433. Instead of a single metal plane, it could be a question of several third connection pads, each third connection pad being connected to a lower electrode.

[0125] The method described in connection with Figures 2A to 2H can be adapted to produce the probes described in connection with Figures 4A, 4B, 5A, 5B. The method can in particular be adapted to connect only the first connection pads 212 to the first interconnection elements 432 via the first metal tracks 241A insulated from the first lateral flank 210C by the first dielectric layer 202A. There are no second connection pads on the front face of the monolithic chip, no second dielectric layer, and no second metal portion or second metal tracks, since the connections of the lower electrodes to the second interconnection elements are made on the rear face of the monolithic chip, that is to say on the rear face of the elementary chips.

[0126] [Fig.6] represents three examples of assembly of the monolithic chip to the interconnect substrate in an ultrasonic probe according to one embodiment.

[0127] In the examples shown in Figures 4A, 4B, 5A, 5B, the monolithic chip can be assembled to the interconnection substrate 430, in particular to the metal plane 434 of the interconnection substrate, by an electrically conductive adhesive 402, for example an anisotropic conductive adhesive, as seen in [Fig.4A].

[0128] This is also shown in [Fig.6] (A), where a conductive adhesive 602 is seen in the form of a conductive film between the monolithic chip, for example the lower electrode 543 of [Fig.5A], and the metal plane 434 of the interconnect substrate 430.

[0129] In [Fig.6] (B), a conductive glue 604 is introduced between the monolithic chip, for example the lower electrode 543 of [Fig.5A], and the metal plane 434 of the interconnect substrate 430.

[0130] In [Fig.6] (C), a conductive glue 606 is introduced into the lower part of a lateral flank of the monolithic chip, for example in an embodiment where the metal plane 434 of the interconnection substrate 430 is not positioned under the monolithic chip but next to said lateral flank, for example to connect the lower electrode 543 of [Fig.5A] to the metal plane 434. The conductive glue 606 can be spread between the monolithic chip and the interconnection substrate 430.

[0131] [Fig.7] is a sectional view showing a detail of an ultrasonic probe 700 according to another embodiment.

[0132] The ultrasonic probe 700 of [Fig. 7] differs from the probes previously described in that it further comprises an insulating layer 702 on the elementary chips and a shielding metallization layer 704 on the insulating layer 702. The insulating layer 702 is made of a dielectric material which further allows the propagation of the ultrasonic waves which pass through it, for example silicone. The metallization layer 704 can be connected to ground via an interconnection element or a ground plane of the interconnection substrate 430, preferably different from the interconnection elements or the ground plane provided for connecting the electrodes in- lower than the elementary chips to the ground.

[0133] The probe 200 of FIGS. 3A and 3B is shown under the silicone layer 702, but this could be the probe 400 of FIGS. 4A and 4B, the probe 500 of FIGS. 5A and 5B or any other ultrasonic probe according to one embodiment.

[0134] The ultrasonic probes previously described, more generally the probes according to the embodiments, may be intended to be integrated into a catheter, for example for diagnostic or intravascular ultrasound treatment applications.

[0135] Other applications can be envisaged, for example curved external ultrasound probes, or probes whose transducer surface is conformable (ultrasound patch).

[0136] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0137] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing an ultrasonic probe (200; 400; 500) comprising the following steps: - attaching a rear face (210B) of a chip (210) to a connection face (230A; 430A) of an interconnection substrate (230; 430) comprising first interconnection elements (232; 432), the chip comprising a plurality of elementary chips (211; 411; 511) each comprising a first electrical connection pad (212) located on a first lateral edge on the front face (210A) of the chip, the first lateral edge having a common edge with a first lateral flank (210C) of the chip, and at least one ultrasonic transducer (340; 440; 540) comprising a first electrode (342; 542) connected to the first electrical connection pad, each first interconnection element being adapted to be connected to the first electrical connection pad of one of the elementary chips; - forming a first layer of dielectric material (202A) so as to cover the first lateral flank (210C) of the chip; - forming a first metal portion (240A) on the first layer of dielectric material (202A), the first electrical connection pads (212) and at least a portion of each of the first interconnection elements (232), so as to electrically connect the first electrical connection pads (212) and the first interconnection elements (232); then - cutting the chip (210) to a given thickness so as to electrically separate the elementary chips, the cutting of said chip including the cutting of the first metal portion (240A) into a plurality of first metal tracks (241A) so that each elementary chip is electrically connected, via its first electrical connection pad, to one of the first interconnection elements (232) by one of said first metal tracks.

2. A method according to claim 1, wherein: - the dielectric material of the first dielectric material layer (202A) is a resin or a silicone; and / or - forming the first layer of dielectric material (202A) comprises a step of depositing a dielectric material and a step of curing the deposited dielectric material; and / or - the first layer of dielectric material (202A) does not extend over the front face (21 OA) of the chip (210).

3. Method according to claim 1 or 2, wherein: - forming the first metal portion (240A) comprises: forming a first mask (203) on the chip (210) and interconnection substrate (230) assembly, the first mask being configured to mask the elementary chips (211) with the exception of the first electrical connection pads (212) which are left uncovered, and to leave at least partially uncovered each of the first interconnection elements (232); depositing a first metal layer (204) on the partially masked chip and interconnection substrate assembly; and removing the first mask, the removal of the first mask also removing the portions of the first metal layer located on said first mask; and / or - forming the first metal portion (240A) comprises a 3D printing step, for example by a metal binder jet technique.

4. Method according to any one of claims 1 to 3, wherein the cutting of the chip (210): - includes the cutting of the first dielectric layer (202A); and / or - comprises a laser cutting step and / or a saw cutting step; and / or - excludes the cutting of the interconnect substrate (230; 430).

5. Method according to any one of claims 1 to 4, in which each elementary chip (211) comprises a second electrode (343) connected to a second electrical connection pad (221) located on a second lateral edge on the front face (210A) of the chip (210), the second lateral edge having a common edge with a second lateral flank (210D) of the chip, and the interconnection substrate (230) comprises second interconnection elements (233) separate from the first interconnection elements (232), each second interconnection element being adapted to be connected to the second electrical connection pad of one of the elementary chips; the method further comprising: - forming a second layer of dielectric material (202B) so as to cover the second lateral flank (210D) of the chip; - forming a second metal portion (240B) on the second layer of dielectric material (202B), the second electrical connection pads (221) and at least a portion of each of the second interconnection elements (233), so as to electrically connect the second electrical connection pads (221) and the second interconnection elements (233); the cutting of the chip including the cutting of the second metal portion (240B) into a plurality of second metal tracks (241B) so that each elementary chip is electrically connected, via its second electrical connection pad, to one of the second interconnection elements (232) by one of said second metal tracks.

6. Method according to claim 5, wherein: - the dielectric material of the second layer of dielectric material (202B) is a resin or a silicone; and / or - forming the second layer of dielectric material (202B) comprises a step of depositing a dielectric material and a step of curing the deposited dielectric material; and / or - the second layer of dielectric material (202B) does not extend onto the front face (210A) of the chip (210).

7. Method according to claim 5 or 6, wherein: - forming the second metal portion (240B) comprises: depositing a second mask (203) on the chip (210) and interconnection substrate (230) assembly, the second mask being configured to mask the elementary chips (211) with the exception of the second electrical connection pads (221) which are left uncovered and to leave at least partially uncovered each of the second interconnection elements (233); depositing a second metal layer (204) on the partially masked chip and interconnection substrate assembly; and removing the second mask, the removal of the second mask also removing the portions of the second metal layer located on said second mask; and / or - forming the second metal portion (240B) comprises a 3D printing step, for example by a metal binder jet technique.

8. A method according to claim 7, wherein the first and second masks are the same mask, the first and second metal layers are the same metal layer, the first and second metal portions being produced simultaneously.

9. Method according to any one of claims 5 to 8, wherein the cutting of the chip (210): - includes the cutting of the second dielectric layer (202B); and / or - comprises a laser cutting step and / or a saw cutting step; and / or - excludes the cutting of the interconnect substrate (230; 430).

10. Method according to any one of claims 1 to 9, further comprising a step of curving the interconnection substrate assembled to the elementary chips into a desired shape, for example a cylindrical shape.

11. An ultrasonic probe (200; 400; 500) comprising: - a chip (210) comprising a plurality of elementary chips (211; 411; 511) electrically separated from one another, each elementary chip comprising: a first electrical connection pad (212) located on a first lateral edge on the front face (210A) of the chip, the first lateral edge having a common edge with a first lateral flank (210C) of the chip; and at least one ultrasonic transducer (340; 440; 540) comprising a first electrode (342; 542) connected to the first electrical connection pad; - an interconnection substrate (230; 430) comprising a connection face (230A; 430A) on which a rear face (210B) of the chip, opposite the front face (210A), is attached, the interconnection substrate comprising first interconnection elements (232; 432); - a first layer of dielectric material (202A) covering the first lateral flank (210C) of the chip;and - a plurality of first metal tracks (241A) on the first layer of dielectric material; each elementary chip being electrically connected, via its first electrical connection pad (212), to one of the first interconnection elements (232) by one of said first metal tracks.;

12. Ultrasonic probe (200) according to claim 11, in which each elementary chip (211) comprises a second electrode (343) connected to a second electrical connection pad (221) located on a second lateral edge on the front face (210A) of the chip (210), the second lateral edge having a common edge with a second lateral flank (210D) of the chip, and the interconnection substrate (230) comprises second interconnection elements (233) separate from the first interconnection elements (232), the probe further comprising: - a second layer of dielectric material (202B) covering the second lateral flank (210D) of the chip; and - a plurality of second metal tracks (241B) on the second layer of dielectric material; each elementary chip being electrically connected, via its second electrical connection pad, to one of the second interconnection elements (232) by one of said second metal tracks.

13. A method according to any one of claims 5 to 9, or an ultrasonic probe according to claim 12, wherein the first interconnection elements (232) and the second interconnection elements (233) are positioned laterally on either side of the chip (210).

14. Method according to any one of claims 1 to 4, or ultrasonic probe according to claim 11, in which each elementary chip (411; 511) comprises a second electrode (443; 543) connected to the rear face (210B) of the chip (210), itself connected to a metal plane (434) or to a third electrical connection pad on the connection face (430A) of the interconnection substrate (430), the interconnection substrate further comprising second interconnection elements (433) connected to said metal plane or to said third electrical connection pad, and separate from the first interconnection elements (432).

15. A method according to claim 14, or an ultrasonic probe according to claim 14, wherein the first interconnection elements (432) and the second interconnection elements (433) are positioned laterally on the same side of the chip, for example alternating with each other.

16. Method according to claim 14 or 15, or ultrasonic probe according to claim 14 or 15, wherein the metal plane (434) or the third electrical connection pad: - is arranged between the chip (210) and the interconnect substrate (430) and is connected to the rear face of the chip by an electrically conductive adhesive (402; 602; 604), for example a film or a glue, positioned between said metal plane or said third electrical connection pad and said rear face; or - is arranged near a lateral flank of the chip (210) and is connected to the rear face back of said chip by an adhesive (606), for example a glue, electrically conductive positioned between said lateral flank and said metal plane or said third electrical connection pad.

17. An ultrasonic probe according to any one of claims 11 to 16, or a method of manufacture according to any one of claims 1 to 10, 13 to 16, wherein: - the interconnection substrate (230; 430) is flexible; and / or - ultrasonic transducers are ultrasonic micromachined capacitive transducers, ultrasonic micromachined piezoelectric transducers or solid or composite piezoelectric transducers.

Images