NFC controller

Abstract

NFC Controller The present description relates to an NFC controller (140) configured to switch from active load modulation to passive load modulation at least when a received signal strength indicator (RSSI) becomes greater than a first RSSI threshold. Figure for abstract: Fig. 2

Description

Title of the invention: NFC controller Technical field

[0001] The present description relates generally to NFC (Near Field Communication) controllers and their operating methods. Prior art

[0002] NFC devices are used worldwide. Therefore, they must comply with various standards and usage situations. Summary of the invention

[0003] There is a need to provide NFC devices comprising NFC controllers that comply with as many international standards and usage situations as possible.

[0004] One embodiment overcomes all or part of the drawbacks of known NFC controllers.

[0005] One embodiment provides an NFC controller configured to switch from active load modulation to passive load modulation at least when a received signal strength indicator becomes greater than a first RSSI threshold.

[0006] One embodiment provides an NFC controller configured to switch from active charging modulation to passive charging modulation at least when a battery power level is below a first power threshold or when an NFC charging session begins.

[0007] One embodiment provides a method of operating an NFC controller, comprising the step of switching from an active charging modulation to a passive charging modulation at least when a power level of the battery is below a first power threshold or when an NFC charging session begins.

[0008] According to one embodiment, the controller switches from passive load modulation to active load modulation when a received signal strength indicator becomes greater than a first RSSI threshold.

[0009] According to one embodiment, the controller switches from active load modulation to passive load modulation when the received signal strength indicator becomes lower than a second RSSI threshold, the first RSSI threshold being higher than the second threshold.

[0010] According to one embodiment, the controller switches from passive load modulation to active load modulation when the battery power level is greater than a second power threshold.

[0011] According to one embodiment, the first and second RSSI thresholds are based on the modulation type.

[0012] According to one embodiment, the switch is performed when the controller is in card emulation mode.

[0013] According to one embodiment, the received signal power indicator is filtered or averaged.

[0014] According to one embodiment, the controller comprises at least one resistive circuit and, during passive modulation of the load, said resistive circuit is configured to adopt a first or a second resistance value based on a level of a load modulation signal.

[0015] According to one embodiment, the controller comprises at least one radio frequency driver and, during passive modulation of the load, said radio frequency driver is configured to adopt a third or a fourth resistance value based on the level of the load modulation signal.

[0016] According to one embodiment, said at least one resistive circuit has a plurality of first branches in parallel, each connecting a ground to the same first node, each of the first branches comprising a first switch and a resistor; and - said at least one radiofrequency pilot comprising a plurality of second branches connecting the ground to a reference voltage rail, each of the second branches comprising: an NMOS transistor and a PMOS transistor in series, a conduction node of said NMOS transistor being connected to ground and a conduction node of said PMOS transistor being connected to the reference voltage rail, a conduction node common to said NMOS transistor and said PMOS transistor being connected to a second node; a second switch configured to connect, in a first state, a control node of said PMOS transistor to the reference voltage rail and, in a second state, the control node of said PMOS and NMOS transistors to the same third node; and a third switch configured to connect, in a first state, a control node of said NMOS transistor to ground and, in a second state, the control node of said PMOS and NMOS transistors to the third node, the first state of the second and third switches occurring simultaneously, and the second state of the second and third switches occurring simultaneously.

[0017] According to one embodiment, the first and second resistance values ​​correspond respectively to a first number of first switches of the first branches being in a conductive state and to a second number of first switches of the first branches being in a conductive state; the first switches of the resistive circuit being controlled based on the level of the load modulation signal, a first level of the load modulation signal corresponding to said first number and a second level of the load modulation signal corresponding to said second number.

[0018] According to one embodiment, the third and fourth resistance values ​​correspond respectively to third and fourth numbers of the second or third switches of the second branches which are in the first state, the first level of the load modulation signal corresponding to said third number and the second level of the load modulation signal corresponding to said fourth number.

[0019] According to one embodiment, during active load modulation, the resistive circuit is configured to adopt, based on a level of a damping signal: a fifth resistor value adapted to lower a quality factor of an antenna coupled to the controller: and a sixth resistance value adapted to increase said quality factor; said fifth and sixth resistance values ​​corresponding to a respective fifth and sixth number of first switches of the first branches which are in a conductive state.

[0020] According to one embodiment, the controller comprises a first logic unit configured to execute, during active modulation of the load, a logic AND function from an NFC carrier signal and the load modulation signal, to generate a control signal on the third node.

[0021] According to one embodiment, the load modulation signal is a Manchester-coded subcarrier of the NFC carrier signal.

[0022] According to one embodiment, the NMOS or PMOS transistors of the second branches are weighted in binary fashion from one second branch to the other and the resistances of the first branches are weighted in binary fashion from one first branch to the other.

[0023] According to one embodiment, the first, second, third, fourth, fifth and sixth numbers are encoded in one or more registers of a non-volatile memory.

[0024] According to one embodiment, the controller comprises a first and a second of said at least one resistive circuit, and a first and a second of said at least one radiofrequency driver; the controller comprising a second logic unit configured to execute, during active load modulation, a logic AND function from the signal inverted NFC carrier and the load modulation signal, to generate an inverted control signal on the third node connected to the second radio frequency driver.

[0025] One embodiment provides an NFC device comprising: - the NFC controller as described above; - an antenna; and - an adaptation circuit coupling the controller to the antenna.

[0026] According to one embodiment, the adaptation circuit comprises: - a first and a second input node connected respectively to the first and second resistive circuits of the controller; - a third and a fourth input node connected respectively to the first and second radiofrequency circuits of the controller; - a first and a second output node connected to the antenna; - a first and a second capacitance respectively coupling the first input node to the first output node and the second input node to the second output node; - a third capacitance coupling the first output node to the second output node; - a resistor connecting the first output node to the second output node; - a first and a second inductance respectively coupling the first radiofrequency driver to a fourth node and the second radiofrequency driver to a fifth node; - a fourth and a fifth capacitance respectively coupling the fourth node and the fifth node to ground; - a sixth and a seventh capacity respectively coupling the fourth node to the first output node and the fifth node to the second output node. Brief description of the drawings

[0027] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0028] [Fig.l] represents a very schematic view of an NFC system to which the embodiments apply;

[0029] [Fig.2] schematically represents circuits of the NFC system according to one embodiment;

[0030] [Fig.3] schematically represents circuits of the NFC system according to a mode of realization ;

[0031] [Fig.4] schematically represents a circuit of [Fig.2] according to one embodiment;

[0032] [Fig.5] schematically represents a circuit of [Fig.3] according to one embodiment;

[0033] [Fig.6] is a timing diagram of the operation of the circuits of [Fig.3];

[0034] [Fig.7] is another operating timing diagram of a circuit of [Fig.3]; and

[0035] [Fig.8] is another operating timing diagram of a circuit of [Fig.3]. Description of the embodiments

[0036] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0038] Unless otherwise specified, when referring to two elements connected between them, it means directly connected without intermediate elements other than conductors, and when we refer to two elements connected (in English "coupled") between them, it means that these two elements can be connected or be linked by means of one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0040] Unless otherwise specified, the expressions "approximately", "approximately", "substantially" and "in the order of" mean within 10%, preferably within 5%.

[0041] [Fig.l] represents a very schematic view of an NFC system 100.

[0042] The NFC system 100 includes a first NFC device 110 that can communicate with a second NFC device 160.

[0043] NFC systems or, in other words, near field communication systems use a radiofrequency electromagnetic field generated by the second device (terminal or reader) 160 to communicate with the other device (card) 110. The same device can, in particular in the case of mobile phones, operate in reader mode by generating a field intended for another device, or in card mode by capturing a field generated by another device. This technology concerns the establishment of very short distance communications (less than ten centimeters) between two devices.

[0044] This NFC technology also allows an NFC device to recharge one or more other NFC devices placed nearby.

[0045] In the present description, the case of a system in which the NFC devices are compatible with NFC technology in accordance with the NFC Forum is considered.

[0046] In the example of [Fig.l], the NFC device 110 comprises a matching circuit 130 (MATCHING CIRCUIT) coupling an antenna 120 (ANTENNA) to an NFC controller 140 (NFC CONTROLLER).

[0047] The NFC controller 140 is for example further connected to a memory 150 (MEM), for example a non-volatile memory, via a communication bus 142. The memory comprises for example registers for storing the configurations of the NFC controller 140.

[0048] The NFC device 110 is for example a telephone or a smart phone, smartphone, emulated in card mode or a card with a battery 170 connected to the NFC controller 140.

[0049] In one example, the NFC device 110 is compatible with the ISO 14443A / B and / or FeliCA standard also known as JIS.X.6319-4.

[0050] This makes it possible to exchange information between the contactless reader and secure elements located in the NFC device 110, for example. Many applications are thus possible, such as mobile ticketing for public transport (the mobile phone serving as a transport ticket) or mobile payment (the mobile phone serving as a payment card).

[0051] During a transmission of information between a reader 160 and an object in card - or tag - emulation mode, the reader generates a magnetic field via its antenna, which is generally a sine wave at 13.56 MHz in the standards used conventionally.

[0052] Two operating modes are possible, a passive modulation mode or an active modulation mode. In the passive mode, only the reader generates the magnetic field and the object 110, in card (or tag) emulation mode, is then passive and serves as a target.

[0053] More precisely, the antenna 120 emulating the ticket or the card modulates the field generated by the reader 160.

[0054] This modulation is carried out by modifying the load connected to the terminals of the antenna 120 of the first NFC device 110.

[0055] By modifying the load at the terminals of the antenna 120, the output impedance of the antenna of the reader 160 changes due to the magnetic coupling between the two antennas. This results in a modification of the amplitudes and / or phases of the voltages and currents present in the antennas of the reader and the object.

[0056] Thus, in this way, the information to be transmitted from the object to the reader is transmitted, by charge modulation, to the antenna currents of the reader.

[0057] The load variation performed in the load modulation is reflected in an amplitude modulation and / or a phase modulation of the signal (voltage or current) at the reader antenna. A copy of the antenna current is generated and injected into the reader's reception chain, where this current is demodulated and processed to extract the transmitted information.

[0058] In the active modulation mode of operation, the reader 160 and the first NFC device 110 in card emulation mode both generate an electromagnetic field. In general, this mode of operation is used when the NFC device 110 has its own power source, for example the battery 170, as is the case for a cellular mobile phone, which is then in card emulation mode.

[0059] Each of the NFC devices transmits data using a modulation scheme, for example an OOK (On-Off-keying) amplitude modulation scheme.

[0060] In this case, the modulation results in a modification of the load, and reference is then made to communication by active load modulation.

[0061] Compared to passive load modulation, greater operating distances are obtained, which can be up to 10 cm depending on the protocol used.

[0062] In addition, the use of active load modulation allows the use of small antennas. However, this type of communication by active load modulation has other disadvantages.

[0063] It is desirable, during communication by active load modulation, that the signal transmitted by the device in card emulation mode is in phase, or in phase opposition, with the signal received from the reader and that it has, at the reader and therefore also at the device in card emulation mode, a modulation amplitude as large as possible in terms of absolute value. Phase adjustment is generally necessary on the device in card emulation mode during development of the device in a known environment, which is not always feasible.

[0064] Additionally, in active load modulation, calibration is required to synchronize the card emulator's local oscillator with the reader's signal. This process requires several milliseconds to be accurate enough to meet the phase drift requirements of ISO 144443, for example.

[0065] However, in the transportation field, the object in card emulation mode must be able to operate with older readers with limited performance, such as those with only envelope detection reception architecture, different from dual-channel architectures. In addition, many readers used for access control in several countries do not comply with all the specifications of the ISO 144443 standard and the start-up time in these cases can be reduced to 30 ps and allow the first commands for example 177 ps after the start of their radio frequency magnetic field.

[0066] An example of envelope detector readers are readers that can implement the Felica protocol. It has been found that the distance between such envelope detector readers and the object in card emulation mode influences the coupling effect, especially when this distance is small, for example less than 50 mm, which causes a lag in the reader-object system and therefore introduces a phase shift between the signal received by the reader and the signal transmitted by the object or vice versa. This phase shift can be in either direction depending on the usage situation and becomes significant enough to be incompatible with some standards.

[0067] It is therefore necessary to find a solution to overcome this phase shift when the distances between the reader 160 and the device in emulated card mode 110 become less than 50 mm.

[0068] Furthermore, active modulation requires power supplied by battery 170, which may cause operational problems in the event of low battery level.

[0069] The described embodiments provide an NFC controller 140 configured to switch from active charging modulation to passive charging modulation at least when the battery power level is below a first power threshold or when an NFC charging session begins.

[0070] In one example, the NFC controller switches from passive load modulation to active load modulation when the battery power level is above a second power threshold.

[0071] These embodiments allow a basic operating state of the device 110 to be maintained even if the battery is low. In addition, they allow a depleted battery to be charged by forcing passive charging modulation to a low battery level and triggering an NFC wireless charging session.

[0072] Other embodiments provide that the controller switches from passive load modulation to active load modulation when the received signal strength indicator (RSSI) becomes greater than a first RSSI threshold or that the controller switches from active load modulation to passive load modulation when the received signal strength indicator becomes less than a second RSSI threshold, the first RSSI threshold being higher than the second threshold.

[0073] The received signal strength indicator is used here to roughly assess the distance between the reader and the NFC device 110, and determine when a phase shift might occur due to close coupling. Passive load modulation has a much shorter response time than active load modulation, which improves interoperability and performance by shortening the response time and preventing phase degradation in the case of tight coupling. It also creates hysteresis to prevent spurious switching between passive load modulation and active modulation mode due to variations in the received signal strength indicator around the first or second RSSI threshold.

[0074] In one example, the first and second RSSI thresholds are based on the modulation type.

[0075] In another example, the switch is performed when the controller is in card emulation mode.

[0076] In another case, the received signal strength indicator is filtered or averaged. This avoids spurious switching between passive load modulation and active modulation mode due to variations in the received signal strength indicator.

[0077] [Fig. 2] schematically represents circuits of the NFC system 100 according to one embodiment. More specifically, [Fig. 2] represents the NFC controller 140, the adaptation circuit 130 and the antenna 120 of the NFC device 110. The NFC controller 140 shown allows alternating between passive load modulation and active load modulation.

[0078] In the antenna shown, the antenna 120 couples an Ant1 node to an Ant2 node.

[0079] In the example shown, the matching circuit 130 comprises two input nodes NRF01, NRF02, a first capacitor Cp coupling the first output node Ant1 to the second output node Ant2; and a resistor Rp connecting the first output node Ant1 to the second output node Ant2. In the matching circuit 130 shown, a first and a second inductance Lem11, Lem12 respectively couple the node NRF01 to a node Nm4 and the node NRF02 to a node Nm5; a second and a third capacitor Cem11, Cem12 respectively couple the nodes Nm4 and Nm5 to ground. In addition, a fourth and a fifth capacitor Cs1, Cs2 respectively couple the node Nm4 to the first output node Ant1 and the node Nm5 to the second output node Ant2. Additionally, a capacitance Crfil and a resistor Rrfil are connected in series between a node RFI1 and the first output node Antl.Another capacitance Crfi2 and another resistor Rrfi2 are connected in series between a node RFI2 and the second output node Ant2. The nodes RFI1 and RFI2 are configured to receive, in card emulation mode, the signal sent by the reader via the antenna 120 and, in reader mode, the charge modulation signal generated by the contactless tag or card coupled to the antenna 120.

[0080] The NFC controller 140 also includes two radio frequency drivers 220,222.

[0081] The load modulation signal is for example a Manchester-coded subcarrier of the NFC frequency 13.56 MHz.

[0082] In the example shown, the radiofrequency driver 220 connects a node NCTRL_SEL1 to the node NRF01 of the adaptation circuit 130 and the radiofrequency driver 222 connects a node NCTRL_SEL2 to the node NRF02 of the adaptation circuit 130.

[0083] The radiofrequency drivers 220, 222 are further configured to receive n adjustment signals ENn, the load modulation signal, a selection signal SEL, and respectively a first and a second control signal CTRL, CTRL / . The first and second control signals CTRL, CTRL / are configured to be sent respectively to the node NCTRL_SEL1 and to the node NCTRL_SEL2. The selection signal SEL is also configured to be sent to the node NCTRL_SEL1 and to the node NCTRL_SEL2. The selection signal SEL and the n adjustment signals ENn are for example emitted by a control unit 260 (Control Unit) of the NFC controller.

[0084] In the example shown, the NFC controller comprises a first and a second logic unit 250, 252 configured to execute, during the active load modulation, respectively: a logic AND function from an NFC carrier signal and the load modulation signal to generate the first control signal CTRL on the node NCTRL_SEL1; and a logic AND function from the inverted NFC carrier signal (i.e. shifted by 180°) and the load modulation signal, to generate the second control signal CTRL / on the node NCTRL_SEL2.

[0085] During passive load modulation, the radio frequency drivers 220, 222 are configured to adopt a third or a fourth resistance value based on the level of the load modulation signal. The n adjustment signals ENn as well as the selection signal SEL set the third and fourth values. The n adjustment signals ENn and the selection signal are for example based on instruction bits which are stored, by means of registers, in the memory 150. When the load modulation signal corresponds to an uncharged state, the radio frequency drivers 220, 222 are set to the third resistance value and, when the load modulation signal corresponds to a charged state, the radio frequency drivers 220, 222 are set to the fourth resistance value. The fourth resistance value is for example less than one Ohm and the third value is set to a high impedance.

[0086] During active load modulation, the radio frequency drivers 220,222 have an on-resistance value that is based on the signals ENn. The signal on the nodes NRF01 or NRF02 is alternately raised to a voltage of VDD reference, also called VDDRF, then pulled down to ground according to the respective CTRL or CTRL / control signals.

[0087] [Fig. 3] schematically represents circuits of the NFC system 100 according to one embodiment

[0088] The example of [Fig.3] includes the circuit of [Fig.2] to which components are added.

[0089] In the example shown, the adaptation circuit 130 comprises other input nodes CDMP1, CDMP2 and a first and a second capacitor Ccdmpl, Ccdmp2 respectively coupling the node CDMP1 to the first output node Ant1 and the input node CDMP2 to the second output node Ant2. The NFC controller 140 also comprises two resistive circuits 210, 212 (RCDMP1, RCDMP2) connecting the ground respectively to the node CDMP1 and to the node CDMP2.

[0090] The resistive circuits 210, 212 are configured to each receive a resistor configuration signal (EN_CDMP), a load modulation signal (Load_modulation_signal) and a damping control signal (Damping_control). First and second resistance values ​​of the resistive circuits 210, 212 are for example defined by the resistor configuration signals (EN_CDMP). The first and second resistance values ​​are for example encoded and stored, by means of registers, in the memory 150.

[0091] In one example, during passive load modulation, the resistance value of the resistive circuits 210,212 switches between the first and second resistance values ​​depending on the level of the load modulation signal. The second resistance value is for example less than one Ohm and the first value is set to a high impedance. In one example, when the load modulation signal corresponds to an unloaded state, the resistive circuits 210,212 are set to the first resistance value and, when the load modulation signal corresponds to a loaded state, the resistive circuits 210,212 are set to the second resistance value.

[0092] In another example, during active load modulation, the resistance value of the resistive circuits 210, 212 switches between a fifth and a sixth resistance value (equal to or different from the first and second resistance values) depending on the damping control signal. In this example, the fifth resistance value is for example set high enough to decrease the quality factor of the antenna 120 and therefore damp an active load modulation signal allowing the resynchronization of an internal phase-locked loop with the signal from the reader 160. The sixth resistance value is for example low enough to guarantee a high quality factor of the antenna 120 during resynchronization with the player signal and transmission of active load modulation.

[0093] The example of [Fig.3] provides an additional means of achieving passive load modulation either by switching between two predefined resistance values ​​of the drivers 220,222, as in [Fig.2], and / or by switching between two predefined resistance values ​​of the resistive circuits 210,212.

[0094] [Fig.4] schematically represents a circuit of [Fig.2] or 3 according to one embodiment. More specifically, [Fig.4] represents examples of radiofrequency drivers 220,222.

[0095] The radiofrequency drivers 220,222 of [Fig.3] comprise for example N (N being an integer) branches 312...312n connecting the ground to a reference voltage rail VDD.

[0096] Each of the branches 312...312n comprises an NMOS transistor Nl...Nn and a PMOS transistor Pl...Pn in series. A conduction node of the NMOS transistor is connected to ground and a conduction node of the PMOS transistor is connected to the voltage rail VDD. A conduction node NCl...NCn, which is common to the NMOS transistor and the PMOS transistor of the respective branch, is connected to the node NRFO1 (respectively NRF02 for the second radio frequency driver 222). In one example, the PMOS and NMOS transistors have a different size from one branch to another. For example, their on-state resistance is weighted binary, that is to say it is twice as high as that of the previous branch.

[0097] Each of the branches 312...312n further comprises a switch 302...302n and another switch 304...304n.

[0098] The switch 302...302n, of each respective branch, connects, in a first state, the control node of the PMOS transistor Pl...Pn to the voltage rail VDD and, in a second state, the control node of the PMOS and NMOS transistors Nl...Nn to the node NCTRL_SEL1 (respectively NCTRL_SEL2 for the radiofrequency driver 222).

[0099] The switch 304...304n, of each respective branch, connects, in a first state, the control node of the NMOS transistor to ground and, in a second state, the control node of the PMOS and NMOS transistors to the node NCTRL_SEL1 (respectively NCTRL_SEL2). In one example, the first state of the switches 302...302n and the switches 304...304n occurs simultaneously and the second state of the switches 302...302n and another switch 304...304n occurs simultaneously. The first and second states are controlled by the respective signals ENl...ENn.

[0100] During passive load modulation, the SEL selection signal is connected to the control nodes of the NMOS and PMOS transistors of all branches 312...312n. If the SEL signal is similar to VDD (or VDDRF), then the impedance of the PMOS transistors is high and the NMOS transistors are turned on, i.e., they are in a conductive state. The NMOS transistors are therefore selected. If the SEL signal is similar to ground, the PMOS transistors are selected. In other words, the SEL signal selects either the NMOS lines or the PMOS lines. The SEL signal depends, for example, on a bit stored in the memory 150. On the other hand, when the signals Enl...ENn set the switches 302...302n and 304...304n to their first state, they block the transistors PL..Pin and Nl...Nln, i.e., they deactivate the respective branch, which becomes non-conductive. The signals Enl...ENn select which of the branches 312...312n are selected. Depending on the number of branches selected, the resistance of the radio frequency drivers 220,222 can be changed.The first and second resistors can thus be predefined and coded on N bits (for example N=8 bits). In one example, the code OxFF means that the branches are conducting which would correspond to the charged state and the code 0x00 means that all the branches are disconnected which places the radiofrequency drivers 220,222 in a high impedance state which would correspond to the discharged state. The configuration bits corresponding to the given resistors are for example stored in the memory 150. The person skilled in the art can choose other codes to implement other resistance values ​​for the charged and uncharged states of the charge modulation signal.

[0101] During active load modulation, the branches of the drivers 220, 222 are made up of push-pull stages (e.g., eight stages if N=8). Each push-pull stage is the pair of PMOS and NMOS transistors Pl...Pn, Nl...Nln of the same branch which alternately raise the output on the node NRF01 (respectively NRF02) to the potential VDD (VDDRF) and lower it to the ground potential. The signals ENl...ENn activate the push-pull stage which is optionally controlled by the signal CTRL (respectively CTRL / ). The deactivated push-pull stages are high impedance. The quiescent state of the signals CTRL and CTRL / can adopt three configurable configurations. They can be both high, both low, or one high and the other low.

[0102] [Fig.5] schematically represents a circuit of [Fig.3] according to one embodiment. More specifically, [Fig.5] represents one embodiment of the resistive circuits 210, 212.

[0103] In the example shown, the resistive circuits 210, 212 have N branches 412...412n in parallel, each connecting the ground to the node CDMP1 (respectively CDMP2).

[0104] Each branch 412...412n comprises a switch 424...424n and a resistor 404...404n ​​which has for example a binary weighted resistance value different from one branch to another. The switches 424...424n are for example transistors.

[0105] In active modulation, the switches 424...424n are selectively activated, following a damping signal (Damping_control), to define at least two resistance values, for example coded on N bits. Depending on which of the switches 424...424n are in the on state (depending on the value of the Nth bit), the resistance of the resistive circuit is low or, on the contrary, high impedance. The resistance obtained is called damping resistance and is used to reduce the quality factor of the antenna 120 and therefore damp an active load modulation signal allowing the resynchronization of an internal phase-locked loop with the signal from the reader 160.

[0106] During passive load modulation, at least two resistors are for example predefined by the resistor configuration signals EN_CDMP. The load modulation signal is used to switch between at least two of the predefined resistance values ​​coded on N bits. For example, if the code is 0x3FF, all branches 412...412n are in a conductive state, which leads to a resistance value of the resistive circuit for example as low as 0.3 Ohms used during the loaded (i.e. modulated) state of the load modulation signal. If the code is 0x000, all branches 412...412n are in a non-conductive state, which leads to a high impedance used during the unloaded (i.e. unmodulated) state of the load modulation signal. The person skilled in the art can choose which switches to select to obtain different resistance values.

[0107] [Fig.6] is a timing diagram of the operation of the circuits of [Fig.3]. More specifically, [Fig.6] represents the charge modulation signal as a function of time during the emulation of a contactless card compliant with the ISO14443-A protocol at the basic rate of 106 kbps.

[0108] In the example shown, between a time t1 and a time t2, then between a time t3 and a time t4, the load modulation signal, which is a Manchester-coded subcarrier of the NFC signal, has two times four pulses between a low state and a high state. The high state corresponds to a loaded state (or modulated state) and the low state corresponds to an unloaded state (or unmodulated state). During this loaded state, a predefined resistance of the resistive circuits 210, 212 or the radio frequency drivers 220, 222 is set and, during the unloaded state, another predefined resistance value is set. This makes it possible to perform passive load modulation using the same resistive circuits and radio frequency drivers as for active load modulation.

[0109] [Fig.7] is another operating timing diagram of a circuit of [Fig.3]. More precisely, [Fig.7] represents the load modulation signal as a function of time as well as the CTRL signal.

[0110] In the example shown, the load modulation signal is similar to that of [Fig. 6]. The CTRL signal is pulsed at the carrier frequency of 13.56 MHz (shown in the shaded area) during the load modulation signal pulses, and is disabled otherwise. The push-pull stages of the radio frequency drivers 220,222 are enabled when the CTRL signal is high to achieve active load modulation.

[0111] [Fig.8] is another operating timing diagram of a circuit of [Fig.3]. More specifically, the example of [Fig.7] represents, during active load modulation, the signal from reader 160 (line 1), the envelope of the signal from reader line 1 (line 2), the signal between nodes NRF01 and NRF02 (line 3), the signal between nodes Ant1 and Ant2 (line 4), the damping signal (line 5) and a phase-locked loop signal.

[0112] Before a time fl, the signal from the reader starts to be detected and the signals of lines 3, 4, 5 are at a low level, only the signal from the phase-locked loop is at a high level.

[0113] At a time fl, the signal between the nodes NRF01 and NRF02 oscillates at the carrier frequency for the duration of a pulse of the load modulation signal in order to obtain a modulation on the reader signal until a time f 2. This modulation signal is present on the antenna output nodes Antl, Ant2 with an increasing amplitude shape until time f2.

[0114] When the signal between nodes NRF01 and NRF02 is stopped at time f2, the damping control signal pulse is activated, which increases the decay rate of the output signal at the antenna outputs. Without the use of the damping control signal, the decay would take longer, as shown by the dotted lines.

[0115] As soon as the damping control signal pulse is terminated, the phase-locked loop signal is brought back to a high level until a modulation signal is again activated at a high level at a time f 3. The process described from time fl to time f 3 is then repeated for each modulation. In the example shown, seven subcarrier modulation periods are applied.

[0116] Other aspects of the present disclosure are summarized below.

[0117] According to an example 1 of a first aspect, an NFC controller 140 is configured to switch from active load modulation to passive load modulation when a battery power level is below a first power threshold or when an NFC charging session begins.

[0118] According to an example 2 of the first aspect, a method of operating an NFC controller (140) comprises the step of switching from active charging modulation to passive charging modulation at least when a power level of the battery is below a first power threshold or when an NFC charging session begins.

[0119] Example 3: The NFC controller of Example 1 or the method according to Example 2, wherein the controller (140) switches from passive load modulation to active load modulation when a received signal strength indicator (RSSI) becomes greater than a first RSSI threshold.

[0120] Example 4: The NFC controller or method according to Example 3, wherein the controller switches from active load modulation to passive load modulation when the received signal strength indicator becomes lower than a second RSSI threshold, the first RSSI threshold being higher than the second threshold.

[0121] Example 5: The NFC controller according to any one of Examples 1, 3 or 4, or the method according to any one of Examples 2 to 4, wherein the controller switches from passive load modulation to active load modulation when the battery power level is above a second power threshold.

[0122] Example 6: The NFC controller or method according to any of examples 4 or 5, wherein the first and second RSSI thresholds are based on the modulation type.

[0123] Example 7: The NFC controller according to any one of Examples 1 or 3 to 6, or the method according to any one of Examples 2 to 6, wherein the switch is performed when the controller is in card emulation mode.

[0124] Example 8: The controller or method according to any one of Examples 3, or 4 to 7 in their dependence on Example 3, in which the received signal strength indicator is filtered or averaged.

[0125] Example 9: The controller according to any one of Examples 1 or 3 to 8, or the method according to any one of Examples 2 to 8, wherein the controller (140) comprises at least one radio frequency driver (220,222) and, during passive load modulation, said radio frequency driver is configured to adopt a third or a fourth resistance value based on a level of the load modulation signal.

[0126] Example 10: The controller or method according to example 9, wherein the controller (140) comprises at least one resistive circuit (210,212) and, during passive load modulation, said resistive circuit is configured to adopt a first or a second resistance value based on the level of the load modulation signal (Load_modulation_signal).

[0127] Example 11: The controller or method according to example 10, wherein said at least one resistive circuit (210) has a plurality of first branches (412...412n) in parallel, each connecting the ground (GND) to a same first node (CDMP1), each of the first branches comprising a first switch (424...424n) and a resistor (404...404n); and - said at least one radiofrequency pilot (220,222) comprising a plurality of second branches (312...312n) connecting the ground to a reference voltage rail (VDD,VDDRF), each of the second branches comprising: an NMOS transistor and a PMOS transistor (Pl...Pn,Nl...Nn) in series, a conduction node of said NMOS transistor being connected to ground and a conduction node of said PMOS transistor being connected to the reference voltage rail, a conduction node common to said NMOS transistor and said PMOS transistor being connected to a second node (NRF01,NRF02); a second switch (302...302n) configured to connect, in a first state, a control node of said PMOS transistor to the reference voltage rail (VDD) and, in a second state, the control node of said PMOS and NMOS transistors to the same third node (NCTRL_SEL1); and a third switch (304...304n) configured to connect, in a first state, a control node of said NMOS transistor to ground and, in a second state, the control node of said PMOS and NMOS transistors to the third node (NCTRL_SEL1), the first state of the second and third switches occurring simultaneously, and the second state of the second and third switches occurring simultaneously.

[0128] Example 12: The controller or method according to Example 11, wherein the first and second resistance values ​​respectively correspond to a first number of first switches (424...424n) of the first branches (412...412n) being in a conductive state and to a second number of first switches of the first branches being in a conductive state; the first switches of the resistive circuit being controlled on the basis of the level of the load modulation signal, a first level of the load modulation signal corresponding to said first number and a second level of the load modulation signal corresponding to said second number.

[0129] Example 13: The controller or method according to any one of Examples 10 to 12, wherein the third and fourth resistance values ​​correspond respectively to the third and fourth numbers of the second or third switches of the second branches which are in the first state, the first level of the load modulation signal corresponding to said third number and the second level of the load modulation signal corresponding to said fourth number.

[0130] Example 14: The controller or method according to any one of Examples 9 to 13, wherein, during active load modulation, the resistive circuit is configured to adopt, based on a level of a damping signal (Damping_control): a fifth resistance value adapted to lower the quality factor of an antenna (120) coupled to the controller; and a sixth resistance value adapted to increase said quality factor; said fifth and sixth resistance values ​​corresponding to a respective fifth and sixth number of first switches (424...424n) of the first branches which are in a conductive state.

[0131] Example 15: The controller or method according to any one of examples 10 to 14, wherein the controller comprises a first logic unit (250) configured to execute, during active load modulation, a logic AND function from an NFC carrier signal and the load modulation signal, in order to generate a control signal (CTRL) on the third node (NCTRL_SEL1).

[0132] Example 16: The controller or method according to Example 15, wherein the load modulation signal (Load_modulation_signal) is a Manchester-coded subcarrier of the NFC carrier signal.

[0133] Example 17: The controller or method according to any one of Examples 10 to 16, in which the NMOS or PMOS transistors of the second branches are binary weighted from one second branch to the other and in which the resistors (404...404n) of the first branches are binary weighted from one first branch (412...412n) to the other.

[0134] Example 18: The controller or method according to any one of Examples 14 to 17, wherein the first, second, third, fourth, fifth and sixth numbers are encoded in one or more registers of a non-volatile memory (150).

[0135] Example 19: The controller or method according to any one of Examples 10 to 18, wherein the controller comprises a first and a second of said at least one resistive circuit (RCDMP1, RCDMP2), and a first and a second of said at least one radio frequency driver (220, 222); the controller comprising a second logic unit (252) configured to execute, during active load modulation, a logic AND function from the inverted NFC carrier signal and the load modulation signal, in order to generate an inverted control signal (CTRL / ) on the third node (NCTRL_SEL2) connected to the second radiofrequency pilot circuit.

[0136] According to an example 20, an NFC device (100) comprises: - the NFC controller (140) according to any one of examples 1 or 3 to 19; - an antenna (120); and - an adaptation circuit (130) connecting the controller (140) to the antenna (120).

[0137] Example 21: The device according to example 20 in which the adaptation circuit comprises: - a first and a second input node (CDMP1, CDMP2) connected respectively to the first and second resistive circuits (210, 212) of the controller; - a third and a fourth input node (NRF01, NRF02) connected respectively to the first and second radiofrequency pilot (220,222) of the controller; - a first and a second output node (Antl,Ant2) connected to the antenna (120); - a first and a second capacity respectively coupling the first input node (CDMP1) to the first output node (Antl) and the second input node (CDMP2) to the second output node (Ant2); - a third capacitance (Cp) coupling the first output node to the second output node; - a resistor (Rp) connecting the first output node (Antl) to the second output node (Ant2); - a first and a second inductance (Lemil, Lemi2) respectively coupling the first radiofrequency pilot (220) to a fourth node (Nm4) and the second radiofrequency pilot (222) to a fifth node (Nm5); - a fourth and a fifth capacity (Cemil,Cemi2) respectively coupling the fourth node (Nm4) and the fifth node (Nm5) to ground; - a sixth and a seventh capacity (Csl,Cs2) respectively coupling the fourth node (Nm4) to the first output node (Antl) and the fifth node (Nm5) to the second output node (Ant2).

[0138] According to an example 22 of a second aspect, an NFC device (100) comprises: an NFC controller (140) comprising a first and a second resistive circuit (210, 212); and an adaptation circuit (130) connecting the controller (140) to the antenna (120) and comprising: - a first and a second input node (CDMP1, CDMP2) connected respectively to the first and to the second resistive circuit (210, 212) of the controller; - a first and a second output node (Antl, Ant2) configured to be connected to an antenna; - a first and a second capacity (Ccdmpl,Ccdmp2) respectively coupling the first input node (CDMP1) to the first output node (Antl) and the second input node (CDMP2) to the second output node (Ant2).

[0139] Example 23: The NFC device according to example 22, wherein the NFC controller (140) is configured to switch from active charging modulation to passive charging modulation at least when a power level of the battery is below a first power threshold or when an NFC charging session begins.

[0140] Example 24: The NFC device according to example 22 or 23, wherein the controller (140) switches from passive load modulation to active load modulation when a received signal strength indicator (RSSI) becomes greater than a first RSSI threshold.

[0141] Example 25: The NFC device according to example 23 or 24, wherein the controller switches from active load modulation to passive load modulation when the received signal strength indicator becomes lower than a second RSSI threshold, the first RSSI threshold being higher than the second threshold.

[0142] Example 26: The NFC device according to any one of examples 23, 24 or 25 in their dependence on example 23, wherein the controller switches from passive load modulation to active load modulation when the battery power level is above a second power threshold.

[0143] Example 26: The NFC device according to example 25, wherein the first and second RSSI thresholds are based on the modulation type.

[0144] Example 27: The NFC device according to any one of Examples 23 to 26, wherein the swiping is performed when the controller is in card emulation mode.

[0145] Example 28: The NFC device according to any one of examples 24 or 25 to 27 in their dependence on example 24, wherein the received signal strength indicator is filtered or averaged.

[0146] Example 29: The NFC device according to any one of examples 23 to 28, wherein, during passive load modulation, said resistive circuit is configured to adopt a first or a second resistance value based on a level of the load modulation signal (Load_modulation_signal).

[0147] Example 30: The NFC device according to any one of examples 23 to 29, wherein the controller (140) comprises at least one radio frequency driver (220, 222) and, during passive load modulation, said radio frequency driver is configured to adopt a third or a fourth resistance value based on the load modulation signal.

[0148] Example 31: The NFC device according to example 30 in its dependence on example 29, wherein said resistive circuit (210) has a plurality of first branches (412...412n) in parallel, each connecting the ground (GND) to the same first node (CDMP1), each of the first branches comprising a first switch (424...424n) and a resistor (404...404n); and - said at least one radiofrequency pilot (220,222) comprising a plurality of second branches (312...312n) connecting the ground to a reference voltage rail (VDD,VDDRF), each of the second branches comprising: an NMOS transistor and a PMOS transistor (Pl...Pn,NL..Nn) in series, a conduction node of said NMOS transistor being connected to ground and a conduction node of said PMOS transistor being connected to the reference voltage rail, a conduction node common to said NMOS transistor and said PMOS transistor being connected to a second node (NRF01,NRF02); a second switch (302...302n) configured to connect, in a first state, a control node of said PMOS transistor to the reference voltage rail (VDD) and, in a second state, the control node of said PMOS and NMOS transistors to the same third node (NCTRL_SEL1); and a third switch (304...304n) configured to connect, in a first state, a control node of said NMOS transistor to ground and, in a second state, the control node of said PMOS and NMOS transistors to the third node (NCTRL_SEL1), the first state of the second and third switches occurring simultaneously, and the second state of the second and third switches occurring simultaneously.

[0149] Example 32: The NFC device according to any one of Examples 29 to 31, wherein the first and second resistance values ​​respectively correspond to a first number of first switches (424...424n) of the first branches (412...412n) which are in a conductive state and to a second number of first switches of the first branches which are in a conductive state; the first switches of the resistive circuit being controlled on the basis of the level of the load modulation signal, a first level of the load modulation signal corresponding to said first number and a second level of the load modulation signal corresponding to said second number.

[0150] Example 33: The NFC device according to any one of Examples 29 to 32, wherein the third and fourth resistance values ​​correspond respectively to the third and fourth numbers of the second or third switches of the second branches which are in the first state, the first level of the load modulation signal corresponding to said third number and the second level of the load modulation signal corresponding to said fourth number.

[0151] Example 34: The NFC device according to any one of Examples 29 to 33, wherein, during active load modulation, the resistive circuit is configured to adopt, based on a level of the damping signal (Damping_control): a fifth resistance value adapted to lower a quality factor of an antenna (120) coupled to the controller; and a sixth resistance value adapted to increase said quality factor; said fifth and sixth resistance values ​​corresponding to a respective fifth and sixth number of first switches (424...424n) of the first branches which are in a conductive state.

[0152] Example 35: The NFC device according to any one of examples 29 to 34, wherein the controller comprises a first logic unit (250) configured to execute, during active load modulation, a logic AND function from an NFC carrier signal and the load modulation signal, in order to generate a control signal (CTRL) on the third node (NCTRL_SEL1).

[0153] Example 36: The NFC device according to Example 35, wherein the load modulation signal (Load_modulation_signal) is a Manchester-coded subcarrier of the NFC carrier signal.

[0154] Example 37: The NFC device according to any one of examples 29 to 36, in which the NMOS or PMOS transistors of the second branches are binary weighted from one second branch to the other and in which the resistors (404...404n) of the first branches are binary weighted from one first branch (412...412n) to the other.

[0155] Example 38: The NFC device according to any one of examples 33 to 37, wherein the first, second, third, fourth, fifth and sixth numbers are encoded in one or more registers of a non-volatile memory (150).

[0156] Example 39: The NFC device according to any one of examples 29 to 38, wherein the controller (140) comprises a first and a second radio frequency driver (220,222), and the adaptation circuit comprises: - a third and a fourth input node (NRF01,NRF02) connected respectively to the first and second radiofrequency pilot (220,222) of the controller; - a third capacitor (Cp) coupling the first output node to the second output node, a resistor (Rp) connecting the first output node (Antl) to the second output node (Ant2); - a first and a second inductance (Lemil, Lemi2) respectively coupling the first radiofrequency pilot (220) to a fourth node (Nm4) and the second radiofrequency pilot (222) to a fifth node (Nm5); - a fourth and a fifth capacitance (Cemil, Cemi2) respectively coupling the fourth node (Nm4) and the fifth node (Nm5) to ground; and - a sixth and a seventh capacity (Csl, Cs2) respectively coupling the fourth node (Nm4) to the first output node (Antl) and the fifth node (Nm5) to the second output node (Ant2).

[0157] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, even though the example of [Fig. 2] describes two resistive circuits and two radio frequency drivers, a controller 140 having one resistive circuit and one radio frequency driver can be envisaged. In this case, nodes NRF01 and NRF02 can be connected together and are in phase.

[0158] Finally, the practical implementation of the described embodiments and variants is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the number of resistance values, the person skilled in the art can use his knowledge to predefine more than two different possible resistance values ​​for the resistive circuits or for the radiofrequency drivers depending on the needs for passive or active load modulations.

Claims

Claims

1. An NFC controller (140) configured to switch from active load modulation to passive load modulation at least when a received signal strength indicator (RSSI) becomes greater than a first RSSI threshold.

2. A method of operating an NFC controller (140), comprising a step of switching from an active load modulation to a passive load modulation at least when a received signal strength indicator (RSSI) becomes greater than a first RSSI threshold.

3. The controller of claim 1 or the method of claim 2, wherein the NFC controller (140) switches from active charge modulation to passive charge modulation when a power level of a battery is below a first power threshold or when an NFC charging session begins.

4. The controller of claim 1 or 3 or the method of claim 2 or 3, wherein the controller switches from active load modulation to passive load modulation when the received signal strength indicator becomes lower than a second RSSI threshold, the first RSSI threshold being higher than the second threshold.

5. A controller or method according to claim 3 or 4 as dependent on claim 3, wherein the controller switches from passive charge modulation to active charge modulation when the battery power level is above a second power threshold.

6. The controller or method of claim 4 or 5, wherein the first and second RSSI thresholds are based on the modulation type.

7. A controller according to any one of claims 1 or 3 to 6 or a method according to any one of claims 2 to 6, wherein the switching is performed when the controller is in card emulation mode.

8. A controller according to any one of claims 1 or 3 to 7 or a method according to any one of claims 2 to 7, wherein the received signal strength indicator is filtered or averaged.

9. A controller according to any one of claims 1 or 3 to 8 or a method according to any one of claims 2 to 8, wherein the controller (140) comprises at least one radio frequency driver (220,222) and, during passive modulation of the load, said radio frequency driver is configured to adopt a third or a fourth resistance value based on a level of the load modulation signal.

10. The controller or method of claim 9, wherein the controller (140) comprises at least one resistive circuit (210,212) and, during passive modulation of the load, said resistive circuit is configured to adopt a first or a second resistance value based on the level of the load modulation signal (Load_modulation_signal).

11. Controller or method according to claim 10, wherein the at least one resistive circuit (210) has a plurality of first branches (412.. .412n) in parallel, each connecting the ground (GND) to a same first node (CDMP1), each of the first branches comprising a first switch (424.. .424n) and a resistor (404...404n); and said at least one radiofrequency driver (220,222) comprising a plurality of second branches (312.. .312n) connecting the ground to a reference voltage rail (VDD,VDDRF), each of the second branches comprising: an NMOS transistor and a PMOS transistor (PI.. .Pn,N 1.. .Nn) in series, a conduction node of said NMOS transistor being connected to the ground and a conduction node of said PMOS transistor being connected to the reference voltage rail, a conduction node common to said NMOS transistor and said PMOS transistor being connected to a second node (NRF01,NRF02); a second switch (302.. .302n) configured to connect, in a first state, a control node of said PMOS transistor to the reference voltage rail (VDD) and, in a second state, the control node of said PMOS and NMOS transistors to the same third node (NCTRL_SEL1); and a third switch (304.. .304n) configured to connect, in a first state, a control node of said NMOS transistor to ground and, in a second state, the control node of said PMOS and NMOS transistors to the third node (NCTRL_SEL1), the. first state of the second and third switches occurring simultaneously, and the second state of the second and third switches occurring simultaneously.

12. The controller or method of claim 11, wherein the first and second resistance values ​​respectively correspond to a first number of first switches (424...424n) of the first branches (412...412n) being in a conductive state and a second number of first switches of the first branches being in a conductive state; the first switches of the resistive circuit being controlled based on the level of the load modulation signal, a first level of the load modulation signal corresponding to said first number and a second level of the load modulation signal corresponding to said second number.

13. A controller or method according to any one of claims 11 or 12, wherein the third and fourth resistance values ​​correspond respectively to the third and fourth numbers of the second or third switches of the second branches which are in the first state, the first level of the load modulation signal corresponding to said third number and the second level of the load modulation signal corresponding to said fourth number.

14. A controller or method according to any one of claims 11 to 13, wherein, during active load modulation, the resistive circuit is configured to adopt, based on a level of a damping signal (Damping_control): a fifth resistance value adapted to lower a quality factor of an antenna (120) coupled to the controller: and a sixth resistance value adapted to increase said quality factor; said fifth and sixth resistance values ​​corresponding to a respective fifth and sixth number of first switches (424.. .424n) of the first branches which are in a conductive state.

15. A controller or method according to any one of claims 11 to 14, wherein the controller comprises a first logic unit (250) configured to perform, during active modulation of the load, a logic AND function from an NFC carrier signal. and the load modulation signal, to generate a control signal (CTRL) on the third node (NCTRL_SEL1).

16. The controller or method of claim 15, wherein the load modulation signal (Load_modulation_signal) is a Manchester-encoded subcarrier of the NFC carrier signal.

17. A controller or method according to any one of claims 11 to 16, wherein the NMOS or PMOS transistors of the second branches are binary weighted from one second branch to the other and wherein the resistors (404.. .404n) of the first branches are binary weighted from one first branch (412.. .412n) to the other.

18. A controller or method according to any one of claims 14 to 17, wherein the first, second, third, fourth, fifth and sixth numbers are encoded in one or more registers of a non-volatile memory (150).

19. A controller or method according to any one of claims 11 to 18, wherein the controller comprises a first and a second of said at least one resistive circuit (RCDMP1, RCDMP2), and a first and a second of said at least one radio frequency driver (220, 222); the controller comprising a second logic unit (252) configured to execute, during active load modulation, a logic AND function from the inverted NFC carrier signal and the load modulation signal, to generate an inverted control signal (CTRL / ) on the third node (NCTRL_SEL2) connected to the second radio frequency driver.

20. NFC device (100) comprising: - the NFC controller (140) according to any one of claims 1 or 3 to 19; - an antenna (120); and - a matching circuit (130) coupling the controller (140) to the antenna (120).

21. Device according to claim 20 in its dependency on claim 19, in which the adaptation circuit comprises: - a first and a second input node (CDMP1, CDMP2) connected respectively to the first and second resistive circuits (210, 212) of the controller; - a third and a fourth input node (NRF01,NRF02) connected respectively to the first and second radiofrequency circuits (220,222) of the controller; - a first and a second output node (Antl,Ant2) connected to the antenna (120); - a first and a second capacity (Ccdmpl,Ccdmp2) respectively coupling the first input node (CDMP1) to the first output node (Antl) and the second input node (CDMP2) to the second output node (Ant2); - a third capacitance (Cp) coupling the first output node to the second output node; - a resistor (Rp) connecting the first output node (Antl) to the second output node (Ant2); - a first and a second inductance (Lemil, Lemi2) respectively coupling the first radiofrequency pilot (220) to a fourth node (Nm4) and the second radiofrequency pilot (222) to a fifth node (Nm5); - a fourth and a fifth capacity (Cemil,Cemi2) respectively coupling the fourth node (Nm4) and the fifth node (Nm5) to ground; - a sixth and a seventh capacity (Csl,Cs2) respectively coupling the fourth node (Nm4) to the first output node (Antl) and the fifth node (Nm5) to the second output node (Ant2).

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