Method and device for correcting errors in resistive memories or flash memories

Abstract

The invention relates to a device and a method for error correction in resistive memories or flash memories, protected by an error correcting code which allows the correction of at least two erroneous bits per code word stored in memory. The device combines a correction module capable of correcting up to r-1 erroneous bits per code word, and a detection module for checking the number of erroneous bits per code word. The detection module is arranged to detect whether the read code word comprises at most r-1 erroneous bits, and if not, to initiate a sequence of decoding operations on a succession of words each of which comprises a single bit inverted with respect to the read code word. A check is then made to verify whether the number of erroneous bits in the version of the code word with inversion of one bit has become correctable. As soon as this condition is satisfied, the code word can be corrected. Figure for abstract: Fig. 1

Description

Title of the invention: Method and device for correcting errors in resistive memories or flash memories Technical field

[0001] The invention lies in the field of resistive memories or flash memories, and more particularly relates to a method and a device for improving error correction in such memories. State of the art

[0002] Resistive memories (RRAM) for "Resistive Random Access Memory" according to the English terminology, are non-volatile memories with a high operating speed, low electrical energy consumption and a long lifespan. For these reasons, resistive memories are among the most promising memory technologies to replace both RAM and current non-volatile memories such as flash memories.

[0003] There are several resistive memory technologies. These include conductive bridge resistive memories, also called CBRAM (for “Conductive-Bridging Random-Access Memory” in English terminology), or oxide-based resistive memories, also called OxRAM (for “Oxide-based Random-Access Memory” in English terminology), or phase change memories, also called PCM (for “Phase Change Memory” in English terminology).

[0004] A resistive memory is composed of a multitude of resistive memory cells arranged in rows and columns so as to form a matrix. An RRAM memory cell is provided with at least one resistive element whose electrical conductance can be modified.

[0005] A factor limiting their wide adoption on the market remains the high error rates during reading operations. The error rate or BER as an acronym for the Anglicism "Bit Error Rate", is impacted due to slippages in the HRS (for "High Resistance State" according to the Anglo-Saxon terminology) or LRS (for "Low Resistance State" according to the Anglo-Saxon terminology) values ​​of the resistances programmed in the memories. The article by B. Giraud et al., "Benefits of Design Assist Techniques on Performances and Reliability of a RRAM Macro" - DOI: 10.1109 / IMW56887.2023.10145984, describes this known phenomenon in more detail.

[0006] It should also be noted that even though NAND flash memory technology is mature and continues to dominate the market for electronic memories used in mass storage devices, these memories can also suffer from a rate significant errors when trying to store multiple bits per cell and / or when they are subjected to a large number of write / erase cycles. The IDC white paper by N. Sundby and D. Taylor, "Beyond capacity: storage architecture choices for the modem datacenter," published by IDC Analyze the Future, explores these elements.

[0007] A known solution for addressing a high error rate affecting a memory of one of these types is to use protection based on error correcting code or ECC for the English acronym for "Error Correcting Code".

[0008] A correction code can be implemented by adding an ECC encoder and decoder within or near the memory controller. Generally, a memory controller is the electronic circuit whose function is to translate requests, generally from a host electronic system, to read or write to memory systems.

[0009] The general principle when encoding data with an ECC is to add check bits to the data bits using an encoder. The check bits are calculated from the data bits and the set forms a code word. During a decoding operation via an ECC decoder, the presence of the check bits allows the detection and correction of errors affecting both data bits and check bits.

[0010] The code words of a binary and linear ECC can be defined through the following equation:

[0011] Hv = 0(l),

[0012] where v is a vector corresponding to a code word, and where H corresponds to a parity matrix which comprises only binary values ​​('0' or '1') and each column of which is different from the other columns, and comprises at least one value different from 0.

[0013] When reading the data present in the memory, each code word which is read (i.e. each vector v is checked by evaluating the value of the matrix product H v .

[0014] The result of this operation is a binary vector called a "syndrome". If the syndrome is a zero vector, i.e. each of the bits in the vector is equal to zero, the code word is considered correct. Conversely, a non-zero syndrome indicates the presence of at least one error in the code word.

[0015] Furthermore, if a syndrome allows the positions of the erroneous bits to be identified, the code word can be corrected.

[0016] In the presence of high error rates, one solution is to use increasingly powerful ECCs, i.e. making it possible to correct more and more erroneous bits in a code word.

[0017] However, this results in an increasingly significant additional cost in terms of surface area, ie the storage area for the verification bits, and in terms of latency and area (consumption) of the ECC decoder.

[0018] Also, faced with the problem of error correction in resistive memories or flash memories, there is a need for a solution that overcomes the various drawbacks of known solutions, in particular the drawbacks related to latency and the surface area of ​​the ECC decoder.

[0019] The present invention meets this need. Summary of the invention

[0020] The subject of the invention is a device making it possible to reduce the cost of the circuits used for correcting errors affecting words read in memories protected by an error correcting code (ECC).

[0021] The invention more particularly addresses resistive memories and flash memories protected by an error-correcting code which allows the correction of at least two erroneous bits per code word stored in memory.

[0022] The device of the invention relates to an ECC decoder, which advantageously offers a smaller surface implementation and improved latency performance.

[0023] Generally speaking, for an ECC making it possible to correct up to r erroneous bits per code word obtained during a memory read operation, the device according to the invention combines a correction module capable of correcting up to r-1 erroneous bits per code word, and a detection module making it possible to verify the number of erroneous bits per code word.

[0024] More specifically, the detection module is arranged to detect whether the initial code word comprises at most r-1 erroneous bits, and, if not, to initiate a sequence of decoding operations on a succession of words each of which comprises a single bit inverted with respect to the initial code word.

[0025] A check is then made to verify whether the number of erroneous bits in the version of the code word with one bit inversion has become correctable, i.e. whether the number of erroneous bits has fallen below r. As soon as this condition is satisfied, the code word can be corrected.

[0026] Thus, the principle of the invention is based on the implementation and use of an ECC decoder of less functional complexity, smaller surface area and reduced latency, than an ECC decoder composed of a single combinatorial module.

[0027] To achieve the desired aim, there is provided a device for correcting errors in code words, a code word comprising a data word formed of data bits and comprising verification bits. The device of the invention comprises a combination of means or modules including (a) means for receiving a code word with potential errors, the word being read from a memory protected by an error-correcting code with a maximum correction capacity of r erroneous bits per code word.

[0028] The device of the invention further comprises (b) a decoding module which comprises: - means for generating a binary vector or syndrome for the received code word or for a version of the code word with inversion of a bit, a code word with inversion of a bit being a word from the received code word where the value of a single bit is inverted; and - correction means for generating from the syndrome, an error vector making it possible to correct up to r-1 erroneous bits.

[0029] The device of the invention further comprises (c) an evaluation module for determining the number of erroneous bits in a code word, which comprises: - detection means for detecting, from the syndrome, whether the number of erroneous bits in the received code word or in a version of the code word with inversion of a bit, is greater than or equal to r; - analysis means for deciding on an operation of inversion of a bit; and - inversion means for inverting a bit in the code word.

[0030] The device of the invention further comprises (d) output means for delivering a data word corrected by the error vector, when the number of erroneous bits in the received code word or in a version of the code word with inversion of one bit, is less than r.

[0031] According to one aspect of the invention, the means for generating a syndrome make it possible to evaluate the value of a matrix product H ■ v where H corresponds to a parity matrix, and where v is a vector corresponding to a received code word or to a code word with inversion.

[0032] In an alternative embodiment, the correction means comprise a combination of logic gates for generating an error vector, each bit of the error vector being an input of an exclusive-or gate of the output means.

[0033] In one implementation, the detection means comprise a combination of logic gates for generating a signal indicating the presence of at most r-1 erroneous bits in the received code word or in a code word with inversion of one bit, said signal being an input of the analysis means.

[0034] According to one aspect of the invention, the analysis means comprise a state machine controlled by the output of the detection means and the output of the inversion means, said state machine making it possible to determine whether a new decoding cycle is to be carried out by the error correction device, and to command the inversion means to invert a single bit in the received code word.

[0035] In an alternative embodiment, the evaluation module further comprises parity calculation means making it possible to generate a total parity signal, said total parity signal allowing the analysis means, in combination with the signal received from the detection means, to detect the presence of an uncorrectable error.

[0036] In one implementation, the correction means are designed according to logical optimization methods allowing the processing of “don't care” type data.

[0037] In an alternative embodiment, the means for generating syndromes are designed to generate oversized syndromes having a number of bits greater than the number of verification bits of the code word.

[0038] Another object of the invention covers an electronic system of FPGA or ASIC type comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to the invention.

[0039] The invention also addresses a method for correcting errors in code words, a code word comprising a data word formed of data bits and comprising verification bits.

[0040] The method of the invention comprising steps consisting of:

[0041] - receiving a code word with potential errors, the word being read in a memory protected by an error-correcting code having a maximum correction capacity of r erroneous bits per code word;

[0042] - in a first decoding cycle:

[0043] - perform a decoding of the received code word;

[0044] - determine whether the code word contains a number of erroneous bits less than or equal to r-1 ; and if not

[0045] - invert a data bit in the code word to generate a version of the code word code with one-bit inversion;

[0046] - repeat a new decoding cycle with the previous steps for each version of the code word with inversion of one bit which is generated, as long as the number of erroneous bits is greater than r-1 or a maximum number of bits to be inverted is reached, the step of inverting one bit consisting in each new cycle of resetting to its initial state the value of the bit inverted in the previous cycle, and inverting the value of a new bit in the received code word; and

[0047] - output a corrected data word if the number of erroneous bits in the code word received or in a version of the code word with one bit inversion is less than r.

[0048] In one embodiment, the method comprises, before the step of determining whether the code word contains a number of erroneous bits less than r, a step of calculating total parity making it possible to determine the presence of an uncorrectable error in the code word.

[0049] Advantageously, the method of the invention is implemented in an electronic system of the FPGA or ASIC type comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to the invention. Description of the figures

[0050] Characteristics, details and advantages of the invention will emerge from reading the description given with reference to the appended drawings given by way of example and which represent, respectively:

[0051] [Fig.l] illustrates an example of architecture of an error correction device according to the invention;

[0052] [Fig.2] illustrates the steps of an error correction method implemented by a device according to [Fig.l];

[0053] [Fig.3] illustrates an architectural variant of an error correction device according to the invention with detection of non-correctable errors;

[0054] [Fig.4] illustrates the steps of an error correction method implemented by a device according to [Fig.3];

[0055] [Fig.5] shows a table comparing area and clock period gains for different types of ECC and circuits implementing devices according to the invention;

[0056] [Fig.6] shows a graph of the average number of additional decoding cycles (clock cycles) vs. the bit error rate for prior art decoders and decoders according to the invention. Detailed description of the invention

[0057] [Fig.l] illustrates an embodiment of an error correction device 100 according to the invention, also referred to as an ECC decoder, and which can be used with an ECC allowing the correction of a maximum of r erroneous bits per code word read in a resistive memory or a flash memory.

[0058] This device can be implemented in an architecture which generally integrates a host electronic system, a memory controller and a memory (resistive or flash).

[0059] The host may consist of one or more processor cores, a microcontroller, a field programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0060] The memory controller controls the write and read operations in the memory. It comprises an ECC encoder and decoder implemented according to the described embodiment variants.

[0061] In alternative embodiments, the error correcting code may be of the DEC (“Double Error Correction”), DEC-TED (“Double Error Correction-Triple Error Correction”), TEC (“Triple Error Correction”), TEC-QED (“Triple Error Correction-Quadruple Error Detection”), QEC (“Quadruple Error Correction”) or QEC-QED (“Quadruple Error Correction-Quintuple Error Detection”) type.

[0062] [Fig.l] shows the functional blocks of the device 100 of the invention, and the data flows circulating between the different blocks.

[0063] The device according to the invention for correcting errors in code words, where a code word comprising a data word formed of data bits and comprising verification bits, comprises:

[0064] - means 110 for receiving a code word with potential errors, the word being read from a resistive memory or a flash memory, the memory being protected by an error-correcting code having a maximum correction capacity of r erroneous bits per code word;

[0065] - a decoding module which comprises: - means 130 for generating a vector binary or syndrome for the received code word or for a code word with inversion of a bit from the received code word, a code word with inversion of a bit being a word obtained from the received code word where the value of a single bit is inverted; and - correction means 140 for generating from the syndrome, an error vector making it possible to correct up to r-1 erroneous bits in the data word;

[0066] - an evaluation module for determining the number of erroneous bits in the word of code which comprises: - detection means 150 for detecting, from the syndrome, whether the number of erroneous bits in the received code word or in a code word with inversion of a bit is greater than or equal to r; - analysis means 170 for deciding on an operation of inversion of a bit in the code word; - inversion means 120 for inverting a bit in the code word;

[0067] - output means 160 for delivering a corrected data word when the number of erroneous bits in the received code word or in a code word with one bit inversion is less than r.

[0068] The ECC decoder 100 receives as input a code word comprising potential programming, storage or reading errors (i.e. erroneous bits). Each bit of the received code word passes through a logic gate 110 of the exclusive-or (XOR) type. Each XOR gate is controlled by a bit of an inversion vector from inversion means 120.

[0069] In one embodiment, the inversion means comprises a shift register 120 for storing an inversion vector having a number of bits equal to the number of bits in the code word minus r-1. Among these bits, at most a single bit can be equal to 1 in order to invert the value of at most a single bit in the word at the input of the ECC decoder.

[0070] A code word at the output of the input logic gates 110 is addressed to a decoding module composed of means 130 for generating a binary vector or syndrome for the received word.

[0071] A word received as input to the syndrome generator 130 is a code word with potential errors which has or has not undergone a single-bit inversion, depending on the value of the inversion vector.

[0072] At initialization, all bits of the inversion vector are initialized to the value zero such that each bit of the received code word that passes through an XOR gate 110 retains its initial value.

[0073] At each decoding iteration, all bits of the inversion vector are shifted by one position with 0 or 1 at the input of the flip-flop located at the input of the shift register, i.e. at the end opposite to the direction of the shift. The value 1 at the input is used just for the first shift operation to produce an inversion vector with a single value of 1 and a version of the code word called "code word with one bit inversion" which is addressed to the syndrome generator.

[0074] The syndrome generator 130 implements multiplication operations to realize the matrix product H • v of equation (1), where the vector v is a code word with potential errors, either received as input by reading the memory, or a code word with inversion of a bit generated during a subsequent decoding cycle.

[0075] From the syndrome, an error vector generator 140 generates a check bit for each data bit, the set of check bits being the error vector.

[0076] Each data bit can be corrected using a two-input exclusive-or (XOR) logic gate 160, one input for the bit to be corrected and another input driven by the control bit that corresponds to it in the error vector.

[0077] Thus the output of the syndrome generator 130 is an input of the correction means 140 which are arranged to generate an error vector making it possible to correct up to r-1 erroneous data bits in the word at the output of the module 110.

[0078] In an advantageous embodiment, the correction means 140 are designed with design tools which allow optimizations of Boolean logic in order to process inputs of the “don't care” (DC) type also referred to as “no matter” inputs.

[0079] Such optimization methods are for example described in the article “Synthesis of Irregular Combinational Functions with Large Don't Care Sets” by V. Gherman et al. (DOI: 10.1145 / 1228784.1228856).

[0080] The notion of DC is defined in conjunction with incompletely specified Boolean functions, ie, y - y J where X represents a value undefined which can take the value 0 or 1, in the case of a hardware implementation of f. The combinations of N bits, -y Π{ 0 1} A in the domain of de completion of f which are mapped to X, are called DC.

[0081] Advantageously, in the presence of a large number of DCs, it becomes possible to obtain hardware implementations of a function f which are more optimized in terms of latency, surface area or dissipated power.

[0082] Thus, a large number of DCs can be identified for the functions implemented by the correction module 140 (and by similarity by the correction module 340 of the variant of [Fig.3]).

[0083] In this way, all syndromes generated for errors affecting r and r+1 bits can be considered as DC type data because in these cases the output of the ECC decoder is not used. This particular type of DC is considered as so-called observation DCs.

[0084] In an alternative embodiment, the number of DCs for the correction means 140 (and 340) can be further increased by generating oversized syndromes by the syndrome generator 130 (and by similarity by the syndrome generator 330 of [Fig. 3]), i.e., syndromes having a number of bits greater than the number of verification bits of the code word.

[0085] Such oversized syndromes can be generated by adding redundant lines to the parity matrix H, e.g. lines which are linear combinations of already existing lines. For each additional bit added to the syndromes, the number of possible combinations at the input of the module 130 (or 330) is multiplied by 2.

[0086] In such a process, only the number of DCs can increase because the value of each redundant syndrome bit is defined by the values ​​of the non-redundant syndrome bits. Therefore, for each combination of non-redundant syndrome bits, there is only one possible combination of the redundant syndrome bits, and any other combination of redundant syndrome bits cannot be realized. All combinations of syndrome bits that contain non-realizable redundant syndrome bit values ​​are considered so-called controllability DCs.

[0087] Returning to [Fig. 1], the output of the syndrome generator is also an input of the detection means 150 of the evaluation module.

[0088] The detection means are arranged to allow, by evaluating the syndrome, the detection of r or r+1 erroneous bits in the code word at the output of the module 110.

[0089] The output of the module 150 is used by a state machine 170 or (FSM) acronym “Finite State Machine” in English.

[0090] The state machine determines whether a new decoding cycle must be performed by the ECC decoder.

[0091] The FSM controls the shift register 120 via START and EN signals. During the first decoding cycle, if at least r erroneous bits are detected in the code word received at the input of the device 100 (and at the output of the module 110, the inversion vector being in its initial state, all values ​​at 0), the two START and EN signals take the value 1 and the FSM forces the start of a new decoding cycle. The first bit of register 120 is set to 1. In this way, the bit of the received code word that enters the first XOR gate is inverted. At the same time, a new decoding cycle is performed with the version of the code word whose first bit is inverted.

[0092] At each subsequent decoding cycle, the START signal is reset to 0 and the EN signal is maintained at 1, and this as long as a number r or r+1 of erroneous bits is detected, i.e. until the cycle where the decoding becomes successful. The EN signal makes it possible to reset all the bits of the register 120 to zero.

[0093] Thus, after each unsuccessful decoding cycle, i.e. where the detection module 150 indicates the presence of at least r erroneous bits in the version of the word at the output of the module 110, the value 1 is advanced by one position in the register 120 so that another bit of the word at the input of the device 100 is inverted.

[0094] The iterative process of decoding operations stops either when the detection module 150 indicates a number of at most r-1 erroneous bits (i.e. a number of errors which can be corrected by the error vector), or when the value 1 is assigned to the bit in the last position in the shift register 120.

[0095] Each decoding cycle may be executed in one clock cycle that controls the device 100.

[0096] After the positive decoding cycle, a correction of the erroneous data bits in the version of the word output from the input module 110 is carried out using the exclusive-or gates 160, the gates being driven by the bits of the error vector generated by the module 140.

[0097] To the outside of the device, the stopping of the decoding process is indicated by a Ready signal generated at the output of the FSM.

[0098] [Fig.2] illustrates the steps of an error correction method according to the invention which can be implemented by a device according to [Fig.l].

[0099] The method 200 applies when reading from a memory protected by an ECC capable of correcting up to r bits per code word, and it makes it possible to improve error correction.

[0100] The method begins with a step 210, of receiving a code word which potentially may contain erroneous bits.

[0101] In a following step 220, the method allows a first decoding of the code word 220, and allows checking in a following or simultaneous step 230 whether the number of erroneous bits is less than or equal to r-1.

[0102] If the number of erroneous bits is at most r-1, the method allows the correction of the erroneous bits and allows a corrected word to be delivered in step 270.

[0103] According to alternative embodiments, the method makes it possible to deliver either the corrected code word in full, or only the corrected data bits (for implementa- reduced ECC decoder information).

[0104] Returning to step 230, if the number of erroneous bits is greater than r-1, the method makes it possible to initiate an execution of a new decoding cycle for a version of the code word where a single bit is inverted. The method comprises a step 240 in which a bit of the initially received code word is inverted.

[0105] When executing a new decoding cycle, except for the first execution, the method makes it possible to reset to its initial value the bit which was inverted during the previous execution.

[0106] Thus, at each execution of step 240 a new bit of the code word is inverted.

[0107] The method continues the execution of new decoding cycles (branch not of 250) as long as the number of erroneous bits is not less than or equal to r-1, or as long as a maximum number of bits to be inverted in the initially received word is not reached.

[0108] When the maximum number is reached, the method generates in step 260 a signal indicating an uncorrectable error.

[0109] The error correction method according to the invention allows, for an ECC circuit capable of correcting r erroneous bits per code word, that it can be processed up to r-1 erroneous bits in one decoding cycle.

[0110] Thus advantageously the method of the invention implemented on an optimized device such as that of [Fig.l] or with variant embodiments, makes it possible to reduce the latency and the surface area of ​​the error correction logic.

[0111] [Fig.3] illustrates an architectural variant of an error correction device according to the invention, which comprises additional means for performing a total parity calculation.

[0112] The device 300 can be used with an ECC which allows the correction of at most r erroneous bits and the detection of r+1 erroneous bits per code word.

[0113] In this variant, it is assumed that the detection of r+1 erroneous bits is ensured by using code words having a total parity bit added, which allows the resulting code words to be all even words or all odd words.

[0114] Different functional blocks are identical to the blocks of [Fig.l], and a detailed description is not given, which can be taken from the previous description. Thus, the blocks or modules 310 to 360 of [Fig.3] are respectively identical to the modules 110 to 160 of [Fig.l].

[0115] The device 300 further comprises a total parity evaluation module 380.

[0116] Module 380 is designed to select a syndrome bit that corresponds to the total parity of the word at the output of the module 310, in the syndrome calculated by the syndrome generator 330, and send a total parity signal to the state machine 370.

[0117] In an alternative embodiment, the syndrome bit corresponding to the total parity, can be calculated from all the input bits of the syndrome generator 330 using a tree of XOR gates having all these bits as input.

[0118] In the variant of [Fig.3], the state machine 370 is very similar to that of the architecture in [Fig.l], except that during the first decoding cycle, the FSM 370 uses the total parity signal generated at the output of the module 380 to identify the presence of an uncorrectable error which affects r+1 bits.

[0119] This variant makes it possible to take advantage of the fact that a code word with r erroneous bits has a different total parity from a code word with r+1 erroneous bits, while the output of the module 350 remains the same in both cases.

[0120] Thus, in the event that an uncorrectable error is indicated during the first decoding cycle, no additional decoding cycle is initiated and a signal is generated at the output of the FSM 370 indicating the presence of an uncorrectable error.

[0121] [Fig.4] illustrates the steps of an error correction method that can be implemented by a device according to [Fig.3].

[0122] The method 400 applies when reading from a memory protected by an ECC capable of correcting up to r bits per code word and detecting r+1 erroneous bits per code word.

[0123] Different steps are identical to the steps of [Fig.2], and a detailed description is not given, which can be taken from the previous description. Thus, steps 410, 430, 440, 450, 460 and 470 are respectively identical to steps 210, 230, 240, 250, 260 and 270 of the method 200.

[0124] After receiving in step 410 a code word potentially containing erroneous bits, the following decoding step 420 makes it possible to identify the presence of uncorrectable errors in the code word, such as errors affecting r+1 bits.

[0125] The result of this detection of uncorrectable errors is processed in step 425. In the case where a number of r+1 erroneous bits is detected, the method continues with a step 460 in order to signal the presence of uncorrectable errors in the code word.

[0126] In the case where no uncorrectable errors are detected, the method continues with step 430.

[0127] Then according to the result of step 430, the method continues by setting up a loop of decoding cycles on code word versions with inversion of a single bit, according to steps (440, 450) and in accordance with the corresponding steps (240, 250) described for method 200.

[0128] According to different embodiments of the methods 200 and 400, the step (240, 440) of inverting a single bit in the code word at each decoding cycle, can consist either of applying a unitary inversion only on the data bits of the code word initially received in step 210 or 410, or of applying a unitary inversion on all the bits (data bits and verification bits) minus r-1 bits of the word of code received at step 210 or 410.

[0129] In one embodiment of a BCH type ECC (acronym of the initials of the authors Bose, Ray-Chaudhuri and Hocquenghem), the detection modules 150 and 350 respectively of figures 1 and 3, can be implemented according to a method presented in the paper entitled "Encoding and Error-Correction Procedures for the Bose-Chaudhuri Codes" by WW Peterson (DOI: 10.1109 / TIT. 1960.1057586). This paper introduces matrices called Peterson matrices for BCH type ECCs. If the ECC can correct up to r erroneous bits per code word, the Peterson matrix Mr+i is singular, i.e., its determinant is equal to 0, if the number of erroneous bits present in a code word is less than or equal to r-1. The Peterson matrix Mr+i is singular only if the number of erroneous bits present in a codeword is equal to r or r+1.

[0130] The method of [Fig.4] can then be adapted to detect an error that affects r bits by evaluating the determinant of the Peterson matrix Mr and the total parity of the received word (equal to r modulo 2 if all the code words are even), and detect an error that affects r+1 bits by evaluating the determinant of the Peterson matrix Mr+[ and the total parity of the received word (equal to r+1 modulo 2 if all the code words are even).

[0131] [Fig.5] illustrates the area and clock cycle gains of different types of ECC and circuits implementing error correction devices according to architectures such as proposed in [Fig.l] or [Fig.3].

[0132] The state-of-the-art ECCs considered are of the BCH type and allow the correction of a maximum of 3 erroneous bits per code word (r=3) on code words with 32, 64 or 128 bits of data. The codes considered are identified as being TEC (acronym for "triple-error correction") or TEC-QED (acronym for "triple-error correction and quadruple-error detection"), depending on whether the detection of 4 erroneous bits is ensured or not.

[0133] The calculation of gains, reduction on the clock period and reduction of the logic area, is done with respect to decoders implemented according to solutions presented in the paper entitled "A Low-Complexity Three-Error-Correcting BCH Decoder with Applications in Concatenated Codes" by J. Freudenberger, M. Rajab and S. Shavgulidze (DOI: 10.30420 / 454862002). All decoders were synthesized with the Synopsis Design Compiler tool in a 28nm FDSOI technology.

[0134] The error correction approach by iterative decoding cycles allows for example to reduce the clock period by up to -20% for 32-bit TEC codes, in parallel with reductions in the logic area by up to -45%.

[0135] [Fig.6] illustrates on a graph the average number of additional decoding cycles “cycle overhead” according to the bit error rate “RBER”, for decoders of the prior art and decoders according to the invention.

[0136] According to the invention, additional decoding cycles are introduced only if the received code word contains a maximum number of correctable erroneous bits. Decoding according to the prior art (label "ail errors") requires additional decoding cycles as soon as the received word contains an erroneous bit. The number of additional cycles is at least equal to (a) the number of data bits plus (b) the maximum number of correctable erroneous bits minus (c) the actual number of erroneous bits. It can be noted that the proposed solution (label "largest errors") has a significant advantage and its decoding cycle (clock) overhead becomes negligible with the reduction of the RBER.

[0137] For RBERs below 10 4, this overhead drops below 2x107, 2x107 and 2x105 respectively for TEC codes with 32, 64 and 128 data bits. The entries under the label "ail errors" correspond to the overhead of one known method presented in the paper entitled "Step-by-step decoding of the Bose-Chaudhuri-Hocquenghem codes" by J. Massey (DOI: 10.1109 / TIT. 1965.1053833).

[0138] In this prior art approach, although there is a bit inversion, this method is strictly different from the method of the invention with respect to (a) the correction of code words affected by less than r errors and (b) the correction of the remaining errors once a first erroneous bit is corrected in the event of r erroneous bits.

[0139] In this so-called "step-by-step" approach, additional erroneous bits are initially injected into the verification bits in order to reach a maximum number of r erroneous bits. The method then makes it possible to invert 1 bit at a time and to check after decoding whether the number of erroneous bits has decreased. If the number of erroneous bits has decreased, the method makes it possible to identify that this inverted bit is erroneous. Then the method continues to invert and test all the data bits one by one. There is then a very large number of cycles to be carried out as soon as an error is encountered.

[0140] On the contrary, according to the methods and devices of the invention, if a maximum number of erroneous bits is not detected, the correction takes place in a single cycle (yes branches of steps 230 and 430). This presents a major advantage verified and illustrated in [Fig.6].

[0141] The present description illustrates a preferred implementation of the invention, but which is not limiting. Examples are chosen to allow a good understanding of the principles of the invention and a concrete application, but are in no way exhaustive and must allow those skilled in the art to make modifications and implementation variants to the different circuits while retaining the same principles. In alternative embodiments, each functional module for encoding, counting, comparison and inversion can be implemented by a dedicated module such as an ASIC.

[0142] The invention can be implemented using hardware and / or software elements. It may be available as a computer program product executed by a dedicated processor or by a memory controller of a storage system, and which includes code instructions for carrying out the steps of the methods in their various embodiments.

Claims

Claims

1. Device for correcting errors in code words, a code word comprising a data word formed of data bits and comprising verification bits, the device comprising: - means (110) for receiving a code word with potential errors, the word being read from a memory protected by an error-correcting code having a maximum correction capacity of r erroneous bits per code word; - a decoding module, comprising: - means (130) for generating a binary vector or syndrome for the received code word or for a version of the code word with inversion of a bit, a code word with inversion of a bit being a word from the received code word where the value of a single bit is inverted; - correction means (140) for generating from the syndrome, an error vector making it possible to correct up to r-1 erroneous bits;- an evaluation module for determining the number of erroneous bits in a code word, comprising: - detection means (150) for detecting, from the syndrome, whether the number of erroneous bits in the received code word or in a version of the code word with inversion of one bit, is greater than or equal to r; - analysis means (170) for deciding on an operation of inversion of one bit; - inversion means (120) for inverting a bit in the code word - output means (160) for delivering a data word corrected by the error vector, when the number of erroneous bits in the received code word or in a version of the code word with inversion of one bit, is less than r.;

2. The device according to claim 1 in which the means for generating a syndrome make it possible to evaluate the value of a matrix product H • v where H corresponds to a parity matrix, and where v is a vector corresponding to a received code word or to a code word with inversion.

3. The device of claim 1 or 2 wherein the correction means (140) comprises a combination of logic gates for generating an error vector, each bit of the error vector being an input to an exclusive-or gate of the output means (160).

4. The device according to any one of claims 1 to 3 wherein the detection means (150, 350) comprise a combination of logic gates for generating a signal indicating the presence of at most r-1 erroneous bits in the received code word or in a code word with inversion of one bit, said signal being an input of the analysis means.

5. The device according to any one of claims 1 to 4 wherein the analysis means comprise a state machine (170) driven by the output of the detection means and the output of the inversion means, said state machine making it possible to determine whether a new decoding cycle is to be carried out by the error correction device, and to command the inversion means to invert a single bit in the received code word.

6. The device according to any one of claims 1 to 5 wherein the evaluation module further comprises parity calculation means (380) for generating a total parity signal, said total parity signal allowing the analysis means (370) in combination with the signal received from the detection means (350), to detect the presence of an uncorrectable error.

7. The device according to any one of claims 1 to 6 wherein the correction means (140, 340) are designed according to logical optimization methods making it possible to process “don't care” type data.

8. The device according to any one of claims 1 to 7 wherein the means for generating syndromes are adapted to generate oversized syndromes having a number of bits greater than the number of verification bits of the code word.

9. An FPGA or ASIC type electronic system comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to any one of claims 1 to 8.

10. A method of correcting errors in code words, a code word comprising a data word formed of data bits and comprising check bits, the method comprising steps of: - (210) receiving a code word with potential errors, the word being read from a memory protected by an error-correcting code having a maximum correction capacity of r erroneous bits per code word; - in a first decoding cycle: - (220) performing a decoding of the received code word; - (230) determining whether the code word contains a number of erroneous bits less than or equal to r-1; - (240) if not, invert a data bit in the code word to generate a one-bit inverted version of the code word; - repeating a new decoding cycle with the preceding steps (220) to (240) for each version of the code word with inversion of a bit which is generated, as long as the number of erroneous bits is greater than r-1 or a maximum number of bits to be inverted is reached, the step of inverting a bit consisting in each new cycle of resetting to its initial state the value of the bit inverted in the previous cycle, and of inverting the value of a new bit in the received code word; and - deliver a corrected data word if the number of erroneous bits in the received code word or in a version of the code word with one bit inversion is less than r.

11. The method according to claim 10 comprising before the step (430) of determining whether the code word contains a number of erroneous bits less than r, a step (425) of calculating total parity making it possible to determine the presence of uncorrectable error in the code word.

12. The method according to claim 10 or 11 implemented in an electronic system of FPGA or ASIC type comprising a resistive memory or a flash memory, an ECC encoder and an error correction device according to any one of claims 1 to 8.

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