Switching step-down converter

Abstract

Switching buck converter The present description relates to a switching buck converter (3). A first terminal (200) receives a regulated voltage and is coupled to a reference potential (GND) by a resistive element (R). A main loop (208) regulates the regulated voltage from a comparison of a first voltage (Vfb) on the first terminal to a first threshold. A circuit (C) activates a current source (CS) providing a first current (I1) to the first terminal (200) when the first voltage is lower than a second threshold. A current loop (A2) regulates the first voltage to the value of a third threshold by drawing a second current (I2) on the first terminal (200) if the first voltage is higher than the third threshold. Figure for abstract: Fig. 2

Description

Title of the invention: Switching step-down converter Technical field

[0001] The present description relates generally to electronic circuits, and, more particularly, to buck switched mode power supply converters. Prior art

[0002] [Fig.l] illustrates an example of a device 1 comprising a switching step-down converter 2.

[0003] The converter 2 is configured to regulate a voltage Vout to a set value determined by a threshold Thl.

[0004] The converter 2 comprises a terminal 200 configured to receive the regulated voltage Vout. The converter 2 comprises a resistive element R (delimited by dotted lines in [Fig.l]) coupling the terminal 200 to a terminal 202 of the converter 2, the terminal 2 being configured to receive a reference potential GND, for example ground. For example, one terminal of the element R is connected to the terminal 200 and another terminal of the element R is connected to the terminal 202.

[0005] The converter 2 comprises a high side switch HS. The switch HS is connected between a terminal 204 of the converter 2 and an output terminal 206 of the converter 2. The terminal 204 is configured to receive a supply potential Vin, the potential Vin being greater than the potential GND and the set value of the regulated voltage Vout.

[0006] Terminals 200 and 206 of converter 2 are configured to be coupled to each other. Preferably, as is the case in device 1, terminals 200 and 206 are coupled to each other by an inductor L. For example, one terminal of inductor L is connected to terminal 200, another terminal of inductor L being connected to terminal 206. Preferably, inductor L is not part of converter 2.

[0007] Terminals 200 and 202 of converter 2 are configured to be coupled to each other by a capacitive element C. Regulated voltage Vout is available across element C. For example, one terminal of element C is connected to terminal 200, another terminal of element C being connected to terminal 202. Preferably, element C is not part of converter 2. For example, element C corresponds to a smoothing capacitor and / or to a capacitor of a load (not shown in [Fig.l]) powered by voltage Vout.

[0008] In the example of [Fig.l], the converter 2 further comprises a switch of low side LS. The LS switch is connected between terminals 206 and 202.

[0009] The converter 2 comprises a main regulation loop 208 (delimited by dotted lines in [Fig. 1]).

[0010] Loop 208 is configured to compare voltage Vfb on terminal 200 with threshold Thl, and to control switches HS and LS on the basis of the result of this comparison so as to regulate voltage Vfb, and therefore voltage Vout, to its setpoint value. For example, the value of threshold Thl is equal to the setpoint value of voltage Vout.

[0011] By way of example, the control loop 208 controls the switches HS and LS in pulse width modulation (PWM) and / or in pulse frequency modulation (PFM) and / or in pulse skip modulation (PSM).

[0012] By way of example, the regulation loop 208 comprises an operational amplifier AMP1 configured to compare the voltage Vfb to the threshold Thl, and to provide a signal sigl resulting from this comparison.

[0013] For example, the amplifier AMP1 has an input receiving a voltage Vfbl determined by the voltage Vfb, another input receiving a voltage Vthl determined by the threshold Thl, and an output providing the signal sigl. For example, the resistive element R is a voltage divider bridge comprising two resistors RI and R2 connected to each other in series between the terminals 200 and 202, and the voltage Vfbl is available on a node connecting the resistors RI and R2 together. The values ​​of the resistors RI and R2, and those of the voltage Vthl are then determined so that the comparison of the voltage Vthl to the voltage Vfbl amounts to comparing the voltage Vfb to the threshold Thl.

[0014] For example, loop 208 includes a CTRL circuit configured to receive signal sigl, and to control switches HS and LS based on signal sigl.

[0015] More particularly, the loop 208 is configured to control switching of the switches HS and LS in a manner capable of increasing the value of the voltage Vout when the voltage Vfb is lower than the threshold Thl. In other words, the loop 208 is configured to increase the regulated voltage Vout when the voltage Vfb is lower than the Thl.

[0016] Thus, when the voltage Vout decreases below its set value and the voltage Vfb becomes lower than the threshold Thl, the regulation loop 208 controls the switches HS and LS so that the voltage Vout increases towards its set value. When the voltage Vout increases and becomes greater than or equal to its set value, the result is that the voltage Vfb becomes greater than or equal to the threshold Thl. Preferably, once the voltage Vfb is greater than or equal to the threshold Thl, the loop 208 no longer controls the switches HS and LS so as to increase the voltage Vout.

[0017] The operation described above is true as long as terminal 200 receives the voltage Vout, that is to say as long as the voltage Vfb is equal to Vout.

[0018] Indeed, if terminal 200 is disconnected from voltage Vout, that is to say that terminal 200 no longer receives voltage Vout, for example, because a solder of a wire or a conductive track to terminal 200 is destroyed or defective, resistive element R draws the potential of terminal 200 to the potential of terminal 202, from which it follows that voltage Vfb is zero.

[0019] The voltage Vfb is then lower than the threshold Thl and the loop 208 therefore controls the switches HS and LS so as to increase the voltage Vout. In the absence of a disconnection between the voltage Vout and the terminal 200, this would have resulted in an increase in the voltage Vfb. However, although the voltage Vout increases, the voltage Vfb remains zero due to the disconnection between the voltage Vout and the terminal 200. The voltage Vout then increases well above its set value and can reach values ​​likely to damage a load supplied by the voltage Vout, or even to damage the converter 2 itself, which is not desirable.

[0020] Although this is not shown in [Fig.l], there are converters similar to converter 2 further comprising a circuit configured to detect an undervoltage of the voltage Vout relative to its setpoint value. This circuit is configured to compare the voltage Vfb to a threshold Th2 lower than the threshold Thl. This circuit is further configured to activate an alarm signal when the voltage Vfb remains below the threshold Th2 for a duration greater than a debounce period. When terminal 200 is properly connected to the voltage Vout, activation of the alarm signal means that the voltage Vout has fallen below a low value lower than its setpoint value for a duration greater than the debounce period, i.e. there is an undervoltage detected on the voltage Vout.

[0021] When there is a disconnection between terminal 200 and voltage Vout, because voltage Vfb is zero, this signal detecting an undervoltage of voltage Vout is therefore activated at the end of the debounce period. One could therefore consider using this alarm signal to deactivate the main regulation loop so that, in the event of a disconnection between terminal 200 and voltage Vout, voltage Vout does not increase to values ​​that could damage the converter or the load it supplies.

[0022] However, this would lead to deactivations of the main regulation loop in the event of undervoltage of the voltage Vout while terminal 200 is properly connected to the voltage Vout, which is not desirable.

[0023] Furthermore, in the event of a disconnection between terminal 200 and voltage Vout, voltage Vout would still have time, during the debounce period preceding activation of the alarm signal, to reach values ​​likely to damage the converter or the load it supplies, which is not desirable. Summary of the invention

[0024] There is a need to overcome all or part of the disadvantages of known switching step-down converters, for example switching step-down converters of the type described in relation to [Fig.l].

[0025] For example, there is a need to overcome all or part of these drawbacks when they result from, or are linked to, a disconnection between the voltage regulated by the converter and a terminal of the converter configured to receive this regulated voltage, that is to say when these drawbacks result from a disconnection between this terminal of the converter and a node external to the converter on which the voltage regulated by the converter is available.

[0026] One embodiment overcomes all or part of the drawbacks of known switching step-down converters.

[0027] One embodiment provides a switching step-down converter comprising: - a first terminal configured to receive a voltage regulated by the converter; - a resistive element coupling the first terminal and a second terminal configured to receive a reference potential; - a main control loop configured for: * compare a first voltage on the first terminal with a first threshold, and * regulate, on the basis of this comparison, the regulated voltage to a set value determined by the first threshold by controlling a high side switch of the converter or the high side switch and a low side switch of the converter, - a selectively activatable current source configured in the active state to provide a first current to the first terminal; - an activation circuit configured to activate the current source for at least a first duration when the first voltage becomes lower than a second threshold lower than the first threshold; and - a current control loop configured for: * compare the first voltage to a third threshold higher than the first threshold, * regulate the first voltage to the value of the third threshold by drawing a second current on the first terminal if the first voltage is greater than the third threshold, and * do nothing if the first voltage is lower than the third threshold.

[0028] According to one embodiment, a product of a value of the resistive element by a value of the first current is greater than the third threshold.

[0029] According to one embodiment, the main control loop is configured to increase the regulated voltage when the first voltage is below the first threshold.

[0030] According to one embodiment, the current source is connected between the first terminal and a terminal of the converter configured to receive a supply potential.

[0031] According to one embodiment, the current regulation loop is configured so that, when the first voltage is greater than the third threshold, the second current drawn on the first terminal has a value determined by the difference between the first voltage and the third threshold.

[0032] According to one embodiment, the current regulation loop comprises a transimpedance amplifier having a first input configured to receive a voltage determined by the first voltage, a second input configured to receive a voltage determined by the third threshold, and an output coupled, preferably connected, to the first terminal and configured to draw the second current on the first terminal when the first voltage is greater than the third threshold.

[0033] According to one embodiment, the transimpedance amplifier comprises: - a differential pair receiving the respective inputs of the transimpedance amplifier; and - a transistor coupling the output of the transimpedance amplifier to the second terminal, a gate of the transistor being controlled by the differential pair.

[0034] According to one embodiment, the current regulation loop comprises a detection circuit configured to detect that the second current is non-zero, and to provide a signal indicating when the second current is non-zero, the detection circuit comprising: - a transistor connected between a node and the second terminal and having a gate connected to the gate of the transimpedance amplifier transistor, and - another transistor configured to supply a current to said node, the signal indicating when the second current is non-zero being determined from a potential of said node.

[0035] According to one embodiment, the current control loop comprises a detection circuit configured to detect that the second current is non-zero, and to provide a signal indicating when the second current is non-zero.

[0036] According to one embodiment, the activation circuit comprises: - a comparator configured to compare the first voltage to the second threshold and to provide a binary signal indicating the result of said comparison; and - a circuit receiving said binary signal and being configured to activate the current source for at least the first duration when the binary signal switches to a state indicating that the first voltage is lower than the second threshold.

[0037] According to one embodiment, a value of the first current is configured so that, when the first terminal receives the regulated voltage, a variation in the regulated voltage during the first duration when the first terminal receives the first current is negligible, for example so that an increase in the regulated voltage caused by the first current has a slope of less than 10 pV per microsecond.

[0038] According to one embodiment, the first duration is greater than the reaction time of the current regulation loop.

[0039] According to one embodiment: - the converter includes a third terminal; - the high side switch is connected between a terminal configured to receive a supply potential and the third terminal; and - the converter is configured so that its first and third terminals are coupled together, preferably by an inductance, and so that a capacitive element is connected between its second and first terminals.

[0040] According to one embodiment, the main regulation loop is configured to control switchings of the high side switch or the high side and low side switches so as to increase the regulated voltage when the first voltage is lower than the first threshold.

[0041] Another embodiment provides a device comprising a converter as defined above, an inductor connected between the first and third terminals of the converter and a capacitive element connected between the first and second terminals of the converter. Brief description of the drawings

[0042] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0043] [Fig.l], described previously, represents a device comprising an example of a switching step-down converter;

[0044] [Fig.2] represents an exemplary embodiment of a switching step-down converter;

[0045] [Fig.3] represents an example of implementation of a circuit of the converter of [Fig.2] according to one embodiment;

[0046] [Fig.4] illustrates by means of timing diagrams an example of operation of a switching step-down converter comprising an undervoltage detection circuit as described previously;

[0047] [Fig.5] illustrates by means of timing diagrams an example of operation of the converter of [Fig.2]. Description of the embodiments

[0048] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different examples and embodiments may have the same references and may have identical structural, dimensional and material properties.

[0049] For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed. In particular, the various circuits that can be powered by a voltage regulated by a switching step-down converter have not been detailed, these circuits also being able to be powered by a voltage regulated by a switching step-down converter according to the embodiments and variants described.

[0050] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0051] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0052] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0053] [Fig. 2] shows an example of a switching step-down converter 3 according to one embodiment. Although not illustrated in [Fig. 2], the converter 3 can be used in the device 1 of [Fig. 1], instead of the converter 2.

[0054] Converter 3 comprises, like converter 2 of [Fig.l], terminals 200, 202, 204 and 206, switch HS, switch LS, resistive element R and main regulation loop 208.

[0055] However, compared to converter 2, converter 3 further comprises a secondary regulation loop, or current regulation loop, A2, a selectively activatable current source CS, and an activation circuit C.

[0056] The current source CS is configured, when it is controlled in the active state, to supply a current II to the terminal 200. For example, the current source CS is connected to the terminal 200, for example between the terminal 204 and the terminal 200. The current II is a direct current (DC). When it is in the inactive state, the CS current source does not deliver current.

[0057] Thus, when terminal 200 is disconnected from voltage Vout and current source CS is activated, current source CS is in series with resistive element R and current II flows in resistive element R.

[0058] The circuit C is configured to activate the current source CS for at least a duration Tl when the voltage Vfb becomes lower than a threshold Th2. The threshold Th2 is lower than the threshold Thl.

[0059] For example, the circuit CS is configured to compare the voltage Vfb with the threshold Th2, and to activate the source CS for at least the duration T1 when the result of this comparison indicates that the voltage Vfb has just passed below the threshold Th2. No delay other than those linked to the propagation of the signals is provided between the moment when the voltage Vfb has just passed below the threshold Th2 and the moment when the circuit C activates the current source CS. Furthermore, because the current source CS is activated for at least the duration T1 when the voltage Vfb passes below the threshold Th2, the source CS remains activated for the entire duration T1 even if the voltage Vfb rises above the threshold Th2 before the end of the duration TL.

[0060] As an example, the circuit CS comprises a comparator COMP2 configured to compare the voltage Vfb with the threshold Th2, and to provide a signal sig2 indicating the result of this comparison. As an example, the signal sig2 is a binary signal. As an example, the comparator COMP2 has a first input receiving a voltage determined by the voltage Vfb, a second input receiving a voltage Vth2 determined by the threshold Th2, and an output providing the signal sig2. In the example illustrated in [Fig.2], the first input of the circuit COMP2 directly receives the voltage Vfb.

[0061] As an example, the circuit CS comprises a circuit PG in addition to the comparator COMP2. The circuit PG is configured to receive the signal sig2, and to activate the current source CS for at least the duration T1 when this signal sig2 switches to a state indicating that the voltage Vfb is lower than the threshold Th2.

[0062] The current control loop A2 is configured to compare the voltage Vfb to a threshold Th3. The threshold Th3 is greater than the threshold Thl.

[0063] The regulation loop A2 is further configured, when the voltage Vfb is greater than the threshold Th3, to regulate the voltage Vfb to the value of the threshold Th3.

[0064] Thus, if the voltage Vfb is greater than the threshold Th3, it is also greater than the threshold Thl, from which it follows that the main regulation loop 208 does not control the switches HS and LS so as to increase the voltage Vout. It follows that, when the voltage Vfb is greater than the threshold Th3, the voltage Vout does not increase due to an action of the main regulation loop 208.

[0065] More particularly, when the voltage Vfb is greater than the threshold Th3, the loop of regulation A2 is configured to regulate the voltage Vfb to the value of the threshold Th3 by drawing a current 12 on the terminal 200. Preferably, the value of the current 12 drawn on the terminal 200 when the voltage Vfb is greater than the threshold Th3 is determined, for example is proportional, to the difference between the voltage Vfb and the threshold Th3.

[0066] Furthermore, when the voltage Vfb is lower than the threshold Th3, the current regulation loop A2 is configured not to regulate the voltage Vfb, i.e. not to supply or draw current from the terminal 200. In other words, when the voltage Vfb is lower than the threshold Th3, the loop A2 is configured not to do anything.

[0067] The operation of the converter 3 when terminal 200 is suddenly disconnected from the voltage Vout is therefore as follows.

[0068] First, the voltage Vfb is pulled to the potential GND by the resistive element R, and therefore passes below the threshold Th2.

[0069] This causes the current source CS to be activated for at least a duration T1.

[0070] Activation of the current source CS causes the current II to flow in the resistive element, and that the voltage Vfb is established at a value greater than the threshold Th3. The product of the current II by the value of the resistive element R is therefore greater than the threshold Th3. Preferably, the product of the current II by the resistive element R is less than a maximum value of the voltage Vfb beyond which one or more circuits of the converter 3 could be damaged.

[0071] Because the voltage Vfb is greater than the threshold Th3, the current regulation loop A2 starts to draw the current 12 on the terminal 200. As a result, the current flowing in the resistive element R is equal to the current II minus the current 12, and the voltage Vfb decreases until it reaches the value of the threshold Th3.

[0072] Since the threshold Th3 is greater than the threshold Thl, the main regulation loop 208 does not increase the value of the voltage Vout as long as the voltage Vfb remains regulated to the value of the threshold Th3 by the regulation loop A2. Thus, as long as the value Vfb is regulated to the value of the threshold Th3 by the loop A2, the voltage Vout does not increase to reach values ​​which could damage the converter 3 or the load which it supplies.

[0073] Furthermore, when terminal 200 is properly connected to voltage Vout, the operation of converter 3 is as follows.

[0074] If terminal 200 receives voltage Vout, and voltage Vout is greater than threshold Th2, main control loop 208 regulates voltage Vout to its set value by comparing voltage Vfb, hence Vout, to threshold Thl and controlling switches HS and LS accordingly. Voltage Vfb is then less than threshold Th3, and loop 2 does not draw current from terminal 200. The operation of converter 3 is then identical to that of converter 2, circuits C, CS and A2 having no influence on this operation here.

[0075] If terminal 200 does receive voltage Vont, and voltage Vont is lower than threshold Th2, for example because converter 3 is in a start-up phase or because the load powered by converter 3 draws a current which causes voltage Vout to become lower than threshold Th2, circuit C activates current source CS for at least duration T1. Current II is then supplied to terminal 200, i.e. to the load powered by the converter, capacitive element C and resistive element R. The value of current II is configured so that, in this case, the variation in voltage Vout induced by the supply of current II to terminal 200 for duration T1 is negligible. Thus, voltage Vout, and therefore voltage Vfb, remain lower than threshold Th3, which means that loop A2 does not draw any current from terminal 200.Since loop A2 does not draw any current from terminal 200 and the activation of current source CS has only a negligible influence on the value of voltage Vout, the operation of converter 3 is then identical to that of converter 2, circuits C, CS and A2 having no influence on this operation here.

[0076] Preferably, the duration T1 is chosen to be greater than the reaction time of the loop A2, or, in other words, is determined by the bandwidth of the loop A2. This allows that, in the event of a disconnection between the terminal 200 and the voltage Vout, the current source CS is still supplying the current II to the terminal 200 when the loop A2 begins to draw a non-zero current I2 on this terminal.

[0077] By way of example, the current II is configured so that an increase in the regulated voltage caused by the supply of the current II to the terminal 200 has a slope of less than 10 pV per microsecond. For example, since the capacitive element C has a generally high value, for example greater than 10 pF, the current II is for example chosen to be less than 100 pA, from which it follows that the slope of the increase in the voltage Vout resulting solely from the supply of the current II to the terminal 200 is less than 10 pV per microsecond.

[0078] For example, circuit A2 comprises an operational transimpedance amplifier (OTA). The OTA amplifier has a first input configured to receive a voltage determined by voltage Vfb, a second input configured to receive a voltage determined by threshold Th3, and an output coupled, preferably connected, to terminal 200. The output of the OTA amplifier is configured to draw current I2 on terminal 200 when voltage Vfb is greater than threshold Th3.

[0079] For example, the OPA amplifier receives a voltage Vfb3 on its first input and a voltage Vth3 on its second input. For example, the resistive element R is a voltage divider bridge comprising three resistors R3, R4 and R5 connected in series between terminals 200 and 202 with resistor R5 connected to terminal 202, and the voltage Vfb3 is available on a node connecting resistors R5 and R4 together. In this example, the voltage Vfbl is for example available on the node connecting resistor R4 to resistor R3. The values ​​of resistors R3, R4, and R5 are then determined so that comparing voltage Vthl to voltage Vfbl amounts to comparing voltage Vfb to threshold Thl and comparing voltage Vfb3 to voltage Vth3 amounts to comparing voltage Vfb to threshold Th3. In this particular example, the values ​​of resistors R3, R4, and R5 are preferably determined so that voltages Vthl and Vth3 are equal, which makes it possible to generate only one voltage instead of two, for example with a band-gap circuit.

[0080] An exemplary embodiment of a converter 3 has been described above for protecting a load supplied by the regulated voltage Vout from a disconnection between terminal 200 and voltage Vout.

[0081] It may be desirable for the converter 3 to indicate when such a disconnection occurs.

[0082] Thus, optionally, loop A2 is configured to provide a signal FBDIS indicating when such a disconnection occurs. For example, loop A2 is configured to indicate when a non-zero current I2 is drawn on terminal 200. Indeed, when loop 200 draws a non-zero current I2 on terminal 200, this means that terminal 200 is disconnected from voltage Vout.

[0083] By way of example, the current regulation loop comprises a detection circuit DET configured to detect that the current 12 is non-zero, for example greater than a non-zero current value, and to provide the signal FBDIS indicating when the current 12 is non-zero, or, in other words, indicating that the terminal 200 is not connected to the voltage Vout.

[0084] For example, when loop A2 includes the OTA amplifier as previously described, the DET circuit is coupled to the output of the OTA amplifier.

[0085] For example, when loop A2 is configured to provide the FBDIS signal, this signal can be provided on an output terminal (not shown in [Fig.2]) of the converter 3, for example so as to indicate to the environment of the converter 3 that the terminal 200 is disconnected from the voltage.

[0086] As an alternative or complementary example, when loop A2 is configured to provide the FBDIS signal, the main control loop 208 can be controlled by this FBDIS signal, for example so as to deactivate the control loop 208 when a disconnection of terminal 200 is detected. In the example of [Fig. 2], the FBDIS signal is provided to a LOGIC circuit, and the LOGIC circuit controls loop 208 from the FBDIS signal. In other examples not shown, the FBDIS signal is provided directly to loop 208 to control the latter.

[0087] Optionally, when loop A2 is configured to provide the FBDIS signal, the converter 3 further comprises a circuit for detecting undervoltage of the voltage Vout. In the example of [Fig.2], in the absence of a disconnection between terminal 200 and voltage Vout, it is considered that voltage Vout has an undervoltage if it is lower than a threshold Th5 lower than threshold Thl. The undervoltage detection circuit is then configured to detect when voltage Vfb is lower than threshold Th5 throughout an anti-bounce period and, if the FBDIS signal does not indicate a disconnection between terminal 200 and voltage Vout, to indicate with a true-UV alarm signal that voltage Vout has an undervoltage.

[0088] By way of example, the undervoltage detection circuit comprises a comparator configured to compare the voltage Vfb to the threshold Th5, to provide a UV signal, for example binary, indicating the result of this comparison. The undervoltage detection circuit further comprises a circuit configured to receive the UV signal and the FBDIS signal, and to provide the true-UV signal from the UV and FBDIS signals.

[0089] More particularly, in the example of [Fig.2], the threshold Th5 is considered equal to the threshold Th2. Thus, when the circuit C comprises the comparator COMP2, this comparator COMP2 can be shared between the circuit C and the undervoltage detection circuit, the UV signal then being available on the output of the comparator COMP2. The undervoltage detection circuit further comprises the LOGIC circuit configured to receive the UV and FBDIS signals, and to provide the true-UV signal. By way of example, this true-UV signal can be provided on an output terminal (not shown in [Fig.2]) of the converter 3, for example so as to indicate to the environment of the converter 3 that the voltage Vout has an undervoltage.

[0090] As an alternative example, when the thresholds Th5 and Th2 are equal, the true-UV signal can be determined solely from the UV signal, for example by the LOGIC circuit. Indeed, in this case: - if terminal 200 is disconnected from voltage Vout, voltage Vfb is first lower than threshold Th2 equal to Th5 before being regulated to the value of threshold Th3, and will therefore be higher than threshold Th2 at the end of the debounce period. Thus, at the end of the debounce period, the UV signal will no longer indicate that voltage Vfb is lower than threshold Th2 and the true-UV signal will not be activated; and - if terminal 200 is connected to voltage Vout, voltage Vfb will always be lower than threshold Th2 at the end of the debounce period if voltage Vout does indeed have an undervoltage. At the end of the debounce period, the UV signal will therefore indicate that voltage Vfb is lower than threshold Th2 and the true-UV signal will be activated

[0091] Optionally, the converter 3 further comprises an overvoltage detection circuit for the voltage Vout. The overvoltage detection circuit is configured to detect when the voltage Vfb is greater than a threshold. Th4 for a whole debounce period and, if so, to indicate with a true-OV alarm signal that the voltage Vout has an overvoltage. For example, this true-OV signal can be provided on an output terminal (not shown in [Fig.2]) of the converter 3, for example so as to indicate to the environment of the converter 3 that the voltage Vout has an overvoltage.

[0092] By way of example, the overvoltage detection circuit comprises a comparator COMP3 configured to compare the voltage Vfb to the threshold Th4, to provide a signal OV, for example binary, indicating the result of this comparison. The overvoltage detection circuit further comprises a circuit, for example the circuit LOGIC in the example of [Fig.2], configured to receive the signal OV, and to provide the true-OV signal from the signal OV. By way of example, the comparator COMP3 has a first input receiving a voltage determined by the voltage Vfb, a second input receiving a voltage Vth4 determined by the threshold Th4, and an output providing the signal OV. In the example illustrated in [Fig.2], the first input of the circuit COMP3 directly receives the voltage Vfb.

[0093] For example, the threshold Th4 is higher than the threshold Th3. Thus, when the terminal 200 is disconnected from the voltage, even if the voltage Vfb goes above the threshold Th4 when the current source CS switches from an inactive state to an active state, the voltage Vfb becomes lower than the threshold Th4 before the end of the debounce period due to the regulation of the voltage Vfb to the value of the threshold Th3 by the loop A2.

[0094] As an alternative example, when the threshold Th4 is less than or equal to the threshold Th3, when the signal OV indicates throughout the debounce period that the voltage Vfb is greater than the threshold Th4, the circuit providing the true-OV signal then determines this signal from the signal OV and the signal FBDIS. Indeed, at the end of this debounce period, the true-OV signal will only indicate an undervoltage if the signal FBDIS does not indicate a disconnection of the terminal 200 at the voltage Vout.

[0095] [Fig.3] represents an example of implementation of the circuit A2 of the converter of [Fig.2] according to one embodiment.

[0096] In the implementation of [Fig.3], circuit A2 includes the OTA amplifier.

[0097] The OTA amplifier comprises a differential pair 300 receiving the respective inputs of the OTA amplifier, namely the voltages Vfb3 and Vth3 in this example. The OTA amplifier further comprises a transistor T1 coupling the output of the OTA amplifier to the terminal 202, the output of the OTA amplifier being connected to the terminal 200 and a gate of the transistor T1 being controlled by the differential pair. More particularly, the transistor is controlled by the differential pair 300 such that the transistor T1 is blocked if the voltage Vfb3 is lower than the voltage Vth3 (voltage Vfb lower than the threshold Th3) and is conducting if the voltage Vfb3 is higher than the voltage Vth3 (voltage Vfb higher than the threshold Th3). When the transistor Tl is on, current 12 is drawn on terminal 200 by the output of the OTA amplifier. Preferably, the value of current 12 drawn on terminal 200, i.e. the on-state resistance of transistor Tl, when voltage Vfb3 is higher than voltage Vth3 depends on the difference between its two voltages.

[0098] For example, transistor T1 is an NMOS transistor and has its source coupled, preferably connected, to terminal 202, and its drain coupled, preferably connected, to terminal 200.

[0099] For example, the differential pair 300 comprises two transistors T2 and T3, for example two PMOS transistors. The transistor T2 receives the voltage Vfb3 on its gate and the transistor T3 receives the voltage Vth3 on its gate. The gate of the transistor T1 is then connected to the first conduction terminal of the transistor T3.

[0100] Transistors T2 and T3 have their first conduction terminals, for example their drains, coupled to terminal 202. For example, transistor T2, respectively T3, has its first conduction terminal coupled to terminal 202 by a transistor T4, respectively T5. Transistors T4 and T5 are, for example, NMOS transistors. Transistors T4 and T5 are connected in mirror image to each other. For example, transistor T4, respectively T5, has its source connected to terminal 202 and its drain connected to the first conduction terminal of transistor T2, respectively T3. Transistors T4 and T5 have their gates connected to each other and to the drain of transistor T4. Transistors T4 and T5 form, for example, an active load of differential pair 300.

[0101] The differential pair 300 is biased by a current source 302. The current source 302 is connected between the second conduction terminals, for example the sources, of the transistors T2 and T3 and a node 304 set to a supply potential VDD of the OTA amplifier. Preferably, the potential VDD is lower than the potential Vin ([Fig.2]).

[0102] By way of example, the current source 302 comprises a transistor T6, for example PMOS, connected between the node 304 and the second conduction terminals of the transistors T2 and T3, and a transistor T7, for example PMOS. The transistor T7 is configured so that a current I3 flows therein, and the transistors T6 and T7 are connected in mirror image of each other, so that a current Ibias determined by the current I7 flows in the transistor T6 and biases the differential pair 300. For example, the source of each of the transistors T6 and T7 is coupled, preferably connected, to the node 304, the gates of the transistors T6 and T7 are connected to each other and to the drain of the transistor T7, and the source of the transistor T6 is coupled, preferably connected, to the second conduction terminals of the transistors T3 and T2.

[0103] Preferably, the gate of transistor T1 is coupled to terminal 200 by a series connection of a resistor R6 and a capacitor C6.

[0104] In the example of [Fig.2], the control loop comprises the DET circuit optional.

[0105] The DET circuit comprises, in this example where the OTA circuit comprises the differential pair 300 and the transistor T1, a transistor T8 connected between a node 308 and the terminal 202, the gate of the transistor T8 being connected to the gate of the transistor T1. Thus, the current 14 flowing in the transistor T8 is determined by the current 12 in the transistor T1, for example is equal to the current 12. For example, the transistor T8 is an NMOS transistor having its source connected to the terminal 202 and its drain connected to the node 308.

[0106] The DET circuit further comprises a transistor T9, for example PMOS, configured to supply a current 15 to the node 308. The signal FBDIS is determined from the potential on the node 308. For example, the current 15 is determined so that the potential of the node 308 is below a threshold Th6 when the current 14 determined by the current 12, for example equal to the current 12, is greater than the current 15, and above this threshold Th6 when the current 14 is zero or less than the current 15. In other words, in an example where the current 14 is equal to the current 12, the DET circuit indicates that the current 12 is non-zero when the current 12 has a value greater than the value of the current 15.

[0107] For example, transistor T9 is mirror-connected to transistors T6 and T7 of current source 302. For example, transistor T9 has its source connected to node 302, its drain connected to node 308 and its gate connected to the gates of transistors T6 and T7.

[0108] As an example, to determine the signal FBDIS from the potential of the node 308, the circuit DET comprises a shaping circuit. For example, this shaping circuit comprises a comparator 310 configured to compare the potential of the node 308 to the threshold Th6, and to provide a binary signal sig resulting from this comparison. The comparator 310 is, for example, a Schmitt trigger. The signal FBDIS is determined from the signal sig. For example, the signal sig is provided at the input of an inverter 312 whose output provides the signal FBDIS. As an alternative example, the signal FBDIS is the signal sig.

[0109] Figures 4 and 5 illustrate the difference in operation of converter 3 compared to a converter 2 in which a circuit a UVDET signal for detecting an undervoltage of the voltage Vout would be used to indicate a disconnection between terminal 200 and the voltage Vout.

[0110] [Fig.4] illustrates by timing diagrams the operation of a converter 2 comprising a circuit for detecting undervoltage of the voltage Vout, this circuit being configured to provide a signal UVDET in the high state when at the end of a debouncing period TEMP during which the voltage Vfb has remained below a threshold Th2. [Fig.4] represents the evolution, in volts, of the voltage Vout, the voltage Vfb and the UVDET signal as a function of time t in milliseconds.

[0111] Before a time t0, terminal 200 is connected to voltage Vout, and voltage Vout is regulated to its set value. In this example, the set value of voltage Vout is equal to 3.3 V. Voltage Vfb is then, in this example, equal to threshold Thl.

[0112] At a time t0, the connection between terminal 200 and voltage Vout is interrupted, and terminal 200 no longer receives voltage Vout.

[0113] From time t0, voltage Vfb decreases. In particular, at time t1, voltage Vfb becomes lower than threshold Th2. In this example, threshold Th2 is equal to 1.2 V. As a result, a TEMP debounce period begins at time t1. In this example, the duration of the TEMP period is equal to approximately 25 ps.

[0114] At a time t2 equal to tl + TEMP, as the voltage Vfb has remained below the threshold Th2 for the entire duration TEMP, the signal UVDET is switched to the high state.

[0115] However, using this switching of the UVDET signal to deactivate the main regulation loop 208 is not sufficient. Indeed, during the duration TEMP, because the voltage Vfb is lower than the threshold Thl, the loop 208 has controlled the switches HS and LS so as to increase the voltage Vout. As a result, the voltage Vout increases from the instant t0, and quickly reaches, during the duration TEMP, values ​​likely to damage a load supplied by the voltage Vout. In the example of [Fig.4], the voltage Vout increases until it reaches 9 V at the end of the period TEMP.

[0116] [Fig.5] illustrates by means of timing diagrams the operation of the converter 3. [Fig.5] represents the evolution, in volts, of the voltage Vout, the voltage Vfb and the signal FBDIS as a function of time t in milliseconds.

[0117] Before time t0, the situation is the same as in [Fig.4].

[0118] At a time t0, the connection between terminal 200 and voltage Vout is interrupted, and terminal 200 no longer receives voltage Vout.

[0119] From time t0, voltage Vfb decreases. In particular, at time t1, voltage Vfb becomes lower than threshold Th2. In this example, as in [Fig.4], threshold Th2 is equal to 1.2 V. As a result, circuit C activates source CS for at least duration T1, and voltage Vfb rises to a value higher than threshold Thl and threshold Th3.

[0120] Because the voltage Vfb is higher than the threshold Th3, the regulation loop A2 starts to supply a non-zero current 12 to the terminal 200 and regulates the voltage Vfb to the value of the threshold Th3, as long as the source CS is active. In this example, the threshold Th3 is equal to 4 V. The circuit DET detects that the current 12 is non-zero, and switches the signal FBDIS to a state, here the high state, indicating that a disconnection of terminal 200 at the voltage Vout has been detected.

[0121] Furthermore, from time tl, because the voltage Vfb is greater than the threshold Thl, loop 208 does not control switches HS and LS so as to increase voltage Vout. On the contrary, from time tl, voltage Vout decreases with a slope determined by the consumption of the load supplied by voltage Vout and by the capacitance value of capacitive element C.

[0122] In this example, the signal FBDIS is used to deactivate the converter 3 when a disconnection between the terminal 200 and the voltage Vout is detected. Thus, at a time t3 after the time tl, for example equal here to tl+Tl, the converter 3 is deactivated, from which it follows that the voltage Vfb becomes zero and the signal FBDIS switches to its low state.

[0123] As can be seen in [Fig.5], the overvoltage on the voltage Vout resulting from a disconnection between terminal 200 and the voltage Vout is less than 200 mV in this example, which prevents damage to the load supplied by the voltage Vout.

[0124] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. For example, the implementation of circuits A2 and C is not limited to the exemplary embodiments described above.

[0125] In particular, although a converter 3 comprising an HS switch and an LS switch and a regulation loop 208 controlling these two switches has been described above, in other examples not illustrated, the LS switch is replaced by a diode having its anode connected to terminal 202, the loop 208 then being configured to control only the HS switch.

[0126] Furthermore, although examples have been described in which the voltages Vthl and Vth3 are equal and the respective voltages Vfbl and Vfb3 are different, the person skilled in the art will be able to adapt these examples to cases where these two voltages Vthl and Vth3 are different and the corresponding voltages Vthl and Vth3 are different.

[0127] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, the person skilled in the art will be able to determine the value of the resistive element R, the value of the current II, the duration Tl, etc. to obtain the operation described above.

Claims

Claims

1. A switching step-down converter (3) comprising: - a first terminal (200) configured to receive a voltage (Vout) regulated by the converter; - a resistive element (R) coupling the first terminal (200) and a second terminal (202) configured to receive a reference potential (GND); - a main regulation loop (208) configured to: * compare a first voltage (Vfb) on the first terminal with a first threshold (Thl), and * regulate, on the basis of this comparison, the regulated voltage (Vout) to a setpoint value determined by the first threshold by controlling a high-side switch (HS) of the converter or the high-side switch (HS) and a low-side switch (LS) of the converter, - a selectively activatable current source (CS) configured in the active state to supply a first current (II) to the first terminal (200);- an activation circuit (C) configured to activate the current source (CS) for at least a first duration (Tl) when the first voltage (Vfb) becomes lower than a second threshold (Th2) lower than the first threshold; and - a current regulation loop (A2) configured to: * compare the first voltage (Vfb) to a third threshold (Th3) higher than the first threshold, * regulate the first voltage (Vfb) to the value of the third threshold by drawing a second current (12) on the first terminal (200) if the first voltage is higher than the third threshold, and * do nothing if the first voltage (Vfb) is lower than the third threshold (Th3).;

2. Converter according to claim 1, in which a product of a value of the resistive element (R) by a value of the first current (II) is greater than the third threshold (Th3).

3. Converter according to claim 1 or 2, in which the main regulation loop (208) is configured to increase the regulated voltage (Vout) when the first voltage (Vfb) is lower than the first threshold (Thl).

4. Converter according to any one of claims 1 to 3, wherein the current source (CS) is connected between the first terminal (200) and a terminal (204) of the converter configured to receive a supply potential (Vin).

5. Converter according to any one of claims 1 to 4, in which the current regulation loop (A2) is configured so that, when the first voltage (Vfb) is greater than the third threshold (Th3), the second current (12) drawn on the first terminal (200) has a value determined by the difference between the first voltage (Vfb) and the third threshold (Th3).

6. A converter according to any one of claims 1 to 5, wherein the current regulation loop (A2) comprises a transimpedance amplifier (OTA) having a first input configured to receive a voltage (Vfb3) determined by the first voltage (Vfb), a second input configured to receive a voltage (Vth3) determined by the third threshold (Th3), and an output coupled, preferably connected, to the first terminal (200) and configured to draw the second current (12) on the first terminal when the first voltage (Vfb) is greater than the third threshold (Th3).

7. Converter according to claim 6, wherein the transimpedance amplifier (OTA) comprises: - a differential pair (300; T2, T3) receiving the respective inputs of the transimpedance amplifier; and - a transistor (T1) coupling the output (200) of the transimpedance amplifier to the second terminal (202), a gate of the transistor being controlled by the differential pair.

8. Converter according to claim 7, wherein the current regulation loop (A2) comprises a detection circuit (DET) configured to detect that the second current (12) is non-zero, and to provide a signal (FBDIS) indicating when the second current is non-zero, the detection circuit comprising: - a transistor (T8) connected between a node (308) and the second terminal (202) and having a gate connected to the gate of the transistor (T1) of the transimpedance amplifier (OTA), and - another transistor (T9) configured to provide a current (15) to said node, the signal indicating when the second current is non-zero (FBDIS) being determined from a potential of said node (308).

9. Converter according to any one of claims 1 to 7, in which the current regulation loop (A2) comprises a detection circuit (DET) configured to detect that the second current (12) is non-zero, and to provide a signal (FBDIS) indicating when the second current is non-zero.

10. Converter according to any one of claims 1 to 9, wherein the activation circuit (C) comprises: - a comparator (COMP2) configured to compare the first voltage (Vfb) with the second threshold (Th2) and to provide a binary signal (UV) indicating the result of said comparison; and - a circuit (PG) receiving said binary signal (UV) and being configured to activate the current source (CS) for at least the first duration (Tl) when the binary signal switches to a state indicating that the first voltage (Vfb) is lower than the second threshold (Th2).

11. A converter according to any one of claims 1 to 10, wherein a value of the first current (II) is configured so that, when the first terminal (200) receives the regulated voltage (Vout), a variation in the regulated voltage (Vout) during the first duration (Tl) when the first terminal (200) receives the first current (II) is negligible, for example so that an increase in the regulated voltage caused by the first current has a slope of less than 10 pV per microsecond.

12. Converter according to any one of claims 1 to 11, in which the first duration (T1) is greater than the reaction time of the current regulation loop (A2).

13. Converter according to any one of claims 1 to 12, wherein: - the converter (3) comprises a third terminal (206); - the high side switch (HS) is connected between a terminal (204) configured to receive a supply potential (Vin) and the third terminal (206); and - the converter is configured so that its first and third terminals (200, 206) are coupled together, preferably by an inductance (L), and so that a capacitive element (C) is connected between its second and first terminals (202, 200).

14. Converter according to claim 13, wherein the main regulation loop (208) is configured to control switchings of the high side switch (HS) or of the high side (HS) and low side (LS) switches so as to increase the regulated voltage (Vout) when the first voltage (Vfb) is lower than the first threshold (Thl).

15. Device (1) comprising a converter (3) according to claim 13 or 14, an inductance (L) connected between the first and third terminals (200, 206) of the converter and a capacitive element (C) connected between the first and second terminals (200, 202) of the converter.

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