Radio frequency amplifier

Abstract

Radio Frequency Amplifier The present description relates to an amplifier (100). A first transistor (Mcg1) couples a first input node (In1) to a first output node (Out1). A second transistor (Mcg2) couples a second input node (In2) to a second output node (Out2). The control terminals of the first and second transistors are connected. A third transistor (Mcs1) has a control terminal connected to the first input node and a conduction terminal connected to the second output node. A fourth transistor (Mcs1) has a control terminal connected to the second input node and a conduction terminal connected to the first output node. A circuit (CTRL1) controls a current (I1, I2; It) in the first and second transistors (Mcg1, Mcg2). A circuit (CTRL2) provides a control signal to the control terminals of the first and second transistors (Mcg1, Mcg2). Figure for abstract: Fig. 1

Description

Title of the invention: Radiofrequency amplifier Technical field

[0001] The present description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, to radiofrequency circuits configured to operate at frequencies for example between 3 kHz and 300 GHz, preferably between 1 GHz and 100 GHz. Prior art

[0002] Many radio frequency electronic circuits include radio frequency amplifiers configured to receive a radio frequency signal between two input nodes of the amplifier, and to provide a corresponding amplified radio frequency signal between two output nodes of the amplifier. Summary of the invention

[0003] There is a need to overcome all or part of the disadvantages of known radiofrequency amplifiers.

[0004] For example, it would be desirable to have a radio frequency amplifier in which the gain and input impedance of the amplifier can be adjusted independently of each other.

[0005] For example, it would be desirable to have a radio frequency amplifier suitable for low voltage applications, for example applications where the amplifier receives a nominal supply voltage substantially equal to 1.8 V.

[0006] For example, it would be desirable to have a radio frequency amplifier having good stability conditions.

[0007] For example, it would be desirable to have a radiofrequency amplifier having good isolation between its two input nodes and its two output nodes.

[0008] One embodiment overcomes all or part of the drawbacks of known radiofrequency amplifiers.

[0009] One embodiment provides an amplifier comprising: a first input node and a second input node; a first output node and a second output node; a first transistor coupling the first input node to the first output node; a second transistor identical to the first, coupling the second input node to the second output node, the first and second transistors having their control terminals connected to each other; a third transistor having a control terminal connected to the first node input and a first conduction terminal connected to the second output node; a fourth transistor identical to the third, having a control terminal connected to the second input node and a first conduction terminal connected to the first output node; a first circuit configured to control a current flowing through the first and second transistors; and a second circuit configured to control a control signal applied to the control terminals of the first and second transistors.

[0010] According to one embodiment, a ratio between a value of a capacitance between the conduction terminals of each of the first and second transistors and a capacitance value between the control terminal and the first conduction terminal of each of the third and fourth transistors is between 0.8 and 1.2, preferably between 0.9 and 1.1, for example equal to 1.

[0011] According to one embodiment: each of the third and fourth transistors has a second conduction terminal connected to a node for applying a first supply potential; and each of the first and second output nodes is coupled to a node for applying a second supply potential.

[0012] According to one embodiment, a first inductor couples the first output node to the node of application of the second supply potential and a second inductor couples the second output node to the node of application of the second supply potential.

[0013] According to one embodiment, the first and second inductances constitute a primary winding of a transformer.

[0014] According to one embodiment, a capacitor has a first terminal connected to a connection node of the control terminals of the first and second transistors to each other.

[0015] According to one embodiment, the capacitor has a second connected to the application node of the first supply potential.

[0016] According to one embodiment, the amplifier comprises a summing node configured to receive the sum of the currents flowing in the first and second transistors, the first and second input nodes each being coupled to the summing node.

[0017] According to one embodiment, a third inductor couples the first input node to the summing node and a fourth inductor couples the second input node to the summing node.

[0018] According to one embodiment, the third and fourth inductances constitute a secondary winding of a transformer.

[0019] According to one embodiment: - the first circuit comprises a transistor connected between the summing node and the node for applying the first supply potential; - the first circuit comprises a control circuit configured to supply, to a control terminal of said transistor, a signal determining the value of the current in said transistor; and - the transistor connected between the summing node and the node for applying the first supply potential is preferably twice as large as each of the first and second transistors.

[0020] According to one embodiment, the control circuit of the first circuit comprises a transistor and a current source connected in series between the application nodes of the first and second supply potentials, said transistor being mounted in mirror with the transistor connected between the summing node and the application node of the first supply potential.

[0021] According to one embodiment, the second circuit comprises: an error amplifier having a first input connected to the summing node and an output coupled to the control terminals of the first and second transistors so as to apply thereto the control signal of the first and second transistors; and a control circuit configured to provide a reference signal to the second input of the error amplifier.

[0022] According to one embodiment, the control circuit of the second circuit comprises a current source and a transistor connected in series between the nodes of application of the first and second supply potentials, said transistor having a control terminal connected to the second input of the error amplifier and to a node of connection of said transistor to said current source.

[0023] According to one embodiment: a dimension ratio between the transistor of the control circuit of the first circuit and the transistor connected between the summing node and the node for applying the first supply potential determines, with a value of the current of the current source of the control circuit of the first circuit, a value of the current in each of the first and second transistors; and a dimension ratio between the transistor of the control circuit of the second circuit and the transistor connected between the summing node and the application node of the first supply potential determines, with a value of the current of the current source of the control circuit of the second circuit, a value of a control signal of each of the first and second transistors. Brief description of the drawings

[0024] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0025] [Fig.l] represents, schematically and partly in the form of blocks, an exemplary embodiment of a radiofrequency amplifier;

[0026] [Fig. 2] represents, schematically and partly in the form of blocks, a more detailed example of an embodiment of a radiofrequency amplifier;

[0027] [Fig. 3] schematically represents an exemplary embodiment of a part of a circuit of the amplifier of [Fig.2];

[0028] [Fig.4] schematically represents an exemplary embodiment of a part of another circuit of the amplifier of [Fig.2];

[0029] [Fig.5] illustrates by curves a gain adjustment of the amplifier of figures 1 and 2; and

[0030] [Fig.6] illustrates by curves an adjustment of the input impedance of the amplifier of figures 1 and 2; and

[0031] [Fig.7] illustrates by curves the isolation between the input nodes and the output nodes and the stability of the amplifier of figures 1 and 2. Description of the embodiments

[0032] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various known circuits, applications and electronic systems in which a radiofrequency amplifier is implemented have not been detailed, the described embodiments and variants being compatible with these known circuits, applications and electronic systems.

[0034] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0035] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., it is made reference unless otherwise specified to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0037] [Fig.l] represents, schematically and partly in the form of blocks, an exemplary embodiment of a radiofrequency amplifier 100.

[0038] The amplifier 100 comprises two input nodes Inl and In2. The amplifier 100 is configured to receive an input signal to be amplified between the nodes Inl and In2. For example, the input signal applied between the nodes Inl and In2 is a differential signal.

[0039] The amplifier 100 further comprises two output nodes Out1 and Out2. The amplifier 100 is configured to provide an amplified output signal between the nodes Out1 and Out2. For example, the output signal available between the nodes Out1 and Out2 is a differential signal.

[0040] The amplifier 100 comprises a pair of identical transistors Mcgl and Mcg2.

[0041] In this example, the transistors Mcgl and Mcg2 are MOS (Metal Oxide Semiconductor) transistors. In this example, the transistors Mcgl and Mcg2 are each mounted in a common gate.

[0042] The amplifier 100 is, for example, powered by a supply voltage defined by a difference between a first supply potential GND, for example ground, and a second supply potential VDD. In this example, the potential VDD is positive relative to the first supply potential, and the transistors Mcg1 and Mcg2 are then N-channel.

[0043] The transistor Mcgl couples the node Inl to the node Outl. For example, the transistor Mcgl has a first conduction terminal, for example its drain, coupled, preferably connected, to the node Outl and a second conduction terminal, for example its source, coupled, preferably connected, to the node Inl.

[0044] Symmetrically, the transistor Mcg2 couples the node In2 to the node Out2. For example, the transistor Mcg2 has a first conduction terminal, for example its drain, coupled, preferably connected, to the node Out2 and a second conduction terminal, for example its source, coupled, preferably connected, to the node In2.

[0045] The transistors Mcgl and Mcg2 are controlled in an identical manner, by a control circuit CTRL2. Thus, according to one embodiment, the transistors Mcgl and Mcg2 have their control terminals, for example their gates, connected to each other.

[0046] Preferably, a capacitor C, for example a smoothing capacitor, is connected to a node 102 for connecting the control terminals of the transistors Mcg1 and Mcg2 to each other. For example, the capacitor C has one terminal connected to the node 102, the other terminal of the capacitor C being, for example, connected to a node 104 configured to receive the first GND supply potential.

[0047] The amplifier 100 comprises another pair of identical transistors Mcsl and Mcs2.

[0048] Preferably, the transistors Mcsl and Mcs2 are transistors of the same technology as the transistors Mcgl and Mcg2, namely MOS in this example.

[0049] Furthermore, transistors Mcsl and Mcs2 are transistors of the same type as transistors Mcgl and Mcg2, namely N-channel MOS transistors in this example.

[0050] In this example, the transistors Mcsl and Mcs2 are each mounted as a common source.

[0051] The transistor Mcsl has a control terminal, for example its gate, connected to the node Inl, or, in other words, to the second conduction terminal of the transistor Mcgl. Furthermore, the transistor Mcsl has a first conduction terminal, for example its source, connected to the node 104.

[0052] Symmetrically, the transistor Mcs2 has a control terminal, for example its gate, connected to the node In2, or, in other words, to the second conduction terminal of the transistor Mcg2. Furthermore, the transistor Mcs2 has a first conduction terminal, for example its source, connected to the node 104.

[0053] Transistors Mcsl and Mcs2 have their second conduction terminals, for example their drains, coupled to the respective nodes Out2 and Outl. For example, the second conduction terminal of transistor Mcsl is connected to node Out2, the second conduction terminal of transistor Mcs2 being connected to node Inl.

[0054] The amplifier 100 further comprises a circuit CTRL1. The circuit CTRL1 is configured to control a current II, respectively 12, flowing in the transistor Mcgl, respectively Mcg2. The currents II and 12 are, in practice, direct currents (DC), or, in other words, bias currents. More particularly, the amplifier 100 and its circuit CTRL1 are configured so that the currents II and 12 are equal.

[0055] For example, the amplifier 100 is configured so that the MOS transistors Mcsl, Mcs2, Mcgl and Mcg2 are biased in their saturation regions.

[0056] For a given value of the currents II and I2 controlled by the circuit CTRL1, a modification of the value of the control signal applied to the control terminals of the transistors Mcgl and Mcg2 by the circuit CTRL2 results in a modification of the gain of the amplifier. Indeed, the modification of the control signal of the transistors Mcgl and Mcg2 for a given value of the currents II, I2 results in a modification of the signal on the control terminal of the transistors Mcsl and Mcs2, therefore a modification of the gain of the amplifier. This modification of the gain of the amplifier 100 does not result in a significant modification of the input impedance of the amplifier 100. For example, for a modification of 5 dB of the gain of the amplifier 100, the impedance input of amplifier 100 is changed from minus 50 ohms, for example from minus 30 ohms.

[0057] For example, the circuit CTRL2 regulates the control signal of the transistors Mcgl and Mcg2 to a value determined by a target gain value of the amplifier.

[0058] Symmetrically, for a given value of the control signal applied to the control terminals of the transistors Mcgl and Mcg2 by the circuit CTRL2, a modification of the value of the currents II and I2 by the circuit CTRL1 results in a modification of the input impedance of the amplifier 100. This modification of the input impedance of the amplifier 100 does not result in a significant modification of the gain of the amplifier 100. For example, for a modification by a factor of 2 of the input impedance of the amplifier 100, the gain of the amplifier 100 is modified by less than 2 dB, for example by less than 1 dB.

[0059] For example, the circuit CTRL1 regulates the currents II and I2 to a value determined by a target value of input impedance of the amplifier.

[0060] The amplifier 100 therefore allows independent adjustment of its gain and its input impedance.

[0061] According to one embodiment, the nodes Out1 and Out2 are each coupled to a node (not shown in [Fig.l]) for applying the potential VDD.

[0062] For example, node Out1 is coupled to potential VDD by an inductor, and node Out2 is coupled to potential VDD by another inductor.

[0063] For example, these two inductances may constitute the primary winding of a transformer configured to receive the output signal from the amplifier.

[0064] As another example, the two inductors are not part of a transformer, and each of the nodes Out1 and Out2 is further coupled to the node 104 by a corresponding capacitance. In this case, two alternating current (AC) components of a differential output signal can be received on these two capacitances.

[0065] As another example, each of the nodes Out1 and Out2 can be coupled to the potential VDD so as to implement a DC coupling of each of the nodes Out1 and Out2 with this potential VDD.

[0066] Because the transistors Mcsl and Mcgl are not connected in series between the potentials VDD and GND, and, symmetrically, because the transistors Mcs2 and Mcg2 are not connected in series between the potentials VDD and GND, these transistors can remain biased in their saturation zones with lower VDD potential values ​​than if these transistors had been connected in series. Thus, the amplifier 100 can be used in low voltage applications.

[0067] According to one embodiment, the transistors Mcgl and Mcs2 are configured so that the ratio Cr between the capacitance between the conduction terminals of the transistor Mcgl, in practice an intrinsic capacitance of the transistor Mcgl, by the capacitance between the control terminal and the second conduction terminal of the transistor Mcs2, corresponding in practice to an intrinsic capacitance of the transistor Mcs2, i.e. between 0.8 and 1.2, preferably between 0.9 and 1.1, for example equal to 1. This makes it possible to ensure good stability properties for the amplifier 100 and, in addition, good isolation between its input nodes Inl and In2 and its output nodes Outl and Outl. For example, this makes it possible to obtain a factor K greater than 4, for example greater than 10 when the ratio Cr is equal to 1, with K = (l-^Al 1| - ^|£22| + ^511^22-512*521| )(^215121 *i11) where S11, S22, S12 and S21 are the S parameters of the amplifier 100. For example, this makes it possible to obtain a power isolation S12 in dB of less than -35 dB, for example less than -44 dB when the ratio Cr is equal to 1.

[0068] In practice, choosing a ratio Cr included in the above ranges of values, preferably equal to 1, makes it possible to implement neutrodyning in the amplifier 100 without resorting to connecting capacitors and capacitor-mounted transistors, therefore without increasing the surface area of ​​the amplifier. Here, advantage is taken of the intrinsic capacities of the transistors Mcsl, Mcs2, Mcgl, Mcg2.

[0069] According to one embodiment, the nodes Inl and In2 are each coupled to a node 106 of the amplifier 100. The node 106 is a current summing node, configured to receive the sum It of the currents II and I2. Preferably, the nodes Inl and In2 are not directly connected to the node 106.

[0070] For example, node In1 is coupled to node 106 by an inductor, and node In2 is coupled to node 106 by another inductor.

[0071] For example, these two inductances can constitute the secondary winding of a transformer configured to apply the input signal of the amplifier.

[0072] As another example, the two inductors are not part of a transformer, and each of the nodes In1 and In2 is coupled to the node 104 by a corresponding capacitance. In this case, two alternating current (AC) components of an input differential signal can be applied to these two capacitances.

[0073] According to one embodiment, the circuit CTRL1 is connected to the node 106 and is configured to control the value of the current It so as to control the value of the currents II and I2 to a set value determining the value of the input impedance of the amplifier 100. By way of example, the circuit CTRL1 couples the node 106 to the node 104.

[0074] Preferably, node 106 is also a bias node configured to receive, for example from the circuit CTRL1, a continuous bias potential.

[0075] Alternatively (not shown), circuit CTRL1 may be configured to individually (or independently) control currents II and I2 in transistors Mcgl and Mcg2, so that these currents are equal.

[0076] According to one embodiment, the circuit CTRL2 is connected to the node 106 and is configured to control, for a given value of the currents II, I2, and therefore It, the control signal of the transistors Mcgl and Mcg2 so as to control, for each of the transistors Mcsl and Mcs2, the value of the control signal received by this transistor, and therefore the value of the gain of the amplifier.

[0077] For example, the circuit CTRL2 is connected to the node 106 to receive the potential of the node 106, and is configured to control the transistors Mcgl and Mcg2 so as to regulate the potential of the node 106 to a control value determining the value of the gain of the amplifier.

[0078] [Fig. 2] represents, schematically and partly in the form of blocks, a more detailed example of an embodiment of the radiofrequency amplifier 100.

[0079] The amplifier 100 of [Fig. 2] includes many elements in common with the amplifier 100 of [Fig. 1], and only the differences between these amplifiers are highlighted here. Thus, unless otherwise indicated, everything indicated in relation to [Fig. 1] applies to [Fig. 2].

[0080] In the example of amplifier 100 of [Fig.2], the node Out1, respectively Out2, is coupled to a node 200 for applying the potential VDD by an inductance Loi, respectively Lo2. The inductances Loi and Lo2 form, for example, the primary winding of a transformer receiving the output signal from the amplifier 100.

[0081] In the example of amplifier 100 of [Fig. 2], the node In1, respectively In2, is coupled to the node 106 by an inductance Lil, respectively Li2. The inductances Lil and Li2 form, for example, the secondary winding of a transformer providing the input signal of the amplifier 100.

[0082] In the exemplary embodiment of [Fig.2], the circuit CTRL1 of the amplifier 100 comprises a transistor Mr connected, by its conduction terminals, between the nodes 106 and 104.

[0083] Preferably, the transistor Mr is in the same technology as the transistors Mcgl and Mcg2, and is for example a MOS transistor when these transistors Mcgl and Mcg2 are MOS transistors.

[0084] Preferably, the transistor is of the same type as the transistors Mcgl and Mcg2, and is for example an N-channel MOS transistor when these transistors Mcgl and Mcg2 are N-channel MOS transistors.

[0085] For example, transistor Mr has a first conduction terminal, for example its source, coupled, preferably connected, to node 104, and a second conduction terminal, for example its drain, coupled, preferably connected, to node 106.

[0086] Preferably, the transistor Mr is twice as large as the transistors Mcgl and Mcg2.

[0087] In this exemplary embodiment, the circuit CTRL1 further comprises a control circuit BIAS1 for the transistor Mr. The circuit BIAS1 is configured to provide a control signal determining the value of the current It in the transistor Mr, therefore the value of the currents II and I2 in the respective transistors Mcgl and Mcg2. By way of example, the value of the signal provided by the BIAS circuit to the control terminal of the transistor Mr is determined by a target value of input impedance of the amplifier.

[0088] The circuit CTRL2 is configured to regulate the DC potential of the node 106, or, in other words, the DC potentials of the nodes Inl and In2, to a setpoint value determining the gain of the amplifier 100. In the exemplary embodiment of [Fig. 2], the circuit CTRL2 comprises an error amplifier Aerr. The amplifier Aerr has a first input, for example non-inverting (+), coupled, preferably connected, to the node 106. The circuit CTRL2 further comprises a control circuit BIAS2 configured to provide a setpoint signal to the second input, for example inverting (-), of the error amplifier Aerr. The output of the error amplifier Aerr determines the value of the control signal provided to the control terminals of the transistors Mcgl, Mcg2. For example, the output of the error amplifier Aerr is coupled to node 102, for example by a resistive element R as shown in the example of [Fig.2].

[0089] It will be noted that the implementation of the circuit CRTL1 as described in relation to [Fig.2] is independent of the implementation of the circuit CTRL2 as described in relation to [Fig.2]. Thus, the circuit CTRL1 can be implemented in the manner described above, without the circuit CTRL2 being implemented in the manner described above, and vice versa.

[0090] [Fig.3] schematically represents an example of an embodiment of the BIAS1 circuit of the CTRL1 circuit of the amplifier 100 of [Fig.2], it being understood that the person skilled in the art will be able to provide other implementations of this BIAS1 circuit, and more generally, of the CTRL1 circuit.

[0091] In this exemplary embodiment, the BIAS1 circuit includes a current source 300 and a transistor M31 connected in series between nodes 104 and 200. The transistor M31 is connected as a mirror image of the transistor Mr. For example, the transistor M31 has a first conduction terminal connected to node 104, a second conduction terminal coupled to the current source 300, and a control terminal connected to its second conduction terminal.

[0092] Transistor M31 is of the same technology and type as transistor Mr, and is, in this example, an N-channel MOS transistor. For example, its source is connected to node 104 and its drain is coupled to current source 300 and connected to the gate of transistor M31.

[0093] In the example of [Fig. 3], transistor M31 is coupled to current source 300 by a diode-connected transistor M32. Transistor M32 is preferably of the same technology and type as transistor M31, and is, in this example, an N-channel MOS transistor. For example, a first conduction terminal of transistor M32, in this example its source, is connected to the second conduction terminal of transistor M31, in this example its drain, and a second conduction terminal of transistor M32, for example its drain, is connected to one terminal of current source 300, the other terminal of current source 300 being connected to node 200.

[0094] The current source 300 is configured to provide a control current Icmdl. The value of the current Icmdl determines, with a size ratio of the transistors M31 and Mr, the value of the currents II and I2, therefore of the input impedance of the amplifier 100. For example, the circuit BIAS1 is configured so that the current It is equal to A times the current Icmdl, with A a positive factor, and the ratio of the dimensions of the transistor M31 to the ratio of the dimensions of the transistor Mr is equal to A. For example, when the transistor Mr is twice as large as each of the transistors Mcgl and Mcg2, the transistor M31 is 2A times as large as each of the transistors Mcgl and Mcg2.

[0095] [Fig.4] schematically represents an example of an embodiment of the BIAS2 circuit of the CTRL2 circuit of the amplifier 100 of [Fig.2], it being understood that the person skilled in the art will be able to provide other implementations of this BIAS2 circuit, and more generally, of the CTRL2 circuit.

[0096] In this exemplary embodiment, the BIAS2 circuit comprises a current source 400 and a transistor M4 connected in series between the nodes 104 and 200. The transistor M4 has a control terminal connected to the second input, for example inverting (-), of the error amplifier Aerr. Furthermore, the transistor M4 is connected as a diode, and has its control terminal connected to a connection node of the transistor M4 to the current source 400.

[0097] Preferably, the transistor M4 is of the same technology and the same type as the transistor Mr, and is, in this example, an N-channel MOS transistor. For example, its source is connected to the node 104 and its drain is coupled, for example connected, to the current source 400 and to the gate of the transistor M4.

[0098] The current source 400 is configured to provide a current Icmd2 of command. The value of the current Icmd2 determines, with the sizing of the transistor M4, the value of the reference signal supplied to the amplifier Aerr, or, more generally, the value of the control signal of the transistors Mcgl and Mgc2, therefore of the gain of the amplifier 100.

[0099] For example, when the circuit CTRL1 comprises the transistor Mr between the nodes 106 and 104, a dimension ratio between the transistor M4 and the transistor Mr determines, with a value of the current Icmd2, a value of a control signal of each of the transistors Mcgl and Mcg2, therefore, for a given value of the currents II and I2, a value of a control signal of each of the transistors Mcsl and Mcs2. By way of example, the circuit BIAS2 is configured so that the potential of the connection node of the transistor M4 to the current source 400 determines the value of the potential of the node 106.

[0100] [Fig.5] illustrates by curves 500 and 502 an example of adjustment of the gain of the amplifier 100. In this example, the curves 500 and 502 are obtained with the circuits CTRL1 and CTRL2 implemented in the manner described in relation to FIGS. 2 to 4, in particular with regard to the circuits BIAS1 and BIAS2.

[0101] Curve 500 illustrates the evolution of the gain G, in dB, of the amplifier 100 as a function of a setpoint value, this setpoint value corresponding here to the value of the current Icmd2, in pA. Curve 502 illustrates the evolution of the input impedance Rin, in ohms, of the amplifier 100 as a function of a setpoint value, here the value of the current Icmd2.

[0102] Curve 500 shows that, by varying the setpoint value of the circuit CTRL2, i.e. here the value of the current Icmd2, for example between 6 pA and 48 pA, it is possible to adjust the value of the gain G, for example to vary the value of the gain G between 4.5 dB and 11 dB.

[0103] Furthermore, curve 502 shows that this adjustment of the gain G by the circuit CTRL2 does not significantly modify the value of the input impedance Rin. In other words, when the gain G varies by one dB, the input impedance Rin varies by less than 10%, preferably by less than 5%.

[0104] For example, when the setpoint value of the circuit CTRL2, i.e. the value of the current Icmd2, varies between 6 pA and 48 pA, the value of the gain G varies between 4.5 dB and 11 dB, while the input impedance Rin remains between 225 and 198 ohms.

[0105] [Fig.6] illustrates by curves 600 and 602 an example of adjustment of the input impedance Rin of the amplifier 100. In this example, the curves 600 and 602 are obtained with the circuits CTRL1 and CTRL2 implemented in the manner described in relation to FIGS. 2 to 4, in particular with regard to the circuits BIAS1 and BIAS2.

[0106] Curve 600 illustrates the evolution of the gain G, in dB, of the amplifier 100 in function of a setpoint value, this setpoint value corresponding here to the value of the current Icmdl, in pA. Curve 602 illustrates the evolution of the input impedance Rin, in ohms, of the amplifier 100 as a function of a setpoint value, here the value of the current Icmdl.

[0107] Curve 602 shows that, by varying the setpoint value of the circuit CTRL1, that is to say here the value of the current Icmdl, for example between 6 pA and 48 pA, it is possible to adjust the value of the input impedance Rin, for example to vary the value of the impedance Rin between 150 and 500 ohms.

[0108] Furthermore, curve 600 shows that this adjustment of the impedance Rin by the circuit CTRL1 does not significantly modify the value of the gain G. For example, when the impedance Rin varies by a factor of 2, the gain G varies by less than 2 dB, preferably by less than 1 dB. In other words, when the impedance Rin varies, for example, by 100 ohms, the gain G varies by less than 1 dB.

[0109] For example, when the setpoint value of the circuit CTRL1, i.e. the value of the current Icmdl, varies between 6 pA and 48 pA, the value of the input impedance Rin varies between 150 and 500 ohms, while the gain G remains between 9.25 and 11.25 dB.

[0110] [Fig.7] illustrates by curves the evolution of the power isolation S12, in dB, between the nodes Inl, In2 and the nodes Outl, Out2 (curve 700) and of the stability K of the amplifier 100 (curve 702), as a function of the evolution of the ratio between the intrinsic capacitance Cg between the source and the drain of the transistor Mcgl, respectively Mcg2, and the intrinsic capacitance Cs between the gate and the drain of the transistor Mcsl, respectively Mcs2.

[0111] Curves 700 and 702 show that the closer the Cg / Cs ratio is to 1, the better the stability and isolation in amplifier 100.

[0112] For example, curves 700 and 702 show that, for a Cg / Cs ratio between 0.8 and 1.2, the insulation S12 is less than -35 dB, that is to say has negative values ​​greater, in absolute value, than 35, and that the value of the stability factor K is greater than 4.

[0113] For example, curves 700 and 702 show that, for a Cg / Cs ratio between 0.8 and 1.1, the insulation S12 is less than -42 dB, i.e. has negative values ​​greater, in absolute value, than 42, and that the value of the stability factor K is greater than 7.5.

[0114] For example, curves 700 and 702 show that, for a Cg / Cs ratio equal to 1, the insulation S12 is equal to -45 dB and that the value of the stability factor K is equal to 10.5.

[0115] Thus, as already indicated previously, the transistors Mcgl, Mcg2, Mcsl and Mcs2 are configured so that the ratio Cr between the intrinsic capacitance between the conduction terminals of each of the transistors Mcgl, Mcg2, by the capacitance in intrinsic between the control terminal and the second conduction terminal of each of the transistors Mcsl and Mcs2, i.e. between 0.8 and 1.2, preferably between 0.9 and 1.1, for example equal to 1.

[0116] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0117] In particular, in the examples described, the transistors are in MOS technology and are of the N-channel type. However, the person skilled in the art will be able to adapt the description given above of these examples, in the case where the potential VDD is negative with respect to the potential GND, for example by replacing all the N-channel MOS transistors with P-channel MOS transistors.

[0118] More generally, the person skilled in the art will be able to adapt the description given above of examples in which the transistors are in MOS technology to cases where the transistors are in bipolar technology, for example all of the PNP type or all of the NPN type depending on whether the VDD potential is positive or negative with respect to the GND potential, or even to transistors in BiCMOS technology.

[0119] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An amplifier (100) comprising: a first input node (Inl) and a second input node (In2); a first output node (Outl) and a second output node (Out2); a first transistor (Mcgl) coupling the first input node to the first output node; a second transistor (Mcg2) identical to the first, coupling the second input node to the second output node, the first and second transistors (Mcgl, Mgc2) having their control terminals connected to each other; a third transistor (Mcsl) having a control terminal connected to the first input node (Inl) and a first conduction terminal connected to the second output node (Out2); a fourth transistor (Mcsl) identical to the third, having a control terminal connected to the second input node (In2) and a first conduction terminal connected to the first output node (Outl); a first circuit (CTRL1) configured to control a current (II, 12;It) flowing in the first and second transistors (Mcgl, Mcg2); and a second circuit (CTRL2) configured to control a control signal applied to the control terminals of the first and second transistors (Mcgl, Mcg2).;

2. Amplifier according to claim 1, wherein a ratio (Cr) between a value of a capacitance (Cg) between the conduction terminals of each of the first and second transistors (Mcgl, Mcg2) and a capacitance value (Cs) between the control terminal and the first conduction terminal of each of the third and fourth transistors (Mcsl, Mcs2) is between 0.8 and 1.2, preferably between 0.9 and 1.1, for example equal to 1.

3. An amplifier according to claim 1 or 2, wherein: each of the third and fourth transistors (Mcsl, Mcs2) has a second conduction terminal connected to a node (104) for applying a first supply potential (GND); and each of the first and second output nodes (Outl, Out2) is coupled to a node (200) for applying a second potential power supply (VDD).

4. Amplifier according to claim 3, wherein a first inductance (Loi) couples the first output node (Outl) to the application node (200) of the second supply potential and a second inductance (Lo2) couples the second output node (Out2) to the application node (200) of the second supply potential.

5. An amplifier according to claim 4, wherein the first and second inductances (Loi, Lo2) constitute a primary winding of a transformer.

6. An amplifier according to any one of claims 3 to 5, wherein a capacitor (C) has a first terminal connected to a node (102) for connecting the control terminals of the first and second transistors (Mcgl, Mcg2) to each other.

7. Amplifier according to claim 6, wherein the capacitance (C) has a second connected to the node (104) of application of the first supply potential (GND).

8. An amplifier according to any one of claims 3 to 7, wherein the amplifier (100) comprises a summing node (106) configured to receive the sum (It) of the currents (II, I2) flowing in the first and second transistors (Mcgl, Mcg2), the first and second input nodes (Inl, In2) each being coupled to the summing node (106).

9. The amplifier of claim 8, wherein a third inductor (Lil) couples the first input node (Inl) to the summing node (106) and a fourth inductor (Li2) couples the second input node (In2) to the summing node (106).

10. An amplifier according to claim 9, wherein the third and fourth inductances (Lil, Li2) constitute a secondary winding of a transformer.

11. Amplifier according to any one of claims 8 to 10, wherein: - the first circuit (CTRL1) comprises a transistor (Mr) connected between the summing node (106) and the node (104) for applying the first supply potential (GND); - the first circuit (CTRL1) comprises a control circuit (BIAS1) configured to supply, to a control terminal of said transistor (Mr), a signal determining the value of the current (It) in said transistor (Mr); and - the transistor (Mr) connected between the summing node (106) and the node (104) for applying the first supply potential is preferably twice as large as each of the first and second transistors (Mcgl, Mcg2).

12. Amplifier according to claim 11, wherein the control circuit (BIAS1) of the first circuit (CTRL1) comprises a transistor (MM31) and a current source (300) connected in series between the nodes (200, 104) of application of the first and second supply potentials (VDD, GND), said transistor (M31) being mounted in mirror with the transistor (Mr) connected between the summing node (106) and the node (104) of application of the first supply potential (GND).

13. An amplifier according to any one of claims 8 to 12, wherein the second circuit (CTRL2) comprises: an error amplifier (Aerr) having a first input connected to the summing node (106) and an output coupled to the control terminals of the first and second transistors (Mcgl, Mcg2) so as to apply thereto the control signal of the first and second transistors (Mcgl, Mcg2); and a control circuit (BIAS2) configured to provide a reference signal to the second input of the error amplifier (Aerr).

14. Amplifier according to claim 13, wherein the control circuit (BIAS2) of the second circuit (CTRL2) comprises a current source (400) and a transistor (M4) connected in series between the nodes (200, 104) of application of the first and second supply potentials (VDD, GND), said transistor (M4) having a control terminal connected to the second input of the error amplifier (Aerr) and to a node of connection of said transistor (M4) to said current source (400).

15. Amplifier according to claim 14 taken in its dependence on claim 11, in which: a dimension ratio between the transistor (M31) of the control circuit (BIAS1) of the first circuit (CTRL1) and the transistor (Mr) connected between the summing node (106) and the node (104) for applying the first supply potential (GND) determines, with a value of the current (Icmdl) of the current source (300) of the control circuit (BIAS1) of the first circuit (CTRL1), a value of the current (II, 12; It) in each of the first and second transistors (Mcgl Mcg2); and a dimension ratio between the transistor (M4) of the control circuit (BIAS2) of the second circuit (CTRL2) and the transistor (Mr) connected between the summing node (106) and the node (104) for applying the first supply potential (GND) determines, with a value of the current (Icmd2) of the current source (400) of the control circuit (BIAS2) of the second circuit (CTRL2), a value of a control signal of each of the first and second transistors (Mcgl, Mcg2).

Images