Method of manufacturing an electronic chip having electromagnetic shielding

Abstract

Method for manufacturing an electronic chip having electromagnetic shielding The present description relates to a method comprising the following steps: i) providing a chip (100) comprising: - an insulating substrate (12), covered by an interconnection structure (22), comprising an insulating layer (24) in which conductive tracks (26) are formed, the conductive tracks (26) emerging at an upper face of the interconnection structure (22) and on one of the flanks of the interconnection structure (22), - connection pads (30) being partially coated by a resin (40), so as to be connected to the conductive tracks (26) and to be able to be connected to an external element, ii) forming a conductive coating (50) to cover the substrate (12) and the flanks of the interconnection structure (22), whereby the conductive coating (50) is connected to the conductive tracks (26). Figure for abstract: Fig. 2

Description

Title of the invention: Method for manufacturing an electronic chip having electromagnetic shielding Technical field

[0001] The present description relates to the field of CSP ('Chip-Scale Package') or WLCSP ('Wafer Chip Scale Package') type chips. It relates more particularly to a method of manufacturing an electronic chip having electromagnetic shielding. Prior art

[0002] Electronic chips comprise a substrate, in or on which electronic circuits have been fabricated. The substrate is covered by connection pads in order to allow assembly of the chip, for example, with a printed circuit board.

[0003] However, chips may be subject to electromagnetic interference (EMI) which disrupts their operation or may even cause significant damage, and / or may generate such electromagnetic interference.

[0004] In order to protect them from unwanted electromagnetic radiation, it is conventional to make, at the component scale, a molding around the chip and to form an electromagnetic shield around the molding. A second molding can optionally be formed on the electromagnetic shield. The grounding of the electromagnetic shield can be achieved by means of vias and / or laminates, and can allow an antenna to be added.

[0005] To manufacture electronic chips, it is possible to use low temperature co-fired ceramics (LTCC for 'Low Temperature Co-fired Ceramic') comprising several dielectric layers, conductive materials (for example screen-printed) and holes to interconnect the different layers. Shielding is then easily done using holes / vias.

[0006] However, such chips comprise many layers and interconnection elements and are therefore complex to manufacture and / or increase the size of the final chip. Summary of the invention

[0007] There is a need to improve at least in part certain aspects of known methods of manufacturing electronic chips comprising electromagnetic shielding.

[0008] This aim is achieved by a method of manufacturing an electronic chip having electromagnetic shielding comprising the following steps: (i) provide an electronic chip comprising: - an insulating substrate comprising a lower face, a side face and an upper face, - an interconnection structure covering the upper face of the substrate, the interconnection structure comprising an insulating layer in which conductive tracks are formed, connection pads being arranged on the interconnection structure, the conductive tracks being arranged so as to emerge on at least one of the sides of the interconnection structure, - a resin covering an upper face of the interconnection structure and partially coating the connection pads so that they can be connected to an external element, ii) forming a conductive coating on the side face and on the bottom face of the substrate as well as on the flanks of the interconnection structure, whereby the conductive coating is connected to the conductive tracks at at least one of the flanks of the interconnection structure.

[0009] According to a particular embodiment, step ii) is carried out by spraying a solution or by ink jet.

[0010] According to a particular embodiment, the solution or ink contains silver nanoparticles.

[0011] According to a particular embodiment, the electronic chip provided in step i) is obtained according to the following steps: - providing a substrate covered by the interconnection structure, connection pads being arranged on the interconnection structure, the conductive tracks being arranged so as to emerge on at least one of the sides of the interconnection structure, - depositing a resin on the interconnection structures and on the connection pads, - thinning the resin until part of the connection pads are accessible, - possibly, thinning the substrate and / or covering the rear face of the chips with an additional layer of resin, - cut the substrate to form different chips.

[0012] This goal is also achieved by an electronic chip comprising: - an insulating substrate comprising a lower face, a side face and an upper face, - an interconnection structure covering the upper face of the substrate, the interconnection structure comprising an insulating layer in which conductive tracks are formed, connection pads being arranged on the interconnection structure, the conductive tracks being arranged so as to emerge on at least one of the sides of the interconnection structure, - a resin covering the interconnection structure and leaving part of the connection pads accessible, - a conductive coating covering and being in contact with the side face and the lower face of the chip substrate as well as with the sides of the interconnection structure, so as to connect the conductive tracks to the conductive coating at at least one of the sides of the interconnection structure.

[0013] According to a particular embodiment, the thickness of the conductive tracks is between 2 and 12 μm.

[0014] According to a particular embodiment, the width of the conductive tracks is greater than 10 μm.

[0015] According to a particular embodiment, the conductive coating is made of silver.

[0016] According to a particular embodiment, the conductive tracks, emerging on the flank of the interconnecting structure, have a comb-shaped end.

[0017] According to a particular embodiment, the conductive tracks emerge on two opposite sides of the interconnection structure.

[0018] This aim is also achieved by the use of such an electronic chip in an automobile, for example in an advanced driving assistance system, in personal electronics, in communication equipment, such as a computer, a mobile phone ('smartphone'), a connected object (loT) or one of their peripherals.

[0019] This aim is also achieved by an automobile, communication equipment, such as a computer, a mobile phone ('smartphone'), a connected object (loT) or one of their peripherals comprising such an electronic chip. Brief description of the drawings

[0020] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0021] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF], [Fig.lG], [Fig.lH], [Fig.II] and [Fig.U] represent sectional views illustrating different steps of a method of manufacturing an electronic chip having electromagnetic shielding according to a particular embodiment;

[0022] [Fig.2] represents a sectional view of an electronic chip having electromagnetic shielding, according to another particular embodiment;

[0023] [Fig.3] represents a top view of an electronic chip having electromagnetic shielding, according to another particular embodiment. Description of the embodiments

[0024] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0025] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0027] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0028] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0029] We will now describe in more detail the method of manufacturing an electronic chip having electromagnetic shielding with reference to Figures 1A to U.

[0030] The method comprises the following steps: (i) provide an electronic chip 100 comprising: - an insulating substrate 12 comprising a lower face 14, a lateral face 15 and an upper face 16, - an interconnection structure 22 covering the upper face 16 of the substrate 12, the interconnection structure 22 comprising an upper face, flanks and a lower face in contact with the substrate 12, the interconnection structure 22 comprising an insulating layer 24 in which conductive tracks 26 are formed, the conductive tracks emerging on the one hand at the upper face to form connection pads and on the other hand on one of the flanks of the interconnection structure 22, - connection pads 30 being fixed to the connection pads 26, - a resin 40 covering the interconnection structure 22 and leaving part of the connection pads 30 accessible, so as to be able to connect them to an external element, ii) forming a conductive coating 50 on the side face 15 and on the lower face 16 of the substrate 12 of the chip 100 as well as on the sides of the interconnection structure 22, whereby the conductive tracks 26 are connected to the conductive coating 50 at the side of the interconnection structure 22.

[0031] With such a method, the grounding of the electromagnetic coating 50 is carried out directly at the level of the tracks 26 of the interconnection structure 22 of the chip 100. This allows, not only, a saving of space since there is no need for other additional elements to connect the chip to the coating but, also, to leave the interconnection pads 30 accessible to subsequently assemble the chip to an external element (chips or printed circuits for example).

[0032] The electromagnetic (EMI) shield is connected to ground via the interconnect structure. The conductive traces connected to the electromagnetic shield are the ground interconnects.

[0033] The method does not require covering the sides of the substrate 12 with a layer of resin or forming vias in the substrate 12.

[0034] More particularly, the method may comprise the following steps: a) providing a structure comprising several chips 100, the structure comprising a substrate 12 covered by an interconnection structure 22, connection pads 30 being fixed on the interconnection structure 22 ([Fig.lA]), b) depositing a resin 40 on the interconnection structures 22 and on the connection pads 30 and thinning the resin 40 until part of the connection pads 30 is accessible (figure 1B), c) preferably, thinning the substrate 12 ([Fig.lC]) and / or covering the rear face 16 of the chips 100 with an additional layer of resin, d) separating the chips 100, by cutting the structure between the chips, whereby individualized chips 100 are obtained as defined previously in step i) ([Fig.lD]), the cutting step being able to be carried out by gluing the structure obtained in step c) onto a first adhesive 201 (or support ('carrier')), the substrate 12 being, preferably, glued onto the first adhesive 201 by its rear face to carry out the cutting step from the front face, e) simultaneously gluing the cut chips 100 onto a second adhesive 202, the chips being glued by their front face, i.e. the resin 40 and the connection pads 30 of the chips 100 being glued onto the second adhesive 202 ([Fig.lE]), f) removing the first adhesive 201 ([Fig.lF]), g) if necessary, stretch the second adhesive 202 so as to make the lateral face of the substrate 12 and the sides of the interconnection structures 22 of the chips 100 more accessible ([Fig.lG]), h) implementing step ii), i.e. depositing the electromagnetic coating 50 on the rear face 14 and on the side face 15 of the chip 100 as well as on the sides of the interconnection structure 22 ([Fig. 1H]).

[0035] The method may, furthermore, comprise, after step ii), the following steps: - fixing the chips 100 on a third adhesive 203 ('carrier'), from their rear, by sticking the coating 50 on the third adhesive 203 (figure II), - removing the third adhesive 203 (figure IJ).

[0036] The steps of the method are preferably implemented to simultaneously handle all the chips coming from the same substrate.

[0037] At the end of the process, a chip 100 comprising an electromagnetic coating 50 is obtained ([Fig.2] and [Fig.3]).

[0038] We will now describe each of the different stages in more detail.

[0039] During step a), the active parts of the chips 100 are formed in the same substrate 12 and have not yet been individualized.

[0040] During step a), one or more discrete components, not shown, may already have been formed. The discrete component(s) are, for example, chosen from transistors, diodes, thyristors, triacs, filters, etc. The chip 100 may comprise one or more electronic circuits. The chip 100 makes it possible to implement different electronic functions.

[0041] The chips may be the same or different.

[0042] Each electronic chip 100 comprises: - an insulating substrate 12, - an interconnection structure 22 covering the substrate 12, - connection pads 30 arranged on the interconnection structure 22.

[0043] According to one embodiment, at this stage of the procedure the substrate 12 corresponds to a plate.

[0044] The substrate 12 is an insulating substrate ('high insulative substrate'). It has, for example, a resistivity greater than IkQ.cm. It is, for example, a resistive silicon substrate (HRSI for 'High-Resistivity Silicon') or a glass substrate. Any other substrate with high electrical insulating power or electrically insulating can be used.

[0045] The substrate 12 has, for example, a thickness of between 100 and 900 μm, preferably between 300 and 900 μm, for example a thickness of approximately 725 μm.

[0046] The substrate 12 comprises a first face 16 (upper face or front face or active face) and a second face 14 (lower face or rear face). The two faces 14 and 16 are parallel to each other. They are connected to each other by side walls 15. An insulating layer may cover the lower face 14.

[0047] The interconnection structure 22 comprises one or more (two or three for example) levels of conductive tracks 26, and insulating layers 24.

[0048] The conductive tracks 26 are, for example, made of one or more of the materials chosen from copper, a copper alloy, titanium, a titanium alloy, titanium nitride, gold, tungsten, platinum, and a platinum alloy. It may also be aluminum. According to one embodiment, the thickness of each metal track 26 is between 2 and 40 μm, for example between 2 and 12 μm. Tracks having thicker thicknesses promote the contact surface between the track 26 and the electromagnetic coating 50. Tracks 26 of smaller thicknesses will be easier to cut.

[0049] The insulating layer 24 may be a multilayer formed of several insulating layers. According to one embodiment, the thickness of each insulating layer 24 is between 0.5 μm and 15 μm.

[0050] The insulating layer 24 may be made of a dielectric material, for example an oxide or a nitride, preferably, it is a silicon oxide (SiO2), a silicon nitride (for example Si3N4). Alternatively, the insulating layer may be made of a polymer, and in particular of polyimide.

[0051] The interconnection structure 22 comprises an upper face, a lower face and flanks. The lower face is in contact with the upper face 16 of the substrate 12.

[0052] Metal tracks 26 are flush with the upper face so as to form connection pads. The connection pads (also called electrical contacts) make it possible to connect the chip 100 to other elements (chips or printed circuits for example), by means of the connection pads 30.

[0053] The electrical connection pads are also called “UBM” (for the English expression “Under Bump Metallization”). Preferably, there are at least two connection pads. For example, in [Fig.3], six electrical connection pads are visible.

[0054] The electrical connection pads are, for example, at a distance of 10 to 30 pm from the side wall of the chip. This distance depends on the chips. It can be up to several hundred micrometers or even up to a millimeter depending on the component produced.

[0055] A portion of the metal tracks 26 is accessible from the sides of the interconnection zones 22 so that they can be directly connected to the metal coating 50, in order to provide grounding for the coating 50. The metal tracks are accessible on at least one side of the chip 100. They could be accessible on several sides of the chip 100, for example on two opposite sides.

[0056] Connection pads 30 are fixed on the connection pads. The connection pads 30 are, advantageously, soldered on the electrical connection pads. The connection pads 30 are formed from an electrically conductive and "wettable" (i.e. solderable or weldable) material, i.e. a material on which it is possible to perform soldering. For example, the metal pads are made of a tin-based solderable material, typically SnAgCu or Cu / SnAg.

[0057] During step b), a layer of resin 40 is deposited on the front face of the interconnection structure 22 and on the connection pads 30.

[0058] The resin 40 is an electrically insulating resin. It may be a thermosetting resin or a thermoplastic resin. The material will be chosen so as not to be fusible over the operating temperature range of the electronic components. The resin may be chosen from the group comprising: epoxy type resins, and phenolic type resins, acrylic type resins.

[0059] The resin may also comprise electrically insulating particles. The particles are, for example, oxide particles, and in particular alumina or silica particles.

[0060] The resin layer 40 comprises an upper face, a lower face in contact with the interconnection structure 22 and a side face.

[0061] After being deposited, the resin 40 is thinned in order to make the upper part of the pads accessible.

[0062] During step c), the substrate 12 may be thinned at the rear face 14 and / or a layer of resin 40 may be deposited on the rear of the substrate 12. For this, the structure is turned over and fixed by its front face on a first support 201. The first support 201 is, for example, a strip of adhesive tape. The structure is then thinned by its rear face so that the substrate 12 has its final thickness.

[0063] Preferably, the side faces of the substrate 12 are not covered with a resin.

[0064] During step d), the substrate 110 is cut between the chips 100 to distinguish the chips. For this, trenches, passing right through the structure obtained in step c), are formed. The trenches 120 define the lateral contours of the chips 100.

[0065] The width of the trenches 120 is, for example, between 20 and 80 μm.

[0066] This cutting step can be carried out by means of a cutting device or engraving. The cutting device is, for example, a mechanical cutting tool, such as a saw. Cutting can be done with one blade or two blades.

[0067] It can also be laser cutting ('laser grooving' or 'laser dicing') or plasma cutting ('plasma dicing'). These different cutting processes can also be used in common.

[0068] The formation of the trenches can also be carried out by a cutting step by introducing dislocation by laser (so-called 'stealth dicing' step) then an expansion step. The so-called 'stealth dicing' step consists, with a specific laser, of generating dislocations within the substrate, in the cutting paths. These Dislocations are defects present in the thickness of the substrate which, under the effect of mechanical stress, will allow the chips to separate. It is then sufficient to stretch the adhesive support to separate the chips and proceed with the deposition of the material.

[0069] It is also possible to implement a first step during which a laser is used to cut the upper part of the device going from the front face to the lower part of the interconnection structure 22, then a second step during which a saw is used to cut the substrate 12. The use of a laser to cut the tracks (in particular copper) and the insulating layer of the interconnection structure makes it possible to obtain a clean cut and to avoid delamination phenomena.

[0070] The cutting step is preferably carried out from the front face. For this, the rear face of the structure obtained in step c) is glued by its rear face onto a first adhesive 201.

[0071] Once the substrate has been cut, the structure is turned over to be able to deposit the coating from the rear face. For this, a second adhesive 202 is glued to the front face of the cut chips (step e)). The second adhesive 202 is a stretchable adhesive.

[0072] The first adhesive 201 is removed (step f)). Then the second adhesive 202 is stretched so as to increase the gap between two chips 100 and make the sides of the electronic chips more easily accessible (step g)). This step is optional. It depends on the width of the cutout made in step d) and / or the type of deposition process of the shielding layer 50.

[0073] Alternatively, during step c), the chips 100 can be glued to a stretchable adhesive by their front face. The cutting step (step c) and the coating deposition step (step h) can then be carried out on the same stretchable adhesive. There is no need to turn the chips 100 over.

[0074] The various adhesives used in the process may be ultraviolet (UV) radiation sensitive adhesives for cutting applications ('UV dicing tape').

[0075] Step ii) is then implemented.

[0076] The coating can be deposited in one go. In other words, the back face and the side face of the chip 100 are covered simultaneously.

[0077] Preferably, the coating 50 is deposited by liquid means. The electromagnetic coating 50 is deposited, for example, by spraying a solution or by ink jet. It can also be deposited by screen printing. The coating can also be deposited by an evaporation technique or by atomic layer deposition (ALD).

[0078] The solution or ink used contains conductive nanoparticles, typically metallic nanoparticles, for example silver nanoparticles. Alternatively to nanoparticles, they can also be particles or microparticles.

[0079] Depending on the method implemented, the sidewall 15 of the chip may be partially or completely covered by the coating. For example, the sidewall of the resin layer 40 may or may not be covered by the coating 50.

[0080] At the end of the method, a chip 100 as shown in FIGS. 2 and 3 is obtained. The electronic chip 100 comprises: - an insulating substrate 12 comprising a lower face 14, a lateral face 15 and an upper face 16, - an interconnection structure 22 covering the upper face 16 of the substrate, the interconnection structure 22 comprising an upper face, flanks and a lower face in contact with the substrate 12, the interconnection structure comprising an insulating layer 24 in which conductive tracks 26 are formed, the conductive tracks emerging on the one hand at the upper face of the interconnection structure to form connection pads and on the other hand on one of the flanks of the interconnection structure 22, - connection pads 30 being connected to the connection pads, - a resin 40 covering the interconnection structure and leaving part of the connection pads accessible, - a conductive coating 50 covering and being in contact with the lateral face 15 and the lower face 14 of the substrate of the chip 100 as well as with the sides of the interconnection structure 22, so as to connect the conductive tracks 26 to the conductive coating at the side of the interconnection structure 22.

[0081] The conductive coating is, for example, a metallic coating. It may be silver.

[0082] The conductive tracks 26 emerging on the side of the interconnection structure 22 may have a comb-shaped end ([Fig.3]) or have a solid shape, for example a ribbon shape.

[0083] A single chip 100 may comprise identical or different tracks. The conductive tracks 26 may be symmetrical or asymmetrical.

[0084] We will seek to maximize the contact surface between the metal tracks 26 and the conductive coating 50 to ensure good electrical contact.

[0085] Preferably, the different conductive tracks 26 emerge on several sides of the interconnection structure 22. Preferably, the conductive tracks 26 emerge on two opposite sides of the interconnection structure 22.

[0086] The tracks 26 are preferably made of copper or aluminum.

[0087] Each electronic chip 100 can then be attached to an external element, for example another chip, a housing, a printed circuit board or another electronic chip.

[0088] Such electronic chips find applications in many industrial fields, and in particular, in the automotive field, for personal electronics, notably in the field of communication equipment, computers and peripherals.

[0089] This may, for example, be 5G connection devices or more generally connected devices.

[0090] It can also be an advanced driver assistance system (ADAS for 'advanced driver-assistance Systems').

[0091] The electronic chip can be used in a smartphone or for the Internet of Things (IoT). The device is, for example, connected by 5G, WIFI or ultra-wide band (UWB).

[0092] The chip may also be of interest for other fields, such as for example for the industrial field, in particular for green energies.

[0093] Such applications are given for illustrative purposes and are not limiting.

[0094] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing an electronic chip (100) having electromagnetic shielding (50) comprising the following steps: i) providing an electronic chip (100) comprising: - an insulating substrate (12) comprising a lower face (14), a side face (15) and an upper face (16), - an interconnection structure (22) covering the upper face (16) of the substrate, the interconnection structure (22) comprising an insulating layer (24) in which conductive tracks (26) are formed, connection pads (30) being arranged on the interconnection structure (22), the conductive tracks (26) being arranged so as to emerge on at least one of the sides of the interconnection structure (22), - a resin (40) covering an upper face of the interconnection structure (22) and partially coating the connection pads (30) so as to be able to connect them to an external element,ii) forming a conductive coating (50) on the side face (15) and on the bottom face (14) of the substrate (12) as well as on the flanks of the interconnection structure (22), whereby the conductive coating (50) is connected to the conductive tracks (26) at at least one of the flanks of the interconnection structure (22).,

2. A method according to claim 1, wherein step ii) is carried out by spraying a solution or by ink jet.

3. The method of claim 2, wherein the solution or ink contains silver nanoparticles.

4. Method according to any one of the preceding claims, in which the electronic chip (100) provided in step i) is obtained according to the following steps: - providing a substrate (12) covered by the interconnection structure (22), the connection pads (30) being arranged on the interconnection structure (22), the conductive tracks (26) being arranged so as to emerge on at least one of the sides of the interconnection structure (22), - depositing a resin (40) on the interconnection structures (22) and on the connection pads (30),

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10. - thin the resin (40) until part of the connection pads (40) is accessible, - possibly, thin the substrate (12) and / or cover the rear face of the chips with an additional layer of resin, - cutting the substrate (12) to form different chips (100). Electronic chip (100) comprising: - an insulating substrate (12) comprising a lower face (14), a side face (15) and an upper face (16), - an interconnection structure (22) covering the upper face (16) of the substrate, the interconnection structure (22) comprising an insulating layer (24) in which conductive tracks (26) are formed, connection pads (30) being arranged on the interconnection structure (22), the conductive tracks (26) being arranged so as to emerge on at least one of the sides of the interconnection structure (22), - a resin (40) covering the interconnection structure (22) and leaving part of the connection pads (30) accessible, - a conductive coating (50) covering and being in contact with the lateral face (15) and the lower face (16) of the substrate (12) of the chip (100) as well as with the sides of the interconnection structure (22), so as to connect the conductive tracks (26) to the conductive coating (50) at at least one of the sides of the interconnection structure (22). Chip according to the preceding claim, in which the thickness of the conductive tracks (26) is between 2 and 12 pm. Chip according to one of claims 5 and 6, in which the width of the conductive tracks (26) is greater than 10 pm. Chip according to one of claims 5 to 7, in which the conductive coating (50) is silver. Chip according to any one of claims 5 to 8, in which the conductive tracks (26), emerging on the flank of the interconnection structure (22), have a comb-shaped end. Chip according to any one of claims 5 to 9, in which the conductive tracks (22) emerge on two opposite flanks of the interconnection structure (22).

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