Coaxial waveguide-type power divider / combiner component in SIW technology

Abstract

Coaxial waveguide-type power divider / combiner component in SIW technology. The present invention relates to a coaxial waveguide-type power divider / combiner component, characterized in that it is implemented using "substrate-integrated waveguide" technology, in a multilayer integrated circuit board, which comprises a stack of a plurality of conductive layers (21, 22, 23, 24, 25, 26, 27) separated from each other by insulating layers. Figure for the abstract: Figure 4

Description

Title of the invention: Power divider / combiner component of the coaxial guide type in SIW technology

[0001] The present invention relates to the domain of power divider and / or combiner components of the coaxial guide type.

[0002] A power divider / combiner component must have a wide operating frequency band, that is, a band over which its characteristics remain substantially constant. In particular, the component exhibits low losses. It exhibits low ripple, that is, low variations in transmission losses.

[0003] Conventional solutions, based on transmission lines etched onto a conductive layer of a printed circuit board (PCB), induce excessive power losses. Consequently, it is necessary to use alternative solutions, in particular spatial dividers / combiners.

[0004] A spatial divider / combiner is based on a waveguide (coreless guide) or a coaxial guide (guide with core).

[0005] To date, spatial dividers / combiners constitute an effective solution in terms of permissible radio frequency - RF power and low losses.

[0006] However, as shown, for example, in document US7215220B1, spatial dividers / combiners consist of multiple subassemblies of complex mechanical parts and radio frequency (RF) substrates, which make them bulky, heavy, and expensive. Interconnections with active elements are complex to implement.

[0007] Moreover, the assembly is poorly suited to production using an automated process and requires numerous manual operations, which are poorly suited to mass production and / or low cost production.

[0008] Furthermore, when they consist of a coaxial waveguide (cylindrical or rectangular in cross-section), the latter is often oversized and therefore susceptible to performance degradation, particularly transmission variations, depending on internal (manufacturing) or external (components connected to their paths) symmetry defects. Impedance transformations, achieved using antipodal lines, have low cutoff frequencies that significantly limit the bandwidth of such power divider / combiner components.

[0009] The aim of the invention is therefore to address these problems by proposing a new type of power divider / combiner components.

[0010] For this purpose, the invention relates to a coaxial guide type power divider / combiner component, characterized in that it is made using "substrate integrated waveguide" technology, in a multilayer integrated circuit board, which comprises a stack of a plurality of conductive layers separated from each other by insulating layers.

[0011] According to other advantageous aspects of the invention, the component comprises one or more of the following features, taken individually or in all technically possible combinations:

[0012] - the coaxial guide comprises an external conductor and an internal conductor, the with the external conductor brought to a ground potential, the internal conductor flowing inside the external conductor and connecting a first port of the component to each second port of a plurality of second ports of the component.

[0013] - the external conductor comprises at least one upper ground plane, delimited in an upper conductive layer of the multilayer integrated circuit, a lower ground plane, delimited in a lower conductive layer of the multilayer integrated circuit, and a plurality of lateral metallized vias electrically connecting the upper and lower ground planes.

[0014] - the component comprising successively, along a longitudinal axis: a an input impedance transformation section, on which the internal conductor has a common track connected to the first port; an output channel separation section, on which the internal conductor has a plurality of derived tracks; and, an intermediate multi-channel subdivision section, on which the internal conductor has a plurality of intermediate tracks, which are superimposed along a thickness of the multilayer integrated circuit and connected to each other by vias, the plurality of intermediate tracks having at least one central intermediate track connected to the common track of the input section, and at least one subdivision intermediate track having a plurality of branches, each branch being connected to a derived track of the output section.

[0015] - the common track has one or more impedance transformation stage(s), the width of the common track widening between the two ends of an impedance transformation stage.

[0016] - the central track has first and second transformation stages of impedance arranged successively, a first pair of first ground planes arranged on either side of the central track being associated with the first stage and a second pair of second ground planes arranged on either side of the central track being associated with the second stage, the first ground planes overlapping the first and second floors, the second mass planes covering only the second floors, the second mass planes being closer to the central layer than the first mass planes.

[0017] - each derivative track comprises at least one section widening by in order to adjust the impedance of the waveguide to the output section.

[0018] - the intermediate section constitutes a spatial divider / combiner.

[0019] - the intermediate section comprises a plurality of first intermediate tracks carried by as many different layers of the multilayer circuit, each first intermediate track having a plurality of branches, each branch of the intermediate section being connected to a corresponding derived track among the derived tracks of the output section.

[0020] - the intermediate section comprises a plurality of intermediate second tracks, each second intermediate track comprising a plurality of branches, which are not connected, each second intermediate track comprising at least one subdivision portion arranged opposite at least one subdivision portion of a first intermediate track.

[0021] - the output section includes an intermediate ground plane between the tracks derivatives connected to the branches of a first intermediate track and the derivative tracks connected to the branches of another first intermediate track.

[0022] - the plurality of second ports forms a matrix on a plurality of N levels, each level corresponding to a different layer of the multilayer circuit, each level having M second ports.

[0023] The invention will become clearer upon reading the following description, given solely by way of non-limiting example, and made with reference to the drawings in which:

[0024] [Fig-1] [Fig.1] is a schematic representation of an amplification device top view power, integrating two components in SIW technology according to the invention, the first functioning as a power divider and the second as a power combiner;

[0025] [Fig.2] [Fig.2] is a schematic top view representation of an embodiment of the power divider component of [Fig.1];

[0026] [Fig.3] [Fig.3] represents different cross-sections of the component of [Fig.2]; and,

[0027] [Fig.4] [Fig.4] is a schematic exploded perspective representation of a subdivision section of the component of [Fig.2].

[0028] The power divider / combiner component according to the invention is a coaxial guide type power divider / combiner component made using SIW technology.

[0029] The "substrate integrated waveguide" - SIW (for "substrate integrated waveguide" in English) technology makes it possible to make the component within the thickness of a multilayer printed circuit board.

[0030] SIW technology makes it possible to meet all technical performance requirements and industrial constraints. This solution improves the size, cost, and weight of the component, for RF performance halfway between that obtained for mechanical spatial dividers / combiners and that obtained for conventional dividers / combiners.

[0031] In what follows, the case of a power divider component will be presented in more detail, that is, a component used as a power divider, while bearing in mind that it is equally a power combiner component, that is, the same component but used as a power combiner. This depends in fact on how this component is integrated into the electrical assembly on the board.

[0032] The method of implementing a power divider in SIW technology mainly concerns the method of implementing the subdivision of the channels, while ensuring high performance over a wide bandwidth, this high performance being characterized in particular in terms of ripple in the transmission of RF signals and low insertion losses.

[0033] Fig. 1 is a schematic representation of a top view power amplification device.

[0034] The amplification device 1 is an electronic circuit made on a multilayer printed circuit board - PCB (Printed circuit board), or PCB 2.

[0035] The PCB 2 card results from the stacking of a plurality of conductive layers, in copper, two successive layers being separated by an insulating layer, in a dielectric material.

[0036] PCB card 2 bears: - an input connector 3, connected to electronics for generating a signal to be amplified (the generation electronics are not shown in the figure). - a bank of NxM power amplifiers, referenced by the number 7 in [Fig. 1], where N is an integer strictly greater than one and M is preferably an integer greater than one. In the present embodiment, M is equal to two and N is equal to four. Thus, four amplifiers 7 are mounted on the top side of PCB 2 (and therefore visible in [Fig. 1]) and four amplifiers are mounted on the bottom side of PCB 2 (and therefore not shown in [Fig. 1]). - an output connector 11, for transmitting the amplified signal, for example, to a radiating element of an antenna.

[0037] PCB card 2 incorporates a component according to the invention used as a power divider:

[0038] This component 5 has a first port 100 connected, by a micro ribbon line 4 etched in the PCB 2, to the input connector 3.

[0039] The component 5 has a plurality of second ports 105, each second port being connected, by a micro ribbon line 6 etched in the PCB 2, to a particular amplifier 7 of the amplifier bank.

[0040] PCB card 2 incorporates a component according to the invention used as a power combiner:

[0041] This component 9 has a plurality of second ports 105, each port 105 being connected, by a micro ribbon line 8 etched in the PCB 2, to a particular amplifier 7 of the amplifier bank.

[0042] The component 9 has a first port 100 connected, by a micro ribbon line 10 etched in the PCB 2, to the output connector 11.

[0043] The power divider component 5 and the power combiner component 9 are identical. They are mounted back-to-back in the circuit of device 1.

[0044] In what follows, component 5 will be described in more particular, but a similar description could be made for component 9.

[0045] A preferred embodiment of a power divider component in SIW technology will now be presented with reference to Figures 2 to 4.

[0046] Figure 2 is a schematic representation of the power divider component 5 in top view, with the ground planes of the different layers omitted for clarity. Figure 2 therefore represents the traces of the internal conductive layers constituting the core of the coaxial waveguide of component 5.

[0047] Different cross-sections of component 5 by transverse planes are shown in [Fig.3].

[0048] Finally, [Fig.4] is a perspective representation of component 5.

[0049] Component 5 is a spatial divider, more specifically a spatial divider of the coaxial guide type.

[0050] Component 5 is made within the thickness of PCB board 2.

[0051] In the present embodiment, the PCB 2 is formed by stacking, along a Z-axis, seven conductive layers 21 to 27, each conductive layer being insulated from the preceding one by an insulating layer. More specifically, as illustrated in [Fig. 4], the PCB 2 comprises:

[0052] - a lower outer layer 21.

[0053] - an upper outer layer 27.

[0054] - a central internal layer 24.

[0055] - between the lower outer layer 21 and the central inner layer 24, a second lower intermediate inner layer 22 and a first lower intermediate inner layer 23.

[0056] - symmetrically, between the central inner layer 24 and the outer layer upper 27, a first upper intermediate inner layer 25 and a second upper intermediate inner layer 26.

[0057] A conductive layer is etched so as to delimit tracks (which can be planes, in particular ground planes).

[0058] The tracks of two (or more) conductive layers of the PCB 2 can be electrically connected by one or more metallized vias running according to the thickness of the PCB 2.

[0059] An orthonormal XYZ frame is attached to an origin point O, which is located on the intermediate layer 24, at the level of the first port 100, constituting the input port of the component operating as a power divider.

[0060] The Z axis is the stacking axis of the layers of PCB board 2.

[0061] The X axis constitutes the longitudinal axis of component 5 from port 100 to the second ports 105, constituting the output ports of the component operating as a power divider.

[0062] The Y axis is the transverse axis.

[0063] Thus, the plane of the central internal layer 24 lies in the XY plane.

[0064] In the present embodiment, component 5 is symmetrical with respect to the XZ plane and the XY plane.

[0065] As illustrated in [Fig.2], component 5 can be subdivided along the X axis into successive sections.

[0066] The first section 101 has an SIW structure similar to that of a conventional triple-plate transmission line (“stripline”).

[0067] More specifically, as illustrated in section A of [Fig.3], component 5 has an upper ground plane track 37, delimited in the upper external conductive layer 27, and a lower ground plane track 31, delimited in the lower external layer 21.

[0068] The upper ground planes 37 and lower ground planes 31 are connected by rows of lateral vias 41 and 42.

[0069] The assembly formed by the two ground planes 37 and 31 and the lateral vias 41 and 42 constitutes the external conductor, or shielding, of the triple-plate line.

[0070] The inner conductor, or core, of the triple-plate line is a so-called "common" line.

[0071] In the present embodiment, the common line is made of a central track 54, delimited in the central internal layer 24.

[0072] The central internal layer 24 is electrically connected to the input port 100 of component 5, and consequently to the input connector 3 to receive the signal to be amplified.

[0073] The central track 54 has a width L1 and a thickness EL

[0074] The central track has a thin profile and, as such, the first section 101 corresponds to a triple-plate line rather than a coaxial guide.

[0075] The central track 54 is shaped to perform an impedance transformation function.

[0076] The width of the central track 54 gradually widens when moving along the X axis.

[0077] Knowing that at a point along the X axis, the value of the width of a track defines the impedance of that track at that point, widening the central track 54 allows a decrease in impedance.

[0078] The impedance of the central track 54 at its proximal end, i.e. the input of the first section 101, is chosen by configuration of the component 5 equal for example to a usual nominal, or standard, impedance of 50 ohms.

[0079] The impedance of the central track 54 at its distal end, i.e. output of the first section 101 is chosen by configuration of component 5 equal for example to 30 Ohms.

[0080] Advantageously, to achieve a significant reduction in impedance between the ends of track 54 without resulting in an excessively wide track, the central track 54 is shaped in a sawtooth pattern to present three successive impedance transformation stages. The transition between two successive stages is associated with the introduction of a pair of ground planes.

[0081] Thus the first stage 541 is located between the ground planes 31 and 37 of the layers 21 and 37 (as illustrated in section A of [Fig.3]), the second stage 542 is located, moreover, between the ground planes 32 and 36 reserved in the layers 22 and 26 (as illustrated in section A' of [Fig.3]), and the third stage 543 is located, moreover, between the ground planes 33 and 35, reserved in the layers 23 and 25 (as illustrated in section A” of [Fig.3]).

[0082] The waveguide has only one central track, which forms the core at the center of the structure, and ground planes, which form the shielding and which gradually approach the central track.

[0083] The advantage of this stepped structure is to transform a standard impedance, typically 50 Ohms, into a low impedance, typically less than 10 Ohms, over a wide frequency band and with a minimum of RF losses and, correlated, with maximum power handling.

[0084] The middle section of component 5, called the channel subdivision section, includes a second section 102 and a third section 103.

[0085] The mass planes of the intermediate layers which had gradually moved closer to the core in section 101 disappear at the level of the transition with section 102.

[0086] The second section 102 has a SIW structure similar to that of a low-impedance rectangular coaxial waveguide. The core gradually thickens along the Z direction in section 102.

[0087] More specifically, as illustrated in section B of [Fig.3], we find the external conductor, which consists of the upper and lower ground planes, 31 and 37, and the lateral vias 41 and 42 electrically connecting these ground planes.

[0088] The internal conductor now consists of a so-called "subdivision" line. This consists of a plurality of internal tracks 52 to 56 superimposed one on top of the other, respectively etched in the internal conductive layers 22 to 26.

[0089] The internal tracks are electrically connected to each other by central vias, for example distributed in two rows, 61 and 62.

[0090] The internal conductor now having a high thickness, we can speak of a waveguide for the second section 102.

[0091] The central track 54 of the second section 102 constitutes the continuation of the central track 54 of the first section 101.

[0092] Runs 52, 53, 55 and 56 are therefore brought to the potential of the central run 54 by vias 61 and 62.

[0093] Advantageously, the internal tracks can have a width that evolves along the X axis so as to provide the second section 102 with an impedance transformation function, in this case an impedance reduction function, so as to present, at the output end of the second section, a very low impedance, for example of 10 Ohms.

[0094] The third section 103 presents a SIW channel separation structure as such. It presents NxM outputs.

[0095] More specifically, as illustrated in section C of [Fig.3], we find the external conductor of the coaxial guide consisting of the upper ground planes 37 and lower ground planes 31 and the lateral vias 41 and 42.

[0096] The internal conductor of the coaxial guide has tracks called first lower and upper internal tracks, 53 and 55, respectively carried by the first lower and upper internal conductive layers, 23 and 25.

[0097] For example, the first upper internal track 55 subdivides, in a subdivision zone, into a plurality of four branches, respectively 71 to 74 and the The first lower internal track 53 is subdivided into a plurality of four branches, respectively 75 to 78.

[0098] The distal end of each of these branches constitutes the outlet of the subdivision section of the pathways.

[0099] Preferably, the inner conductor of the coaxial guide also includes tracks called upper and lower second inner tracks, 52 and 56, respectively carried by the lower and upper second internal conductive layers, 22 and 26.

[0100] The second internal tracks 52 and 56 are interrupted substantially at the level of the subdivision zones of the first internal tracks 53 and 55. They have a capacitive role to improve power transfer.

[0101] The principle of the channel separation section is thus that of spatial dividers / combiners, that is to say that the fields of the mode propagated by the internal conductor of the coaxial waveguide are subdivided in space into NxM approximating modes (to ensure the smoothest possible transition). Here M represents the number of levels, that is to say of first internal tracks, and N represents the number of branches of each first internal track.

[0102] The subdivision section of the channels is designed to ensure optimal distribution (typically an equal distribution of power and impedance) to the high impedance derived lines constituting the fourth section 104 of component 5.

[0103] The internal conductor has, upstream of the subdivision, a sufficient cross-section to allow an efficient transition to the MxN high impedance derived lines.

[0104] Conversely, the cross-section of each of the branches of the subdivision is sufficiently reduced so as to minimize the influence of parasitic propagation modes.

[0105] The location of the ground vias in the transition zone is sensitive and must be adjusted.

[0106] The fourth section 104 has an SIW structure similar to that of a plurality of three-plate transmission lines running parallel.

[0107] It performs a distancing function of each of the derived lines located in the extension of each of the branches of the third section 103.

[0108] It also advantageously performs an impedance transformation function.

[0109] More specifically, as illustrated in section D of [Fig.3], in addition to the upper and lower ground planes, an intermediate half ground plane 34 is delimited in the central conductive layer 24. These three ground planes are connected by rows of vias, not only lateral via rows 41 and 42 but also intermediate via rows 43.

[0110] The tracks delimited in the first upper and lower internal layers, which constitute so many high impedance derived lines, are now isolated from each other.

[0111] Thus, an NxM matrix of triple-plate lines (or coaxial guides, by extension) is formed. In the present embodiment, there are four triple-plate lines per level and two levels within the thickness of the PCB 2.

[0112] Enlarging the width of a derived line forming the core of a triple-plate line between the input and output of the fourth section 104 makes it possible to reduce the impedance.

[0113] The impedance is for example lowered from 80 Ohms at the input to 50 Ohms at the output.

[0114] The distance between the lateral vias is increased to allow spatial separation of the different paths.

[0115] Fig. 4 is an exploded perspective representation of component 5.

[0116] Only the conductive layers are shown in this figure, and the tracks or The ground planes delimited in these layers after engraving are represented with hatching.

[0117] The upper and lower ground planes 31 and 37 are connected by lateral vias, 41 and 42. It should be noted that in [Fig.4], only the intersection of a via with a conductive layer is shown.

[0118] In the central layer 24, the central track 54 extends to a substantially rectangular distal end.

[0119] At the transition between the first and second floors, 541 and 542 of the central runway 54, begin the ground plans 32 and 36.

[0120] At the transition between the second and third floors, 542 and 543 of the central runway 54, begin the ground plans 33 and 35.

[0121] The mass plans 32, 33, 35 and 36 are interrupted at the end of the third floor 543, i.e. between the first and second sections 101 and 102 of component 5.

[0122] The first upper intermediate internal track 55 (respectively lower 53), which is electrically connected to the central track 54 by central vias 61, 62, has a trapezoidal proximal end.

[0123] It travels in a straight line along the longitudinal axis X.

[0124] At the level of the third section 103, it first subdivides into two branches, then each branch in turn subdivides into two new branches. The four branches 71 to 74 (respectively 75 to 78) are connected to the four derived lines 81 to 84 (respectively 85 to 88).

[0125] The geometry of each subdivision is optimized to transmit power to the derivative lines as gradually as possible.

[0126] At the exit of the third section 103, an intermediate ground plane 34, reserved in the central layer 24, allows the lines derived from the two different levels to be isolated.

[0127] 43 vias between the planes of niasse allows the lines derived from the same level to be isolated.

[0128] The second upper internal track 56 (respectively lower 52), which is electrically connected to the central track 54 and to the first internal tracks 53 and 55 by central vias 61, 62, extends between a proximal, trapezoidal end and a pair of distal, substantially rectangular ends resulting from a subdivision into two extensions of the body of the second internal track.

[0129] The subdivision portion of a second internal track is located essentially at the right of the first subdivision portion of the first upper and lower internal tracks and the distal end of the central track 54.

[0130] Its extensions are connected by vias to the first upper and lower internal tracks.

[0131] These extensions constitute adjustable capacitive reinforcements.

[0132] The shape of the subdivision portion of the internal tracks 52 and 56 (width and length of branches / ramifications) is adjusted to optimize the adaptation of the impedances present on either side of the interface between the third and fourth sections 103 and 104 of component 5.

[0133] The component according to the invention can be made in different ways:

[0134] In general, the component has NxM channels, distributed over M levels or layers of the PCB and, on each level, in N derived lines.

[0135] The subdivision section can be carried out according to different geometries to create more or fewer lanes: for example, to generate only four lanes, it is possible not to proceed with the second subdivision; for example again, to create sixteen lanes, it is possible to proceed with a third order of subdivision; in yet another example, to create another number of lanes per level, it is possible to create subdivisions by three branches rather than by two branches.

[0136] This structure, designed primarily to function as a divider, can also operate, in reverse, as a power combiner on similar signals (in spectrum, phase, and amplitude). The recombination of the waves carried by the NxM derivative lines back to the common line is also optimal.

[0137] Advantageously, other ground planes can be provided to enhance the isolation of the coaxial waveguide's central core. In particular, the central conductive layer 24 comprises, on either side of the central track 54 and at a distance from its edges, two lateral half-ground planes. These are connected to the upper and lower ground planes by lateral vias.

[0138] The solution presented above makes it possible to control ripples over a wide bandwidth, phase, power and impedance matching disparities, in particular to minimize the presence and excitation of parasitic modes.

[0139] Advantageously the shape of the subdivision zone results from a three-dimensional electromagnetic simulation to ensure the best compromise between power handling, low losses and wide bandwidth.

[0140] With regard to the insulating layers of the PCB, substrates of various permittivities and / or thicknesses can be used simultaneously. Preferably, the substrates with the highest permittivity are located near the ground planes.

[0141] Instead of a mechanical assembly, the component according to the invention is made using SIW technology, which is more economical, lighter and has a reduced footprint.

[0142] Being compact, the component according to the invention reduces the risk of carrying multiple transmission modes, which are sources of performance degradation, particularly at high frequencies.

[0143] Instead of a structure that separates the tracks with slot-type interfaces and then transitions to microstrip lines, called antipodal lines, the component according to the invention uses subdivisions of tracks (or ribbon lines) with matched impedances, combined with impedance transformers. The component according to the invention has a particularly low cutoff frequency because it is not constrained by the short circuit imposed by the use of antipodal lines.

[0144] Thus, the component according to the invention is characterized by a wide bandwidth.

[0145] The component according to the invention has multiple applications in amplification of power, as a channel-forming element on electronically scanned broadband active antennas, especially for onboard antennas.

Claims

Demands

1. Component (5) power divider / combiner of the coaxial guide type, characterized in that it is made in "substrate integrated waveguide" technology, in a multilayer integrated circuit board (2), which comprises a stack of a plurality of conductive layers separated from each other by insulating layers.

2. Component according to claim 1, wherein the coaxial guide comprises an external conductor and an internal conductor, the external conductor being brought to a ground potential, the internal conductor running inside the external conductor and connecting a first port (100) of the component (5) to each second port (105) of a plurality of second ports of the component (5).

3. Component according to claim 2, wherein the external conductor comprises at least one upper ground plane (37), delimited in an upper conductive layer (27) of the multilayer integrated circuit (2), a lower ground plane (31), delimited in a lower conductive layer (21) of the multilayer integrated circuit (2), and a plurality of lateral metallized vias (41, 42) electrically connecting the upper and lower ground planes.

4. Component according to claim 3, comprising successively, along a longitudinal axis: - an input section (101) for impedance transformation, on which the internal conductor has a common track (54) connected to the first port (100); - an output section (104) for channel separation, on which the internal conductor has a plurality of derived tracks (81 to 88);and, - an intermediate section (102, 103) of subdivision into several paths, on which the internal conductor has a plurality of intermediate tracks (52 to 56), which are superimposed according to a thickness of the multilayer integrated circuit (2) and connected to each other by vias, the plurality of intermediate tracks having at least one central intermediate track (54) connected to the common track of the input section, and at least one intermediate subdivision track having a plurality of branches, each branch being connected to a derived track of the output section.;

5. Component according to claim 4, wherein the common track (54) has one or more impedance transformation stage(s) (541, 542, 543), the width of the common track widening between the two ends of an impedance transformation stage.

6. Component according to claim 5, wherein the central track 54 has first and second impedance transformation stages (542, 543) arranged successively, a first pair of first ground planes (32, 36) arranged on either side of the central track being associated with the first stage and a second pair of second ground planes (33, 35) arranged on either side of the central track being associated with the second stage, the first ground planes covering the first and second stages, the second ground planes covering the second stages only, the second ground planes being closer to the central layer than the first ground planes.

7. Component according to any one of claims 4 to 6, wherein each derived track (81 to 88) has at least one widening section to match a waveguide impedance to the output section.

8. Component according to any one of claims 4 to 7, wherein the intermediate section (102, 103) constitutes a spatial divider / combiner.

9. Component according to any one of claims 4 to 8, wherein the intermediate section (102, 103) comprises a plurality of first intermediate tracks (53, 55) carried by as many different layers of the multilayer circuit, each first intermediate track comprising a plurality of branches (71 to 74, 75 to 78), each branch of the intermediate section being connected to a corresponding derived track among the derived tracks of the output section (104).

10. Component according to claim 9, wherein the intermediate section (102, 103) comprises a plurality of second intermediate tracks (52, 56), each second intermediate track comprising a plurality of branches, which are not connected, each second intermediate track comprising at least one subdivision portion disposed opposite at least one subdivision portion of a first intermediate track.

11. A component according to any one of claims 9 to 10, wherein the outlet section comprises an intermediate ground plane 15 between the derived tracks connected to the branches of a first intermediate track and the derived tracks connected to the branches of another first intermediate track.

12. Component according to any one of claims 2 to 10, wherein the plurality of second ports (105) forms a matrix on a plurality of N levels, each level corresponding to a different layer of the multilayer circuit, each level comprising M second ports.

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