Multi-valued differential reading of a memory device

Abstract

The invention relates to a memory circuit comprising: at least one dual memory structure comprising: a first non-volatile resistive memory cell having a first associated input / output node; a second non-volatile resistive memory cell having a second associated input / output node; a third input / output node common to the first memory cell and the second memory cell, a circuit for reading multi-valued data stored in said dual memory structure, comprising: a detection circuit for performing a comparison operation between the first and second resistors; the detection circuit being configured to generate a comparison result signal and a comparison operation completion indicator signal; a calculation circuit configured to determine the absolute value of the stored data from a time period measured relative to the switching time of the completion indicator signal.Figure for the summary: Fig. 2.

Description

Title of the invention: Multi-valued differential reading of a memory device. Scope of application

[0001] The present invention relates to the field of design of non-volatile memory circuits and more particularly to differential read circuits of resistive memory cells. Technical problem

[0002] Non-volatile memory technologies offer promising components for the design of low-power, dense integrated circuits. Non-volatile memories offer advantages related to data movement efficiency, zero power consumption at rest, and the ability to store more than a single binary bit in a single cell. A memory cell offering this last characteristic is called a "multivalued memory cell." More specifically, in resistive non-volatile memories, information is stored in the components in the form of a resistance whose value varies during a write operation and is estimated during each read operation.

[0003] However, in non-volatile resistive components, the difference between the maximum resistance Rmax and the minimum resistance Rmin remains limited. This drawback leads to a limitation in the dynamic range (also called the memory window) of the memory points constituting the data storage circuit. The limitation in the dynamic range of the memory points considerably reduces the ability of the read circuits to differentiate the resistance levels that can be used to represent multivalued data.

[0004] Thus, there is a need to design new memory cell and read circuit architectures enabling multivalued mode storage and reliable reading despite a narrow memory window.

[0005] Another technical problem addressed by the invention concerns the effect of variability on the reliability of read results for non-volatile memories. "Variability" refers to the inherent deviations or differences that may exist between the individual performances of supposedly identical components within the same integrated circuit. These variations may be due to various factors, such as variations in the manufacturing process, environmental conditions, supply voltages, or temperatures. Variability within a single integrated circuit can lead to differences in the electrical characteristics of individual components on the chip, which can induce false reads in the context of a memory circuit.

[0006] Thus, there is a need to design new memory cell and read circuit architectures that minimize the impact of variability and guarantee reliable read results under various conditions.

[0007] Prior art / Prior art restrictions

[0008] The scientific publication [1] describes techniques for improving the robustness of non-volatile memories to mitigate the effects of single events on data paths. The described solution implements a binary differential read between the resistances of two adjacent cells. The solution proposed in [1] does not resolve the narrow dynamic range problem in resistive non-volatile memory cells. This drawback leads to limited reliability for reading multivalued data from resistive non-volatile memories. Answer to the problem and provision of a solution

[0009] To overcome the limitations of existing solutions, the invention proposes a memory circuit based on dual resistive non-volatile memory cells and several embodiments of suitable read circuits. Dual memory structures (or dual memory points) are formed by pairs of resistive memories whose write values ​​vary inversely. The read circuit according to the invention implements a differential read by comparing the resistances of two resistive elements of a dual memory point. Within the scope of the invention, the evaluation of the stored data is based on the result of the comparison and the time required for the comparison operation.

[0010] In the memory circuit according to the invention, the comparison is applied to a single memory point, therefore between resistive memory cells whose compared resistances exhibit reduced variability. Thus, the invention makes it possible to solve the problems related to variability by eliminating the need for comparison with a reference, as is the case in prior art solutions.

[0011] Furthermore, the read circuit according to the invention makes it possible to exploit the multivalued aspect in emerging resistive non-volatile memory technologies by providing reliable multivalued reads despite a narrow memory window. This advantage is achieved through reading based on the combination of the comparison result and the time measurement extracted from the comparison operation.

[0012] Summary / Claims

[0013] The invention relates to a memory circuit comprising: - at least one dual memory structure comprising: • a first non-volatile resistive memory cell having a first associated input / output node; • a second non-volatile resistive memory cell having a second associated input / output node; • a third input / output node common to the first memory cell and the second memory cell, said third input / output node being intended to receive a common write voltage to vary the first resistance of the first memory cell and the second resistance of the second memory cell in an opposite manner; - a circuit for reading multi-valued data stored in said dual memory structure, the absolute value of said multi-valued data being encoded by the amplitude of the difference between the first resistance and the second resistance, the reading circuit comprising: • a detection circuit to perform a comparison operation between the first and second resistors via the first and second input / output nodes; the detection circuit being configured to generate a comparison result signal and a signal indicating completion of the comparison operation; • a calculation circuit configured to determine: • the sign of the stored data from the comparison result signal; • the absolute value of the stored data from a measured time period relative to the switching time of the completion indicator signal.

[0014] According to a particular aspect of the invention, the calculation circuit includes a first digital stopwatch configured to convert the measured time period into a binary subword; the calculation circuit being configured to concatenate the binary subword with a sign bit corresponding to the comparison result signal to obtain a first signed digital data.

[0015] According to a particular aspect of the invention, the computing circuit further comprises an artificial neuron computing circuit having a first input for receiving the first signed digital data corresponding to a synaptic coefficient and a second input for receiving input data and an output for generating digital output data. The artificial neuron computing circuit includes a multiplier-accumulator circuit to calculate a weighted sum and an activation circuit to apply an activation function to said weighted sum.

[0016] According to a particular aspect of the invention, the computing circuit further comprises a pulsed neuron computing circuit including a digital counter configured to accumulate a plurality of signed first digital data points resulting from a succession of comparison operations performed by the circuit detection and a pulse generator configured to generate a pulse when the digital counter exceeds a predetermined digital threshold.

[0017] According to a particular aspect of the invention, the computing circuit further comprises a pulsed neuron computing circuit comprising an analog accumulator configured to inject a current during the duration of the comparison operation through an accumulation capacitance configured to generate a pulse when its voltage exceeds a predetermined voltage threshold.

[0018] According to a particular aspect of the invention, the memory circuit further comprises a control circuit configured to: - trigger the comparison operation by applying a common read voltage to the third input / output node; - stop the comparison operation when its duration exceeds a predetermined time threshold.

[0019] According to a particular aspect of the invention, the detection circuit comprises a differential current subtraction circuit comprising: - a first transistor having a source connected to ground, having a gate connected to the first input / output node and a drain connected to the first input / output node; - a second transistor having a source connected to ground, having a gate connected to the first input / output node and a drain connected to the second input / output node; - a third transistor having a source connected to ground, having a gate connected to the second input / output node and a drain connected to the second input / output node; - a fourth transistor having a source connected to ground, having a gate connected to the second input / output node and a drain connected to the first input / output node;

[0020] According to a particular aspect of the invention, the detection circuit comprises: - a first inverter having an input connected to the second input / output node and an output connected to the first input / output node; - a second inverter having an input connected to the first input / output node and an output connected to the second input / output node.

[0021] According to a particular aspect of the invention, the detection circuit comprises: - a first reset switch between the first input / output node and an initialization node providing an initialization voltage - a second reset switch between the second input / output node and an initialization node providing the initialization voltage.

[0022] According to a particular aspect of the invention, the detection circuit comprises: - a first capacitive element between the first input / output node and ground; - a second capacitive element between the second input / output node and ground.

[0023] According to a particular aspect of the invention, the control circuit is configured to perform the following steps to trigger a comparison operation: - Reset the first and second input / output nodes to the initialization voltage by temporarily putting the first and second reset switches in a conducting state; - Apply a common read voltage to the third input / output node to load simultaneously: - a first RC circuit formed by the first capacitive element and the first resistive memory cell - and a second RC circuit formed by the second capacitive element and the second resistive memory cell.

[0024] According to a particular aspect of the invention, the detection circuit comprises: - a first analog voltage binarization circuit at the first input / output node; - a second analog voltage binarization circuit at the second input / output node LectB.

[0025] According to a particular aspect of the invention, the detection circuit comprises an OR type logic cell having a first input connected to the output of the first binarization circuit, a second input connected to the output of the second binarization circuit and an output to generate the indicator signal of completion of the comparison operation.

[0026] According to a particular aspect of the invention, the detection circuit further comprises: - an AND type logic cell having a first input connected to the output of the first binarization circuit, a second input connected to the output of the second binarization circuit and an output to generate the indicator signal of completion of the comparison operation. - a logic cell of type OR having a first input connected to the output of the first binarization circuit, a second input connected to the output of the second binarization circuit and an output to generate a signal indicating the triggering of the integration operation.

[0027] According to a particular aspect of the invention, the detection circuit comprises: - a current mirror having a first branch connected to the first input / output node and a second branch connected to the second input / output node; - a comparator having a first input connected to the first input / output node and a second input connected to the second input / output node.

[0028] According to a particular aspect of the invention, the comparator has a switching speed greater than 10 ns. Detailed description

[0029] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0030] Fig. 1a illustrates a first electrical diagram of a dual memory structure used in the memory circuit according to the invention.

[0031] Fig.lb illustrates a second electrical diagram of a dual memory structure used in the memory circuit according to the invention.

[0032] Fig. 1e illustrates an electrical diagram of a memory matrix used in the memory circuit according to the invention.

[0033] Fig. 1d illustrates a cross-sectional view of an example of programmable resistive storage structures used in the memory circuit according to the invention.

[0034] Figure [Fig. 2] illustrates a functional diagram of the reading circuit according to the invention.

[0035] Fig. 3a illustrates a timing diagram of the output signals of the detection circuit according to the invention in response to a first configuration.

[0036] Fig. 3b illustrates a timing diagram of the output signals of the detection circuit according to the invention in response to a second configuration.

[0037] Fig. 3c illustrates a timing diagram of the output signals of the reading circuit according to the invention in response to a third configuration.

[0038] Fig. 4a illustrates a calculation circuit in the reading circuit according to a first embodiment.

[0039] Fig. 4b illustrates a calculation circuit in the reading circuit according to a second embodiment.

[0040] Fig. 4c illustrates a calculation circuit in the reading circuit according to a third embodiment.

[0041] Fig. 4d illustrates a calculation circuit in the reading circuit according to a fourth embodiment.

[0042] Fig. 5a illustrates a detection circuit in the reading circuit according to a first embodiment.

[0043] Fig. 5b illustrates a first example of the subtraction circuit in the reading circuit according to the first embodiment.

[0044] Fig. 5c illustrates a second example of the subtraction circuit in the reading circuit according to the first embodiment.

[0045] Fig. 6a illustrates a detection circuit in the reading circuit according to a second embodiment.

[0046] Fig. 6b illustrates a timing diagram of the output signals obtained by the detection circuit in the reading circuit according to the second embodiment.

[0047] Figure 7 illustrates a detection circuit in the reading circuit according to a third embodiment.

[0048] Figure 1a illustrates a first electrical diagram of a dual memory structure SMj used in the memory circuit 10 according to the invention. The memory circuit 10 comprises a memory matrix including at least one memory point comprising the dual memory structure SMj illustrated. At this stage, we will only present the dual memory structure SMj as such.

[0049] The dual memory structure SM<; j> comprises a first non-volatile resistive memory cell MRA and a second non-volatile resistive memory cell MRb connected in series. Non-volatile resistive memory technology is based on the phenomenon of variable material resistance. Each of the two memory cells consists of a resistive element whose electrical resistance can be reversibly modified by applying, for example, a voltage between an upper and a lower electrode. The first memory cell MRA comprises an upper electrode sup_A and a lower electrode inf_A. The second memory cell MRB comprises an upper electrode sup_B and a lower electrode inf_B. According to a convention chosen for illustrative purposes, when a positive voltage is applied to the third input / output node ELI, the resistance of the resistive element MRA gradually decreases, tending towards a low resistive value.When a negative voltage is applied to the third ELI input / output node, the resistance of the MRA resistive element gradually increases, tending towards a high resistive value.

[0050] According to a first alternative, the materials of the second MRB memory cell are chosen so as to behave oppositely to those of the first non-volatile resistive MRA memory cell following the application of a common write voltage. When a negative voltage is applied to the upper electrode sup_B, the resistance of the resistive element MRB gradually decreases, tending towards a low resistive value. When a positive voltage is applied to the upper electrode sup_B, the resistance of the resistive element MRB gradually increases, tending towards a high resistive value. In this case, the first MRA memory cell and the second MRB memory cell are mounted as follows: The lower electrode inf_A of the first MRA memory cell is connected to the lower electrode inf_B. of the second memory cell MRB so as to form a central node NC of the dual memory structure SM< ; j > .

[0051] The dual memory structure SM<; j> further comprises a first input / output node LectA, a second input / output node LectB, a third input / output node ELI, and a fourth floating node EL2. The upper electrode sup_A of the first memory cell MRA constitutes the first input / output node LectA. The upper electrode sup_B of the second memory cell MRB constitutes the second input / output node LectB. The third input / output node ELI is separated from the central node NC by a resistance RI (which may be a parasitic resistance) on the row (or column) connected to said dual memory structure SM<; j>. The fourth input / output node EL2 is symmetric to the third input / output node ELI with respect to the central node NC. The fourth input / output node EL2 is separated from the central node NC by a parasitic resistance R2 on the row (or column) connected to said dual memory structure SM<; j>.

[0052] Applying a common write voltage to the third ELI input / output node allows the first resistance RA of the first memory cell MRa and the second resistance RB of the second memory cell MRB to vary in opposite ways.

[0053] According to a first alternative, the second memory cell MRB is identical to the first memory cell MRA. In this case, the first memory cell MRA and the second memory cell MRB are mounted as follows: The lower electrode inf_A of the first memory cell MRA is connected to the upper electrode sup_B of the second memory cell MRB so as to form a central node NC of the dual memory structure SM< ; j >. Thus, when a common write voltage is applied to the third input / output node ELI, the first memory cell MRA has a voltage opposite to that seen by the second memory cell MRB. Applying a common write voltage to the third input / output node ELI allows the first resistance RA of the first memory cell MRA and the second resistance RB of the second memory cell MRB to vary in opposite ways.

[0054] According to a specific aspect of the invention, the first and second memory cells MRA and MRB are implemented using a single common electronic component. This implementation makes it possible to obtain compact dual memory structures SM<; j>. This results in a reduction in the memory circuit area and an improvement in data read and write speeds. Implementing the dual memory cell with a common component also reduces the energy consumption of the memory circuit by halving the number of write accesses.

[0055] Alternatively, each of the first and second memory cells MRA and MRB is implemented by a separate associated electronic component. Preferably, the two components are adjacent to limit the effect of variability. In this case, it is possible to write the first and second memory cells MRA and MRB by applying a single write voltage or by applying two separate write voltages of opposite signs.

[0056] Fig. 1b shows a second electrical diagram of a dual memory structure SMj used in the memory circuit 10 according to the invention. This embodiment of the dual structure is adapted for integration into a memory matrix composed of several dual memory structures. The dual memory structure SMj further comprises a write transistor Tl, a first read transistor TA, and a second read transistor TB. The write transistor Tl is mounted between the third input / output node, denoted here as SL, and the resistor RL. The gate of the write transistor Tl is controlled by a selection signal WLWR1TE. When Tl is in the conducting state, it is possible to apply the common write voltage VSL to the central node NC through the write transistor Tl and the parasitic resistor RL. The first read transistor TA is mounted between the first input / output node LectA and the upper electrode sup_A.The second read transistor TB is mounted between the second input / output node LectB and the upper electrode sup_B. The read transistors TA and Tb are controlled by a common control signal WLREAD. The integration of the transistors allows selection of the dual memory structure from among others for a read and / or write operation. Preferably, the gates of transistors Tl, TA, and TB are thick-film, for a given technology node, to limit leakage currents in the dual memory structure and thus in the memory circuit.

[0057] Figure 11 illustrates an electrical diagram of a memory matrix Mx used in the memory circuit 10 according to the invention. By way of illustrative and non-limiting example, the memory matrix Mx comprises two rows and three columns. Each memory point of the matrix Mx is formed by a dual memory structure SMj described in Figure 11.

[0058] Fig. 1d illustrates a cross-sectional view of an example of an embodiment of a resistive storage structure SM<; j> on a single common component 11 and used in the memory circuit 10 according to the invention.

[0059] The component 11 comprises a stack of thin films including a central layer 110 having a first face and a second face opposite the first face, an upper layer 111 disposed on said first face, and a lower layer 112 disposed on the second face. The central layer 110 is a magnetic and conductive layer comprising a first magnetic domain 110u In which the magnetic polarization is directed upwards, and a second magnetic domain 110d in which the magnetic polarization is directed downwards. The two domains are separated by a movable barrier under the action of the passage of an electric current through the central layer 110. The upper layer 111 is a magnetically conductive layer having a uniform magnetic polarization directed upwards. The upper layer 111 is separated from the central layer 110 by a non-magnetic layer 113. The lower layer 112 is a magnetically conductive layer having a uniform magnetic polarization directed downwards. The lower layer 112 is separated from the central layer 110 by a non-magnetic layer 114. The component 11 includes a first electrode deposited on the upper layer 111 and acting as the first input / output node LectA.The component 11 further comprises a second electrode deposited on the outer face of the lower layer 112 and acting as a second input / output node LectB. The component 11 further comprises a third electrode deposited on one of the faces of the central layer 110 and acting as a third input / output node ELI (or SL in the context of a matrix). The component 11 further comprises a fourth electrode deposited on one of the faces of the central layer 110 and acting as the fourth input / output node EL2 (or BL in the context of a matrix).

[0060] When the magnetic domain of the central layer 110 is oriented in the same direction as the fixed domain of the upper layer 111, the resistive element formed by the central layer 111, the insulating layer 113, and the upper layer 111 exhibits a low resistive state.Conversely, when the magnetic domain of the central layer 110 is oriented in the opposite direction to that of the fixed domain of the upper layer 111, the resistive element MRA formed by the central layer 111, the insulating layer 113 and the upper layer 111, exhibits a low resistive state. Symmetrically, the lower layer 112 behaves in the same way.

[0061] Applying a writing voltage to the ELI electrode allows continuous control of the barrier position and thus continuous control of the resistance of the first MRA memory cell associated with the upper layer 111 and the resistance of the second MRB memory cell associated with the lower layer 112. Since the magnetic polarization is opposite between the upper and lower layers, an opposite variation is obtained between the two memory cells for the same write access and a single common write operation.

[0062] According to an alternative aspect, the two layers 111 and 112, with opposite fixed polarizations, are arranged adjacently on the same face of the central layer 110 with variable polarization.

[0063] For example, the thickness of the central layer 110 is greater than or equal to 5 nm. The central layer 110 may be a ferromagnetic material, a ferrimagnetic material, or a combination thereof and an antiferromagnetic material whose magnetic state can be modified by a current. The central layer 110 may be formed by a stacking of several sublayers. Preferably, each of the sublayers should have at least one element selected from the group comprising Co, Ni, Fe, Pt, Pd, Gd, Tb, Mn, Ge, and Ga.

[0064] For example, the upper layer 111 is composed of a material that promotes a coherent tunneling effect with the displacement layer of the magnetic domain wall 30. It may consist of a metal such as Cr, Mn, Co, Fe, or Ni, an alloy including these metals, an alloy combining these metals with B, C, and N, or equivalent. Examples include Co-Fe, Co-Fe-B, Ni-Fe, or a Heusler alloy such as Co2FeSi. A similar material with opposite polarization may also be used for the lower layer 112. The thickness of each of the upper and lower layers is greater than or equal to 5 nm.

[0065] For example, the insulating layer 113, 114 can be made of a non-magnetic insulator, a semiconductor, or a metal. Examples of non-magnetic insulators include Al₂O₃, SiO₂, MgO, and MgA₂O₄, with variations where Al, Si, and Mg are partially replaced by Zn, Be, or equivalent materials. These materials, having a large band gap, offer excellent insulating properties. The insulating layer 113, 114 acts as a tunnel barrier. Non-magnetic metals such as Cu, Au, and Ag, or semiconductors such as Si, Ge, CuInSe₂, CuGaSe₂, and Cu(In,Ga)Se₂ can also constitute this layer. The thickness of the insulating layer 113, 114, for example, can be 20 Å or more. By adjusting the thickness or material of the insulating layer 113, 114, the resistance of a resistive memory cell MRa, MRb can be adjusted.

[0066] Figure 2 illustrates a functional diagram of the memory circuit 10 according to the invention. To simplify the explanation of the reading according to the invention, we will limit ourselves to illustrating a single memory structure SMj without loss of generality and by way of non-limiting example. The memory circuit comprises at least one dual memory structure SMj. <ijj>(previously described) and a CLect read circuit for multi-valued data stored in said dual memory structure SM <ijj>The absolute value of said multi-valued data is encoded by the magnitude of the difference between the first resistor Ra and the second resistor RB. The sign of the stored multi-valued data is encoded by the comparison between the first resistor RA and the second resistor RB. The memory circuit 10 further includes a control circuit CONT configured for select a dual memory structure SM <ijj>target and control the triggering and stopping of write and read operations.

[0067] The CLect read circuit is configured to perform a multi-valued differential read of the data stored in the dual memory structure SM <ijj>The CLect read circuit comprises a SENSE detection circuit and a UE calculation circuit. The CLect read circuit is connected to the first input / output node LectA and the second input / output node LectB. The SENSE detection circuit is configured to perform a comparison operation between the first and second resistors MRA and MRB via the first and second input / output nodes LectA and LectB. The SENSE detection circuit generates a comparison result signal s2 and a completion indicator signal (if) from the comparison operation to the UE calculation circuit. The UE calculation circuit determines the sign of the stored data from the comparison result signal s2. The UE calculation circuit also determines the absolute value of the stored data from a time period At measured relative to the switching time of the completion indicator signal (if).The UE computing circuit thus determines a signed and multi-valued (not limited to a binary result) digital read result from the stored data by exploiting the two aforementioned pieces of information: a temporal information and a binary comparison information.

[0068] For example, the measured time At is an indicator of the time required to perform the comparison operation. In this case, the read operation according to the invention consists of performing a comparison of the two resistive elements MRA and MRb of the dual memory structure SM <ijj>The magnitude of the difference between the two resistances determines the switching time of the SENSE detection circuit to perform the comparison operation. The larger the absolute value of the resistance difference AR=RA-RB, the faster the comparison operation. Conversely, the closer the resistances MRA and MRB are, the longer the switching time for the comparison operation. Measuring the duration of the comparison operation thus allows for the evaluation of the stored analog data. A multitude of values ​​can therefore be encoded by the magnitude of the resistance difference AR=RA-RB and can be read by measuring the duration of the comparison operation.

[0069] Fig. 3a illustrates a timing diagram of the binary output signals of the SENSE detection circuit in response to a first configuration defined by RA > RB with a small AR difference.

[0070] In the initial state t0, the comparison result signal s2 is at a logic low state and the completion indicator signal si is at a logic low state. At tl, the control circuit CONT triggers the read operation by activating the detection circuit SENSE is activated via the activation signal d0 (not shown here). The comparison operation takes place over a relatively long time interval At = t2 - t1 because the difference AR is small. This is due to the need for more time for the SENSE detection circuit to decide whether or not to switch, depending on the comparison result. According to a non-exhaustive convention, when RA > RB, the SENSE detection circuit generates a low logic result s2. When Ra <Rb le circuit de détection SENSE génère un résultat de comparaison s2 à l’état logique haut. A t2, le signal indicateur d’achèvement si bascule à un état logique haut indiquant la fin de l’opération de comparaison. Même après t2, le résultat de comparaison s2 est maintenu à un état logique bas indiquant que RA> RB.The absolute value of the stored data is determined by quantifying the resistance difference RA-RB, which is quantified by the duration of the comparison operation (switchover time required).

[0071] Figure 3b illustrates a timing diagram of the binary output signals of the SENSE detection circuit in response to a second configuration defined by RA <RB avec une différence AR forte.

[0072] In the initial state t0, the comparison result signal s2 is at a logic low state and the completion indicator signal si is at a logic low state. At tl, the CONT control circuit triggers the read operation by activating the SENSE detection circuit via the activation signal d0 (not shown here). The comparison operation takes place over the relatively short time period At = t2 - tl because the difference AR is high. This is explained by the need for a short time for the SENSE detection circuit to decide whether or not to switch over, depending on the comparison result. At t2, the completion indicator signal si switches to a logic high state, indicating the end of the comparison operation. In addition, the comparison result s2 switches to a logic high state, indicating that RA <RB.The absolute value of the stored data is determined by quantifying the resistance difference RA-RB, which is quantified by the short duration of the comparison operation (switchover time required).

[0073] In the illustrated examples, the output signals si and s2 are binary signals. Alternatively, it is possible to implement a SENSE detection circuit that generates a single ternary signal s12 containing both the comparison result and the duration of the comparison operation. The following table illustrates the two binary and ternary embodiments: States Signal Type Signals Initial Final RA>RB Final RA <RB ternaire sl2 0 -1 +1 binaires si 0 1 1 s2 X 0 1

[0074] Thus, in this embodiment, the UE computing circuit is configured to determine the absolute value of the stored data according to the following relationship: the absolute value of the data stored in the dual memory structure is inversely proportional to the time period At= t2-tl.

[0075] Advantageously, the CONT control circuit is configured to trigger the comparison operation by applying a common read voltage to the third input / output node SL. Furthermore, the CONT control circuit is configured to stop the comparison operation when the duration At = t2 - t1 exceeds a predetermined time threshold Atmax. This configuration is advantageous when the resistance difference RA - RB is small, corresponding to stored data close to zero. In this case, stopping the comparison operation after a predetermined time threshold Atmax limits the energy consumption of the read circuit according to the invention, prevents the system from freezing for too long while waiting for a switch that never occurs, and clearly implements a zero value.

[0076] Figure 3c illustrates timing diagrams of the SENSE detection circuit, indicating the completion signal of the SENSE detection circuit, in which the switching time is alternatively quantified. Timing diagram 301 corresponds to the configuration defined by Ra > Rb with a small difference AR. Timing diagram 302 corresponds to the configuration defined by RA <RB avec une différence AR fort.

[0077] According to this embodiment, the CONT control circuit is configured to trigger the comparison operation at time t1 and to stop the comparison operation at a predetermined time t3. The switching of the SENSE detection circuit occurs at time t2 between t1 and t3. The duration of the comparison operation is quantified between the switching time t2 of the completion indicator signal si and the predetermined stopping time t3. When RA-RB is low, the time difference A't = t3 - t2 is small because the switching time is closer to t3. Conversely, when RA-RB is high, the time difference A't = t3 - t2 is large because the switching time is closer to t1.Thus, in this implementation, the UE computing circuit is configured to determine the absolute value of the stored data according to the following relationship: the absolute value of the data stored in the dual memory structure is proportional to the time period A't= t3-t2. .

[0078] Figure 4a illustrates a calculation circuit UE within the reading circuit Ciect according to a first embodiment. The calculation circuit UE includes a first digital timer chrl. The result comparison signal s2 is stored as a unit bit. The control circuit CONT triggers the digital timer chrl simultaneously with the triggering of the comparison operation by The SENSE detection circuit. The digital timer chrl is stopped when the completion indicator signal si is activated. The digital timer chrl thus functions as a digital counter configured to convert the time period At=t2-tl into a binary subword according to the embodiment described in Figures 3a and 3b.

[0079] Alternatively, the digital timer chrl is activated during the switchover t2 and the predetermined time t3 defined in the embodiment of [Fig. 3c]. The digital timer chrl thus functions as a digital counter configured to convert the time period A't=t3-t2 into a binary subword.

[0080] In both cases, the UE calculation circuit is configured to concatenate the binary subword corresponding to the measured time information (At or A't) with the sign bit corresponding to the comparison result signal s2 to obtain a first signed digital data point xout. The first signed digital data point xout is then processed by calculation means, not shown, internal or external to the memory circuit 10.

[0081] Figure 4b illustrates a UE calculation circuit within the Ciect reading circuit according to a second embodiment. The UE calculation circuit according to the second embodiment retains the characteristics and advantages of the first embodiment. The UE calculation circuit further comprises an artificial neuron calculation circuit ANi. The artificial neuron calculation circuit ANi receives the concatenation of the binary subword corresponding to the measured temporal information with the binary sign bit. The received binary word corresponds to a synaptic coefficient w associated with the artificial neuron Ni. Furthermore, the artificial neuron calculation circuit ANi receives an external input data xin. The artificial neuron calculation circuit ANi is configured to generate a digital output data xout from the external input data xinet of the synaptic weight w.The ANi artificial neuron computing circuit includes a multiplier-accumulator circuit to calculate a weighted sum of sequentially supplied external input data with synaptic weights read from the different dual memory structures SM<; j>. The ANi artificial neuron computing circuit further includes an ACT activation circuit to apply an activation function to said weighted sum. The activation function implemented by the ACT activation circuit is a non-linear function, such as a ReLu function.

[0082] Figure 4c illustrates a UE calculation circuit within the Ciect reading circuit according to a third embodiment. The UE calculation circuit according to the third embodiment retains the characteristics and advantages of the first embodiment. The UE calculation circuit further comprises a calculation circuit for SNi impulse neuron. The SNi impulse neuron computing circuit includes a digital counter chr2, an XOR logic gate, and a DS pulse generator. At each read operation, the digital counter chr2 receives the binary subword corresponding to the time information measured by the first stopwatch chrl. The digital counter chr2 is configured to accumulate a plurality of signed first digital data points resulting from a series of comparison operations. The XOR logic gate receives, on the one hand, the sign bit generated from the comparison result s2 and, on the other hand, the sign of the external pulse to determine the sign of the integration performed by the SNi impulse neuron computing circuit. If the sign of the integration is positive, the digital counter chr2 increments the binary subword corresponding to the time information measured by the first stopwatch chrl; otherwise, it decrements it.

[0083] When the sum accumulated in the digital counter chr2 reaches a predetermined threshold, the pulse generator DS is configured to generate a pulse and the digital counter chr2 is reset to zero.

[0084] The third embodiment allows for the implementation of a pulsed neural network within the memory circuit 10. The advantage of this implementation is the ability to eliminate data exchange operations between the memory circuits and the processing circuits. These data exchange operations are generally very energy-intensive.

[0085] Figure 4d illustrates a UE calculation circuit within the Ciect reading circuit according to a fourth embodiment. The fourth embodiment of the UE calculation circuit differs from that of the third embodiment by an analog implementation of the integration function (increment or decrement). The digital counter chr2 is replaced by an analog accumulator AAN comprising a storage capacitor. In this case, the integration consists of injecting a current, the sign of which depends on the result of the comparison, onto said capacitor for a duration dependent on the comparison time. The voltage of said capacitor is controlled to generate a pulse above a predetermined voltage threshold. The fourth embodiment retains the same advantages detailed for the third embodiment.

[0086] Figure 5a illustrates the SENSE detection circuit according to a first embodiment. The SENSE detection circuit is connected to the first input / output node LectA via a conduction line LCA. The conduction line LCA has an intrinsic capacitance CA between the first input / output node LectA and ground. Alternatively, the capacitance CA can be implemented by a capacitive element. Physically, the SENSE sensing circuit is connected to the second input / output node LectB via a conduction line LCB. The conduction line LCB has an intrinsic capacitance CB between the second input / output node LectB and ground. Alternatively, the capacitance CB can be implemented using a physical capacitive element. The capacitances CA and CB, in combination with the resistors RA and Rb, allow for time constants greater than 10 ns. This is slow enough to allow for accurate measurement of the duration of the comparison operation At and thus the measurement of the resistance difference AR. The SENSE sensing circuit includes a current subtraction circuit SC to perform the comparison operation between the resistors RA and RB. The SENSE sensing circuit generates the result comparison signal s2 from a current injection through the first memory cell MRA and the second memory cell MRB.

[0087] The SENSE detection circuit further includes a first reset switch i1 between the first input / output node LectA and an initialization node providing an initialization voltage Vinit (Vinit = 0, for example). The SENSE detection circuit further includes a second reset switch i2 between the second input / output node LectB and an initialization node providing the initialization voltage Vinit.

[0088] Prior to executing a read operation, the first and second reset switches, i1 and i2, are set to a forward state by the CONT control circuit to bring the input / output nodes LectA and LectB to the initialization voltage Vinit. Vinit=0 is used as a non-limiting example. When the CONT control circuit triggers the read operation, a non-zero read voltage VSL is applied to the third node, SL.This induces a current flow in the following two branches: a first branch formed by the conduction line LCA, the first memory cell MCA, and the capacitor CA; and a second branch formed by the conduction line LCB, the second memory cell MCB, and the capacitor CapB. In response to the application of the read voltage VSL, the current subtraction circuit SC switches the potential at node LectA to a non-zero voltage and node LectB to zero voltage, or vice versa, depending on the inequality between RA and Rb. Thus, the SENSE detection circuit acts on the potential across capacitors CA and Cb following the application of the read voltage. The switching speed of the current subtraction circuit SC depends on the magnitude of the difference between RA and Rb.

[0089] Optionally, the SENSE detection circuit includes a first analog voltage binarization circuit at the first input / output node LectA and a second analog voltage binarization circuit at the second input / output node LectB. For example, each of the two BUFF binarization circuits is implemented using chains of inverters to shape the voltages at nodes LectA and LectB to logic high or low levels. Thus, the first binarization circuit generates the comparison result signal s2 at its output, and the second binarization circuit generates the complement / 2 of the comparison result signal s2 at its output.

[0090] The SENSE detection circuit further includes an OR logic gate that receives the comparison result signal s2 associated with the first branch and the complementary signal / 2 associated with the second branch. Initially, both signals s2 and s'2 are in a low logic state, and therefore the output of the OR logic gate is also in a low logic state. At the moment of switching of the current subtraction circuit SC (end of the comparison), at least one of the signals s2, s'2, goes to a high logic state. Thus, the OR logic gate generates a high state at its output corresponding to the completion indicator signal s'.

[0091] Figure 5b illustrates a first example of the SC subtraction circuit in the Ciect read circuit according to the first embodiment. In this example, the SC subtraction circuit comprises a first transistor N1 having its source connected to ground, its gate connected to the first input / output node LectA, and its drain connected to the first input / output node LectA. The SC subtraction circuit further comprises a second transistor N2 having its source connected to ground, its gate connected to the first input / output node LectA, and its drain connected to the second input / output node LectB. The SC subtraction circuit further comprises a third transistor N3 having its source connected to ground, its gate connected to the second input / output node LectB, and its drain connected to the second input / output node LectB.The SC subtraction circuit further includes a fourth transistor, N4, with its source connected to ground, its gate connected to the second input / output node LectB, and its source connected to the first input / output node LectA. This creates two crossed current mirror branches that compete during a transient state following the application of the read voltage to the SL node. The first branch is connected to the first input / output node LectA, associated with the first memory cell MRA. The second branch is connected to the second input / output node LectB, associated with the second memory cell MRB. In steady state, the LectA and LectB nodes are biased such that the voltage at the node connected to a low resistance is significantly higher than that at the node connected to a high resistance.

[0092] In this example, the first reset switch is implemented by a reset transistor N5' controlled by a RaZ signal generated by the circuit of CONT control. In addition, the second reset switch i2 is implemented by a reset transistor N5 controlled by the RaZ signal.

[0093] Figure 5c illustrates a second example of the SC subtraction circuit in the Ciect read circuit according to the first embodiment. In this example, the SC subtraction circuit includes a first inverter formed by transistors N6 and P6. The first inverter has an input connected to the second input / output node LectB and an output connected to the first input / output node LectA. The SC subtraction circuit further includes a second inverter formed by transistors N7 and P7. The second inverter has an input connected to the first input / output node LectA and an output connected to the second input / output node LectB. This creates a latch-type loop. Applying a read voltage to the SL node causes a transient response in the outputs of the latch-type loop until a steady state is reached.In steady state, nodes LectA and LectB are biased such that the voltage at the node connected to a low resistance is much greater than that at the node connected to a high resistance.

[0094] Figure 6a illustrates a SENSE detection circuit within the readout circuit according to a second embodiment. In the second embodiment, there is no current injection through the conduction lines LCA and LCB. The SENSE detection circuit comprises equal capacitors CA and CB and reset switches i1 and i2 mounted similarly to the first embodiment of the SENSE detection circuit. The SENSE detection circuit includes a first and a second binarization circuit mounted similarly to the first embodiment of the SENSE detection circuit. The second embodiment differs from the first embodiment by the absence of the current subtraction circuit.Furthermore, the SENSE detection circuit includes an OR logic gate with a first input connected to the output of the first binarization circuit BUFFA and a second receiving input connected to the output of the second binarization circuit BUFFb. Additionally, the SENSE detection circuit includes an AND logic gate with a first input connected to the output of the first binarization circuit BUFFa and a second receiving input connected to the output of the second binarization circuit BUFFb.

[0095] Figure 6b illustrates a timing diagram of the output signals obtained by the detection circuit in the reading circuit according to the second embodiment. The SENSE detection circuit according to the second embodiment operates as follows: Initially at t0, the initialization switches i11 and i2 are set to a conducting state to initialize the two nodes LectA and LectB to the initialization voltage Vinit. This induces the initialization of the two capacitors CA and CB to the same initial voltage Vinit. For example, at tl, the CONT control circuit applies a common read voltage VSL to the third VSL node. This triggers the simultaneous charging of the first capacitance CA and the second capacitance CB. The first capacitance CA is charged through the first resistive memory cell MRA according to the first time constant rA = CA RA. Similarly, the second capacitance CB is charged through the second resistive memory cell MRB according to the second time constant rB = CB RB. If RA < RB, the first capacitance CA charges before the second capacitance CB, and vice versa when RA > RB. In the example shown, Ra > Rb. Thus, at tl, the voltage across the first capacitance CA exceeds the switching threshold of the first binarization circuit BUFFA, whose output s2 switches to a logic high. This indicates to the UE computing circuit the result of the comparison between RA and RB.This switching induces the switching of the OR gate's output s3 to a high logic state. The OR gate thus generates a signal indicating that the integration operation s3 has been triggered by the processing circuit UE. Later, at t3, the second capacitance CB exceeds the switching threshold of the second binarization circuit BUFFB, whose output $2 switches to a high logic state. This switching induces the switching of the AND gate's output si to a high logic state, thus indicating the completion of the comparison (and therefore the read) operation. The time period A''t = t3 - t2 is proportional to the difference rA - rB, which depends on the difference AR = Ra - Rb. The duration A''t is measured by the processing circuit UE as described previously.

[0096] The second embodiment of the SENSE detection circuit makes it possible to avoid the injection of current into the conduction lines LCA and LCB at each read operation and thus reduce the energy consumption of the memory circuit 10.

[0097] Figure 7 illustrates a SENSE detection circuit within the readout circuit according to a third embodiment. The SENSE detection circuit comprises a current mirror MC acting as a load and a comparator COMP for performing a voltage comparison. The current mirror MC has a first branch connected to the first input / output node LectA and a second branch connected to the second input / output node LectB. Each branch constitutes a voltage divider. The comparator COMP has a first input connected to the first input / output node LectA and a second input connected to the second input / output node LectB. The comparator COMP is designed to have a switching speed greater than 10 ns. This allows the switching time to be measured and thus the resistance difference AR = Ra - Rb to be estimated. The advantage of this embodiment lies in limiting the voltage variations at the input / output nodes LectA and LectBet thus limits the noise between dual memory structures SM< ; j > of the same matrix Mx.

[0098] References: [1] Hardening techniques for MRAM-based non-volatile storage cells and logic; Lakys et al, Proceedings of the European Conference on Radiation and its Effects on Components and Systems, RADECS, 2011.< / ijj> < / ijj> < / ijj> < / ijj> < / ijj>

Claims

1. Demands Memory circuit (10) comprising: at least one dual memory structure (SM< ; j >) comprising: • a first non-volatile resistive memory cell (MRA) having a first associated input / output node (LectA); • a second non-volatile resistive memory cell (MRB) having a second associated input / output node (LectB); • a third input / output node (SL) common to the first memory cell (MRA) and the second memory cell (MRB), said third input / output node (SL) being intended to receive a common write voltage (VSl) to vary the first resistance (RA) of the first memory cell (MRA) and the second resistance (RB) of the second memory cell (MRB) in an opposite manner; a reading circuit (CLect) for multi-valued data stored in said dual memory structure (SM< ; j > ), the absolute value of said multi-valued data being encoded by the amplitude of the difference between the first resistance and the second resistance, the reading circuit (CLect) comprising: • a detection circuit (SENSE) to perform a comparison operation between the first and second resistors via the first and second input / output nodes (LectALectB); the detection circuit (SENSE) being configured to generate a comparison result signal (s2) and a completion indicator signal (si) of the comparison operation; • a computing circuit (UE) configured to determine: • the sign of the data stored from the comparison result signal (s2); • the absolute value of the data stored from a time period (At) measured with respect to the switching time of the completion indicator signal (si).

2. Memory circuit (10) according to claim 1 wherein the computing circuit (UE) comprises a first digital timer (chrl) configured to convert the measured time period (At) into a binary subword; the computing circuit (UE) being configured to concatenate the binary subword with a sign bit corresponding to the comparison result signal (s2) to obtain a first signed digital data (w, xout).

3. Memory circuit (10) according to claim 2 wherein the computing circuit (UE) further comprises an artificial neuron computing circuit (ANi) having a first input for receiving the first signed digital data (w) corresponding to a synaptic coefficient (w) and a second input for receiving input data (xin) and an output for generating digital output data (xout), the artificial neuron computing circuit (ANi) comprising a multiplier-accumulator circuit for calculating a weighted sum and an activation circuit for applying an activation function to said weighted sum.

4. Memory circuit (10) according to claim 2 wherein the computing circuit (UE) further comprises a pulse neuron computing circuit (SNi) comprising a digital counter (chr2) configured to accumulate a plurality of first signed digital data from a succession of comparison operations performed by the sensing circuit (SENSE) and a pulse generator configured to generate a pulse when the digital counter (chr2) exceeds a predetermined digital threshold.

5. Memory circuit (10) according to claim 2 wherein the computing circuit (UE) further comprises a neuron computing circuit impulse (SNi) comprising an analog accumulator (AAN) configured to inject a current during the comparison operation through an accumulation capacitor configured to generate a pulse when its voltage exceeds a predetermined voltage threshold.

6. Memory circuit (10) according to any one of claims 1 to 5 further comprising a control circuit (CONT) configured to: - trigger the comparison operation by applying a common read voltage to the third input / output node (SL); - stop the comparison operation when its duration exceeds a predetermined time threshold.

7. Memory circuit (10) according to any one of claims 1 to 6 in which the sensing circuit (SENSE) comprises a differential current subtraction circuit (SC) comprising: - a first transistor (NI) having a source connected to ground, having a gate connected to the first input / output node (LectA) and a drain connected to the first input / output node (LectA); - a second transistor (N2) having a source connected to ground, having a gate connected to the first input / output node (LectA) and a drain connected to the second input / output node (LectB); - a third transistor (N3) having a source connected to ground, having a gate connected to the second input / output node (LectB) and a drain connected to the second input / output node (LectB);- a fourth transistor (N4) having a source connected to ground, having a gate connected to the second input / output node (LectB) and a drain connected to the first input / output node (LectA);

8. Memory circuit (10) according to any one of claims 1 to 6 in which the detection circuit (SENSE) comprises: - a first inverter (N6,P6) having an input connected to the second input / output node (LectB) and an output connected to the first input / output node (LectA); - a second inverter (N7,P7) having an input connected to the first input / output node (LectA) and an output connected to the second input / output node (LectB).

9. Memory circuit (10) according to any one of claims 1 to 8 in which the sensing circuit (SENSE) comprises: - a first reset switch (il, N5',N8) between the first input / output node (LectA) and an initialization node providing an initialization voltage (Vinit) - a second reset switch (i2, N5,N9) between the second input / output node (LectB) and an initialization node providing the initialization voltage (Vinit).

10. Memory circuit (10) according to any one of claims 1 to 9 in which the sensing circuit (SENSE) comprises: - a first capacitive element (CA) between the first input / output node (LectA) and ground; - a second capacitive element (CB) between the second input / output node (LectB) and ground.

11. A memory circuit (10) according to claim 10 in combination with claim 9, wherein the control circuit (CONT) is configured to perform the following steps to trigger a comparison operation: - Reset the first and second input / output nodes (LectA LectB) to the initialization voltage (Vinit) by temporarily setting the first and second reset switches to a conducting state; - Apply a common read voltage to the third input / output node (SL) to simultaneously load: - a first RC circuit formed by the first capacitive element (CA) and the first resistive memory cell (MRa) - and a second RC circuit formed by the second capacitive element (CB) and the second resistive memory cell (MRB)

12. Memory circuit (10) according to any one of claims 1 to 11 wherein the sensing circuit (SENSE) comprises: - a first analog voltage binarization circuit at the first input / output node (LectA); - a second analog voltage binarization circuit at the second input / output node LectB.

13. Memory circuit (10) according to claim 12 wherein the sensing circuit (SENSE) comprises an OR type logic cell having a first input connected to the output of the first binarization circuit, a second input connected to the output of the second binarization circuit and an output for generating the completion indicator signal (if) of the comparison operation.

14. Memory circuit (10) according to claim 12, wherein the detection circuit (SENSE) further comprises: - an AND logic gate having a first input connected to the output of the first binarization circuit, a second input connected to the output of the second binarization circuit, and an output for generating the completion indicator signal (s3) of the comparison operation; - an OR logic gate having a first input connected to the output of the first binarization circuit, a second input connected to the output of the second binarization circuit, and an output for generating a trigger indicator signal (s3) of the integration operation.

15. Memory circuit (10) according to any one of claims 1 to 6 in which the sensing circuit (SENSE) comprises: - a current mirror (MC) having a first branch connected to the first input / output node (LectA) and a second branch connected to the second input / output node (LectB); - a comparator (COMP) having a first input connected to the first input / output node (LectA) and a second input connected to the second input / output node (LectB); the comparator (COMP) exhibiting a switching speed greater than 10 ns.