ELECTRONIC CHIP ASSEMBLY INCLUDING SUPERCONDUCTIVE INTERCONNECTION PINS

Abstract

One aspect of the invention relates to an assembly (100) of electronic chips comprising: a first chip (10) and a second chip (20) superimposed and electrically and mechanically connected to each other; first superconducting interconnect pads (31) arranged on a first face (10a) of the first chip (10) and having in a first direction (X) a first repetition pitch (PX1) less than or equal to 10 µm; and second superconducting interconnect pads (32) arranged on a first face (20a) of the second chip (20) and having in the first direction (X) a second repetition pitch (PX2) equal to the first repetition pitch (PX1); the first superconducting interconnect pads (31) being in direct contact with the second superconducting interconnect pads (32); and the first face (10a) of the first chip (10) and the first face (20a) of the second chip (20) being separated by a space (G) empty of solid matter.Figure to be published with the abbreviation: Figure 2.

Description

Title of the invention: ASSEMBLY OF ELECTRONIC CHIPS COMPRISING SUPERCONDUCTIVE INTERCONNECTION PINS TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of three-dimensional assemblies of electronic chips. The invention relates more particularly to an assembly comprising two electronic chips and superconducting interconnect pads for electrically connecting the two chips while minimizing heat transfer between them. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] Three-dimensional (3D) integration consists of stacking several electronic chips (also called integrated circuits) and electrically connecting them, for example, using a bonding technique. This approach makes it possible, in particular, to reduce the size of so-called "heterogeneous" systems, which are composed of circuits belonging to different generations of the same semiconductor device technology or of circuits belonging to different technologies, for example, an image sensor comprising a photodiode array and a CMOS image processing circuit comprising logic circuits. 3D integration also makes it possible to increase the transistor density per unit area without reducing their size, to decrease power consumption, and / or to increase the operating speed of a system by replacing long horizontal interconnections with short vertical interconnections.

[0003] Several 3D stacking architectures can be distinguished, depending in particular on how the chips are stacked, the orientation of the chips and the type of bonding.

[0004] Stacking can be carried out using different approaches: wafer-to-wafer, die-to-wafer, or die-to-die. The wafer-to-wafer stacking technique is the fastest in terms of the number of chips bonded per hour, as it involves collective bonding at the scale of the silicon wafers. It is also the most precise for a given bonding speed. However, unlike the other two techniques, it does not offer the possibility of assembling only the functional chips (known as "Known Good Dies"), selected after a series of tests and wafer cutting. The die-to-die stacking technique is naturally the most time-consuming to implement, as the chips are bonded together in pairs after the wafers have been cut.

[0005] When the chips (or plates) are oriented in the same direction, the front face of one chip is bonded to the back face of another chip (this assembly method is called "face-to-back"). Conversely, when the chips (or plates) are assembled after one of them has been turned over, the chips are bonded face-to-face or back-to-back.

[0006] The article [“Hybrid bonding for 3D stacked image sensors: impact of pitch shrinkage on interconnect robustness”; J. Jourdon et al., 2018 IEEE International Electron Devices Meeting (IEDM), pp. 7.3.1-7.1.4, 2018] describes an example of a 3D stack comprising two electronic chips assembled face-to-face by hybrid bonding (Cu / SiO2). The upper chip is a back-illuminated image sensor (BSI), and the lower chip is an image processing logic circuit manufactured using CMOS technology. The two chips are joined by copper interconnect pads surrounded by silicon dioxide. The interconnect pads (also called “HBM pads” for “Hybrid Bonding Metal pads”) have a repetition pitch ranging from 1.44 pm to 8.8 pm.

[0007] In certain applications, interconnections are designed to minimize heat transfer between the electronic chips they connect. Typically, when a first chip is intended to operate at very low temperatures, it is necessary to limit as much as possible the heat transfer between this first chip and a second chip that dissipates heat or is subjected to a different temperature, without compromising electrical conductivity between the two chips.

[0008] Quantum computing chips designed to operate at temperatures close to absolute zero (typically below 1.5 K) and to contain quantum bits, commonly called qubits, whose state is highly temperature-sensitive, may be cited as an example. Such a quantum chip is generally disposed in a dilution cryostat and can be electrically coupled to a read / control circuit using CMOS technology, also disposed within the cryostat. This read / control circuit, commonly called "cryo-CMOS," is designed to generate minimal heat, but must nevertheless be thermally decoupled from the quantum chip to avoid impairing its operation.

[0009] One solution for enabling excellent electrical conduction while limiting thermal conduction between two chips is to use one or more superconducting materials to interconnect them. Indeed, there are two main mechanisms for heat conduction at low temperatures. On the one hand, heat is transferred by free electrons from one material to the other. This phenomenon therefore only occurs in conductive materials. On the other hand, heat is also transferred through the vibrations of the atomic lattice, in other words, the phonons, of the material(s) constituting the interconnection. In a superconducting material cooled below its critical temperature Tc (the superconductor-conductor phase transition temperature), in other words, in the superconducting state, free electrons condense into Cooper pairs. These Cooper pairs have the characteristic of not conducting heat. Using one or more superconducting materials to create the interconnection therefore reduces thermal conduction by free electrons. However, when the interconnection temperature is close to the critical temperature Tc, residual electrons that have not formed Cooper pairs continue to conduct heat.

[0010] For a given superconducting material, the lower the temperature, the more electrons organize themselves into Cooper pairs in the material, and therefore the less efficient the thermal conduction by the remaining free electrons. To significantly reduce thermal conduction by free electrons, it is generally estimated that a temperature T lower than Tc / 10 must be reached.

[0011] Figures IA and IB represent an assembly of two electronic circuits 1 and 2, described in patent application FR2984602A1. Electronic circuits 1 and 2 are assembled and electrically connected to each other by means of an interconnection network 8. Each interconnection 8 comprises two stacks of superconducting thin films 3-4, located at the ends of the interconnection 8. These stacks of thin films 3-4 form phonon mirrors and consequently limit the thermal conduction by the phonons of the interconnection 8.

[0012] Each interconnection 8 further comprises: • metallic layers 5, arranged on the stacks of thin layers 3-4 and forming a wetting surface for a brazing material; and • a ball-shaped solder pad 6 arranged between the metal layers 5.

[0013] This type of interconnection is particularly complex and time-consuming to manufacture. Furthermore, the use of solder balls limits the integration density, as the manufacturing techniques impose ball sizes and inter-ball distances that are very difficult to reduce.

[0014] The solder balls are made of indium, which is also a superconducting material. However, this material has a lower critical temperature Tc than superconducting materials forming 3-4 thin-film stacks, for example, niobium (Nb) and titanium nitride (TiN), which necessitates operating at an even lower temperature to reach the "T" regime <Tc / 10 ».

[0015] Furthermore, the article [“Nb-Nb direct bonding at room temperature for superconducting interconnects”, M. Fujino et al., Journal of Applied Physics 133, 015301, 2023] describes the assembly of two silicon substrates by direct bonding of niobium interconnect pads. The interconnect pads, formed on the surface of each substrate, have a diameter of 200 pm and a repetition rate of 650 pm. Such a repetition rate is notably incompatible with the large-scale integration of quantum chips.

[0016] The bonding process used in this article is surface activated bonding (SAB), which relies on the formation of metallic bonds between the surfaces to be bonded. The bonding process comprises a surface activation step, carried out under ultra-high vacuum (pressure: 2 x 10⁶ Pa), consisting of bombarding the two surfaces to be bonded with argon atoms to create pendant bonds, followed by a step of bringing the surfaces into contact, also under ultra-high vacuum, with a compressive force of 1000 N applied for 30 s.

[0017] This bonding process is very demanding and creates an argon-rich interface layer (since SAB involves argon implantation to a thickness of 4-5 nm from the surface). This argon-rich interface layer can degrade the superconducting properties of the interconnect, such as the critical temperature (Tc), critical current density (Jc), and critical field (Bc). Summary of the invention

[0018] There is therefore a need to provide an assembly of electronic chips which is simple to produce and in which the interconnections between chips have good superconducting properties and a high density.

[0019] According to a first aspect of the invention, this need is met by providing an assembly of electronic chips comprising: • a first chip and a second chip superimposed and electrically and mechanically connected to each other, each of the first and second chips comprising a first face and a second face opposite the first face, the first face of the first chip being arranged opposite the first face of the second chip; • a plurality of first superconducting interconnect pads arranged on the first face of the first chip and having, in a first direction, a first repetition pitch less than or equal to 10 pm; and • a plurality of second superconducting interconnect pads arranged on the first face of the second chip and having in the first direction a second repetition step equal to the first repetition step.

[0020] Furthermore, in this assembly, the first superconducting interconnect pads are in direct contact with the second superconducting interconnect pads, and the first face of the first chip and the first face of the second chip are separated by a gap of solid material.

[0021] The inter-chip space, devoid of material, and in particular of dielectric material, reduces thermal conduction between the chips (as does the use of superconducting interconnect pads), crosstalk, and dielectric losses. Direct contact between the first and second superconducting interconnect pads imparts good superconducting properties to the interconnections between chips. These properties, combined with the high interconnection density provided by the repetition rate, allow the chip assembly to meet the requirements of numerous applications in the fields of quantum computing, superconducting electronics, and aerospace.

[0022] Preferably, the first superconducting interconnecting pads are glued to the second superconducting interconnecting pads by direct hydrophilic bonding.

[0023] In a first embodiment of the assembly, the first superconducting interconnecting pads and / or the second superconducting interconnecting pads are made of one and the same superconducting material.

[0024] The first superconducting interconnect pads and / or the second superconducting interconnect pads may each comprise a stack of at least one first superconducting layer and at least one second superconducting layer, said at least one first superconducting layer being formed of a first superconducting material and said at least one second superconducting layer being formed of a second superconducting material different from the first superconducting material.

[0025] In a second embodiment, the first superconducting interconnecting pads and / or the second superconducting interconnecting pads each comprise a stack of several alternating first superconducting layers and several alternating second superconducting layers. The first superconducting layers are formed of a first superconducting material, and the second superconducting layers are formed of a second superconducting material different from the first superconducting material.

[0026] According to one development, the first superconducting material and the second superconducting material are chosen so as to form at least one acoustic mismatch interface.

[0027] In addition to the characteristics mentioned in the preceding paragraphs, the assembly of electronic chips according to the first aspect of the invention may have one or more additional characteristics from among the following, considered individually or according to all technically possible combinations: • the first superconducting interconnecting pads have a third repetition step in a second direction secant to the first direction and the second superconducting interconnecting pads have in the second direction a fourth repetition step equal to the third repetition step; • the third repetition step is less than or equal to 10 pm, preferably between 1 pm and 7 pm; • the third repetition step is equal to the first repetition step; • the first chip is a quantum circuit and the second chip is a circuit for reading and controlling the quantum circuit; • The first chip is an infrared bolometric sensor, and the second chip is a multiplexing circuit or a readout circuit for the infrared bolometric sensor; and • the first repetition step is between 1 pm and 7 pm.

[0028] A second aspect of the invention relates to a method for manufacturing an assembly of electronic chips comprising a first chip and a second chip superimposed and electrically and mechanically connected to each other, each of the first and second chips comprising a first face and a second face opposite the first face. The method comprises the following steps: • form a plurality of first superconducting interconnect pads on the first face of the first chip, the first superconducting interconnect pads having in a first direction a first repetition step less than or equal to 10 pm; • form a plurality of second superconducting interconnect pads on the first face of the second chip, the second superconducting interconnect pads having in the first direction a second repetition step equal to the first repetition step; • assemble the first chip and the second chip by direct hydrophilic bonding, by bringing the first superconducting interconnect pads into contact with the second superconducting interconnect pads, so that the first face of the first chip and the first face of the second chip are arranged opposite each other and separated by a gap of solid material.

[0029] In a preferred embodiment, the formation of the first superconducting interconnect pads comprises the following sub-steps: • form a superconducting layer on the first face of the first chip; • polish the superconducting layer to obtain a surface roughness of less than 0.5 nm; • form an etching mask on the superconducting layer; • etch the superconducting layer through the etching mask; and • Remove the engraving mask.

[0030] Advantageously, the manufacturing process further comprises: • before the formation of the superconducting layer, the deposition of a barrier layer on the first side of the first chip; and • after the etching of the superconducting layer, the etching of the barrier layer.

[0031] For example, the superconducting layer comprises niobium and the barrier layer is made of titanium nitride.

[0032] The manufacturing process may further include: • between polishing the superconducting layer and forming the etching mask, the deposition of a protective layer on the superconducting layer; • before etching the superconducting layer, the protective layer is etched through the etching mask to expose the superconducting layer; and • after removing the etching mask, the protective layer is removed.

[0033] In addition to the features mentioned in the preceding paragraphs, the manufacturing process according to the second aspect of the invention may have one or more additional features from among the following, considered individually or in all technically possible combinations: • Hydrophilic direct bonding is carried out at room temperature and under atmospheric pressure; • Direct hydrophilic bonding is carried out under vacuum, with a residual pressure between 10² Pa and 1000 Pa (10⁴ mbar and 10 mbar); and • the manufacturing process includes, after the step of assembling the first chip and the second chip, a step of annealing the assembly at a temperature between 100 °C and 400 °C, preferably between 100 °C and 350 °C, and even more preferably between 100 °C and 300 °C. BRIEF DESCRIPTION OF THE FIGURES

[0034] Other features and advantages of the invention will become clear from the description given below, by way of example and not limitation, with reference to the accompanying figures, among which: • the [Fig.1A], previously described, represents an assembly of chips according to the prior art; • the [Fig.1B], previously described, represents one of the interconnections of the chip assembly of the [Fig.1A], this interconnection comprising several superconducting layers; • [Fig.2] represents in cross-section a first embodiment of a chip assembly according to the first aspect of the invention; • Figure 3 shows, in cross-section, a second embodiment of a chip assembly according to the first aspect of the invention; • [Fig.4] represents the first face of one of the chips in the assembly of [Fig.2] or [Fig.3]; • Figures 5A-5D, 6A-6D and 7 represent steps in a manufacturing process for assembling electronic chips according to the second aspect of the invention.

[0035] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION

[0036] Figure 2 is a partial, schematic cross-sectional view of an electronic chip assembly 100 according to a first embodiment of the invention. The electronic chip assembly 100, hereinafter referred to simply as "assembly 100," comprises at least two electronic chips: a first chip 10 and a second chip 20. The term "electronic chip" refers to an electronic component based on a semiconductor material, performing one or more electronic functions and integrating several electronic components within a small volume. The term "integrated circuit" will be considered a synonym for electronic chip.

[0037] The first chip 10 and the second chip 20 are stacked, that is, arranged one on top of the other. Thus, the assembly 100 can also be referred to as a "chip stack". In the orientation of [Fig. 2], the first chip 10, referred to as the upper chip, is arranged above the second chip 20, referred to as the lower chip. Furthermore, the first chip 10 and the second chip 20 are electrically and mechanically connected to each other.

[0038] The assembly 100 is intended to operate at very low temperatures, i.e., at a temperature less than or equal to 1.5 K, typically at a temperature less than or equal to 100 mK. It is designed to limit heat transfer between the chips 10 and 20 to prevent, for example, heat generated by one chip from spreading to the other chip and preventing its operation (at very low temperatures) or impairing its performance. Assembly 100 finds particularly advantageous applications in the fields of quantum computing, superconducting electronics, and space applications.

[0039] By way of example, the first chip 10 is a quantum circuit, that is to say a circuit intended to contain quantum bits or qubits, and the second chip is a circuit for reading and controlling the quantum circuit, for example in CMOS technology. To be brought to very low temperatures, the assembly 100 can be placed in a dilution cryostat.

[0040] According to another example, the first chip 10 is a bolometric image sensor (for example for space observation) and the second chip 20 is a bolometric image sensor readout circuit or a multiplexing circuit.

[0041] The first chip 10 may include a substrate 11 and one or more interconnection levels, also called routing levels, arranged on the substrate 11. The substrate 11 of the first chip 10 includes an active layer made of a semiconductor material, such as silicon. It may contain electronic components or devices (not shown), such as transistors, photodiodes, memory cells, quantum devices, bolometers, etc. These electronic devices are formed, at least in part, within the semiconductor active layer. The routing level(s) 12 may electrically connect the electronic devices of the first chip 10 to each other.

[0042] Similarly, the second chip 20 may comprise a substrate 21 and one or more routing levels 22 arranged on the substrate 21. The substrate 21 of the second chip 20 may contain electronic devices (transistors, photodiodes, memory cells, quantum devices, etc.), formed at least in part in a semiconductor active layer (the semiconductor material may be different from that of the substrate 11). The routing level(s) 22 may electrically connect the electronic devices of the second chip 20 to each other.

[0043] The electronic devices of the same chip belong to a first functional block (or set of technology levels) called "Front End Of Line" or FEOL, while the routing levels 12, 22 of the same chip belong to a second functional block called "Back End Of Line" or BEOL.

[0044] Each of the first and second chips 10, 20 comprises a first face 10a, 20a and a second face 10b, 20b opposite the first face 10a, 20a. The first face 10a of the first chip 10 is arranged opposite the first face 20a of the second chip 20. Preferably, the first faces 10a and 20a of the chips are flat surfaces that extend parallel to each other.

[0045] In addition to the first and second chips 10, 20, the assembly 100 includes first superconducting interconnect pads 31 (hereinafter referred to as "first pads 31") arranged on the first face 10a of the first chip 10 and second superconducting interconnect pads 32 (hereinafter referred to as "second pads 32") arranged on the first face 20a of the second chip 20.

[0046] Preferably, the first pads 31 have identical shape and dimensions (within manufacturing tolerances). The second pads 32 also preferably have identical shape and dimensions, which may nevertheless be different from those of the first pads.

[0047] In a plane parallel to the first face 10a, 20a, the first and second studs 31-32 can have a rectangular (for example square), round, hexagonal... cross-section. Their dimensions in this same plane can be between 100 nm and 7 pm, preferably between 1 pm and 5 pm.

[0048] Each first pad 31 is electrically connected to one of the routing levels 12 of the first chip 10 (for example, the one closest to the first pads 31), preferably by a first via conductor 4L. The first pads 31 are thus electrically connected to the electronic devices of the first chip 10. Similarly, each second pad 32 is electrically connected to one of the routing levels 22 of the second chip 20 (for example, the one closest to the second pads 32), preferably by a second via conductor 42. When the first or second chip 10, 20 comprises several superimposed routing levels 12, 22, these are also electrically connected to each other by via conductors. Each routing level 12, 22 comprises one or more conductive traces, which extend in a plane parallel to the first face 10a, 20a of the chip in question. The via conductors extend in a direction perpendicular to this plane.The conductive tracks and via conductors are coated with a dielectric material.

[0049] Conductive tracks and via conductors are advantageously made of one or more superconducting materials, in order to limit thermal transport inside the chips.

[0050] The first pads 31 are in direct contact with the second pads 32. These first and second pads 31-32 ensure the electrical and mechanical connection between the two chips.

[0051] More precisely, each of the first pads 31 is in direct contact with a second pad 32, and conversely, each of the second pads 32 is in direct contact with a first pad 31. In other words, the first and second pads 31-32 are all connected in pairs.

[0052] The chips 10 and 20 are interconnected with each other by means of the first and second pads 31-32 using a direct bonding technique, i.e. without Introducing an intermediate compound (such as an adhesive, wax, or low-melting-point alloy) at the bonding interface, particularly through direct hydrophilic bonding, is avoided. Thus, the interconnections between chips 10 and 20 are free of intermediate compounds, and specifically of solder material. Each interconnection preferably consists of a first pad 31 and a second pad 32. The interconnection is then entirely superconducting.

[0053] In assembly 100, a space G separates the first face 10a of the first chip 10 and the first face 20a of the second chip 20. This space G also separates the pairs of first and second pads 31-32 from each other. This space G is devoid of solid material, and in particular of dielectric material. It may contain a gas or a mixture of gases, for example air.

[0054] The space G constitutes an inter-chip cavity in which the first pads 31 and the second pads 32 extend. This inter-chip cavity is preferably open to the external environment. Thus, when using the assembly 100, for example in a dilution cryostat, the pressure of the gas or gas mixture in the space G can be reduced until a given vacuum level is obtained.

[0055] The material-free G-space improves thermal insulation between chips 10 and 20 (by limiting the thermal transport of phonons between the chips), compared to two chips separated by an underfill material or an oxide (as in the case of hybrid Cu / SiO2 bonding, for example). Furthermore, the G-space limits crosstalk between RF signals propagating in the two chips. "RF signals" refers to signals with frequencies between 3 kHz and 300 GHz. Since the G-space also separates the first pads 31 from each other and the second pads 32 from each other, it also limits crosstalk between RF signals propagating in different interconnections. Finally, due to the absence of dielectric material between the interconnect pads, dielectric losses are also reduced.

[0056] The distance d separating the first face 10a of the first chip 10 and the first face 20a of the second chip 20 (in other words, the height of the interchip cavity) is advantageously between 100 nm and 2 pm. It is measured perpendicular to the first faces 10a and 20a.

[0057] The first pads 31 have, in a first direction X of the plane of the first face 10a, a first repetition pitch PXi less than or equal to 10 pm, and preferably between 1 pm and 7 pm. In addition, the second pads 32 have, in the same direction X, a second repetition pitch Px2 equal to the first repetition pitch Px[.

[0058] Such repetition steps ensure excellent mechanical strength between the chips 10 and 20 and allow for a high density of interconnections between the chips, compatible with certain high-density integration applications. These repetition steps are particularly well-suited to the scalability requirements of quantum circuits. Indeed, quantum circuits are designed to contain a very large number of qubits, which must be individually connected to the readout and control circuitry. The required number of interconnects between chips is therefore very high, especially in quantum circuits with spin qubits in silicon.

[0059] The use of superconducting interconnect pads reduces thermal conduction by electrons between the chips 10 and 20 (when used at very low temperatures). Fully superconducting interconnects are also particularly advantageous when the first chip 10 is a superconducting qubit quantum circuit, as they allow the phase and amplitude properties of the signal to be preserved during transmission from one chip to the other.

[0060] The first and second pads 31-32 are made of one or more superconducting materials, for example, selected from niobium (Nb), niobium-titanium (NbTi), niobium-germanium (Nb3Ge), niobium nitride (NbN), niobium alumina (Nb3Al), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), vanadium (V), and vanadium silicide (V3Si). The first pads 31 and / or the second pads 31-32 may be formed from an alloy of at least two of these materials. They may also comprise several stacked superconducting layers made of different materials.

[0061] In this first embodiment, the first pads 31 are made of a single superconducting material (preferably chosen from the aforementioned materials and their alloys). Similarly, the second pads 32 are made of a single superconducting material, which may be identical or different from that of the first pads 31. The first and second pads 31-32 are, for example, made of niobium.

[0062] In an alternative embodiment not shown in the figures, the first pads 31 and / or the second pads 32 each comprise a stack of a first superconducting layer and a second superconducting layer. The first superconducting layer is formed of a first superconducting material, for example TiN, and the second superconducting layer is formed of a second superconducting material different from the first superconducting material, for example niobium. The first superconducting layer is the one in contact with the chip 10, 20. Thus, when the first and second pads 31-32 all comprise stacks, the bonding occurs between the second superconducting layers.

[0063] The first superconducting material and the second superconducting material can be chosen so as to form an acoustic mismatch interface (also called a Kapitza interface). Such an interface allows for the reflection of a This reduces the thermal conductivity of the phonons in the interconnections. Indeed, an interface thermal resistance is created at the interface between the first and second superconducting layers. This interface thermal resistance is greater when the difference in the speed of sound between the two superconducting materials is significant. This speed difference induces very efficient reflection of phonons at the interface, which is why the term "phonon mirror" is also used.

[0064] Examples of superconducting material pairs for creating an acoustic mismatch interface are described in patent applications FR3125359A1 and FR2984602A1.

[0065] Fig. 3 represents, according to the same partial sectional view, a second embodiment of the assembly 100, which differs from the first embodiment only in the composition of the first and second pads 31-32.

[0066] Here, the first pads 31 and the second pads 32 each comprise a stack of several alternating first and second superconducting layers, in order to form a multitude of acoustic mismatch interfaces (preferably more than 10 interfaces) and thus drastically reduce thermal conduction by phonons between the two chips. The greater the number of interfaces, the more effective the phonon mirror.

[0067] Fig. 4 represents an example of the layout of the first studs 31 on the first face 10a of the first chip 10 or of the second studs 32 on the first face 20a of the second chip 20. The first and second studs 31-32 here have a square section.

[0068] As shown, the first plots 31 may have a third repetition step PY1 in a second direction Y intersecting the first direction X, and the second plots 32 may have a fourth repetition step PY2 in the second direction Y, equal to the third repetition step PY1. Thus, the first and second plots 31-32 are arranged in a regular lattice, or matrix, comprising rows and columns. The second direction Y is preferably perpendicular to the first direction X. The third repetition step PY1 is advantageously less than or equal to 10 pm, preferably between 1 pm and 7 pm. It may be equal to the first repetition step PY1. The first or second plots 31, 32 then form a square mesh lattice.

[0069] The first and second pads 31-32 are functional pads in the sense that they are connected to the electronic devices of the chips 10, 20 by the routing levels 12, 22. They are advantageously contained in an area called active of the first face 10a, 20a.

[0070] In addition to these functional pads, the assembly 100 may include, on the first face 10a, 20a of each of the chips 10, 20, other pads, notably non-functional connecting pads 33, also called "dummy" pads. These non-functional pads 33 are exclusively dedicated to the bonding of two chips. In other words, they are purely mechanical (and not electrical) connecting pads. They are not connected to any electronic devices of the chips 10, 20, nor even to the routing layers 12, 22.

[0071] The non-functional pads 33 are advantageously placed to avoid having large empty areas of pads, typically greater than 100x100 pm2, advantageously greater than 20x20 pm2. They are for example in the form of squares with sides of 2 pm to 100 pm and are spaced two by two with a distance of between 2 pm and 50 pm.

[0072] Finally, the assembly 100 may include, on the first face 10a, 20a of each of the chips 10, 20, one or more test pads 34 allowing verification of the proper functioning of the chips before they are glued. These test pads 34 participate in the gluing process, just like the first and second pads 31-32 and the non-functional pads 33. These test pads 34 typically have dimensions much larger than those of the functional pads 31-32 and the non-functional pads 33.

[0073] The non-functional pads 33 and the test pads 34 of each chip are advantageously formed from the same superconducting material(s) as the first or second pads 31, 32. This helps to reduce thermal conduction between the two chips.

[0074] The surface (of bonding) of the connecting pads, of all types combined (first / second pads, non-functional pads and test pads), is preferably greater than 30% of the surface of the first face 10a, 20a, more preferably greater than 45%.

[0075] Figures 5A to 5D, 6A to 6D and 7 schematically represent steps SI to S3 of a manufacturing process for the chip assembly 100.

[0076] The manufacturing process includes a step SI of forming the first pads 31 on the first face 10a of the first chip 10 and a step S2 of forming the second pads 32 on the first face 20a of the second chip 20.

[0077] According to a preferred embodiment, the SI step of forming the first plots 31 comprises several sub-steps Sl-1 to Sl-4 represented by figures 5 A to 5D.

[0078] Substep Sl-1 of [Fig.5A] includes the formation of a superconducting layer 51 on the first face 10 of the first chip 10. The thickness of the superconducting layer 51 can be between 100 nm and 10 pm, for example equal to 400 nm.

[0079] The superconducting layer 51 may include several sublayers formed of different superconducting materials, in order to form in particular one or more acoustic mismatch interfaces, as indicated previously.

[0080] The manufacturing process may also include the deposition of a barrier layer 52 prior to the formation of the superconducting layer 51. The barrier layer 52 enables the superconducting layer 51 to adhere more effectively to the first face 10a of the first chip 10 and protects the superconducting layer 51 from oxidation by forming a barrier to the diffusion of oxidizing species. It is made of an electrically conductive material, advantageously a superconductor, preferably titanium nitride (TiN). Titanium nitride is particularly well-suited to a superconducting layer 51 comprising niobium (NbNbTi, Nb3Ge, NbN, Nb3Al...). The thickness of the barrier layer 52 may be between 5 nm and 200 nm, for example, 20 nm. With such a thickness, the barrier layer 52 becomes superconducting by proximity effect with the superconducting layer 51 even if it is made of a non-superconducting material.

[0081] The superconducting layer 51 is preferably in electrical contact with first via conductors 41 (which open onto the first face 10a of the first chip 10), through the barrier layer 52 where appropriate, in order to connect the future first pads 31 to an underlying routing level 12 (not shown in Figures 5A-5D).

[0082] Substep S1-2 of [Fig. 5B] consists of polishing the superconducting layer 51 to obtain a surface roughness compatible with hydrophilic direct bonding, typically less than 0.5 nm, preferably less than 0.2 nm. These roughness values ​​are expressed as root mean square (Rq). The Rq roughness (denoted Rq) is determined by statistical analysis of an atomic force microscope image, using a 1x1 pm² area as the sample.

[0083] This S1-2 polishing substep can be accomplished by chemical mechanical polishing (or CMP).

[0084] The polished superconducting layer 51 is then structured to form the first pads 31. This structuring is accomplished here in two sub-steps S1-3 and S1-4 illustrated by figures 5C and 5D.

[0085] In S1-3 (see [Fig. 5C]), an etching mask 53 is formed on the superconducting layer 51. The etching mask 53 may be a resin mask or a hard mask. Its formation includes, in particular, a photolithography step. The etching mask 53 comprises first patterns (formed by solid parts of the mask) whose shape and dimensions correspond to those of the first pads 31 to be formed. The etching mask 53 may also comprise other patterns (not shown) corresponding to the other chip connection pads (non-functional pads 33 and test pads 34).

[0086] Then, during substep Sl-4 (see [Fig. 5D]), the superconducting layer 51 is etched through the etching mask 53, thus obtaining the first pads 31 (and where applicable, the non-functional pads 33 and test pads 34). The superconducting layer 51 is preferably etched by reactive-ion etching (or RIE).

[0087] The barrier layer 52 is also etched through the etching mask 53 during substep Sl-4, so as not to short-circuit the first pads 31. The etching of the barrier layer 52 can be immediately following the etching of the superconducting layer 51 and accomplished in the same etching frame, preferably using the same chemistry.

[0088] Finally, the engraving mask 53 is removed after the Sl-4 engraving substep.

[0089] Advantageously, the manufacturing process further comprises, between polishing the superconducting layer 51 (substep Sl-2) and forming the etching mask 53 (substep Sl-3), the deposition of a protective layer on the superconducting layer 51. This protective layer, also called an encapsulation layer, protects the superconducting layer 51 from the formation of the etching mask 53, from the etching of the superconducting layer 51, and from the removal of the etching mask 53 so that the first pads 31 have a top surface free from alteration (e.g., oxidation), defects, or residues. The protective layer is, for example, made of silicon dioxide (SiO2), silicon nitride (SiN), or titanium (Ti). Its thickness is preferably between 5 nm and 2 pm in the case of SiO2 or SiN and between 5 nm and 500 nm in the case of titanium.

[0090] Between the formation of the etching mask 53 (substep Sl-3) and the etching of the superconducting layer 51 (substep Sl-4), the protective layer is etched through the etching mask 53 to expose the superconducting layer 51 (the so-called protective layer opening substep). The protective layer is removed after the etching mask 53 has been removed, preferably by wet etching, for example in a dilute hydrofluoric acid (HF) solution.

[0091] The formation of the second pads 32 on the first face 20a of the second chip 20 can be accomplished in the same way as the formation of the first pads 31. Thus, the above description of step S1 applies mutatis mutandis to step S2, which includes, in particular, substeps S2-1, S2-2, S2-3, and S2-4, illustrated respectively by [Fig. 6A], [Fig. 6B], [Fig. 6C], and [Fig. 6D]. This will (advantageously) form a second barrier layer 52', a second superconducting layer 51', (advantageously) a second protective layer, and a second hard mask 53'.

[0092] At the end of steps SI and S2, the first studs 31 protrude from the first face 10a of the first chip 10 and the second studs 32 protrude from the first face 20a of the second chip 20. They are raised here by portions of the barrier layer 52, 52'.

[0093] Step S3 of [Fig.7] consists of assembling the first and second chips 10, 20 by direct hydrophilic bonding, by bringing the first pads 31 into contact with the second pads 32, from which assembly 100 results.

[0094] Hydrophilic direct bonding, or hydrophilic molecular adhesion bonding, is a bonding technique that utilizes hydrophilic bonding surfaces (as is the case for the upper faces of the first and second pads 31-32) and whose principle is based on the spontaneous adhesion of the surfaces through van der Waals forces (including hydrogen bonds and capillary bridges). It can be performed at room temperature and atmospheric pressure, unlike surface activation bonding (SAB), which is carried out under ultra-high vacuum. Alignment of the first pads 31 with the second pads 32 is also easier than in the case of SAB. It can be performed in a hybrid bonding machine commonly used for 3D applications. Furthermore, it is not necessary to apply a compressive force between the two chips, as this type of bonding is spontaneous.For all these reasons, hydrophilic direct bonding is particularly simple and quick to implement. It is also compatible with microelectronics industry processes.

[0095] Furthermore, direct hydrophilic bonding causes very few defects at the bonding interface, such as voids. In addition, it does not produce an interface layer with, for example, implanted argon atoms, which can lead to a degradation of the superconducting properties of the interconnect, such as the critical temperature (Tc), the critical current density (Jc), and the critical field (Bc).

[0096] Hydrophilic direct bonding can, however, be carried out under vacuum as an option, with a vacuum level between 10² Pa and 1000 Pa (10⁴ mbar and 10 mbar), which is much easier and more economical to achieve than ultra-high vacuum (10⁶–10¹⁰ Pa, or 10⁸–10¹² mbar). It can also be carried out under an atmosphere containing helium, or even a humid atmosphere containing helium, with a humidity level of up to 80%.

[0097] After bonding, the manufacturing process may also include a low-temperature annealing step of the assembly 100, in order to further create metallic bonds between the superconducting pads and thus strengthen the connection between the chips. The annealing temperature is low enough not to damage the electronic devices of the chips. It can range from 100 °C to 400 °C. Preferably between 100 °C and 350 °C, and even more preferably between 100 °C and 300 °C. This annealing step is optional, as the adhesion strength of chips bonded by direct hydrophilic bonding is already high.

[0098] Optionally, one of the two substrates 11 and 21 can also be thinned by grinding and / or etching (dry or wet).

[0099] Steps S1, S2, and S3 (plus any annealing) of the manufacturing process are advantageously implemented at the wafer level. Thus, the first chip belongs to one wafer and the second chip belongs to a second wafer. The chip assembly 100 is then separated by cutting the assembly from the two wafers.

[0100] The first plate may include several copies of the first chip 10 and the second plate may include several copies of the second chip 20, in order to obtain several copies of the assembly 100.

[0101] Direct hydrophilic bonding between two plates generally does not require the application of force to the back faces of the plates. However, it may be advantageous to apply pressure after or during the bonding operation to ensure contact between all the pads. This is particularly useful if one or both plates exhibit significant deflection (typically between 100 µm and 500 µm).

[0102] After bonding, the wafer assembly may undergo further manufacturing steps, some involving one or more fluids (gas, liquid, or plasma). To prevent fluid penetration into the space G between the chips 10 and 20, which could damage the chips, the interconnect pads, or impair the bonding quality, a peripheral sealing ring may be formed in the area between the wafers. This sealing ring may comprise two parts, one on the surface of the first wafer and the other on the surface of the second wafer. Preferably, the first part of the sealing ring is formed simultaneously with the first pads 31 (by etching the first superconducting layer 51, previously deposited as a full wafer), and the second part of the sealing ring is formed simultaneously with the second pads 32 (by etching the second superconducting layer 51', previously deposited as a full wafer).The first and second parts of the ring are brought into (direct) contact during step S3 of hydrophilic direct bonding.

[0103] A peripheral sealing ring can alternatively be provided for each chip assembly (forming a half-ring on each chip), and not at the level of the plate assembly, to facilitate degassing during annealing and thus avoid stresses due to pressure.

[0104] The peripheral sealing ring can have a width between 10 µm and 2 mm, depending on the number and nature of the technological steps to be carried out after bonding.

[0105] In one embodiment, only steps S1 and S2 of the manufacturing process are implemented at the wafer scale. The hydrophilic direct bonding step S3 is implemented according to the chip-to-wafer or chip-to-chip approach, that is, after the first chip has been diced and / or the second chip has been diced.

[0106] The assembly of electronic chips and its manufacturing process are not limited to the embodiments described above. The first and second embodiments of the assembly can in particular be combined into a third embodiment, in which the first pads 31 are formed of a single superconducting material and in which the second pads 32 each comprise a stack of superconducting layers, or vice versa.

Claims

Demands

1. Assembly (100) of electronic chips comprising: - a first chip (10) and a second chip (20) superimposed and electrically and mechanically connected to each other, each of the first and second chips (10, 20) comprising a first face (10a, 20a) and a second face (10b, 20b) opposite the first face, the first face (10a) of the first chip (10) being arranged opposite the first face (20a) of the second chip (20); - a plurality of first superconducting interconnect pads (31) arranged on the first face (10a) of the first chip (10) and having in a first direction (X) a first repetition step (PXi) less than or equal to 10 pm; and - a plurality of second superconducting interconnect pads (32) arranged on the first face (20a) of the second chip (20) and having in the first direction (X) a second repetition step (Px 2) equal to the first repetition step (PXi);in which the first superconducting interconnect pads (31) are in direct contact with the second superconducting interconnect pads (32); and in which the first face (10a) of the first chip (10) and the first face (20a) of the second chip (20) are separated by a space (G) devoid of solid material.

2. Assembly (100) according to claim 1, wherein the first superconducting interconnect pads (31) are bonded to the second superconducting interconnect pads (32) by direct hydrophilic bonding.

3. Assembly (100) according to any one of claims 1 and 2, wherein the first superconducting interconnecting pads (31) have a third repeating step (PY 1) in a second direction (Y) secant to the first direction (X) and wherein the second superconducting interconnecting pads (32) have in the second direction (Y) a fourth repetition step (PY2) equal to the third repetition step (PY i).

4. Assembly (100) according to claim 3, wherein the third repetition step (PY J) is less than or equal to 10 pm.

5. Assembly (100) according to any one of claims 3 and 4, wherein the third repetition step (PY i) is equal to the first repetition step (Px i).

6. Assembly (100) according to any one of claims 1 to 5, wherein the first superconducting interconnect pads (31) and / or the second superconducting interconnect pads (32) are made of one and the same superconducting material.

7. Assembly (100) according to any one of claims 1 to 5, wherein the first superconducting interconnect pads (31) and / or the second superconducting interconnect pads (32) each comprise a stack of at least one first superconducting layer and at least one second superconducting layer, said at least one first superconducting layer being formed of a first superconducting material and said at least one second superconducting layer being formed of a second superconducting material different from the first superconducting material.

8. Assembly (100) according to claim 7, wherein the first superconducting material and the second superconducting material are chosen so as to form at least one acoustic mismatch interface.

9. Assembly (100) according to any one of claims 7 and 8, wherein the first superconducting interconnect pads (31) and / or the second superconducting interconnect pads (32) comprise a stack of several first superconducting layers and several second superconducting layers in alternation.

10. Assembly (100) according to any one of claims 1 to 9, wherein the first chip (10) is a quantum circuit and the second chip (20) is a quantum circuit readout and control circuit.

11. Assembly (100) according to any one of claims 1 to 9, wherein the first chip (10) is a bolometric sensor infrared and the second chip (20) is a multiplexing circuit or an infrared bolometric sensor readout circuit.

12. Assembly (100) according to any one of claims 1 to 11, wherein the first repetition step (Px i) is between 1 pm and 7 pm.

13. Method of manufacturing an assembly (100) of electronic chips comprising a first chip (10) and a second chip (20) superimposed and electrically and mechanically connected to each other, each of the first and second chips (10, 20) comprising a first face (10a, 20a) and a second face (10b, 20b) opposite to the first face, the method comprising the following steps: - forming (SI) a plurality of first superconducting interconnect pads (31) on the first face (10a) of the first chip (10), the first superconducting interconnect pads (31) having in a first direction (X) a first repetition step (PXi) less than or equal to 10 pm;- form (S2) a plurality of second superconducting interconnecting pads (32) on the first face (20a) of the second chip (20), the second superconducting interconnecting pads (32) having in the first direction (X) a second repetition step (Px 2) equal to the first repetition step (Pxi); - assemble (S3) the first chip (10) and the second chip (20) by direct hydrophilic bonding, by bringing the first superconducting interconnecting pads (31) into contact with the second superconducting interconnecting pads (32), so that the first face (10a) of the first chip (10) and the first face (20a) of the second chip (20) are arranged opposite each other and separated by a space (G) empty of solid material.;

14. A method according to claim 13, wherein the formation of the first superconducting interconnect pads (31) comprises the following substeps: - forming (S 1-1) a superconducting layer (51) on the first face (10a) of the first chip (10); - polish (S 1-2) the superconducting layer (51) so as to obtain a surface roughness of less than 0.5 nm; - form (S 1-3) an etching mask (53) on the superconducting layer (51); - etch (S 1-4) the superconducting layer (51) through the etching mask (53); and - remove the etching mask (53).

15. A method according to claim 14, further comprising: - before the formation (S 1-1) of the superconducting layer (51), the deposition of a barrier layer (52) on the first face (10a) of the first chip (10); and - after the etching (S 1-4) of the superconducting layer (51), the etching of the barrier layer (52).

16. Method according to claim 15, wherein the superconducting layer (51) comprises niobium and the barrier layer (52) is titanium nitride.

17. A method according to any one of claims 14 to 16, further comprising: - between polishing (S 1-2) the superconducting layer (51) and the formation (S 1-3) of the etching mask (53), the deposition of a protective layer on the superconducting layer (51); - before etching (S 1-4) the superconducting layer (51), the etching of the protective layer through the etching mask (53) to expose the superconducting layer (51); and - after removal of the etching mask (53), the removal of the protective layer.

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