System for reading a charge contained in a single-pixel photodiode and associated method

Abstract

A system for reading a charge contained in a photodiode (10) of a pixel (2) is proposed. The pixel has a power input (2a), an output (2b), and a readout node (SN). The readout system further includes means for biasing (8) the output (2b) of pixel (2), a first switch (7), an energy storage capacitor (6), and control means (9). The output (2b) of pixel (2) is connected to the biasing means (8) via the first switch (7). The power input (2a) is connected to the energy storage capacitor (6) and to one end of the second switch (5). The other end of the second switch (5) is intended to be connected to a DC voltage source (100). The system also includes control means (9). (See Figure 1 for abbreviations.)

Description

Title of the invention: System for reading a charge contained in a single-pixel photodiode and associated method

[0001] Some embodiments and implementations relate to reading a charge contained in a pixel.

[0002] A pixel matrix of a sensor comprises pixels arranged in rows and columns.

[0003] It is known that when a pixel is supplied by a noisy supply signal, a signal representative of the optical capture made by the pixel is noisy ("line noise") so that the quality of the image generated from said signal is insufficient, resulting in an image defect.

[0004] In order to minimize the transmission of noise from the power supply signal, it is known to power the pixels from a voltage regulator connected to a power supply delivering a supply voltage.

[0005] However, the voltage regulator causes a voltage drop so that the amplitude of the signal delivered by the pixels is reduced.

[0006] In addition, the voltage regulator results in increased energy consumption and requires a volume to be provided for its implantation on an integrated circuit generally containing the pixel matrix.

[0007] Thus there is a need to remove the voltage regulator while minimizing line noise so that the image generated from the signal delivered by the pixel is of sufficient quality.

[0008] The implementation and embodiment methods defined below are proposed in these respects, and allow the reading of the charge contained in a pixel while minimizing line noise without the implementation of a voltage regulator.

[0009] According to one aspect, a method for reading a charge contained in a photodiode of a pixel is proposed, comprising a power input, an output, a read node, the output of the pixel being connected to means for biasing the output of the pixel via a first switch, a follower transistor having a gate connected to the read node and a drain connected to the power input, a read transistor connecting the source of the follower transistor to the output of the pixel, the power input being connected to an energy storage capacitor and to a first DC voltage source via a second switch.

[0010] The process comprises:

[0011] o a first digitization step of a first value of the potential of the reading node,

[0012] o a transfer of the charge contained in the photodiode to the readout node following the first digitization,

[0013] or a second digitization step of a second value of the potential of the reading node including the transferred charge,

[0014] o the first and second digitization steps comprising:

[0015] - closing the second switch to charge the storage capacity of energy,

[0016] - simultaneously with the closing of the second switch, a closing of the first switch followed by opening of the first switch when the pixel output voltage is established to within a certain establishment accuracy,

[0017] - an opening of the second switch following the opening of the first switch, and

[0018] - a digitization of the potential value of the read node on the pixel output when the first and second switches are open, the pixel is powered by the storage capacity.

[0019] The pixel output signal readings are performed when the power switch is open so that line noise transmitted by the DC power supply is not transmitted to the pixel, the pixel being powered by the energy storage capacitor. The pixel is disconnected from the power supply provided by the first DC voltage source during the reading of the pixel output signals.

[0020] The voltage regulator known from the prior art is removed without altering the quality of the signals delivered by the pixel.

[0021] Furthermore, since the power-consuming voltage regulator is eliminated, the electrical energy delivered by the power supply is reduced. In addition, since the voltage regulator is eliminated, the voltage drop due to the regulator is eliminated, and the output signal amplitude can be increased to improve the signal-to-noise ratio.

[0022] According to one embodiment, the biasing means comprise a current source and the reading transistor being closed during the first and second digitization steps, the method includes for each digitization, a closing of the first switch for a stabilization period allowing the output voltage of the pixel to be established to a desired accuracy.

[0023] According to one embodiment, the time between the opening of the first switch and the opening of the second switch is identical during the first and second digitization steps.

[0024] According to one embodiment, the polarization means comprise a voltage source, the process comprising, for each digitization, a closure of the first switch until a desired setting accuracy is reached, opening of the first switch when said accuracy is reached, and closing of the reading transistor.

[0025] According to one embodiment, the time between the closing of the reading transistor and the opening of the second switch is identical during the first and second digitization steps.

[0026] According to another aspect, a system for reading a charge contained in a photodiode of a pixel is proposed, comprising a power input, an output, a readout node, the readout system further comprising means for biasing the output of the pixel, a first switch, an energy storage capacitor, and control means, the output of the pixel being connected to the biasing means via the first switch, the pixel further comprising a follower transistor having a gate connected to the readout node and a drain connected to the power input, a readout transistor (14) connecting the source of the follower transistor to the output of the pixel, the power input being connected to the energy storage capacitor and to a first end of the second switch, the second end of the second switch being intended to be connected to a DC voltage source, and control means,the control means being configured for: ,

[0027] o during a first digitization step, perform a first digitization of a first value of the potential of the reading node,

[0028] to transfer the charge contained in the photodiode to the readout node following the first digitization,

[0029] o during a second digitization step, perform a second digitization of a second value of the potential of the reading node containing the transferred charge,

[0030] o during the first and second digitization stages, the control means being further configured to:

[0031] - close the second switch to charge the energy storage capacity,

[0032] - simultaneously with the closing of the second switch, close the first switch, then open the first switch following the closing of the first switch when the pixel output voltage is established to a desired establishment accuracy.

[0033] - open the second switch following the opening of the first switch, and

[0034] - the first and second digitizations of the potential value of the read node the pixel output being performed when the first and second switches are open, the pixel being powered by the storage capacity.

[0035] According to one embodiment, the biasing means comprise a current source, the control means being configured to close the reading transistor, and for each digitization close the first switch for a stabilization period allowing the pixel output voltage to be established to a desired accuracy.

[0036] According to one embodiment, the time between the opening of the first switch and the opening of the second switch is identical during the first and second digitization steps.

[0037] According to one embodiment, the biasing means comprise a voltage source, the control means being configured for each digitization, close the first switch until a desired establishment accuracy is reached, open the first switch when said accuracy is reached, and close the reading transistor.

[0038] According to one embodiment, the time between the closing of the reading transistor and the opening of the second switch is identical during the first and second digitization steps.

[0039] According to yet another aspect, a column of pixels is proposed comprising a system as defined above and at least a second pixel identical to the first pixel, the output of the second pixel being connected to the polarization means via the first switch, the power input of the second pixel being connected to the energy storage capacity and to the first end of the second switch.

[0040] According to another aspect, a pixel matrix is ​​proposed comprising at least a first column of pixels as defined above and a second column of pixels as defined above.

[0041] According to one embodiment, the energy storage capacity of the first column of pixels and the energy storage capacity of the second column of pixels are grouped into a common storage capacity.

[0042] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and implementations, which are by no means limiting, and the accompanying drawings in which the figures:

[0043] [Fig.l] ;

[0044] [Fig.2] ;

[0045] [Fig.3] ;

[0046] [Fig.4] ;

[0047] [Fig.5] ;

[0048] [Fig.6];

[0049] illustrate embodiments and implementations of the invention.

[0050] Fig. 1 schematically illustrates a first example of an integrated circuit IC comprising a column 1 of pixels and a converter 4.

[0051] Column 1 comprises a plurality of identical pixels 2, 3.

[0052] For clarity, only two pixels 2, 3 are shown.

[0053] Of course, column 1 may contain more than two pixels.

[0054] The integrated circuit IC further comprises a first switch 7, a second switch 5, an energy storage capacity 6, biasing means 8 and control means 9.

[0055] A capacitor 20 is connected between the output 2b of the first pixel 2 and ground GND.

[0056] The converter 4 is controlled by the control means 9.

[0057] A first end 5a of the second switch 5 is connected to the storage capacity 6 and to a power input 2a, 3a of each pixel 2, 3 of column 1.

[0058] The second end 5b of the second switch 5 is connected to a DC voltage source 100.

[0059] The first switch 5 further includes a control input controlled by the control means 9.

[0060] A first end 7a of the first switch 7 is connected to an output 2b, 3b of each pixel 2, 3 of column 1.

[0061] A second end 7b of the first switch 7 is connected to the biasing means 8.

[0062] The first switch 7 is controlled by the control means 9.

[0063] The polarization means 8 comprise a current source 8a delivering a current 18.

[0064] Each pixel 2, 3 further includes an initialization input 2c, 3c, a charge transfer input 2d, 3d and a read (line selection) input 2e, 3e.

[0065] The initialization inputs 2c, 3c, charge transfer inputs 2d, 3d and readout inputs 2e, 3e are controlled by the control means 9.

[0066] Since pixels 2, 3 are identical, only the first pixel 2 is detailed in what follows.

[0067] The first pixel 2 includes a pinched photodiode 10 having an anode connected to ground GND and a charge transfer transistor 11 having a source connected to the cathode of the photodiode 10, a drain connected to a floating SN read node of the first pixel 2 and a gate connected to the transfer input 2d.

[0068] The first pixel 2 further includes an initialization transistor 12 having a drain connected to the power supply input 2a of the first pixel 2, a source connected to the read node SN and a gate connected to the initialization input 2c.

[0069] Alternatively, the drain of the initializing transistor 12 can be connected to a voltage source other than the DC voltage source 100.

[0070] The first pixel 2 has a capacitance 101 connected between the floating SN read node and ground GND.

[0071] The first pixel 2 includes a follower transistor 13 having a drain connected to the power input 2a of the first pixel 2, a gate connected to the floating read node SN.

[0072] The first pixel 2 further comprises a read transistor 14 having a drain connected to the source of the follower transistor 13, a source connected to the output 2b of the first pixel 2 and a gate connected to the read input 2e of the first pixel 2.

[0073] The transfer transistors 11, initialization transistor 12 and readout transistor 14 are, for example, N-type MOS (metal-oxide-semiconductor field-effect transistor) insulated-gate type field-effect transistors, the first pixel 2 comprising four transistors.

[0074] The invention applies to any pixel comprising at least one pinch photodiode, a transfer transistor, an initializer transistor, a readout transistor and an NMOS type follower transistor.

[0075] Pixels 2, 3, energy storage capacity 6, polarization means 8, converter 4, first switch 7, second switch 5 and control means 9 form a system for reading a charge contained in a photodiode 10 of pixels 2, 3 of column 1.

[0076] [Fig.2] illustrates a chronogram of an example of the reading process implementing the digitization system illustrated in [Fig.1].

[0077] In what follows, it is assumed that only the charge contained in the photodiode 10 of the first pixel 2 is read.

[0078] A closed transistor is conducting and an open transistor is not conducting.

[0079] Of course, reading the value of the charge contained in the photodiode 10 into a digital code as described below applies to all the pixels in column 1.

[0080] The timing diagram illustrates an example of the time evolution of SMP, INIT, TG, RST, RD control signals delivered by the control means 9, and of the Vx signal delivered on the output 2b of pixel 2.

[0081] We denote SMP the control signal of the second switch 5, INIT the control signal of the first switch 7, TG the control signal of the transfer transistor 11, RST the control signal of the initialization transistor 12 and RD the control signal of the read transistor 14.

[0082] The method comprises selecting the first pixel 2 by switching the signal RD applied to the read input 2e of said pixel 2 to a high state, a first digitization step 22 of a first value of the potential of the read node SN, and a transfer of the charge 23 contained in the photodiode 10 to the read node SN. following the first digitization, and a second digitization step 24 of a second value of the potential of the SN reading node including the transferred charge.

[0083] Digitization steps 22, 24 are carried out by converter 4.

[0084] The first and second digitization steps 22, 24 comprise:

[0085] - closing the second switch 5 to charge the storage capacity of energy 6, and

[0086] - simultaneously with the closing of the second switch 5, a closing of the first switch 7 and an opening of the first switch when the pixel output voltage is established to a given precision. Establishing the pixel output voltage to a desired precision is a deterministic and indispensable initial condition for obtaining a deterministic pixel 2 output signal by difference of the first and second digitization steps 22, 24,

[0087] - an opening of the second switch 5 following the opening of the first switch 7, and

[0088] - a digitization of the potential value of the SN reading node on output 2b of the pixel when the first and second switches 5 are open, the pixel being powered by the storage capacity.

[0089] The pixel output signal digitizations are performed when the power switch is open so that noise transmitted by the DC power source is not transmitted to the pixel, the pixel being powered by the energy storage capacitor. The pixel is disconnected from the power supplied by the first DC voltage source during the reading of the pixel output signals, preventing the creation of line noise due to noise from source 100.

[0090] The voltage regulator known from the prior art is removed without altering the quality of the signals delivered by the pixel.

[0091] In addition, since the voltage regulator is removed, the voltage drop due to the regulator is eliminated and the output amplitude of the signal can be increased to gain in signal / noise ratio.

[0092] The given accuracy is determined so as not to degrade the desired image quality.

[0093] The first and second digitization steps 22, 24 and the transfer step 23 are now detailed.

[0094] During the first digitization step 22, at a time tl, the second switch 5 is closed (SMP high) to load the storage capacity 6 and power the pixels of column 1, the first switch 7 is closed (INIT high), the initialization transistor 12 is closed (RST high) to initialize the read node SN of the first pixel 2 and the read transistor 14 is closed (RD high).

[0095] At time t2, the initialization transistor 12 is open (RST in the low state).

[0096] At a time t5, when the output voltage Vx of pixel 2 is established to a precision of establishment sought nearby, the first reset switch 7 is open (INIT in low state).

[0097] The establishment accuracy is predetermined from the desired accuracy for the sensor.

[0098] Between times t1 and t5, the reading transistor 14 and the first switch 7 are simultaneously closed for a settling time allowing the output voltage Vx of the first pixel 2 to be established to the desired settling accuracy.

[0099] From time t5, the current consumed by pixel 2 decreases rapidly. When the current consumed by the first pixel 2 is sufficiently low to be supplied by the storage capacity 6, at time t6, the second power switch 5 is opened (SMP in the low state). Pixels 2 and 3 are then powered by the storage capacity 6.

[0100] The time between the opening of the first switch 7 following the closing of the first switch 7 (time t5) and the opening of the second switch 5 (time t6) is referred to as t_set. The current consumed by pixel 2 corresponds to the charging of the capacitor 20 connected to the output 2b of the first pixel 2 by the follower transistor 13. The current consumed decreases rapidly over time. The time t_set is chosen so that the current required to power the first pixel 2 during the scanning time can be supplied by the energy storage capacitor 6, without debiasing the follower transistor 13 of the first pixel 2.

[0101] At a time t7 during a first digitization of the first digitization step 22, following the time t6, the converter 4 digitizes the signal Vx representing a first value of the potential of the reading node SN and a shift of the system.

[0102] When the output signal of the converter 4 representing the reference potential of the signal SN is delivered, the charge transfer step 23 and the second digitization step 24 begin at a time t8.

[0103] At time t8, the second switch 5 is closed to charge the storage capacitance 6 and power the pixels of column 1, the second switch 7 is closed, the transfer transistor 11 is conducting (TG in the high state) to transfer the charge contained in the photodiode 10 to the reading node SN.

[0104] At time t9, when the charge has been transferred from the photodiode 10 to the SN node, the transfer transistor 11 is open (TG in the low state).

[0105] At an instant tlO, when the output voltage Vx of pixel 2 is established to the desired establishment accuracy, the first switch 7 is opened.

[0106] At time tl 1, the second switch 5 is open. Pixels 2, 3 are powered by the storage capacity 6.

[0107] The time between the opening of the first switch 7 following the closing of the first switch 7 (time tl0) and the opening of the second switch 5 (time tl1) is equal to the time t_set between times t5 and t6.

[0108] The t_set duration allows the current consumed by the first pixel 2 to be sufficiently low so that the storage capacity 6 is able to power the first pixel 2 without desaturating the follower transistor 13.

[0109] The equality of the durations between the instants t5 and t6 and between the instants tl0 and tl1 makes it possible to guarantee identical evolutions of the signal Vx of pixel 2 from the instants t5 and tl0 to prevent the appearance of voltage shifts when determining the difference of the two digitizations by the converter 4.

[0110] At a time tl2, when the second power switch 5 is open (SMP in the low state), the converter 4 digitizes the signal Vx representing a second value of the potential of the reading node SN including the transferred charge and a shift of the system.

[0111] For example, the time tl2 is defined so that the duration between the times t7 and t6 is equal to the duration between the times tl1 and tl2.

[0112] The required establishment accuracy at times t5 and tl0 defines respectively the accuracy of the signal obtained by difference of the signal Vx at times t7 and tl2.

[0113] In a known manner, the converter 4 can further perform the subtraction between the results of the first and second digitization (classical correlated double sampling operation) so that the system offset is eliminated and the result is proportional to the load transferred during step 23.

[0114] The duration between times t5 and t6 is for example equal to the duration between times tl0 and tl1.

[0115] From the Vx signals delivered during the first and second digitizations, the value of the charge stored in the photodiode 10 during the capture of a light signal by said diode is digitized.

[0116] The capacitance 6, the time between times tl and t6 and the time between times t8 and tl 1 are chosen so that the capacitance 6 is able to power pixels 2, 3 when the second switch 5 is open.

[0117] Figure 3 illustrates a second example of the CL integrated circuit

[0118] The second IC differs from the first IC illustrated in [Fig.1] in that the IC includes a second embodiment of the biasing means 8, the biasing means 8 comprising a voltage source 15 connected to the second end 7b of the first switch.

[0119] The voltage source 15 delivers a voltage which can be, for example, zero.

[0120] Fig. 4 illustrates a timing diagram of an example of the reading process implementing the digitization system illustrated in Fig. 3 of the second example of the integrated circuit IC.

[0121] In what follows, it is assumed that only the charge contained in the photodiode 10 of the first pixel 2 is read.

[0122] The timing diagram illustrates an example of the time evolution of the signals SMP, INIT, TG, RST, RD

[0123] The method includes a first digitization step 25 of a first value of the potential of the reading node SN, a transfer of the charge 26 contained in the photodiode 10 to the reading node SN following a first digitization of the first digitization step 25, and a second digitization of a second digitization step 27 of a second value of the potential of the reading node SN including the transferred charge.

[0124] The first and second digitizations are carried out by converter 4.

[0125] The first and second digitization steps 25, 27 comprise:

[0126] - closing the second switch 5 to charge the storage capacity energy 6,

[0127] - simultaneously with the closing of the second switch 5, a closing of the first switch 7 and an opening of the first switch when the pixel output voltage is established,

[0128] -a closure of the reading switch 14 (controlled by RD), this closure being non-overlapping with that of the switch 7,

[0129] - an opening of the second switch 5 following the opening of the first switch 7, and

[0130] - a digitization of the potential value of the SN reading node on output 2b of the pixel when the first and second switches 5 are open, the pixel being powered by the storage capacity 6.

[0131] As described previously, the pixel output signal readings are taken when the power switch is open so that line noise transmitted by the DC power supply is not transmitted to the pixel, the pixel being powered by the energy storage capacitor. The pixel is disconnected from the power supplied by the first DC voltage source during the reading of the pixel output signals.

[0132] The voltage regulator known from the prior art is removed without altering the quality of the signals delivered by the pixel.

[0133] Furthermore, since the power-consuming voltage regulator is removed, the electrical energy delivered by the power source is reduced. In addition, since the voltage regulator is removed, the voltage drop due to the The regulator is removed and the signal output amplitude can be increased to improve the signal-to-noise ratio.

[0134] The first and second digitization steps 25, 27 and the transfer step 26 are now detailed.

[0135] During the first digitization step 25, at a time t20, the second switch 5 is closed to charge the storage capacity 6 and power the pixels of column 1, the first switch 7 is closed to initialize Vx to ground GND, the initialization transistor 12 is closed to initialize the read node SN of the first pixel 2.

[0136] In addition, the transfer transistor 11 is open (TG in the low state) and the readout transistor 14 is open.

[0137] At a time t21, when the output voltage Vx of pixel 2 is established at the voltage imposed by the voltage generator 15 to a desired establishment accuracy, the first reset switch 7 is open (INIT in the low state).

[0138] The establishment accuracy is predetermined from the desired accuracy for the sensor.

[0139] The closing time of the reset switch 7 between times t20 and t21 is referenced t_init.

[0140] At a time t22, when the initialization transistor 12 is open, the reading transistor 14 is closed (RD signal).

[0141] The reading switch 14 is closed following the opening of the first switch 7 so that the first switch and the reading switch 14 are not closed simultaneously (without overlap) to prevent a direct electrical connection between the source 100 and ground GND.

[0142] The follower transistor 13 recharges the capacitance 20 through the readout transistor 14 up to a voltage representative of the potential of the SN node.

[0143] At time t25, when the capacity 6 is able to power pixels 2, 3 between times t22 and t28, the second switch 5 is opened. Pixels 2, 3 are powered by the storage means 6.

[0144] At a time t26 between time t25 and time t27, the converter 4 digitizes the signal Vx representing a first value of the potential of the reading node SN and a shift of the system.

[0145] The first digitization of the first digitization step 25 is carried out at time t26 between times t25 and t27.

[0146] When the output signal of the converter 4 representing the reference potential of the signal SN is delivered, at time t26, the reading transistor 14 is open.

[0147] The charge transfer step 26 and the second digitization step 27 begin at time t28.

[0148] At time t28, the second switch 5 is closed to charge the storage capacity 6 and power the pixels of column 1, the first switch 7 is closed, the transfer transistor 11 is closed to transfer the charge contained in the photodiode 10 to the SN node.

[0149] The reading switch 14 is open before the first switch 7 is closed so that the first switch 7 and the reading switch 14 are not closed simultaneously (without overlap).

[0150] At time t29, the first switch 7 is open.

[0151] The time between the closing of the reading switch 14 and the opening of the second switch 5 is identical during the first and second digitizations.

[0152] At a time t30 following t29, the read transistor 14 is closed.

[0153] At time t31, when the charge has been transferred from the photodiode 10 to the node SN, the transfer switch 11 is open.

[0154] At time t32, the second power switch 5 is open. Pixels 2, 3 are powered by the storage capacity 6.

[0155] At time t33, when the second power switch 5 is open (SMP in the low state), the converter 4 digitizes the signal Vx representing a second value of the potential of the readout node SN containing the transferred charge

[0156] The second digitization of the second digitization step 27 is carried out at time t33.

[0157] In a known manner, the converter 4 can further perform the subtraction between the results of the first and second digitization (classical correlated double sampling operation) so that the system offset is eliminated and the result is proportional to the load transferred during step 26.

[0158] The duration between times t22 and t25 is equal to the duration between times t30 and t32.

[0159] The duration between times t25 and t26 is equal to the duration between times t32 and t33.

[0160] From the Vx signals delivered during the first and second digitizations, the The value of the charge stored in the photodiode 10 when a light signal is detected by said diode is determined.

[0161] The output signal readings of the first pixel 2 are performed when the power switch 5 is open so that the line noise transmitted by the source 100 is not transmitted to pixels 2, 3, pixels 2, 3 being powered by means 6.

[0162] The voltage regulator known from the prior art is removed without altering the quality of the signals delivered by pixels 2, 3.

[0163] As the voltage regulator is removed, the amplitude of variation of the output signal (“swing”) of the pixel is increased and consequently the signal-to-noise ratio of said signal is increased.

[0164] Fig. 5 illustrates a first example of a pixel matrix.

[0165] The matrix comprises the first column 1 of pixels and a second column 100 of pixels identical to the first column 1.

[0166] Of course, the pixel matrix can comprise more than two columns of pixels.

[0167] The first column 1 of pixels is connected to the first and second switches 5, 7, to the storage capacitor 6, to the biasing means 8, to the control means 9, to the capacitor 20 and to the converter 4 as described previously.

[0168] The second column 100 of pixels is connected to first and second switches 50, 70, to a storage capacity 60, to polarization means 80, to control means 9, to a capacity 200 and to the converter 4.

[0169] The first switch 70 connects the biasing means 80 to the outputs of the pixels in the second column 100 and is controlled by the control means 9; the capacitor 200 connects the outputs of the pixels in the second column 100 to ground GND. The pixel outputs are further connected to the converter 4.

[0170] The second switch 50 connects the source 100 to the power inputs of the pixels in the second column 10 and is controlled by the control means 9.

[0171] The power inputs of the pixels in the second column 100 are further connected to ground GND via the storage capacitance 60.

[0172] Fig. 6 illustrates a second example of a pixel matrix.

[0173] The second example differs from the first example of the matrix illustrated in [Fig.5] in that the power inputs of the pixels in the second column 100 are connected to the power inputs of the pixels in the first column 1, the matrix having a second switch 500 common to columns 1, 2 and a storage capacity 600 common to columns 1, 2, the common storage capacity 600 grouping the storage capacities 6 and 60 of the first and second columns 1, 10.

Claims

1. Demands A method for reading a charge contained in a photodiode (10) of a pixel (2) comprising a power input (2a), an output (2b), a readout node (SN), the output (2b) of the pixel being connected to biasing means (8) of the output (2b) of the pixel (2) via a first switch (7), a follower transistor (13) comprising a gate connected to the readout node (SN) and a drain connected to the power input, a readout transistor (14) connecting the source of the follower transistor (13) to the output (2b) of the pixel (2), the power input being connected to an energy storage capacitor (6) and to a DC voltage source (100) via a second switch (5), the method comprising: • a first digitization step of a first value of the read node (SN) potential, • a transfer of the charge (23, 26) contained in the photodiode (10) to the readout node (SN) following the first digitization, • a second digitization step of a second value of the read node (SN) potential containing the transferred charge, • The first and second digitization stages, comprising: - closing the second switch (5) to charge the energy storage capacity (6), - simultaneously with the closing of the second switch (5), a closing of the first switch (7) followed by an opening of the first switch when the pixel output voltage is established to a desired establishment accuracy, - an opening of the second switch (5) following the opening of the first switch (7), and - a digitization of the potential value of the read node (SN) on the output (2b) of the pixel when the first and second switches (5) are open, the pixel being powered by the storage capacity.

2. Method according to claim 1, the biasing means (8) comprising a current source (8a), the read transistor (14) being closed during the first and second digitization steps, the method comprising for each digitization, a closing of the first switch (7) for a stabilization period allowing the output voltage of the pixel to be established to a desired accuracy.

3. A method according to claim 2, wherein the time between the opening of the first switch (7) and the opening of the second switch (5) is identical during the first and second digitization steps.

4. Method according to claim 1, the biasing means (8) comprising a voltage source (15), the method comprising for each digitization, a closing of the first switch (7) until a desired establishment accuracy is reached, an opening of the first switch (7) when said accuracy is reached, and a closing of the reading transistor (14).

5. Method according to claim 4, wherein the time between the closing of the reading transistor (14) and the opening of the second switch (5) is identical during the first and second digitization steps.

6. A system for reading a charge contained in a photodiode (10) of a pixel (2) comprising a power input (2a), an output (2b), a readout node (SN), the readout system further comprising means for biasing (8) the output (2b) of the pixel (2), a first switch (7), an energy storage capacitor (6), and control means (9), the output (2b) of the pixel (2) being connected to the biasing means (8) via the first switch (7), the pixel further comprising a follower transistor (13) having a gate connected to the readout node (SN) and a drain connected to the power input (2a), a readout transistor (14) connecting the source of the follower transistor (13) to the output (2b) of the pixel (2), the power input (2a) being connected to the energy storage capacitor (6) and to a first end of the second switch (5),the second end of the second switch (5) being intended to be connected to a DC voltage source (100), and control means (9), the control means being configured to: • during a first scanning step, perform a first scan of a first value of the potential of the read node (SN), • transfer the charge (23, 26) contained in the photodiode (10) to the read node (SN) following the first scan, • during a second scanning step, perform a second scan of a second value of the potential of the read node (SN) containing the transferred charge, • during the first and second scanning steps, the control means being further configured to: - close the second switch (5) to charge the energy storage capacity (6), - simultaneously with the closing of the second switch (5),close the first switch (7) and then open the first switch following the closure of the first switch when the pixel output voltage is established to a desired establishment accuracy, - open the second switch (5) following the opening of the first switch (7), and - the first and second digitizations of the potential value of the read node (SN) on the output (2b) of the pixel are performed when the first and second switches (5) are open, the pixel being powered by the storage capacitor.

7. System according to claim 6, wherein the biasing means (8) comprise a current source (8a), the control means (9) being configured to close the read transistor (14), and for each digitization close the first switch (7) for a stabilization time enabling the pixel output voltage to be established to a desired accuracy.

8. System according to claim 7, wherein the time between the opening of the first switch (7) and the opening of the second switch (5) is identical during the first and second digitization steps.

9. System according to claim 6, wherein the biasing means (8) comprising a voltage source (15), the control means (9) being configured for each digitization, close the first switch (7) until a desired establishment accuracy is reached, open the first switch (7) when said accuracy is reached, and close the read transistor (14).

10. System according to claim 9, wherein the time between the closing of the reading transistor (14) and the opening of the second switch (5) is identical during the first and second digitization steps.

11. Column (1) of pixels comprising a system according to any one of claims 6 to 10 and at least a second pixel (3) identical to the first pixel (2), the output (3b) of the second pixel (3) being connected to the biasing means (8) via the first switch (7), the power input (3a) of the second pixel (3) being connected to the energy storage capacitance (6) and to the first end (5a) of the second switch (5).

12. Pixel matrix comprising at least a first column of pixels according to claim 11 and a second column of pixels according to claim 11.

13. Matrix according to claim 12, wherein the energy storage capacity of the first column of pixels and the energy storage capacity of the second column of pixels are grouped into a common storage capacity (600).

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