Reducing energy consumption during programming or erasing of a split-gate memory cell, memory cell and manufacturing process

Abstract

A non-volatile memory device comprising a memory cell (Mi+1,j) having a split-gate state transistor (Ti+1,j) and a vertical-type selector transistor (ST) embedded in a semiconductor substrate, and means (10,20,30) configured to increase carrier mobility in the semiconductor channel (ZCV) of the selector transistor during a hot-carrier programming or erasure operation of the memory cell. Figure for the abstract: Figure 5

Description

Title of the invention: Reduction of energy consumption during programming or erasure of a split-gate memory cell, memory cell and manufacturing method

[0001] Embodiments and implementations relate to non-volatile memories, in particular split-gate non-volatile memories and fully buried selector transistor (including the source) and in particular the reduction of the energy consumption of programming or erasure by hot carriers, of such memories.

[0002] A split-gate memory cell comprises a state transistor having a floating gate separated from the transistor channel by a gate oxide layer and surmounted by a control gate electrically isolated from the floating gate.

[0003] Programming or erasing such a floating-gate state-state transistor can be performed: -by the injection or extraction of electrical charges into the floating gate of the transistor by tunneling effect (Fowler-Nordheim effect) through the gate oxide, or -by the injection of hot carriers (electrons or holes) into the floating gate.

[0004] In the case of using the Fowler-Nordheim effect for programming or erasure, a significant electric field is applied between the substrate of the state-state transistor and the floating gate. This implies applying a high potential difference, typically on the order of 15 V, which also depends on the thickness of the gate oxide, leading to the use of a substantial charge pump and therefore costly in terms of surface area.

[0005] It is therefore generally preferable to use the injection of hot carriers.

[0006] In the case of using the hot carrier effect to program or clear a split-gate state transistor associated with a selector transistor buried in the substrate, the vertical current of electrons passing through the channel of the selector transistor (which is then in saturation mode) is used to create electron / hole pairs on the drain side of the selector transistor, which is close to the floating gate of the state transistor.

[0007] It is then sufficient to apply to the control grid a positive voltage to attract electrons in the case of programming or a negative voltage to attract holes in the case of erasure.

[0008] It is the kinetic energy of the hot carriers (which has been transferred to them by the electrons of the vertical channel of the selection transistor) that alone enables the injection of these hot carriers (electrons or holes) in the floating gate and the electric field, and consequently the potential difference applied across the terminals of the gate oxide located below the floating gate is very small compared to that used in the Fowler-Nordheim effect.

[0009] There is a need to reduce energy consumption during a hot-carrier programming or erasure operation of a non-volatile memory cell, in particular a split-gate non-volatile memory cell with a fully buried select transistor.

[0010] According to one embodiment, it is proposed to increase the mobility of carriers, for example electrons, in the channel of the selection transistor, in order to increase the density (the number) of hot carriers created.

[0011] This increase in mobility can be achieved by reducing the channel resistance and increasing the current density.

[0012] In this regard, it is advantageously proposed to locate the conduction of electrons in a voltage-constrained silicon layer (in the direction of conduction), which increases the mobility of electrons in the channel during a programming or erasure operation.

[0013] This increase in mobility induces an increase in the number of hot carriers created, which makes it possible to reduce the energy consumption required for programming or erasing the memory cell.

[0014] This energy reduction translates, for example, if the same voltage values ​​are applied to the different electrodes of the memory cell as those generally applied in the prior art, into a reduction in the programming or erasure time.

[0015] It would also be possible to translate this energy reduction into a decrease in the applied voltage values ​​while maintaining the same programming or erasure time.

[0016] However, such a solution is more complex to implement from the point of view of adjusting the electrical conditions, from one memory device to another which may contain different densities of memory cells.

[0017] Therefore, the first solution mentioned above (reduction of programming or erasure time) is preferred because it can be applied to all memory devices regardless of their memory density.

[0018] According to one aspect, a non-volatile memory device is proposed, comprising a memory cell having a split-gate state transistor and a vertical-type selection transistor embedded in a semiconductor substrate, and means configured to increase the mobility of the carriers (e.g., electrons) in the semiconductor channel of the selection transistor during a hot-carrier memory cell programming or erasure operation.

[0019] A vertical type selection transistor buried in the substrate may have its surface source region, i.e. opening onto the surface of the substrate, and its drain region located deep within the substrate.

[0020] Alternatively, the vertical type selection transistor may have a non-surface source region, i.e. located deep within the substrate, typically deeper than the drain region.

[0021] This variant (non-surface source region) is more advantageous in terms of surface footprint and allows two selection transistors to share a common buried gate region and can be associated with two twin memory cells, which is not possible for a vertical type selection transistor with a surface source region.

[0022] According to one embodiment, said means comprise in the semiconductor channel, a silicon region located between a gate oxide region and a region of a silicon germanium alloy.

[0023] Since the lattice parameter of silicon-germanium is greater than that of silicon, the silicon which will be deposited by epitaxy on this silicon-germanium will undergo a positive deformation (biaxial and isotropic) which induces a tensile stress in the silicon and consequently an increase in the mobility of the carriers (electrons for example) in this silicon layer.

[0024] According to one embodiment, the thickness of the silicon region is between 5 and 30 nanometers and the thickness of the region of said silicon germanium alloy is between 5 and 20 nanometers, preferably less than 15 nanometers.

[0025] According to one embodiment, the germanium silicon alloy is a GexSi(i_x) alloy with x between 0.3 and 0.9.

[0026] According to another aspect, a non-volatile memory device is proposed, comprising a memory cell having a split-gate state transistor and a vertical type selection transistor buried in a semiconductor substrate and preferably having a non-surface source region.

[0027] The selection transistor comprises a semiconductor channel having a silicon region located between a gate oxide region and a region of a silicon germanium alloy.

[0028] According to one embodiment, the device includes another memory cell, twin of said memory cell, the two twin memory cells having the same structure and each having a selection transistor buried in the semiconductor substrate and of identical structure.

[0029] The two selection transistors have a common buried gate region framed by a stack comprising a silicon layer framed by a gate oxide layer and a layer of said germanium silicon alloy.

[0030] The silicon layer, the gate oxide layer and the layer of said silicon alloy include respectively the two silicon regions, the two gate oxide regions and the two regions of said germanium silicon alloy of the channels of the two selection transistors of the two twin memory cells.

[0031] According to one embodiment, the thickness of each silicon region is between 5 and 30 nanometers and the thickness of each region of said germanium silicon alloy is between 5 and 20 nanometers.

[0032] According to one embodiment, the germanium silicon alloy is a GexSi(i_x) alloy with x between 0.3 and 0.9.

[0033] According to one embodiment, the device comprises a memory plane having rows and columns of memory cells, and a one-bit-row-per-column structure, all twin memory cells of a column being connected to the bit row of said column.

[0034] Alternatively, the memory plan may have a two-bit-line-per-column structure, with two twin memory cells of a column being connected to different bit lines among the two bit lines of said column, while two adjacent but not twin memory cells of said column are connected to the same bit line of said column.

[0035] According to another aspect, a method is proposed to reduce energy consumption during a programming or erasure operation by hot carriers of a memory cell having a split-gate state transistor and a vertical type selection transistor buried in a semiconductor substrate and preferably having a non-surface source region.

[0036] The method according to this aspect includes an increase in the mobility of the carriers in the semiconductor channel of the selection transistor during said programming or erasure operation.

[0037] According to one embodiment, the mobility increase includes energizing a silicon region of the channel by an underlying region of a silicon germanium alloy, the silicon region being between this silicon germanium alloy region and a gate oxide region.

[0038] The thickness of the silicon region is for example between 5 and 30 nanometers and the thickness of the region of said germanium silicon alloy is for example between 5 and 20 nanometers.

[0039] The germanium silicon alloy is for example a GexSi(i_x) alloy with x between 0.3 and 0.9.

[0040] According to another aspect, a method for manufacturing a non-volatile memory device is proposed, comprising an embodiment of a non-volatile memory cell.

[0041] The realization of the non-volatile memory cell includes an embodiment in and on a semiconductor substrate of a split-gate state transistor and an embodiment of a vertical type selection transistor buried in the semiconductor substrate and preferably having a non-surface source region.

[0042] The implementation of the selection transistor includes -the formation of a trench in the semiconductor substrate, - an epitaxial layer of a silicon-germanium alloy on the trench walls, -an epitaxy of a silicon layer onto the layer of said silicon-germanium alloy, -the formation of a grid oxide layer on the silicon layer, and -filling the trench with polysilicon to form a gate region of the selection transistor.

[0043] According to one embodiment, the method comprises an embodiment in and on a semiconductor substrate, next to said state transistor, of another split-gate state transistor associated with another selection transistor, the two selection transistors having the same gate region framed by the stack formed by the underlying layer of germanium silicon alloy, the silicon layer and the gate oxide layer, so as to form two twin memory cells.

[0044] The thickness of the silicon layer is for example between 5 and 30 nanometers and the thickness of the layer of said germanium silicon alloy is between 5 and 20 nanometers.

[0045] The germanium silicon alloy is for example a GexSi(i_x) alloy with x between 0.3 and 0.9.

[0046] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is by no means limiting, and the accompanying drawings in which:

[0047] [Fig.l] ;

[0048] [Fig.2] ;

[0049] [Fig.3]

[0050] [Fig.4] ;

[0051] [Fig.5] ;

[0052] [Fig.6] ;

[0053] [Fig.7] ;

[0054] [Fig.8] ;

[0055] [Fig.9] ;

[0056] [Fig. 10] and

[0057] [Fig. 11] schematically illustrate methods of implementation and realization of the invention.

[0058] In [Fig. 1], the reference M designates a non-volatile memory cell of the type with split gate, for example of the selector transistor type having a vertical gate buried in the substrate of an integrated circuit.

[0059] More specifically, the memory cell M includes a state transistor T having a floating gate FG surmounted by a control gate CG connected to a gate control line CGL.

[0060] The drain (D) of the state transistor T is connected to a bit line BL while the source (S) of the state transistor T is connected to the drain of a selection transistor ST.

[0061] The ST selection transistor has a CSG gate connected to a WL word line.

[0062] The source (S) of the ST selection transistor is connected to a source line SL.

[0063] As illustrated in [Fig.2], each state transistor of a memory cell cooperates with the selection transistor ST which is of the vertical type and buried in the substrate SB.

[0064] The ZCH channel of the state transistor is referenced ZCH.

[0065] The ST selection transistors connected to the two state transistors Ti,j and Ti+1,j each have a vertical channel ZCV and a vertical buried common selection gate CSG.

[0066] The two memory cells Mi,j and Mi+l,j are, therefore, said to be "twin".

[0067] These two twin cells Mi,j and Mi+l,j belong to the same column j and to the two lines i and i+1.

[0068] It should be noted that for the purpose of simplifying the figure, the contact allowing the connection of the buried common grid CSG to the corresponding word line WLi,i+l, is not shown.

[0069] Similarly, the grid oxide that surrounds the buried CSG grid and separates it from each ZCV channel, as well as the structure of each ZCV channel, are not shown in this [Fig.2], but are shown in Figures 5 and 6.

[0070] The source region S of each selection transistor ST is non-surface, buried in the substrate SB more deeply than the drain region D of the corresponding selection transistor.

[0071] The semiconductor region which contains the drain region D of a selector transistor ST also contains the source region S of the state transistor connected to that selector transistor.

[0072] The state transistor here is advantageously a depletion-type state transistor.

[0073] The ZCH channel of the state transistor is advantageously a surface channel so that it may be possible to block the conduction of the channel by applying an acceptable control voltage to the control gate of the state transistor.

[0074] With such memory cells, different memory plan structures are possible, namely a single line of bits per column structure or a two (or double) line of bits per column structure.

[0075] The present invention is compatible with both of these types of memory plane structure.

[0076] By way of example, [Fig.3] represents a PM memory plan structure with a single row of bits per column and comprising memory cells Mi,j ; Mi,j+1 ;Mi-l,j ; Mi-l,j+l of the type mentioned above.

[0077] Memory cells Mi,j and Mi-l,j having a common selection grid CSG are twins. Similarly, memory cells Mi,j+1 and Mi-l,j+l are twin memory cells.

[0078] Memory cells Mi,j and Mi,j+1 of rank "i" belong to the row or row of rank i of the memory plane and are connected to a word line WLi-l,i and a grid control line CGLi.

[0079] The memory cells Mi-l,j and Mi-l,j+l of rank "i-1" belong to the row or row of rank "i-1" of the memory plane and are connected to the word line WLi-l,i and to a grid control line CGLi-1.

[0080] Memory cells Mi,j and Mi-l,j of rank "j" belonging to column j are accessible for reading and writing via a single line of bit BLj and memory cells Mi,j+1 and Mi-l,j+l of rank "j-1" are accessible for reading and writing via a single line of bit BLj+1.

[0081] The drain regions (D) of the state transistors Ti,j and Ti-l,j are connected to the bit line BLj and the drain terminals of the state transistors Ti,j+1 and Ti-1,j+1 are connected to the bit line BLj+1. The control gates CG of the transistors Ti,j and Ti,j+1 are connected to the gate control line CGLi and the control gates CG of the floating gate transistors Ti-l,j and Ti-1,j+l are connected to the gate control line CGLi-1.

[0082] Each floating gate transistor has its source terminal (S) connected to a source line SL via the selection transistor ST.

[0083] The common selection grids CSG of twin memory cells, are connected to the WLi-l,i word line.

[0084] In read mode, a zero read voltage can be applied to the control gate CG of the state transistor and a positive voltage can be applied to the bit line BL.

[0085] Since the state transistor is depletion-mode with a negative threshold voltage, it is normally conducting for a blank memory cell, that is, when no load is present in the floating gate.

[0086] A state transistor of an erased memory cell will be conducting while the state transistor of a programmed memory cell will be blocked.

[0087] Moreover, the programming or erasure of a floating gate transistor is carried out here by injecting hot carriers (electrons for programming and holes for erasure) into the floating gate of the transistor.

[0088] More particularly, hot-carrier (hot-hole) erasure of a memory cell is achieved by combining a positive voltage applied to the substrate with a negative voltage applied to the control gate of its floating-gate state transistor.

[0089] With regard to the twin cell, if it is desired that it not be simultaneously erased, a positive voltage is applied to the control gate of its state transistor.

[0090] The programming of a hot electron memory cell can be achieved, for example, by applying a positive voltage to the relevant bit line, applying a zero voltage to the substrate, and a positive voltage to the control gate of its floating-gate state transistor.

[0091] The selection of such a memory cell to be programmed is carried out by applying a positive voltage greater than the threshold voltage of the state transistor, on the relevant word line.

[0092] With regard to the twin cell, if it is desired that it not be programmed simultaneously, a weakly negative or zero programming inhibition voltage is applied to the control gate of its state transistor.

[0093] Finally, as indicated above, reading a memory cell is ensured by applying a zero voltage to the control gate CG of its state transistor, as well as a positive voltage to the corresponding bit line.

[0094] The selection of such a memory cell to be read is carried out by applying a positive voltage greater than the threshold voltage of the state transistor, on the relevant word line.

[0095] In practice, in read mode, a zero voltage will be applied to all cells of the memory plane.

[0096] As a result, two selected twin cells will be read simultaneously.

[0097] If, on the other hand, it is not desired that the twin cells not be read simultaneously, a negative reading inhibition voltage will be applied to the control gate of the one of the two twin cells that should not be read.

[0098] Figure 4 illustrates a memory plane and twin memory cell structure known as "double bit row" (two bit rows per column).

[0099] In such a structure each memory cell can be read independently of its twin memory cell by means of the bit line to which it is connected and to which its twin memory cell is not connected without it being necessary to apply a negative read inhibition voltage to the gate control line of the twin memory cell.

[0100] Similarly, each memory cell can be programmed independently of its twin memory cell by means of the bit line to which it is connected and to which its twin memory cell is not connected without it being necessary to apply a negative programming inhibition voltage to the gate control line of the twin memory cell.

[0101] The memory plane PM comprises rows and columns of memory cells, eight memory cells M1,j, M2,j, M3,j, M4,j, M1,j+1, M2,j+1, M3,j+1, M4,j+1 being represented here. Each memory cell includes a state transistor, respectively referenced T1,j, T2,j, T3,j, T4,j, T1,j+1, T2,j+1, T3,j+1, T4,j+1, and a selection transistor ST connected between a source plane SL and the state transistor.

[0102] The memory cells M1,j, M2,j, M3,j, M4,j belong to a column of rank j and the memory cells M1,j+1, M2,j+1, M3,j+1, M4,j+1 belong to an adjacent column of rank j+1. The memory cells M1,j, M1,j+1 belong to a first row of memory cells, and their state transistors T1,j, T1,j+1 have control gates CGI connected to a common gate control line CGL1. The memory cells M2,j, M2,j+1 belong to a second row of memory cells, and their state transistors T2,j, T2,j+1 have control gates CG2 connected to a common gate control line CGL2. The memory cells M3,j, M3,j+1 belong to a third row of memory cells, and their state transistors T3,j, T3,j+1 have control gates CG3 connected to a common gate control line CGL3.The memory cells M4,j, M4,j+1 belong to a fourth row of memory cells and their state transistors T4,j, T4,j+1 have control gates CG4 connected to a common gate control line CGL4.

[0103] In the j-rank column, the memory cells M1,j, M2,j are twin memory cells and their ST selection transistors have a common selection grid CSG 1,2 connected to a common word line WL1,2.

[0104] Similarly, the memory cells M3,j, M4,j are twin memory cells and their selection transistors ST have a common selection grid CSG3,4 connected to a common word line WL3,4.

[0105] In the column of rank j+1, the memory cells Ml,j+1, M2,j+1 are twin memory cells and their selection transistors ST have a common selection grid CSG1,2 connected to the word line WL1,2.

[0106] The memory cells M3,j+1, M4,j+1 are twin memory cells and their selection transistors ST have a common selection grid CSG3,4 connected to the common word line WL3,4.

[0107] The PM memory plan comprises two bit lines per memory cell column. Thus, two bit lines of B1,j, B2,j are allocated to the memory cells of column j, and two bit lines of B1,j+1, B2,j+1 are allocated to the memory cells of column j+1.

[0108] Two twin memory cells are connected to different bit lines among the two bit lines allocated to the column in which they are located, while two adjacent but non-twin memory cells are connected to the same bit line.

[0109] Thus, in column j:

[0110] - the drain terminal (D) of the state transistor Tl,j is connected to the bit line B1,j by via an AI-powered conductor path,

[0111] - the drain terminal of the state transistor T2,j is connected to the bit line B2,j by via a conductive path 23B,

[0112] - the drain terminal of the state transistor T3,j is connected to the bit line B2,j by the intermediate of the conductor path 23B (memory cell M2,j being adjacent but not twin to memory cell M3,j), and

[0113] - the drain terminal of the state transistor T4,j is connected to the bit line B1,j by the intermediary of a conductive path 4A.

[0114] In column j+1:

[0115] - the drain terminal of the state transistor T1,j+1 is connected to the bit line B1,j+1 by via an IC conductive path,

[0116] - the drain terminal of the state transistor T2,j+1 is connected to the bit line B2,j+1 by via a 23D conductive path,

[0117] - the drain terminal of the state transistor T3,j+1 is connected to the bit line B2,j+1 by the intermediate of the conductor path 23D (memory cell M2,j+1 being adjacent but not twin to memory cell M3,j+1), and

[0118] - the drain terminal of the state transistor T4,j+1 is connected to the bit line Bl,j+1 by via a 4C conductive path.

[0119] Each memory cell can be read independently of its twin memory cell by means of the bit line to which it is connected and to which its twin memory cell is not connected. For example, after selecting the twin memory cells C3,j, C4,j by means of a selection voltage applied to the word line WL3,4, and after applying a zero read voltage to the gate control line CGL3, the memory cell C3,j can be read via the bit line B2,j without it being necessary to apply a negative read inhibit voltage to the gate control line CGL4 of the twin memory cell C4,j since this memory cell is not connected to the bit line B2,j but to the bit line Bl,j.

[0120] As a result, a zero read voltage can be applied to the control gates of all memory cells in the memory plane.

[0121] For programming, the same positive voltage can be applied to the control grids of two twin cells, a positive voltage can be applied to the bit line to program that of the twin cells connected to that bit line, and a zero voltage can be applied to the bit line connected to the other memory cell that is not to be programmed.

[0122] We now refer more particularly to figures 5 and 6 to illustrate in more detail the structure of each ZCV channel of the corresponding ST selection transistor of the memory cell Mi,j and Mi+l,j represented very schematically on [Fig.2].

[0123] The buried common gate region CSG of the two ST selection transistors is framed by a stack comprising a silicon (Si) layer 2 framed by a gate oxide layer 1 (for example silicon dioxide (SiO2) and a germanium silicon alloy layer 3 (GexSi(i_x)).

[0124] This stacking includes, on the right part of [Fig.5], a silicon 20 region framed by a gate oxide region 10 and a region 30 of the silicon germanium alloy, and includes on the left part of [Fig.5] a silicon 21 region framed by a gate oxide region 11 and a region 31 of the silicon germanium alloy.

[0125] The ZCV channel of the ST selection transistor of the Mi+l,j memory cell thus has the silicon region 20 framed by the gate oxide region 10 and the germanium silicon region 30.

[0126] The ZCV channel of the ST selection transistor of the memory cell Mi, j has the silicon region 21, framed by the gate oxide region 11 and the germanium silicon region 31.

[0127] In the ZCV semiconductor channel of the corresponding ST selection transistor, the silicon region located between the gate oxide region and the germanium silicon alloy region forms means for increasing the mobility of carriers, here electrons, in this ZCV semiconductor channel during a programming or erasure operation of the memory cell.

[0128] Indeed, the lattice parameter of germanium silicon is greater than that of silicon. Consequently, the silicon, which, as will be seen in more detail below, will be deposited by epitaxy onto the germanium silicon, will undergo positive deformation biaxial and isotropic, which induces a tensile stress in the silicon and consequently an increase in the mobility of hot carriers in this silicon layer.

[0129] This therefore results in a reduction of energy consumption during the programming or erasure of the memory cell.

[0130] As an indication, for a non-volatile memory cell with a split gate and a selection transistor buried in the substrate and a non-surface source, made in a 40 nm CMOS technology, with these means allowing the increase of electron mobility in the channel of the selection transistor, a reduction of about 20% in the programming or erasure time is obtained while keeping the same voltage values ​​applied to the electrodes of the memory cell as those applied to a prior art memory cell.

[0131] As illustrated in [Fig.6], the thickness of the silicon layer 2, and therefore of each silicon region 20 and 21, is for example between 5 nm and 30 nm.

[0132] The thickness of the germanium silicon layer 3 is between 5 and 20nm, for example less than 15nm.

[0133] The value of x for the Gex Si(i_x) alloy is for example between 0.3 and 0.9.

[0134] Figure 7 illustrates very schematically one method of implementing a process enabling the reduction of energy consumption during a programming or hot-carrier erasure operation of a memory cell having a split-gate state transistor and a selection transistor buried in a semiconductor substrate.

[0135] Overall, the method includes an S7 increase in carrier mobility in the semiconductor channel of the selection transistor during the memory cell programming or erasure operation.

[0136] This increase in mobility may include an S70 voltageing of a silicon layer of the channel by an underlying layer of a silicon germanium alloy, this silicon layer being between this silicon germanium alloy layer and a gate oxide layer.

[0137] Reference is now made more particularly to figures 8 to 11 to describe an implementation of a method for manufacturing a non-volatile memory device according to the invention, and in particular an implementation of the channel formation of each ST selection transistor of two twin memory cells.

[0138] More particularly, on [Fig.8], a trench TR is first made (step S80) in the semiconductor substrate SB of the integrated circuit intended to receive the memory device according to the invention, at the location of the future buried gate region.

[0139] This TR trench is obtained in a classic and known manner by engraving through an MSK mask.

[0140] Then, we proceed (step S81), as illustrated in [Fig.9], with a first epitaxy of the silicon germanium layer 2 on the walls of the TR trench and then with a second epitaxy of the silicon 3 layer on the silicon germanium layer 2.

[0141] These steps of epitaxy of germanium silicon and then of silicon are classic steps and known in themselves by those skilled in the art.

[0142] Then, as illustrated in [Fig.10], the grid oxide layer 1 is formed (step S82) on the epitaxial silicon layer 2, for example by thermal growth.

[0143] Finally, after carrying out (step S83) a mechanochemical polishing of the MSK mask surmounted by part of the stack formed by the layers 3, 2 and 1, we obtain, as illustrated in [Fig. 11], the buried grid region CSG framed by the stack formed by the layers of silicon germanium 2 silicon 3 and grid oxide 1.

[0144] The remainder of the formation of the selection transistors, namely the formation of the source and drain regions and the remainder of the formation of the twin memory cells, namely the realization of the state transistors in particular, is classical and known in itself by those skilled in the art, and results in the structure illustrated in [Fig.2].

Claims

Demands

1. Non-volatile memory device, comprising a memory cell (Mi+1,j) having a split-gate state transistor (Ti+1,j) and a vertical-type selection transistor (ST) buried in a semiconductor substrate, and means (10,20,30) configured to increase carrier mobility in the semiconductor channel (ZCV) of the selection transistor during a hot-carrier programming or erasure operation of the memory cell.

2. Device according to claim 1, wherein said means comprise in the semiconductor channel (ZCV), a silicon region (20) located between a gate oxide region (10) and a region of a germanium silicon alloy (30).

3. Device according to claim 2, wherein the thickness of the silicon region (20) is between 5 and 30 nanometers and the thickness of the region (30) of said germanium silicon alloy is between 5 and 20 nanometers.

4. Device according to any one of claims 2 or 3, wherein the germanium silicon alloy is a GexSi(i_x) alloy with x between 0.3 and 0.

9.

5. Device according to any one of the preceding claims, wherein the selection transistor (ST) comprises a non-surface source region.

6. A device according to claims 2 and 5, comprising another memory cell (Mi,j), a twin of said memory cell (Mi+l,j), the two twin memory cells having the same structure and each having a selection transistor (ST) embedded in the semiconductor substrate and of identical structure, the two selection transistors having a common gate region (CSG) embedded within a stack (1, 2, 3) comprising a silicon layer (2) flanked by a gate oxide layer (1) and a layer (3) of said germanium silicon alloy, the silicon layer (2), the gate oxide layer (1) and the layer of said silicon alloy (3) respectively including the two silicon regions (20, 21), the two gate oxide regions (10, 11) and the two regions (30, 31) of said germanium silicon alloy channels (ZCV) of the two selection transistors (ST) of the two twin memory cells (Mi,j ; Mi+l,j).

7. Device according to claim 6, wherein the thickness of each region of silicon (20, 21) is between 5 and 30 nanometers and the thickness of each region (30, 31) of said germanium silicon alloy is between 5 and 20 nanometers.

8. Device according to any one of claims 6 and 7, wherein the germanium silicon alloy is a GexSi(i_x) alloy with x between 0.3 and 0.

9.

9. A device according to any one of the preceding claims, taken in combination with claim 6, comprising a memory plane (MP) having rows and columns of memory cells, and a one-bit-row-per-column structure, all twin memory cells in a column being connected to the bit row of said column.

10. A device according to any one of claims 1 to 8, taken in combination with claim 6, comprising a memory plane (MP) having rows and columns of memory cells, and a two-bit-line-per-column structure, two twin memory cells of a column being connected to different bit lines among the two bit lines of said column, while two adjacent but not twin memory cells of said column are connected to the same bit line of said column.

11. A method for reducing energy consumption during a hot-carrier programming or erasure operation of a memory cell having a split-gate state transistor and a vertical-type selector transistor buried in a semiconductor substrate, the method comprising an increase (S7) in carrier mobility in the semiconductor channel (ZCV) of the selector transistor during said programming or erasure operation.

12. A method according to claim 11, wherein said mobility increase (S7) comprises a voltageing (S70) of a silicon region of the channel by an underlying region of a silicon germanium alloy, the silicon region being between this region of silicon germanium alloy and a gate oxide region.

13. A method according to claim 11 or 12, wherein the thickness of the silicon region is between 5 and 30 nanometers and the thickness of the region of said silicon germanium alloy is between 5 and 20 nanometers.

14. A method according to any one of claims 11 to 13, wherein the germanium silicon alloy is a GexSi(i_x) alloy with x between 0.3 and 0.

9.

15. A method according to any one of claims 11 to 14, wherein the selection transistor (ST) has a non-surface source region.

16. A method for manufacturing a non-volatile memory device comprising an embodiment of a non-volatile memory cell, comprising an embodiment in and on a semiconductor substrate of a split-gate state transistor and an embodiment of a vertical type selector transistor embedded in the semiconductor substrate, in which the embodiment of the selector transistor comprises the formation of a trench (TR) in the semiconductor substrate, the epitaxy of a layer (3) of a silicon germanium alloy on the walls of the trench (TR), the epitaxy of a silicon layer (2) on the layer of said silicon germanium alloy, the formation of a gate oxide layer (1) on the silicon layer and the filling of the trench with polysilicon so as to form a gate region (CSG) of the selector transistor.

17. Method according to claim 16, wherein the embodiment of the selection transistor (ST) comprises an embodiment of a non-surface source region.

18. A method according to claim 17, comprising an embodiment in and on a semiconductor substrate, next to said state transistor, of another split-gate state transistor associated with another selector transistor, the two selector transistors having the same gate region (CSG) framed by the stack formed by the underlying layer (3) of germanium silicon alloy, the silicon layer (2) and the gate oxide layer (1), so as to form two twin memory cells.

19. A method according to any one of claims 16 to 18, wherein the thickness of the silicon layer (2) is between 5 and 30 nanometers and the thickness of the layer (3) of said germanium silicon alloy is between 5 and 20 nanometers.

20. A method according to any one of claims 16 to 19, wherein the germanium silicon alloy is a GexSi(i_x) alloy with x between 0.3 and 0.9.

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