METHOD FOR PREPARING A THIN LAYER OF SINGLE-DOMAIN FERROELECTRIC MATERIAL

Abstract

The invention relates to a method for preparing a single-domain thin film of ferroelectric material, the method comprising transferring the layer from a donor substrate to a recipient substrate, followed by heat treatment (Stab) and then thinning (Thin), the heat treatment comprising: heating to a high temperature between 400°C and the Curie temperature of the ferroelectric material forming the layer; holding the temperature for a period exceeding 30 minutes; and then cooling, the heating comprising a ramp at a rate of temperature change greater than or equal to 7°C / min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp. Figure 2

Description

Title of the invention: METHOD FOR PREPARING A THIN LAYER OF SINGLE-DOMAIN FERROELECTRIC MATERIAL FIELD OF INVENTION

[0001] The present invention relates to a method for preparing a thin film of ferroelectric material. More particularly, it relates to a preparation method that ensures the single-domain character of the ferroelectric material in the thin film of the final product. This preparation method is used, for example, in the fields of microelectronics, micromechanics, photonics, etc. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] As a preliminary point, it is recalled that a ferroelectric material is a material that possesses an electrical polarization in its natural state, a polarization that can be reversed by the application of an external electric field. A ferroelectric domain is defined as each contiguous region of the material in which the polarization is uniform (all dipole moments are aligned parallel to each other in a given direction). A ferroelectric material can therefore be characterized as "single-domain" if it consists of a single region in which the polarization is uniform, or as "multi-domain" if the ferroelectric material comprises a plurality of regions exhibiting potentially different polarities.

[0003] The present invention relates more particularly to the preparation of a ferroelectric thin film obtained by applying the Smart Cut™ technology, according to which a thin film is extracted from a substrate, possibly a bulk substrate, made of ferroelectric material by fracturing at a weak zone (or embrittlement plane) formed in the substrate by implanting so-called "light" species, such as helium or hydrogen. A specific example of the implementation of this process can be found in document EP3646374B1.

[0004] After the layer sampling step according to this process, it is often necessary to apply treatments to improve its surface condition, its crystalline quality, or to modify its thickness. However, the applicant observed that these preparation steps, when applied to a ferroelectric thin film deposited on a silicon substrate, could lead to the formation of a plurality of ferroelectric domains in a superficial portion of the thin film; this portion can have a thickness on the order of 150 nm to 200 nm, possibly more, on the free face side of the thin film, thus giving it a superficial multidomain character. Such a characteristic renders the layer unsuitable for its intended use, as it affects the performance of devices intended to be formed on / in the thin film, such as surface acoustic wave (SAW) devices.

[0005] Document FR2914492 describes a method for manufacturing a thin film of ferroelectric material using Smart Cut technology, in which the layer, taken and transferred onto a substrate, is prepared by subjecting it to an electric field in order to improve or restore its single-domain ferroelectric properties. Such treatment requires a pair of electrodes positioned on either side of the ferroelectric layer to be treated, for example, in electrical contact with this layer. It is not always possible to have such a pair of electrodes, particularly when the ferroelectric layer is transferred onto an electrically insulating substrate or onto a layer of electrical insulation.

[0006] For this reason, it may be preferable to thin the ferroelectric layer, for example by chemical polishing. However, removing a relatively large thickness of material by polishing tends to degrade the thickness uniformity of the polished layer. For example, removing a thickness on the order of 100 nm results in a layer whose thickness uniformity (i.e., the difference between the greatest and thinnest thicknesses when this thickness measurement is performed, for example by reflectometry or ellipsometry, at multiple measurement points over the entire extent of the layer) is degraded by on the order of 10 nm. This variability in thickness is unacceptable, as it makes it impossible to collectively manufacture devices with all the required characteristics from such a layer.

[0007] Alternatives exist to thinning by chemical polishing. One can, in particular, consider thinning the ferroelectric thin film by ion etching, for example by reactive ion etching (RIE). RIE is a type of dry etching that uses a plasma of chemically reactive ions to remove the surface material from a wafer. The plasma is generated under low pressure by an electromagnetic field. The high-energy ions of the plasma attack the surface of the layer and react with it to pulverize it, thus progressively thinning it. Such an approach is described in particular in the document filed under number FR2111960

[0008] However, whether implemented by mechanochemical polishing or by ion etching, the removal of a relatively large thickness of material to eliminate the multi-domain surface portion of the sampled layer This is a drawback of state-of-the-art processes, as this step tends to make the manufacturing process longer and more complex to implement.

[0009] This removal step also requires extracting a relatively thick layer from the ferroelectric material substrate, which necessitates implanting the light species with significant energy. Beyond a certain threshold thickness, the energy required to define the extracted layer is not available with existing implantation equipment. Furthermore, increasing the implantation energy leads to greater heating of the plate, which is accompanied by the appearance of local or widespread defects.

[0010] We therefore see that the known processes for preparing a single-domain thin film in ferroelectric material have limitations that it is desirable to overcome. SUBJECT OF THE INVENTION

[0011] An object of the invention is to provide a method for preparing a thin film of ferroelectric material that addresses at least some of the aforementioned limitations. More particularly, an object of the invention is to provide a method for preparing a thin film of ferroelectric material in which the thickness of material removed to eliminate the multi-domain surface portion of the extracted layer is reduced compared to the thickness removed in prior art methods. BRIEF DESCRIPTION OF THE INVENTION

[0012] With a view to achieving one of these goals, the object of the invention proposes a method for preparing a single-domain thin film of ferroelectric material, the method comprising: a step of implanting a so-called "light" species via a first face of a donor substrate so as to form a weakening plane in the donor substrate; a step of assembling the first face of the donor substrate to a device substrate so as to form an intermediate assembly; a step of fracturing the intermediate assembly at the level of the weakening plane, this step leading to equipping the device substrate with a ferroelectric layer transferred from the donor substrate and having a free face;a finishing step of the transferred ferroelectric layer comprising a heat treatment step and, after the heat treatment step, a thinning step of the transferred ferroelectric layer so as to form the single-domain thin layer, in which the heat treatment includes passing the device substrate equipped with the transferred ferroelectric layer through a controlled furnace to impose: a temperature rise of the transferred ferroelectric layer to a high temperature between 400°C and the Curie temperature of the forming ferroelectric material; the transferred ferroelectric layer; then a holding of the transferred ferroelectric layer at a temperature between the high temperature and said Curie temperature, for a period greater than 30 min; then a temperature decrease of the transferred ferroelectric layer, from the high temperature, in which the furnace is controlled so that the temperature rise of the transferred ferroelectric layer includes a temperature ramp carried out at a rate of temperature variation greater than 7°C / min, preferably greater than or equal to 10°C / min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

[0013] Compared with conventional processes, the process according to the invention results in a reduction of the thickness on which a multi-domain ferroelectric structure is likely to form in a surface region of the ferroelectric layer transferred from a donor substrate to a device substrate.

[0014] Consequently, a first advantage of the invention is a reduction in the thickness of the layer to be removed, and therefore an improvement in the uniformity of the thickness of the remaining layer, the uniformity typically degrading with the thickness of the layer removed.

[0015] A second advantage is that it is possible to transfer a thinner ferroelectric layer than in conventional processes, a thinner thickness of the transferred layer having to be eliminated in order to remove the multi-domain portion.

[0016] A third advantage is the simplification and shortening of the thinning process itself.

[0017] A fourth advantage is the reduction of heat treatment time.

[0018] According to additional, non-limiting features of the first aspect of the invention, considered individually or in any technically feasible combination:

[0019] - the temperature ramp of the transferred ferroelectric layer can be configured to cause a temperature rise of at least 350°C, preferably 400°C, even more preferably 450°C, of ​​the transferred ferroelectric layer;

[0020] - the temperature ramp of the transferred ferroelectric layer can be set to start at a temperature between ambient temperature and the high temperature, and cause a temperature rise of at least 100°C;

[0021] - the thinning step may consist of removing a layer thickness ferroelectric transfer less than 200 nm, preferably less than 150 nm;

[0022] - the device substrate provided with the transferred ferroelectric layer can be placed directly in the oven while it is at a high temperature;

[0023] - the device substrate provided with the transferred ferroelectric layer can be placed in the oven while it is at a first low temperature and removed from the oven while it is at a second low temperature, the first low temperature and the second low temperature each being between the ambient temperature and the high temperature, preferably between 100°C and 500°C, even more preferably between 300°C and 400°C;

[0024] - the single-domain thin film can be made of a piezoelectric material single crystal, such as lithium tantalate or lithium niobate;

[0025] - the donor substrate may consist of a bulk ferroelectric material;

[0026] - the donor substrate may comprise a supporting substrate supporting a layer of ferroelectric material, a material forming the donor substrate being distinct from a ferroelectric material forming the ferroelectric material layer;

[0027] - the finishing step of the transferred ferroelectric layer may include a surface treatment step intended to remove a lithium-rich surface layer, and / or eliminate or prevent the formation of dendrites;

[0028] - the finishing step of the transferred ferroelectric layer may include a surface treatment step intended to introduce hydrogen onto the surface of the transferred ferroelectric layer producing so as to produce a hydrogen concentration greater than 2.1021 atoms / cm3 in a surface thickness of the transferred ferroelectric layer less than 200 nm deep;

[0029] - the process may further include a step of forming at least one layer intercalated, on at least one of a face of the donor substrate and a face, formed of silicon oxide, silicon nitride, and / or silicon oxynitride;

[0030] - the process may further include a step of forming a layer of trapping of electrical charges on a surface of the device substrate, intended to come into contact with the donor substrate. Brief description of the drawings

[0031] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the accompanying figures in which:

[0032] [Fig-1] The [Fig. 1] illustrates a method for preparing a single-domain ferroelectric thin film according to the invention;

[0033] [Fig.2] The [Fig.2] is a diagram summarizing the preparation process of the [Fig.1]

[0034] [Fig.3] Fig.3 represents temperature profile graphs illustrating heat treatments according to the invention;

[0035] [Fig.4] The [Fig.4] illustrates variations of the process illustrated by the [Fig.1];

[0036] [Fig.5] The [Fig.5] illustrates a variant of the process illustrated by the [Fig.1];

[0037] [Fig.6] Fig.6 shows topographies obtained by AFM after a thickness 125 nm was removed from a layer and for different heat treatments;

[0038] [Fig.7] Fig.7 illustrates topographies for two heat treatments and two shrinkage thicknesses; and

[0039] [Fig.8] Fig.8 is a graph of a temperature profile illustrating a treatment thermal according to the invention.

[0040] The figures are schematic representations which, for the sake of readability, are not to scale. In particular, the thicknesses of the layers are not to scale with respect to the lateral dimensions of these layers. DETAILED DESCRIPTION OF THE INVENTION

[0041] The invention relates to a method for preparing a single-domain DevLay thin film of a ferroelectric material transferred from a single-crystal donor substrate DonSub onto a DevSub device substrate by a transfer technique including the implantation of light species in the donor substrate DonSub. Several embodiments of this thin-film supply step exist.

[0042] According to an embodiment illustrated in Figures 1 to 4, a donor substrate DonSub is provided during a step 110 of process 100. The donor substrate DonSub consists of a solid, single-crystal, single-domain block of ferroelectric material, for example, LiTaO3, LiNbO3, LiA1O3, BaTiO3, PbZrTiO3, KNbO3, BaZrO3, CaTiO3, PbTiO3, or KTaO3. The donor substrate DonSub may be in the form of a circular wafer of standardized dimensions, for example, 150 mm or 200 mm in diameter. However, the invention is not limited to these dimensions or this shape. The donor substrate may have been taken from an ingot of ferroelectric material, this taking having been carried out in such a way that the donor substrate DonSub has a predetermined crystal orientation. The orientation is chosen according to the intended application.Thus, it is common to choose an orientation between 30° and 60°RY, or between 40° and 50°RY, when it is desired to exploit the properties of a LiTaO3 thin film to form a SAW filter. However, the invention is by no means limited to a particular crystal orientation.

[0043] Regardless of the crystalline orientation of the donor substrate DonSub, the process includes introducing at least one so-called "light" species into the donor substrate DonSub, in particular chosen from inert gases, helium, and hydrogen, during a step 120Don. This introduction may correspond to implantation, that is, ion bombardment of a top planar DonTop face of the substrate DonSub donor by ions of the chosen light species such as hydrogen and / or helium ions.

[0044] In a manner known per se, and as illustrated by [Fig. 1](A), the implanted ions are intended to form a weakening plane Frgl, which will subsequently serve to separate the donor substrate into a layer of material between the implantation surface and the weakening plane.

[0045] The nature and dose of the implanted species and the implantation energy are chosen according to the thickness of the layer to be separated from the donor substrate DonSub and the physicochemical properties of the latter. In the case of a LiTaO3 donor substrate DonSub, a hydrogen dose of between Ie 16 and 5e 17 at / cm2 can be implanted with an energy between 30 and 300 keV to form the embrittlement plane at a depth of approximately 200 to 2000 nm.

[0046] In a step 110Dev, illustrated in [Fig. 1](B), the DevSub device substrate is provided to support the DevLay single-domain thin film. The DevSub device substrate can have the same dimensions and shape as the SubDon donor substrate. For reasons of availability and cost, the DevSub device substrate is a silicon wafer, either monocrystalline or polycrystalline. More generally, however, the DevSub device substrate can be made of any material, for example silicon, sapphire, or glass, and can have any shape.

[0047] At an assembly step 130, illustrated by [Fig.1](C) and subsequent to step 120Don, the upper flat face DonTop of the donor substrate DonSub is assembled to an upper flat face DevTop of the device substrate DevSub.

[0048] Prior to the assembly step, it is possible to prepare the faces of the substrates to be assembled by a cleaning, brushing, drying, polishing, or activation step, for example by plasma.

[0049] The assembly step may correspond to the intimate contact of the donor substrate DonSub with the device substrate DevSub by molecular adhesion and / or electrostatic bonding.

[0050] At the end of this assembly step, we have a Set resulting from the assembly of the donor substrate DonSub and the device substrate DevSub, the DonTop face of the donor substrate DonSub adhering to the DevTop face of the device substrate DevSub.

[0051] At a step 140, the Set assembly is processed to leave on the DevSub device substrate only a DonSubi layer from the donor substrate DonSub, for example by cleaving the donor substrate at the level of the embrittlement plane Frgl.

[0052] This detachment step may thus include applying a heat treatment to the Set assembly in a temperature range of approximately 80°C to 300°C to enable the transfer of the DonSubl layer to the DevSub device substrate. As a replacement for or in addition to heat treatment, this step may include the application of a sheet or jet of gaseous or liquid fluid to the embrittlement plane Frgl.

[0053] Fig. 1(D) illustrates this operation, with the separation of the donor substrate DonSub into two parts DonSubl and DonSub2 at the level of the embrittlement plane, the DonSub part forming a layer remaining fixed to the device substrate DevSub.

[0054] An alternative could, for example, be to thin the donor substrate until a desired thickness is obtained. However, this option is costly and inefficient, as the entire donor substrate is destroyed except for the DonSubi layer, whereas in the case of separation by cleavage, the donor substrate can be refreshed and reused to form new layers on other device substrates.

[0055] Regardless of the chosen embodiment, and as stated in the introduction to this application, finishing steps for the DonSubi layer are then necessary to improve its crystalline and surface quality and to provide a DevLay layer with a thickness corresponding to, or approaching, a target thickness. These finishing steps, schematically represented by step 150 implemented to go from [Fig. 1](D) to [Fig. 1](E), aim in particular to eliminate a multidomain, hardened, and rough surface layer resulting from the cleavage and detachment of the DonSubi thin layer from the rest of the donor substrate.

[0056] Reducing the thinning of the DonSubi layer is advantageous in several ways. A first advantage is the gain in uniformity of the DevLay layer obtained by thinning the DonSubi layer, which results from a reduction in the thickness required to form a multi-domain structure and therefore from a reduction in the thickness of the layer to be eliminated to get rid of the multi-domain structure and recover a single-domain structure.

[0057] A second advantage is the simplification and shortening of the thinning process itself.

[0058] A third advantage is the reduction in the required thickness of the DonSubl layer transferred from the donor substrate DonSub onto the device substrate DevSub.

[0059] A fourth advantage is the reduction of heat treatment time.

[0060] However, the applicant was able to determine that, surprisingly and unexpectedly, the temperature ramp of the heat treatment, which is usually part of the DonSubl layer finishing step, influences the thickness of the multi-domain layer. As explained below, it is possible to reduce the layer thickness. multi-domain, and therefore to reduce the thinning to be applied to the DonSubi layer, by employing a sufficiently strong temperature ramp.

[0061] Conventionally, a layer transferred from a donor substrate to a receiving substrate, the device substrate mentioned above, is subjected to heat treatment with several objectives: (1) to strengthen the bond between the layer and the receiving substrate and (2) to improve the quality of the transferred layer itself by repairing, for example, crystalline defects induced by the transfer process and, to some extent, improving its surface finish. Ideally, the heat treatment would be carried out immediately at a temperature as high as possible compatible with the materials constituting the layer and the receiving substrate. However, it is necessary to take into account, for example, the differences in thermal expansion between the transferred layer and its substrate by avoiding excessive thermal shock, which could, for example, break the assembly at the bonding surface between the transferred layer and its substrate.It would be possible to place the assembly in a furnace at ambient temperature and very gradually raise the temperature to a treatment temperature of, for example, 500 or 600°C. However, this method has the drawback of immobilizing the furnace for a long period (the temperature decrease also follows a long, downward ramp). Therefore, a compromise is generally used, which may consist of placing the assembly to be treated in a furnace (a so-called "boat-in" operation) already at a temperature of around 350°C, then gradually raising the temperature to a plateau maintained for a certain time, lowering the furnace temperature to approximately 350°C, and removing the treated assembly from the furnace (a so-called "boat-out" operation). In this way, furnace immobilization is limited without damaging the assembly undergoing heat treatment.

[0062] In the context of studies on the thickness of the multi-domain layer, the applicant carries out characterizations according to the following principle. Following a heat treatment applied to a DonSubi layer transferred according to the process explained above, the layer is thinned by chemical mechanical polishing (CMP) and then the topography of the revealed face is measured: a strong topography indicates the multi-domain quality of the material whose face is exposed and, on the contrary, a weak topography indicates the single-domain quality of the material whose face is revealed.

[0063] Indeed, the rate of chemical or physicochemical etching of the DonSubi layer occurring during polishing is made variable by the nature of the polarity of the ferroelectric material removed: the Z- side of this layer etches much faster than the Z+ side. Consequently, the polishing of a layer A single-domain layer will exhibit a much lower surface topography than the polishing of a multi-domain layer.

[0064] Also, according to the proposed characterization technique, by evaluating the topography of the exposed face of the thin film after it has been thinned to a predetermined thickness, it is possible to determine very simply whether the multi-domain layer extended over a depth greater than the determined thickness (revealed by a significant topography) or whether it extended over a thickness less than the determined thickness (revealed by a shallow topography). This somewhat crude characterization of the multi-domain thickness nevertheless allows for an overall assessment of this thickness by repeating the topography measurement at a plurality of locations sampling the entire extent of this layer.

[0065] Using this technique, the applicant evaluated the thickness of the multi-domain zone of DonSubl layers for different heat treatments.

[0066] Fig. 6 illustrates topographies obtained by atomic force microscopy (AFM) for DonSubi layers after a thickness of 125 nm was removed by CMP following the application of test heat treatments.

[0067] Figures 6(A) to 6(E) illustrate topographies after removal of a thickness of approximately 125 nm, for different thermal treatments. The images on the left represent the topographies for measurements on 5 pm x 5 pm fields, the images on the right represent the topographies for measurements on 30 pm x 30 pm fields.

[0068] Figures 6 illustrate (A) to (D) topographies for different heat treatments with a boat-in (insertion into the furnace) in a furnace at 350°C, a temperature ramp up to 500°C, a one-hour holding period, and then a cooling down to 350°C for a boat-out (removal from the furnace). The temperature ramp rates were set at 1°C / min, 5°C / min, 7°C / min, and 10°C / min, respectively. For temperature ramp rates of 7°C / min or less, domains are observed, visible as bright dots in the images. Conversely, for a temperature ramp rate exceeding 7°C / min, and particularly for 10°C / min, no multi-domain structure is observed at the exposed surface of the layer.

[0069] Figure 6 illustrates in (E) topographies for a heat treatment without a temperature ramp, with a boat-in (insertion into the furnace) in a 500°C furnace, a one-hour holding period, and then a boat-out. Here too, no multi-domain structure was observed. The temperature rise of the DonSubi layer is considered to be greater than 10°C / min.

[0070] In all cases, given the low thermal inertia of the DonSubi layer surface, its thermalization at the furnace temperature can be considered almost- instantaneous and that the oven temperature is therefore representative of that of this layer.

[0071] Figure 7 illustrates, from (A) to (D), topographies for two heat treatments and two shrinkage thicknesses: approximately 125 nm of thinning for (A) and (C) and approximately 105 nm of thinning for (B) and (D). Figure 7 illustrates in (A) and (B) topographies for DonSubi layers subjected to a heat treatment similar to that of Figures 6(A) to (D), with boat-in (insertion into the furnace) in a furnace at 350°C, a temperature ramp up to 500°C, a one-hour holding period, then a return to 350°C for boat-out (removal from the furnace), the ramp rates for temperature ramp-up and ramp-down were set at 10°C / min. Figure 7 illustrates in (C) and (D) topographies for DonSubi layers subjected to heat treatment with a boat-in (insertion into the furnace) in a furnace at 500°C, a one-hour rest, then a boat-out.These topographies indicate that, in all cases, a multi-domain structure is observable at a depth of 105 nm but not at 125 nm. It can therefore be deduced that, for temperature ramps with velocity values ​​greater than 10°C / min, the thickness of the multi-domain layer to be eliminated is between 105 nm and 125 nm.

[0072] For comparison, it should be noted that in the case of ramps of 1°C / min, as in case (A) of [Fig. 6], the thickness of the multi-domain layer is typically on the order of 200 nm. Reducing this thickness to a thickness between 105 and 125 nm constitutes a significant improvement.

[0073] Finishing treatment of the transferred layer

[0074] The finishing step 150 to be applied to the DonSubi layer can comprise three steps applied successively in this order: a surface treatment step 150A following step 140; a stabilizing heat treatment step 150B; and a thinning step 150C. Based on the above observations, steps 150B and 150C can be optimized.

[0075] Step 150A of applying a SurfTreat surface treatment is optional, but can advantageously contribute to improving the quality of the DonSubi layer.

[0076] A first type of surface treatment can be provided to remove a lithium-rich surface layer, typically composed of Li2CO3. It may include or consist of brushing the free face of the first layer while simultaneously dispensing deionized water onto this free face. It is also possible to complement this lithium removal step with a step for removing lithium-rich dendrites or preventing / limiting their formation. These dendrites, which have an amorphous structure, are rich in lithium and hydrogen and are susceptible to nucleation on the free face. of the DonSubi layer when it lacks the lithium-rich surface layer. See patent document WO2024022723A1. A first variant of the dendrite removal step could consist of allowing the dendrites to develop and stabilize on the surface for at least 50 hours, preferably at least 75 hours, at room temperature, after the lithium removal step, so that dendrite development is effectively stabilized. Alternatively, the DonSubi layer could be exposed to a temperature above room temperature to promote dendrite development and reduce the waiting time to less than 50 hours. The remaining task would then be to remove the dendrites, for example, by a wet cleaning step of the free face, such as a cleaning step of the same type as that used to remove the surface layer 11 of Li2CO3.A second variant involves treating the free side of the DonSubi layer to prevent dendrite formation. This second preparation step is therefore applied less than 50 hours, preferably less than 10 hours, after the removal of the lithium-rich surface layer. It may include exposing the free side of the first layer to a plasma, for example, a plasma chosen from a list consisting of an O2 plasma, a N2 plasma, and a fluorine-based plasma, such as an SF6 or CxHyFz plasma, or a combination of these plasmas. For example, a 30-second RF (13.55 MHz) nitrogen (N2) plasma at a power of 150 W and a pressure of 50 mT, in a nitrogen flow of 75 SCCM, has proven particularly effective.Similarly, a 30-second RF plasma sequence (at 13.55 MHz), with a power of 150W and a pressure of 50mT, in an oxygen flow of 75 SCCM and SF6 of 3 SCCM, was also shown to be effective in treating the free face 9 of the first layer 8 and preventing the appearance of dendrites 12.

[0077] A second type of surface treatment can consist of introducing hydrogen onto the surface of the DonSubi layer. Indeed, as indicated in international patent application PCT / EP2024 / 059520, introducing a sufficient dose of hydrogen into a surface thickness of the transferred layer, before applying the heat treatment, tends to reduce the thickness of the multi-domain surface portion that is exposed during this heat treatment. Thus, it is advantageous to apply a treatment to the free face of the DonSubi layer that produces a hydrogen concentration greater than 2 x 10²¹ atoms / cm³ in a surface thickness of the DonSubi layer, for example, less than 200 nm deep. For example, a dose of hydrogen greater than or equal to 2 x 10¹⁶ atoms / cm² can be introduced into the layer, or wet cleaning treatments can be performed.

[0078] Step 150B of applying a stabilizing Stab heat treatment to the transferred layer from the donor substrate DonSub to the device substrate DevSub follows optional step 150A.

[0079] As mentioned above, and explained for example in patent document WO2020200986, this heat treatment makes it possible to heal crystalline defects present in the DonSubi transferred layer, and even to reduce the roughness of its free face. Furthermore, it helps to consolidate its adhesion to the DevSub device substrate. The heat treatment raises the entire Set to a temperature between 300°C and the Curie temperature of the ferroelectric material for a duration of between 30 minutes and 10 hours. This heat treatment is preferably carried out by exposing the free face of the DonSubi layer to an oxidizing or neutral gaseous atmosphere, i.e., without covering this face of the thin film with a protective layer.

[0080] A heat treatment according to the invention is illustrated in Figures 3 and 8. The Stab heat treatment comprises passing the Set assembly, and therefore the DevSub device substrate equipped with the DonSubi layer, through a controlled furnace to subject the Set assembly, in this order: (i) a temperature rise TmpRs to a high temperature HT between 400°C and the Curie temperature of the ferroelectric material forming the DonSubi layer; (ii) a holding of the high temperature HT for a duration At greater than 30 minutes; and (iii) a temperature decrease from the high temperature HT. During this heat treatment, the furnace is controlled so that the rise TmpRs includes a rising temperature Rmpl of the transferred layer, carried out at a temperature rate greater than 7°C / min, preferably greater than or equal to 10°C / min.

[0081] Respecting this rate of temperature variation is optional for the temperature descent, additional experiments having shown that it is respecting this rate of temperature variation during the temperature rise that makes it possible to obtain the reduction of the thickness on which a multi-domain ferroelectric structure is likely to form.

[0082] The heat treatment profile applied to the DonSubi layer is not particularly limited, provided that the temperature rise of this layer leading to its maintenance at temperature Stp (the temperature of which is not necessarily fixed, as long as it remains above the indicated upper temperature) includes a temperature ramp Rmpl of the transferred layer with a slope greater than 7°C / min, preferably greater than or equal to 10°C / min, resulting in a temperature rise preferably of at least 100°C, preferably 200°C, more preferably 350°C, even more preferably 400°C and at most preferably of at least 450°C from the temperature of the transferred layer, the Rmpl temperature ramp leading to a layer temperature between 400°C and the Curie temperature.

[0083] Such conditions can be ensured by means of multiple methods, described below.

[0084] The first method, illustrated in (A) of [Fig. 3], consists of placing the assembly Set directly into the furnace while it is at the high temperature HT and removing it from the furnace while it is still at the high temperature. [Fig. 3](A) is a graph schematically showing the evolution of the temperature T° of the DonSubi layer as a function of time t. In this situation, the temperature rise Rmpl occurs from the ambient temperature TAm b at the time t0 of insertion into the furnace, which is already at the high temperature HT, until the time tl when the high temperature HT, between 400°C and the Curie temperature of the material forming the DonSubi layer, is reached by the layer. The high temperature is maintained for temperature maintenance Stp. The temperature drop Rmp2 occurs from the high temperature HT from a time t2 of oven withdrawal, until the time t3 when the layer returns to the ambient temperature TAmb.The time interval At between instants t1 and t2 corresponds to the duration of maintenance at a temperature equal to or greater than the high temperature HT, and lower than the Curie temperature of the material forming the transferred layer. In this case, the instants t0 and t1 on the one hand, and t2 and t3 on the other, are practically identical, due to the rapid thermalization of the DonSubi layer. It is understood that the temperature rise of this layer is rapid here, well above 10°C / min.

[0085] This method has the advantage of simplicity and speed. On the other hand, it may not be suitable for all types of device substrates, ferroelectric materials, or particular combinations thereof.

[0086] The second method is more universal than the first, in that, by imposing a less abrupt thermal stress, it is applicable to a wider range of substrates and ferroelectric materials than the first method. On the other hand, it requires more time than the first. In this second method, illustrated in [Fig. 3](B) by a graph similar to that of the first method, the assembly Set at room temperature TAmb is placed in the furnace at time t0 when it is at a first low temperature LT1 and removed from the furnace at time t5 when it is at a second low temperature LT2, producing a temperature ramp Rmpl between times t0 and t1 and a temperature ramp Rmp2 from time t5, which can respectively have the characteristics of the Rmpl and Rmp2 ramps of the example in [Fig. 3](A).Temperature ramps Rmpl' and Rmp2' are carried out in a controlled manner between the high temperature. The high temperature (HT) of the furnace and the low temperatures LT1 and LT2, between times t1 and t2 and times t3 and t4, respectively. These ramps Rmpl' and Rmp2' can exhibit lower temperature variations and rates of temperature change than the temperature ramps Rmpl and Rmp2, thus limiting the thermal stress imposed on the transferred layer. In this way, the amplitude of the abrupt temperature change applied to the transferred layer during its entry and exit from the furnace is also limited compared to the case of [Fig. 3](A). The time interval At between times t2 and t3 corresponds to the duration for which the transferred layer is held at the high temperature HT. The first low temperature LT1 can be between 400°C and the high temperature HT. The temperature LT2 can be between ambient temperature and the HT temperature. LT1 and LT2 can be equal or different from each other.

[0087] In this scenario, the times t0 and tl are practically identical, due to the rapid thermalization of the DonSubl layer. It is understood that the temperature rise Rmpl of this layer is rapid here, well above 10°C / min.

[0088] The oven can also be configured to impose a rapid temperature ramp, greater than 7°C / min, on the layer transferred during the Rmpl' temperature ramp, possibly slower than the Rmpl temperature ramp.

[0089] Step 150C, the Thinning step, is implemented after step 150B of the stabilization treatment. This step aims, in particular, to remove the multi-domain surface portion of the DonSubi layer, this portion having been created during the preceding heat treatment step. It also aims to provide a single-domain DevLay device thin film with a thickness corresponding to a target thickness, as previously mentioned. This thinning can, generally speaking, correspond to polishing the first free face of the DonSubi layer, for example, by mechanical or mechanochemical thinning techniques. It can also be thinning achieved by ion etching, for example, by reactive ion etching.

[0090] In all cases, this thinning is carried out in such a way as to eliminate at least the thickness of the multi-domain portion of the DonSubi, this thickness being typically less than 125 nm in the process described above. Figure 1 illustrates in (E) the structure obtained after these treatments, with a single-domain DevLay thin film deposited on the DevSub device substrate.

[0091] Thus, even taking into account margins of error regarding the thickness of the multi-domain portion to be removed and the thickness actually removed, the thinning step 150C can be designed to remove 300 nm or less, 200 nm or less, preferably 170 nm or less, more preferably 150 nm or less and even more preferably 125 nm or less DonSubi layer thickness.

[0092] Variants

[0093] The process described above by means of Figures 1 to 3 describes a simple case to which the invention is not limited. Figures 4, 5 and 8 illustrate alternative configurations that can be used alone or in combination as variants of the process 100 described above.

[0094] Figure 4 illustrates in (A) the possibility of forming, during step 110Don, a superficial interlayer Inter which has the advantage of facilitating the assembly of the two substrates DonSub and DevSub, particularly when they are assembled by direct bonding: at least one interlayer Inter can be formed prior to assembly, either on the DonTop face of the donor substrate DonSub, or on the DevTop face to be assembled of the device substrate DevSub, or on both. This interlayer can, for example, consist of one or more layers selected from layers of silicon oxide, silicon nitride, and / or silicon oxynitride. It can have a thickness ranging from a few nanometers to a few microns and optionally have an amorphous structure.

[0095] An interlayer with a low hydrogen concentration or one that acts as a barrier to hydrogen diffusion will be preferred, in accordance with the guidelines of document WO2020200986, thus limiting the formation of a multi-domain zone in the DonSubi layer. The interlayer can be produced using various state-of-the-art techniques, such as oxidation or nitriding heat treatments, chemical deposition (PECVD, LPCVD, etc.).

[0096] Fig. 4 illustrates in (B) the possibility of forming a TrapLay layer for trapping electrical charges on the DevTop surface of the DevSub device substrate during step 110Dew. The trapping layer, as is well known in itself, can be formed from a layer of polycrystalline silicon, and have a thickness typically between 500nm and 10 microns.

[0097] Fig. 4 illustrates in (C) the structure of the Set assembly in the particular case where an intercalated layer is formed on the donor substrate DonSub, an electrical charge trapping layer is formed on the device substrate DevSub, and these two substrates form the Set assembly obtained by intimate contact of the DonTop and DevTop faces of these substrates.

[0098] Fig. 4 illustrates in (D) the final structure obtained by implementing step 150 in the Set assembly, with the trapping layer TrapLay, the interlayer Inter and the single-domain ferroelectric layer DevLay formed in that order on the device substrate DevSub.

[0099] Figure 5 illustrates a variant in which the donor substrate DonSub is a hybrid structure comprising a support substrate CarSub supporting a single-crystal, single-domain ferroelectric layer FerroLay from which the DonSub layer is obtained during step 140 of process 100. Figure 5 more specifically illustrates the implementation of step 120Don of creating the embrittlement plane Frgl by ion implantation through the DonTop surface, which is the free face of the FerroLay layer.

[0100] This variant is particularly suited to the situation in which the DonSubi layer has a coefficient of thermal expansion (in the principal plane defining this layer) that is very different from that of the DevSub device substrate, for example, a difference of more than 10% (at room temperature).

[0101] The CarSub support substrate is advantageously made of a material (or a plurality of materials) giving it a coefficient of thermal expansion close to that of the DevSub device substrate. By "close," we mean that the difference between the coefficients of thermal expansion of the CarSub support substrate and the DevSub device substrate is less, in absolute value, than the difference in thermal expansion between (i) the DevSub device substrate and (ii) the donor substrate when it is made entirely of the ferroelectric material constituting the DonSubi layer.

[0102] Preferably, the CarSub support substrate and the DevSub device substrate have the same coefficient of thermal expansion. During the assembly of the CarSub support substrate and the DevSub device substrate in step 130, a Set assembly can thus be formed that is capable of withstanding heat treatment at a relatively high temperature. For ease of implementation, this can be achieved by choosing the CarSub support substrate to be made of the same material as the DevSub device substrate, for example, monocrystalline silicon.

[0103] To form the DonSub substrate of this variant, a solid block of ferroelectric material is first bonded to the CarSub carrier substrate, for example, using a molecular adhesion technique as previously described or with an adhesive layer. The carrier substrate is chosen for its coefficient of thermal expansion being close to that of the DevSub device substrate, and may, for example, be made of single-crystal silicon. Then, the FerroLay ferroelectric material layer is formed by thinning, for example, by grinding and / or chemical polishing and / or etching. Before assembly, the formation of an adhesive layer (for example, by deposition of silicon oxide and / or silicon nitride, or an adhesive layer, for example, a polymer) may be planned on one or both of the contacting faces. The assembly may include the application of a low temperature heat treatment (for example between 50 and 300°C, typically 100°C) to sufficiently increase the bonding energy to allow the next thinning step.

[0104] The CarSub support substrate is chosen to have a thickness substantially equivalent to that of the DevSub device substrate. The thinning step is carried out in such a way that the FerroLay layer has a sufficiently small thickness to reduce the stresses generated during the heat treatments applied later in the process. At the same time, this thickness is large enough to allow the DonSubi layer, or a plurality of such layers, to be extracted from it. This thickness can, for example, be between 5 and 400 microns.

[0105] This embodiment is advantageous in that the assembly formed by the donor substrate DonSub and the support substrate CarSub can be exposed to a much higher temperature than that applied when the donor substrate DonSub is made of a solid ferroelectric material, without risk of uncontrolled fracture of one of the substrates or delamination of the DonSub layer. The balanced structure, in terms of the coefficient of thermal expansion of this assembly, thus facilitates the detachment step of the DonSub layer by exposing the assembly to a relatively high temperature, for example between 100 and 500 °C.

[0106] Figures 3(A) and (B) illustrate examples in which a steep temperature ramp is imposed on the transferred layer from ambient temperature.

[0107] Conversely, [Fig. 8] illustrates another example of heat treatment, with an initial temperature rise SlRmpl that can be slow, but in reality has an arbitrary slope, bringing the transferred layer DonSubi from ambient temperature TAmb at time t0 to a low temperature LT1 located between the ambient temperature and the high temperature HT at time t'1, followed by a rapid temperature ramp Rmpl bringing the transferred layer to the high temperature HT at time t1, the high temperature being between 400°C and the Curie temperature of the material forming the layer. The high temperature is maintained for a holding stage Stp until time t2, before a first temperature drop Rmp2 to a low temperature LT2 at time t'2 followed by a second temperature drop SlRmp2 to return to ambient temperature at time t3.

[0108] Unless otherwise specified, the characteristics of the LT2 temperature, the velocities of the Rmpl and Rmp2 ramps, and the Stp temperature maintenance can be the same as those described in relation to Figures 3(A) and (B). The SlRmpl and SlRmp2 ramps have arbitrary slopes, but can have less steep slopes than those of the Rmpl and Rmp2 ramps, respectively.

[0109] Preferably, the Rmpl ramp causes a temperature rise in the layer of at least 100°C and leads to a temperature of at least 400°C and below the Curie temperature of the ferroelectric material, so that the effects of this ramp become clearly apparent within the crystalline structure of the DonSubl layer.

[0110] Fig. 8 is only one example in addition to those in Figures 3(A) and 3(B), and the temperature profiles of the heat treatments in these examples are not particularly limited, as long as they contain a holding range above 400°C and below the Curie temperature of the transferred layer material for at least 30 min, and a rapid temperature ramp of the transferred layer of at least 7°C / min, resulting in a temperature rise of the transferred layer, preferably, of at least 100°C, preferably 200°C, more preferably 300°C, and even more preferably 400°C, the rapid temperature ramp being such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp.

[0111] Thus, in general, the 150B heat treatment involves a temperature ramp TmpRs, consisting of the Rmpl ramp for the case of [Fig. 3](A), combining the Rmpl and Rmpl' ramps for the case of [Fig. 3](B), and combining the SlRmpl and Rmpl ramps for the case of [Fig. 8]. It appears from all the tests carried out by the inventor that the effect of reducing the thickness over which a multi-domain ferroelectric structure is likely to form in a surface region of the transferred ferroelectric layer is obtained on the condition that a sufficiently rapid ramp leading to a sufficiently high temperature is applied to the layer. These conditions can also be met for a gentle temperature ramp from room temperature, provided that a rapid temperature ramp leading to a sufficiently high temperature, and therefore having a significant effect on the crystal lattice of the layer, is subsequently applied.

[0112] In this document, the expression "ambient temperature" refers to a room temperature in which human operators work without special equipment, typically between 15 and 25°C.

[0113] Of course the invention is not limited to the described embodiment and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

1. Demands A process for preparing a single-domain thin film (DevLay) in ferroelectric material, the process comprising: - a step (120Don) of implantation of a so-called "light" species via a first face (DonTop) of a donor substrate (DonSub) so as to form a weakening plane (Frgl) in the donor substrate (DonSub); - a step (130) of assembling the first face (DonTop) of the donor substrate (DonSub) to a device substrate (DevSub) so as to form an intermediate assembly (Set); - a step (140) of fracturing the intermediate assembly (Set) at the level of the embrittlement plane (Frgl), this step leading to equipping the substrate (DevSub) with a device of a ferroelectric layer (DonSub 1) transferred from the donor substrate (DonSub) and having a free face (FrFac); - a finishing step (150) of the transferred ferroelectric layer (DonSub 1) comprising a heat treatment step (150B) (Stab) and, after the heat treatment step (150B) (Stab), a thinning step (150C) of the transferred ferroelectric layer (DonSub 1) so as to form the single-domain thin film (DevLay), the preparation process being characterized in that the heat treatment (Stab) comprises passing the substrate (DevSub) of a device equipped with the ferroelectric layer (DonSub 1) into a controlled furnace to impose: - a temperature rise (TmpRs) of the transferred ferroelectric layer (DonSub 1) to a high temperature (HT) between 400°C and the Curie temperature of the ferroelectric material forming the transferred ferroelectric layer (DonSub i); then - a holding (Stp) of the transferred ferroelectric layer at a temperature between the high temperature (HT) and said Curie temperature, for a duration (At) greater than 30 min; then - a temperature decrease (Rmp2) of the transferred ferroelectric layer (DonSub 1), from the high temperature (HT), in which the furnace is controlled so that the temperature rise (TempRs) of the transferred ferroelectric layer (DonSub 1) includes a temperature ramp (Rmpl) carried out at a rate of temperature change greater than or equal to 7°C / min, preferably greater than or equal to 10°C / min, such that the transferred ferroelectric layer reaches a temperature between 400°C and the Curie temperature at the end of the ramp (Rmpl).

2. A method according to claim 1, wherein the temperature ramp of the transferred ferroelectric (DonSubl) layer is parameterized to cause a temperature rise of at least 350°C, preferably 400°C, even more preferably 450°C, of ​​the transferred ferroelectric (DonSubl) layer.

3. Method according to claim 1 or 2, wherein the temperature ramp of the transferred ferroelectric layer (DonSubl) is parameterized to start at a temperature (LT1) located between an ambient temperature and the high temperature (HT), and to cause a temperature rise of at least 100°C.

4. A method according to any one of claims 1 to 3, wherein the thinning step (150C) consists of removing a thickness of the transferred ferroelectric layer (DonSubl) of less than 200 nm, preferably less than 150 nm.

5. Method according to any one of claims 1 to 4, wherein the device substrate (DevSub) equipped with the transferred ferroelectric layer (DonSubl) is placed directly into the furnace while the latter is at high temperature (HT).

6. A method according to any one of claims 1 to 4, wherein the device substrate (DevSub) equipped with the transferred ferroelectric layer (DonSubl) is placed in the furnace while the latter is at a first low temperature (LT1) and removed from the furnace while the latter is at a second low temperature (LT2), the first low temperature (LT1) and the second low temperature (LT2) each being between the ambient temperature and the high temperature, preferably between 100°C and 500°C, even more preferably between 300°C and 400°C.

7. A method according to any one of claims 1 to 6, wherein the single-domain thin film (DevLay) is made of a single-crystal piezoelectric material, such as lithium tantalate or lithium niobate.

8. A method according to any one of claims 1 to 7, wherein the donor substrate (DonSub) is made of a bulk ferroelectric material.

9. A method according to any one of claims 1 to 7, wherein the donor substrate (DonSub) comprises a support substrate (CarSub) supporting a layer (FerroLay) of ferroelectric material, a material forming the donor substrate being distinct from a ferroelectric material forming the layer (FerroLay) of ferroelectric material.

10. A method according to any one of claims 1 to 9, wherein the step (150) of finishing the transferred ferroelectric layer (DonSub 1) comprises a surface treatment step (150A) intended to remove a lithium-rich surface layer, and / or remove or prevent the formation of dendrites.

11. A method according to any one of claims 1 to 10, wherein the step (150) of finishing the transferred ferroelectric (DonSub 1) layer comprises a surface treatment step (150A) provided for introducing hydrogen onto the surface of the transferred ferroelectric (DonSubi) layer producing so as to produce a hydrogen concentration greater than 2.1021 atoms / cm3 in a surface thickness of the transferred ferroelectric (DonSubi) layer less than 200 nm deep.

12. A method according to any one of claims 1 to 11, further comprising a step (110Don) of forming at least one interlayer (Inter), on at least one of a face (DonTop) of the donor substrate (DonSub) and a face (DevTop), formed of silicon oxide, silicon nitride, and / or silicon oxynitride.

13. Method according to any one of claims 1 to 12, further comprising a step (110Dev) of forming an electrical charge trapping layer (TrapLay) on a surface (DevTop) of the device substrate (DevSub), intended to come into contact with the donor substrate (DonSub).

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